Aditya Mehrotra / mbed-dev

Biomimetics MBED Library w/ Added Support for CAN3

Dependents:   CAN_TEST SPIne_Plus_DYNO_SENSORS SPIne_Plus_v2 SPIne_Plus_Dyno_v2

cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.S@0:083111ae2a11, 2020-11-26 (annotated)

Committer:
saloutos
Date:
Thu Nov 26 04:08:56 2020 +0000
Revision:
0:083111ae2a11
first commit of leaned mbed dev lib

Who changed what in which revision?

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saloutos 0:083111ae2a11 1 /* Copyright (c) 2009 - 2012 ARM LIMITED
saloutos 0:083111ae2a11 2
saloutos 0:083111ae2a11 3 All rights reserved.
saloutos 0:083111ae2a11 4 Redistribution and use in source and binary forms, with or without
saloutos 0:083111ae2a11 5 modification, are permitted provided that the following conditions are met:
saloutos 0:083111ae2a11 6 - Redistributions of source code must retain the above copyright
saloutos 0:083111ae2a11 7 notice, this list of conditions and the following disclaimer.
saloutos 0:083111ae2a11 8 - Redistributions in binary form must reproduce the above copyright
saloutos 0:083111ae2a11 9 notice, this list of conditions and the following disclaimer in the
saloutos 0:083111ae2a11 10 documentation and/or other materials provided with the distribution.
saloutos 0:083111ae2a11 11 - Neither the name of ARM nor the names of its contributors may be used
saloutos 0:083111ae2a11 12 to endorse or promote products derived from this software without
saloutos 0:083111ae2a11 13 specific prior written permission.
saloutos 0:083111ae2a11 14 *
saloutos 0:083111ae2a11 15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
saloutos 0:083111ae2a11 16 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
saloutos 0:083111ae2a11 17 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
saloutos 0:083111ae2a11 18 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
saloutos 0:083111ae2a11 19 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
saloutos 0:083111ae2a11 20 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
saloutos 0:083111ae2a11 21 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
saloutos 0:083111ae2a11 22 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
saloutos 0:083111ae2a11 23 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
saloutos 0:083111ae2a11 24 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
saloutos 0:083111ae2a11 25 POSSIBILITY OF SUCH DAMAGE.
saloutos 0:083111ae2a11 26 ---------------------------------------------------------------------------*/
saloutos 0:083111ae2a11 27
saloutos 0:083111ae2a11 28 /*----------------------------------------------------------------------------
saloutos 0:083111ae2a11 29 * Functions
saloutos 0:083111ae2a11 30 *---------------------------------------------------------------------------*/
saloutos 0:083111ae2a11 31 SECTION `.text`:CODE:NOROOT(2)
saloutos 0:083111ae2a11 32 arm
saloutos 0:083111ae2a11 33 PUBLIC __v7_all_cache
saloutos 0:083111ae2a11 34 /*
saloutos 0:083111ae2a11 35 * __STATIC_ASM void __v7_all_cache(uint32_t op) {
saloutos 0:083111ae2a11 36 */
saloutos 0:083111ae2a11 37
saloutos 0:083111ae2a11 38 __v7_all_cache:
saloutos 0:083111ae2a11 39
saloutos 0:083111ae2a11 40
saloutos 0:083111ae2a11 41 PUSH {R4-R11}
saloutos 0:083111ae2a11 42
saloutos 0:083111ae2a11 43 MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */
saloutos 0:083111ae2a11 44 ANDS R3, R6, #0x07000000 /* Extract coherency level */
saloutos 0:083111ae2a11 45 MOV R3, R3, LSR #23 /* Total cache levels << 1 */
saloutos 0:083111ae2a11 46 BEQ Finished /* If 0, no need to clean */
saloutos 0:083111ae2a11 47
saloutos 0:083111ae2a11 48 MOV R10, #0 /* R10 holds current cache level << 1 */
saloutos 0:083111ae2a11 49 Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */
saloutos 0:083111ae2a11 50 MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */
saloutos 0:083111ae2a11 51 AND R1, R1, #7 /* Isolate those lower 3 bits */
saloutos 0:083111ae2a11 52 CMP R1, #2
saloutos 0:083111ae2a11 53 BLT Skip /* No cache or only instruction cache at this level */
saloutos 0:083111ae2a11 54
saloutos 0:083111ae2a11 55 MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */
saloutos 0:083111ae2a11 56 ISB /* ISB to sync the change to the CacheSizeID reg */
saloutos 0:083111ae2a11 57 MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */
saloutos 0:083111ae2a11 58 AND R2, R1, #7 /* Extract the line length field */
saloutos 0:083111ae2a11 59 ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */
saloutos 0:083111ae2a11 60 LDR R4, =0x3FF
saloutos 0:083111ae2a11 61 ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */
saloutos 0:083111ae2a11 62 CLZ R5, R4 /* R5 is the bit position of the way size increment */
saloutos 0:083111ae2a11 63 LDR R7, =0x7FFF
saloutos 0:083111ae2a11 64 ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */
saloutos 0:083111ae2a11 65
saloutos 0:083111ae2a11 66 Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */
saloutos 0:083111ae2a11 67
saloutos 0:083111ae2a11 68 Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */
saloutos 0:083111ae2a11 69 ORR R11, R11, R7, LSL R2 /* Factor in the Set number */
saloutos 0:083111ae2a11 70 CMP R0, #0
saloutos 0:083111ae2a11 71 BNE Dccsw
saloutos 0:083111ae2a11 72 MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */
saloutos 0:083111ae2a11 73 B cont
saloutos 0:083111ae2a11 74 Dccsw: CMP R0, #1
saloutos 0:083111ae2a11 75 BNE Dccisw
saloutos 0:083111ae2a11 76 MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */
saloutos 0:083111ae2a11 77 B cont
saloutos 0:083111ae2a11 78 Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */
saloutos 0:083111ae2a11 79 cont: SUBS R9, R9, #1 /* Decrement the Way number */
saloutos 0:083111ae2a11 80 BGE Loop3
saloutos 0:083111ae2a11 81 SUBS R7, R7, #1 /* Decrement the Set number */
saloutos 0:083111ae2a11 82 BGE Loop2
saloutos 0:083111ae2a11 83 Skip: ADD R10, R10, #2 /* increment the cache number */
saloutos 0:083111ae2a11 84 CMP R3, R10
saloutos 0:083111ae2a11 85 BGT Loop1
saloutos 0:083111ae2a11 86
saloutos 0:083111ae2a11 87 Finished:
saloutos 0:083111ae2a11 88 DSB
saloutos 0:083111ae2a11 89 POP {R4-R11}
saloutos 0:083111ae2a11 90 BX lr
saloutos 0:083111ae2a11 91
saloutos 0:083111ae2a11 92
saloutos 0:083111ae2a11 93 END
saloutos 0:083111ae2a11 94 /*----------------------------------------------------------------------------
saloutos 0:083111ae2a11 95 * end of file
saloutos 0:083111ae2a11 96 *---------------------------------------------------------------------------*/
saloutos 0:083111ae2a11 97