Aditya Mehrotra / mbed-dev

Biomimetics MBED Library w/ Added Support for CAN3

Dependents:   CAN_TEST SPIne_Plus_DYNO_SENSORS SPIne_Plus_v2 SPIne_Plus_Dyno_v2

cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h@0:083111ae2a11, 2020-11-26 (annotated)

Committer:
saloutos
Date:
Thu Nov 26 04:08:56 2020 +0000
Revision:
0:083111ae2a11
first commit of leaned mbed dev lib

Who changed what in which revision?

UserRevisionLine numberNew contents of line
saloutos 0:083111ae2a11 1 /**************************************************************************//**
saloutos 0:083111ae2a11 2 * @file cmsis_gcc.h
saloutos 0:083111ae2a11 3 * @brief CMSIS compiler GCC header file
saloutos 0:083111ae2a11 4 * @version V5.0.2
saloutos 0:083111ae2a11 5 * @date 13. February 2017
saloutos 0:083111ae2a11 6 ******************************************************************************/
saloutos 0:083111ae2a11 7 /*
saloutos 0:083111ae2a11 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
saloutos 0:083111ae2a11 9 *
saloutos 0:083111ae2a11 10 * SPDX-License-Identifier: Apache-2.0
saloutos 0:083111ae2a11 11 *
saloutos 0:083111ae2a11 12 * Licensed under the Apache License, Version 2.0 (the License); you may
saloutos 0:083111ae2a11 13 * not use this file except in compliance with the License.
saloutos 0:083111ae2a11 14 * You may obtain a copy of the License at
saloutos 0:083111ae2a11 15 *
saloutos 0:083111ae2a11 16 * www.apache.org/licenses/LICENSE-2.0
saloutos 0:083111ae2a11 17 *
saloutos 0:083111ae2a11 18 * Unless required by applicable law or agreed to in writing, software
saloutos 0:083111ae2a11 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
saloutos 0:083111ae2a11 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
saloutos 0:083111ae2a11 21 * See the License for the specific language governing permissions and
saloutos 0:083111ae2a11 22 * limitations under the License.
saloutos 0:083111ae2a11 23 */
saloutos 0:083111ae2a11 24
saloutos 0:083111ae2a11 25 #ifndef __CMSIS_GCC_H
saloutos 0:083111ae2a11 26 #define __CMSIS_GCC_H
saloutos 0:083111ae2a11 27
saloutos 0:083111ae2a11 28 /* ignore some GCC warnings */
saloutos 0:083111ae2a11 29 #pragma GCC diagnostic push
saloutos 0:083111ae2a11 30 #pragma GCC diagnostic ignored "-Wsign-conversion"
saloutos 0:083111ae2a11 31 #pragma GCC diagnostic ignored "-Wconversion"
saloutos 0:083111ae2a11 32 #pragma GCC diagnostic ignored "-Wunused-parameter"
saloutos 0:083111ae2a11 33
saloutos 0:083111ae2a11 34 /* CMSIS compiler specific defines */
saloutos 0:083111ae2a11 35 #ifndef __ASM
saloutos 0:083111ae2a11 36 #define __ASM __asm
saloutos 0:083111ae2a11 37 #endif
saloutos 0:083111ae2a11 38 #ifndef __INLINE
saloutos 0:083111ae2a11 39 #define __INLINE inline
saloutos 0:083111ae2a11 40 #endif
saloutos 0:083111ae2a11 41 #ifndef __STATIC_INLINE
saloutos 0:083111ae2a11 42 #define __STATIC_INLINE static inline
saloutos 0:083111ae2a11 43 #endif
saloutos 0:083111ae2a11 44 #ifndef __NO_RETURN
saloutos 0:083111ae2a11 45 #define __NO_RETURN __attribute__((noreturn))
saloutos 0:083111ae2a11 46 #endif
saloutos 0:083111ae2a11 47 #ifndef __USED
saloutos 0:083111ae2a11 48 #define __USED __attribute__((used))
saloutos 0:083111ae2a11 49 #endif
saloutos 0:083111ae2a11 50 #ifndef __WEAK
saloutos 0:083111ae2a11 51 #define __WEAK __attribute__((weak))
saloutos 0:083111ae2a11 52 #endif
saloutos 0:083111ae2a11 53 #ifndef __PACKED
saloutos 0:083111ae2a11 54 #define __PACKED __attribute__((packed, aligned(1)))
saloutos 0:083111ae2a11 55 #endif
saloutos 0:083111ae2a11 56 #ifndef __PACKED_STRUCT
saloutos 0:083111ae2a11 57 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
saloutos 0:083111ae2a11 58 #endif
saloutos 0:083111ae2a11 59 #ifndef __UNALIGNED_UINT32 /* deprecated */
saloutos 0:083111ae2a11 60 #pragma GCC diagnostic push
saloutos 0:083111ae2a11 61 #pragma GCC diagnostic ignored "-Wpacked"
saloutos 0:083111ae2a11 62 #pragma GCC diagnostic ignored "-Wattributes"
saloutos 0:083111ae2a11 63 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
saloutos 0:083111ae2a11 64 #pragma GCC diagnostic pop
saloutos 0:083111ae2a11 65 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
saloutos 0:083111ae2a11 66 #endif
saloutos 0:083111ae2a11 67 #ifndef __UNALIGNED_UINT16_WRITE
saloutos 0:083111ae2a11 68 #pragma GCC diagnostic push
saloutos 0:083111ae2a11 69 #pragma GCC diagnostic ignored "-Wpacked"
saloutos 0:083111ae2a11 70 #pragma GCC diagnostic ignored "-Wattributes"
saloutos 0:083111ae2a11 71 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
saloutos 0:083111ae2a11 72 #pragma GCC diagnostic pop
saloutos 0:083111ae2a11 73 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
saloutos 0:083111ae2a11 74 #endif
saloutos 0:083111ae2a11 75 #ifndef __UNALIGNED_UINT16_READ
saloutos 0:083111ae2a11 76 #pragma GCC diagnostic push
saloutos 0:083111ae2a11 77 #pragma GCC diagnostic ignored "-Wpacked"
saloutos 0:083111ae2a11 78 #pragma GCC diagnostic ignored "-Wattributes"
saloutos 0:083111ae2a11 79 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
saloutos 0:083111ae2a11 80 #pragma GCC diagnostic pop
saloutos 0:083111ae2a11 81 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
saloutos 0:083111ae2a11 82 #endif
saloutos 0:083111ae2a11 83 #ifndef __UNALIGNED_UINT32_WRITE
saloutos 0:083111ae2a11 84 #pragma GCC diagnostic push
saloutos 0:083111ae2a11 85 #pragma GCC diagnostic ignored "-Wpacked"
saloutos 0:083111ae2a11 86 #pragma GCC diagnostic ignored "-Wattributes"
saloutos 0:083111ae2a11 87 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
saloutos 0:083111ae2a11 88 #pragma GCC diagnostic pop
saloutos 0:083111ae2a11 89 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
saloutos 0:083111ae2a11 90 #endif
saloutos 0:083111ae2a11 91 #ifndef __UNALIGNED_UINT32_READ
saloutos 0:083111ae2a11 92 #pragma GCC diagnostic push
saloutos 0:083111ae2a11 93 #pragma GCC diagnostic ignored "-Wpacked"
saloutos 0:083111ae2a11 94 #pragma GCC diagnostic ignored "-Wattributes"
saloutos 0:083111ae2a11 95 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
saloutos 0:083111ae2a11 96 #pragma GCC diagnostic pop
saloutos 0:083111ae2a11 97 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
saloutos 0:083111ae2a11 98 #endif
saloutos 0:083111ae2a11 99 #ifndef __ALIGNED
saloutos 0:083111ae2a11 100 #define __ALIGNED(x) __attribute__((aligned(x)))
saloutos 0:083111ae2a11 101 #endif
saloutos 0:083111ae2a11 102
saloutos 0:083111ae2a11 103
saloutos 0:083111ae2a11 104 /* ########################### Core Function Access ########################### */
saloutos 0:083111ae2a11 105 /** \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 106 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
saloutos 0:083111ae2a11 107 @{
saloutos 0:083111ae2a11 108 */
saloutos 0:083111ae2a11 109
saloutos 0:083111ae2a11 110 /**
saloutos 0:083111ae2a11 111 \brief Enable IRQ Interrupts
saloutos 0:083111ae2a11 112 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
saloutos 0:083111ae2a11 113 Can only be executed in Privileged modes.
saloutos 0:083111ae2a11 114 */
saloutos 0:083111ae2a11 115 __attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
saloutos 0:083111ae2a11 116 {
saloutos 0:083111ae2a11 117 __ASM volatile ("cpsie i" : : : "memory");
saloutos 0:083111ae2a11 118 }
saloutos 0:083111ae2a11 119
saloutos 0:083111ae2a11 120
saloutos 0:083111ae2a11 121 /**
saloutos 0:083111ae2a11 122 \brief Disable IRQ Interrupts
saloutos 0:083111ae2a11 123 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
saloutos 0:083111ae2a11 124 Can only be executed in Privileged modes.
saloutos 0:083111ae2a11 125 */
saloutos 0:083111ae2a11 126 __attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
saloutos 0:083111ae2a11 127 {
saloutos 0:083111ae2a11 128 __ASM volatile ("cpsid i" : : : "memory");
saloutos 0:083111ae2a11 129 }
saloutos 0:083111ae2a11 130
saloutos 0:083111ae2a11 131
saloutos 0:083111ae2a11 132 /**
saloutos 0:083111ae2a11 133 \brief Get Control Register
saloutos 0:083111ae2a11 134 \details Returns the content of the Control Register.
saloutos 0:083111ae2a11 135 \return Control Register value
saloutos 0:083111ae2a11 136 */
saloutos 0:083111ae2a11 137 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
saloutos 0:083111ae2a11 138 {
saloutos 0:083111ae2a11 139 uint32_t result;
saloutos 0:083111ae2a11 140
saloutos 0:083111ae2a11 141 __ASM volatile ("MRS %0, control" : "=r" (result) );
saloutos 0:083111ae2a11 142 return(result);
saloutos 0:083111ae2a11 143 }
saloutos 0:083111ae2a11 144
saloutos 0:083111ae2a11 145
saloutos 0:083111ae2a11 146 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos 0:083111ae2a11 147 /**
saloutos 0:083111ae2a11 148 \brief Get Control Register (non-secure)
saloutos 0:083111ae2a11 149 \details Returns the content of the non-secure Control Register when in secure mode.
saloutos 0:083111ae2a11 150 \return non-secure Control Register value
saloutos 0:083111ae2a11 151 */
saloutos 0:083111ae2a11 152 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
saloutos 0:083111ae2a11 153 {
saloutos 0:083111ae2a11 154 uint32_t result;
saloutos 0:083111ae2a11 155
saloutos 0:083111ae2a11 156 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
saloutos 0:083111ae2a11 157 return(result);
saloutos 0:083111ae2a11 158 }
saloutos 0:083111ae2a11 159 #endif
saloutos 0:083111ae2a11 160
saloutos 0:083111ae2a11 161
saloutos 0:083111ae2a11 162 /**
saloutos 0:083111ae2a11 163 \brief Set Control Register
saloutos 0:083111ae2a11 164 \details Writes the given value to the Control Register.
saloutos 0:083111ae2a11 165 \param [in] control Control Register value to set
saloutos 0:083111ae2a11 166 */
saloutos 0:083111ae2a11 167 __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
saloutos 0:083111ae2a11 168 {
saloutos 0:083111ae2a11 169 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
saloutos 0:083111ae2a11 170 }
saloutos 0:083111ae2a11 171
saloutos 0:083111ae2a11 172
saloutos 0:083111ae2a11 173 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos 0:083111ae2a11 174 /**
saloutos 0:083111ae2a11 175 \brief Set Control Register (non-secure)
saloutos 0:083111ae2a11 176 \details Writes the given value to the non-secure Control Register when in secure state.
saloutos 0:083111ae2a11 177 \param [in] control Control Register value to set
saloutos 0:083111ae2a11 178 */
saloutos 0:083111ae2a11 179 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
saloutos 0:083111ae2a11 180 {
saloutos 0:083111ae2a11 181 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
saloutos 0:083111ae2a11 182 }
saloutos 0:083111ae2a11 183 #endif
saloutos 0:083111ae2a11 184
saloutos 0:083111ae2a11 185
saloutos 0:083111ae2a11 186 /**
saloutos 0:083111ae2a11 187 \brief Get IPSR Register
saloutos 0:083111ae2a11 188 \details Returns the content of the IPSR Register.
saloutos 0:083111ae2a11 189 \return IPSR Register value
saloutos 0:083111ae2a11 190 */
saloutos 0:083111ae2a11 191 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
saloutos 0:083111ae2a11 192 {
saloutos 0:083111ae2a11 193 uint32_t result;
saloutos 0:083111ae2a11 194
saloutos 0:083111ae2a11 195 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
saloutos 0:083111ae2a11 196 return(result);
saloutos 0:083111ae2a11 197 }
saloutos 0:083111ae2a11 198
saloutos 0:083111ae2a11 199
saloutos 0:083111ae2a11 200 /**
saloutos 0:083111ae2a11 201 \brief Get APSR Register
saloutos 0:083111ae2a11 202 \details Returns the content of the APSR Register.
saloutos 0:083111ae2a11 203 \return APSR Register value
saloutos 0:083111ae2a11 204 */
saloutos 0:083111ae2a11 205 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
saloutos 0:083111ae2a11 206 {
saloutos 0:083111ae2a11 207 uint32_t result;
saloutos 0:083111ae2a11 208
saloutos 0:083111ae2a11 209 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
saloutos 0:083111ae2a11 210 return(result);
saloutos 0:083111ae2a11 211 }
saloutos 0:083111ae2a11 212
saloutos 0:083111ae2a11 213
saloutos 0:083111ae2a11 214 /**
saloutos 0:083111ae2a11 215 \brief Get xPSR Register
saloutos 0:083111ae2a11 216 \details Returns the content of the xPSR Register.
saloutos 0:083111ae2a11 217 \return xPSR Register value
saloutos 0:083111ae2a11 218 */
saloutos 0:083111ae2a11 219 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
saloutos 0:083111ae2a11 220 {
saloutos 0:083111ae2a11 221 uint32_t result;
saloutos 0:083111ae2a11 222
saloutos 0:083111ae2a11 223 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
saloutos 0:083111ae2a11 224 return(result);
saloutos 0:083111ae2a11 225 }
saloutos 0:083111ae2a11 226
saloutos 0:083111ae2a11 227
saloutos 0:083111ae2a11 228 /**
saloutos 0:083111ae2a11 229 \brief Get Process Stack Pointer
saloutos 0:083111ae2a11 230 \details Returns the current value of the Process Stack Pointer (PSP).
saloutos 0:083111ae2a11 231 \return PSP Register value
saloutos 0:083111ae2a11 232 */
saloutos 0:083111ae2a11 233 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
saloutos 0:083111ae2a11 234 {
saloutos 0:083111ae2a11 235 register uint32_t result;
saloutos 0:083111ae2a11 236
saloutos 0:083111ae2a11 237 __ASM volatile ("MRS %0, psp" : "=r" (result) );
saloutos 0:083111ae2a11 238 return(result);
saloutos 0:083111ae2a11 239 }
saloutos 0:083111ae2a11 240
saloutos 0:083111ae2a11 241
saloutos 0:083111ae2a11 242 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos 0:083111ae2a11 243 /**
saloutos 0:083111ae2a11 244 \brief Get Process Stack Pointer (non-secure)
saloutos 0:083111ae2a11 245 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
saloutos 0:083111ae2a11 246 \return PSP Register value
saloutos 0:083111ae2a11 247 */
saloutos 0:083111ae2a11 248 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
saloutos 0:083111ae2a11 249 {
saloutos 0:083111ae2a11 250 register uint32_t result;
saloutos 0:083111ae2a11 251
saloutos 0:083111ae2a11 252 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
saloutos 0:083111ae2a11 253 return(result);
saloutos 0:083111ae2a11 254 }
saloutos 0:083111ae2a11 255 #endif
saloutos 0:083111ae2a11 256
saloutos 0:083111ae2a11 257
saloutos 0:083111ae2a11 258 /**
saloutos 0:083111ae2a11 259 \brief Set Process Stack Pointer
saloutos 0:083111ae2a11 260 \details Assigns the given value to the Process Stack Pointer (PSP).
saloutos 0:083111ae2a11 261 \param [in] topOfProcStack Process Stack Pointer value to set
saloutos 0:083111ae2a11 262 */
saloutos 0:083111ae2a11 263 __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
saloutos 0:083111ae2a11 264 {
saloutos 0:083111ae2a11 265 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
saloutos 0:083111ae2a11 266 }
saloutos 0:083111ae2a11 267
saloutos 0:083111ae2a11 268
saloutos 0:083111ae2a11 269 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos 0:083111ae2a11 270 /**
saloutos 0:083111ae2a11 271 \brief Set Process Stack Pointer (non-secure)
saloutos 0:083111ae2a11 272 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
saloutos 0:083111ae2a11 273 \param [in] topOfProcStack Process Stack Pointer value to set
saloutos 0:083111ae2a11 274 */
saloutos 0:083111ae2a11 275 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
saloutos 0:083111ae2a11 276 {
saloutos 0:083111ae2a11 277 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
saloutos 0:083111ae2a11 278 }
saloutos 0:083111ae2a11 279 #endif
saloutos 0:083111ae2a11 280
saloutos 0:083111ae2a11 281
saloutos 0:083111ae2a11 282 /**
saloutos 0:083111ae2a11 283 \brief Get Main Stack Pointer
saloutos 0:083111ae2a11 284 \details Returns the current value of the Main Stack Pointer (MSP).
saloutos 0:083111ae2a11 285 \return MSP Register value
saloutos 0:083111ae2a11 286 */
saloutos 0:083111ae2a11 287 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
saloutos 0:083111ae2a11 288 {
saloutos 0:083111ae2a11 289 register uint32_t result;
saloutos 0:083111ae2a11 290
saloutos 0:083111ae2a11 291 __ASM volatile ("MRS %0, msp" : "=r" (result) );
saloutos 0:083111ae2a11 292 return(result);
saloutos 0:083111ae2a11 293 }
saloutos 0:083111ae2a11 294
saloutos 0:083111ae2a11 295
saloutos 0:083111ae2a11 296 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos 0:083111ae2a11 297 /**
saloutos 0:083111ae2a11 298 \brief Get Main Stack Pointer (non-secure)
saloutos 0:083111ae2a11 299 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
saloutos 0:083111ae2a11 300 \return MSP Register value
saloutos 0:083111ae2a11 301 */
saloutos 0:083111ae2a11 302 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
saloutos 0:083111ae2a11 303 {
saloutos 0:083111ae2a11 304 register uint32_t result;
saloutos 0:083111ae2a11 305
saloutos 0:083111ae2a11 306 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
saloutos 0:083111ae2a11 307 return(result);
saloutos 0:083111ae2a11 308 }
saloutos 0:083111ae2a11 309 #endif
saloutos 0:083111ae2a11 310
saloutos 0:083111ae2a11 311
saloutos 0:083111ae2a11 312 /**
saloutos 0:083111ae2a11 313 \brief Set Main Stack Pointer
saloutos 0:083111ae2a11 314 \details Assigns the given value to the Main Stack Pointer (MSP).
saloutos 0:083111ae2a11 315 \param [in] topOfMainStack Main Stack Pointer value to set
saloutos 0:083111ae2a11 316 */
saloutos 0:083111ae2a11 317 __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
saloutos 0:083111ae2a11 318 {
saloutos 0:083111ae2a11 319 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
saloutos 0:083111ae2a11 320 }
saloutos 0:083111ae2a11 321
saloutos 0:083111ae2a11 322
saloutos 0:083111ae2a11 323 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos 0:083111ae2a11 324 /**
saloutos 0:083111ae2a11 325 \brief Set Main Stack Pointer (non-secure)
saloutos 0:083111ae2a11 326 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
saloutos 0:083111ae2a11 327 \param [in] topOfMainStack Main Stack Pointer value to set
saloutos 0:083111ae2a11 328 */
saloutos 0:083111ae2a11 329 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
saloutos 0:083111ae2a11 330 {
saloutos 0:083111ae2a11 331 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
saloutos 0:083111ae2a11 332 }
saloutos 0:083111ae2a11 333 #endif
saloutos 0:083111ae2a11 334
saloutos 0:083111ae2a11 335
saloutos 0:083111ae2a11 336 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos 0:083111ae2a11 337 /**
saloutos 0:083111ae2a11 338 \brief Get Stack Pointer (non-secure)
saloutos 0:083111ae2a11 339 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
saloutos 0:083111ae2a11 340 \return SP Register value
saloutos 0:083111ae2a11 341 */
saloutos 0:083111ae2a11 342 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
saloutos 0:083111ae2a11 343 {
saloutos 0:083111ae2a11 344 register uint32_t result;
saloutos 0:083111ae2a11 345
saloutos 0:083111ae2a11 346 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
saloutos 0:083111ae2a11 347 return(result);
saloutos 0:083111ae2a11 348 }
saloutos 0:083111ae2a11 349
saloutos 0:083111ae2a11 350
saloutos 0:083111ae2a11 351 /**
saloutos 0:083111ae2a11 352 \brief Set Stack Pointer (non-secure)
saloutos 0:083111ae2a11 353 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
saloutos 0:083111ae2a11 354 \param [in] topOfStack Stack Pointer value to set
saloutos 0:083111ae2a11 355 */
saloutos 0:083111ae2a11 356 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
saloutos 0:083111ae2a11 357 {
saloutos 0:083111ae2a11 358 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
saloutos 0:083111ae2a11 359 }
saloutos 0:083111ae2a11 360 #endif
saloutos 0:083111ae2a11 361
saloutos 0:083111ae2a11 362
saloutos 0:083111ae2a11 363 /**
saloutos 0:083111ae2a11 364 \brief Get Priority Mask
saloutos 0:083111ae2a11 365 \details Returns the current state of the priority mask bit from the Priority Mask Register.
saloutos 0:083111ae2a11 366 \return Priority Mask value
saloutos 0:083111ae2a11 367 */
saloutos 0:083111ae2a11 368 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
saloutos 0:083111ae2a11 369 {
saloutos 0:083111ae2a11 370 uint32_t result;
saloutos 0:083111ae2a11 371
saloutos 0:083111ae2a11 372 __ASM volatile ("MRS %0, primask" : "=r" (result) );
saloutos 0:083111ae2a11 373 return(result);
saloutos 0:083111ae2a11 374 }
saloutos 0:083111ae2a11 375
saloutos 0:083111ae2a11 376
saloutos 0:083111ae2a11 377 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos 0:083111ae2a11 378 /**
saloutos 0:083111ae2a11 379 \brief Get Priority Mask (non-secure)
saloutos 0:083111ae2a11 380 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
saloutos 0:083111ae2a11 381 \return Priority Mask value
saloutos 0:083111ae2a11 382 */
saloutos 0:083111ae2a11 383 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
saloutos 0:083111ae2a11 384 {
saloutos 0:083111ae2a11 385 uint32_t result;
saloutos 0:083111ae2a11 386
saloutos 0:083111ae2a11 387 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
saloutos 0:083111ae2a11 388 return(result);
saloutos 0:083111ae2a11 389 }
saloutos 0:083111ae2a11 390 #endif
saloutos 0:083111ae2a11 391
saloutos 0:083111ae2a11 392
saloutos 0:083111ae2a11 393 /**
saloutos 0:083111ae2a11 394 \brief Set Priority Mask
saloutos 0:083111ae2a11 395 \details Assigns the given value to the Priority Mask Register.
saloutos 0:083111ae2a11 396 \param [in] priMask Priority Mask
saloutos 0:083111ae2a11 397 */
saloutos 0:083111ae2a11 398 __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
saloutos 0:083111ae2a11 399 {
saloutos 0:083111ae2a11 400 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
saloutos 0:083111ae2a11 401 }
saloutos 0:083111ae2a11 402
saloutos 0:083111ae2a11 403
saloutos 0:083111ae2a11 404 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos 0:083111ae2a11 405 /**
saloutos 0:083111ae2a11 406 \brief Set Priority Mask (non-secure)
saloutos 0:083111ae2a11 407 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
saloutos 0:083111ae2a11 408 \param [in] priMask Priority Mask
saloutos 0:083111ae2a11 409 */
saloutos 0:083111ae2a11 410 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
saloutos 0:083111ae2a11 411 {
saloutos 0:083111ae2a11 412 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
saloutos 0:083111ae2a11 413 }
saloutos 0:083111ae2a11 414 #endif
saloutos 0:083111ae2a11 415
saloutos 0:083111ae2a11 416
saloutos 0:083111ae2a11 417 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
saloutos 0:083111ae2a11 418 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
saloutos 0:083111ae2a11 419 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos 0:083111ae2a11 420 /**
saloutos 0:083111ae2a11 421 \brief Enable FIQ
saloutos 0:083111ae2a11 422 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
saloutos 0:083111ae2a11 423 Can only be executed in Privileged modes.
saloutos 0:083111ae2a11 424 */
saloutos 0:083111ae2a11 425 __attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
saloutos 0:083111ae2a11 426 {
saloutos 0:083111ae2a11 427 __ASM volatile ("cpsie f" : : : "memory");
saloutos 0:083111ae2a11 428 }
saloutos 0:083111ae2a11 429
saloutos 0:083111ae2a11 430
saloutos 0:083111ae2a11 431 /**
saloutos 0:083111ae2a11 432 \brief Disable FIQ
saloutos 0:083111ae2a11 433 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
saloutos 0:083111ae2a11 434 Can only be executed in Privileged modes.
saloutos 0:083111ae2a11 435 */
saloutos 0:083111ae2a11 436 __attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
saloutos 0:083111ae2a11 437 {
saloutos 0:083111ae2a11 438 __ASM volatile ("cpsid f" : : : "memory");
saloutos 0:083111ae2a11 439 }
saloutos 0:083111ae2a11 440
saloutos 0:083111ae2a11 441
saloutos 0:083111ae2a11 442 /**
saloutos 0:083111ae2a11 443 \brief Get Base Priority
saloutos 0:083111ae2a11 444 \details Returns the current value of the Base Priority register.
saloutos 0:083111ae2a11 445 \return Base Priority register value
saloutos 0:083111ae2a11 446 */
saloutos 0:083111ae2a11 447 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
saloutos 0:083111ae2a11 448 {
saloutos 0:083111ae2a11 449 uint32_t result;
saloutos 0:083111ae2a11 450
saloutos 0:083111ae2a11 451 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
saloutos 0:083111ae2a11 452 return(result);
saloutos 0:083111ae2a11 453 }
saloutos 0:083111ae2a11 454
saloutos 0:083111ae2a11 455
saloutos 0:083111ae2a11 456 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos 0:083111ae2a11 457 /**
saloutos 0:083111ae2a11 458 \brief Get Base Priority (non-secure)
saloutos 0:083111ae2a11 459 \details Returns the current value of the non-secure Base Priority register when in secure state.
saloutos 0:083111ae2a11 460 \return Base Priority register value
saloutos 0:083111ae2a11 461 */
saloutos 0:083111ae2a11 462 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
saloutos 0:083111ae2a11 463 {
saloutos 0:083111ae2a11 464 uint32_t result;
saloutos 0:083111ae2a11 465
saloutos 0:083111ae2a11 466 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
saloutos 0:083111ae2a11 467 return(result);
saloutos 0:083111ae2a11 468 }
saloutos 0:083111ae2a11 469 #endif
saloutos 0:083111ae2a11 470
saloutos 0:083111ae2a11 471
saloutos 0:083111ae2a11 472 /**
saloutos 0:083111ae2a11 473 \brief Set Base Priority
saloutos 0:083111ae2a11 474 \details Assigns the given value to the Base Priority register.
saloutos 0:083111ae2a11 475 \param [in] basePri Base Priority value to set
saloutos 0:083111ae2a11 476 */
saloutos 0:083111ae2a11 477 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
saloutos 0:083111ae2a11 478 {
saloutos 0:083111ae2a11 479 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
saloutos 0:083111ae2a11 480 }
saloutos 0:083111ae2a11 481
saloutos 0:083111ae2a11 482
saloutos 0:083111ae2a11 483 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos 0:083111ae2a11 484 /**
saloutos 0:083111ae2a11 485 \brief Set Base Priority (non-secure)
saloutos 0:083111ae2a11 486 \details Assigns the given value to the non-secure Base Priority register when in secure state.
saloutos 0:083111ae2a11 487 \param [in] basePri Base Priority value to set
saloutos 0:083111ae2a11 488 */
saloutos 0:083111ae2a11 489 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
saloutos 0:083111ae2a11 490 {
saloutos 0:083111ae2a11 491 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
saloutos 0:083111ae2a11 492 }
saloutos 0:083111ae2a11 493 #endif
saloutos 0:083111ae2a11 494
saloutos 0:083111ae2a11 495
saloutos 0:083111ae2a11 496 /**
saloutos 0:083111ae2a11 497 \brief Set Base Priority with condition
saloutos 0:083111ae2a11 498 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
saloutos 0:083111ae2a11 499 or the new value increases the BASEPRI priority level.
saloutos 0:083111ae2a11 500 \param [in] basePri Base Priority value to set
saloutos 0:083111ae2a11 501 */
saloutos 0:083111ae2a11 502 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
saloutos 0:083111ae2a11 503 {
saloutos 0:083111ae2a11 504 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
saloutos 0:083111ae2a11 505 }
saloutos 0:083111ae2a11 506
saloutos 0:083111ae2a11 507
saloutos 0:083111ae2a11 508 /**
saloutos 0:083111ae2a11 509 \brief Get Fault Mask
saloutos 0:083111ae2a11 510 \details Returns the current value of the Fault Mask register.
saloutos 0:083111ae2a11 511 \return Fault Mask register value
saloutos 0:083111ae2a11 512 */
saloutos 0:083111ae2a11 513 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
saloutos 0:083111ae2a11 514 {
saloutos 0:083111ae2a11 515 uint32_t result;
saloutos 0:083111ae2a11 516
saloutos 0:083111ae2a11 517 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
saloutos 0:083111ae2a11 518 return(result);
saloutos 0:083111ae2a11 519 }
saloutos 0:083111ae2a11 520
saloutos 0:083111ae2a11 521
saloutos 0:083111ae2a11 522 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos 0:083111ae2a11 523 /**
saloutos 0:083111ae2a11 524 \brief Get Fault Mask (non-secure)
saloutos 0:083111ae2a11 525 \details Returns the current value of the non-secure Fault Mask register when in secure state.
saloutos 0:083111ae2a11 526 \return Fault Mask register value
saloutos 0:083111ae2a11 527 */
saloutos 0:083111ae2a11 528 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
saloutos 0:083111ae2a11 529 {
saloutos 0:083111ae2a11 530 uint32_t result;
saloutos 0:083111ae2a11 531
saloutos 0:083111ae2a11 532 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
saloutos 0:083111ae2a11 533 return(result);
saloutos 0:083111ae2a11 534 }
saloutos 0:083111ae2a11 535 #endif
saloutos 0:083111ae2a11 536
saloutos 0:083111ae2a11 537
saloutos 0:083111ae2a11 538 /**
saloutos 0:083111ae2a11 539 \brief Set Fault Mask
saloutos 0:083111ae2a11 540 \details Assigns the given value to the Fault Mask register.
saloutos 0:083111ae2a11 541 \param [in] faultMask Fault Mask value to set
saloutos 0:083111ae2a11 542 */
saloutos 0:083111ae2a11 543 __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
saloutos 0:083111ae2a11 544 {
saloutos 0:083111ae2a11 545 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
saloutos 0:083111ae2a11 546 }
saloutos 0:083111ae2a11 547
saloutos 0:083111ae2a11 548
saloutos 0:083111ae2a11 549 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos 0:083111ae2a11 550 /**
saloutos 0:083111ae2a11 551 \brief Set Fault Mask (non-secure)
saloutos 0:083111ae2a11 552 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
saloutos 0:083111ae2a11 553 \param [in] faultMask Fault Mask value to set
saloutos 0:083111ae2a11 554 */
saloutos 0:083111ae2a11 555 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
saloutos 0:083111ae2a11 556 {
saloutos 0:083111ae2a11 557 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
saloutos 0:083111ae2a11 558 }
saloutos 0:083111ae2a11 559 #endif
saloutos 0:083111ae2a11 560
saloutos 0:083111ae2a11 561 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
saloutos 0:083111ae2a11 562 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
saloutos 0:083111ae2a11 563 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
saloutos 0:083111ae2a11 564
saloutos 0:083111ae2a11 565
saloutos 0:083111ae2a11 566 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
saloutos 0:083111ae2a11 567 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
saloutos 0:083111ae2a11 568
saloutos 0:083111ae2a11 569 /**
saloutos 0:083111ae2a11 570 \brief Get Process Stack Pointer Limit
saloutos 0:083111ae2a11 571 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
saloutos 0:083111ae2a11 572 \return PSPLIM Register value
saloutos 0:083111ae2a11 573 */
saloutos 0:083111ae2a11 574 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
saloutos 0:083111ae2a11 575 {
saloutos 0:083111ae2a11 576 register uint32_t result;
saloutos 0:083111ae2a11 577
saloutos 0:083111ae2a11 578 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
saloutos 0:083111ae2a11 579 return(result);
saloutos 0:083111ae2a11 580 }
saloutos 0:083111ae2a11 581
saloutos 0:083111ae2a11 582
saloutos 0:083111ae2a11 583 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
saloutos 0:083111ae2a11 584 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos 0:083111ae2a11 585 /**
saloutos 0:083111ae2a11 586 \brief Get Process Stack Pointer Limit (non-secure)
saloutos 0:083111ae2a11 587 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
saloutos 0:083111ae2a11 588 \return PSPLIM Register value
saloutos 0:083111ae2a11 589 */
saloutos 0:083111ae2a11 590 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
saloutos 0:083111ae2a11 591 {
saloutos 0:083111ae2a11 592 register uint32_t result;
saloutos 0:083111ae2a11 593
saloutos 0:083111ae2a11 594 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
saloutos 0:083111ae2a11 595 return(result);
saloutos 0:083111ae2a11 596 }
saloutos 0:083111ae2a11 597 #endif
saloutos 0:083111ae2a11 598
saloutos 0:083111ae2a11 599
saloutos 0:083111ae2a11 600 /**
saloutos 0:083111ae2a11 601 \brief Set Process Stack Pointer Limit
saloutos 0:083111ae2a11 602 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
saloutos 0:083111ae2a11 603 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
saloutos 0:083111ae2a11 604 */
saloutos 0:083111ae2a11 605 __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
saloutos 0:083111ae2a11 606 {
saloutos 0:083111ae2a11 607 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
saloutos 0:083111ae2a11 608 }
saloutos 0:083111ae2a11 609
saloutos 0:083111ae2a11 610
saloutos 0:083111ae2a11 611 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
saloutos 0:083111ae2a11 612 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos 0:083111ae2a11 613 /**
saloutos 0:083111ae2a11 614 \brief Set Process Stack Pointer (non-secure)
saloutos 0:083111ae2a11 615 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
saloutos 0:083111ae2a11 616 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
saloutos 0:083111ae2a11 617 */
saloutos 0:083111ae2a11 618 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
saloutos 0:083111ae2a11 619 {
saloutos 0:083111ae2a11 620 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
saloutos 0:083111ae2a11 621 }
saloutos 0:083111ae2a11 622 #endif
saloutos 0:083111ae2a11 623
saloutos 0:083111ae2a11 624
saloutos 0:083111ae2a11 625 /**
saloutos 0:083111ae2a11 626 \brief Get Main Stack Pointer Limit
saloutos 0:083111ae2a11 627 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
saloutos 0:083111ae2a11 628 \return MSPLIM Register value
saloutos 0:083111ae2a11 629 */
saloutos 0:083111ae2a11 630 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
saloutos 0:083111ae2a11 631 {
saloutos 0:083111ae2a11 632 register uint32_t result;
saloutos 0:083111ae2a11 633
saloutos 0:083111ae2a11 634 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
saloutos 0:083111ae2a11 635
saloutos 0:083111ae2a11 636 return(result);
saloutos 0:083111ae2a11 637 }
saloutos 0:083111ae2a11 638
saloutos 0:083111ae2a11 639
saloutos 0:083111ae2a11 640 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
saloutos 0:083111ae2a11 641 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos 0:083111ae2a11 642 /**
saloutos 0:083111ae2a11 643 \brief Get Main Stack Pointer Limit (non-secure)
saloutos 0:083111ae2a11 644 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
saloutos 0:083111ae2a11 645 \return MSPLIM Register value
saloutos 0:083111ae2a11 646 */
saloutos 0:083111ae2a11 647 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
saloutos 0:083111ae2a11 648 {
saloutos 0:083111ae2a11 649 register uint32_t result;
saloutos 0:083111ae2a11 650
saloutos 0:083111ae2a11 651 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
saloutos 0:083111ae2a11 652 return(result);
saloutos 0:083111ae2a11 653 }
saloutos 0:083111ae2a11 654 #endif
saloutos 0:083111ae2a11 655
saloutos 0:083111ae2a11 656
saloutos 0:083111ae2a11 657 /**
saloutos 0:083111ae2a11 658 \brief Set Main Stack Pointer Limit
saloutos 0:083111ae2a11 659 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
saloutos 0:083111ae2a11 660 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
saloutos 0:083111ae2a11 661 */
saloutos 0:083111ae2a11 662 __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
saloutos 0:083111ae2a11 663 {
saloutos 0:083111ae2a11 664 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
saloutos 0:083111ae2a11 665 }
saloutos 0:083111ae2a11 666
saloutos 0:083111ae2a11 667
saloutos 0:083111ae2a11 668 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
saloutos 0:083111ae2a11 669 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos 0:083111ae2a11 670 /**
saloutos 0:083111ae2a11 671 \brief Set Main Stack Pointer Limit (non-secure)
saloutos 0:083111ae2a11 672 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
saloutos 0:083111ae2a11 673 \param [in] MainStackPtrLimit Main Stack Pointer value to set
saloutos 0:083111ae2a11 674 */
saloutos 0:083111ae2a11 675 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
saloutos 0:083111ae2a11 676 {
saloutos 0:083111ae2a11 677 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
saloutos 0:083111ae2a11 678 }
saloutos 0:083111ae2a11 679 #endif
saloutos 0:083111ae2a11 680
saloutos 0:083111ae2a11 681 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
saloutos 0:083111ae2a11 682 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
saloutos 0:083111ae2a11 683
saloutos 0:083111ae2a11 684
saloutos 0:083111ae2a11 685 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
saloutos 0:083111ae2a11 686 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos 0:083111ae2a11 687
saloutos 0:083111ae2a11 688 /**
saloutos 0:083111ae2a11 689 \brief Get FPSCR
saloutos 0:083111ae2a11 690 \details Returns the current value of the Floating Point Status/Control register.
saloutos 0:083111ae2a11 691 \return Floating Point Status/Control register value
saloutos 0:083111ae2a11 692 */
saloutos 0:083111ae2a11 693 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
saloutos 0:083111ae2a11 694 {
saloutos 0:083111ae2a11 695 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
saloutos 0:083111ae2a11 696 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
saloutos 0:083111ae2a11 697 uint32_t result;
saloutos 0:083111ae2a11 698
saloutos 0:083111ae2a11 699 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
saloutos 0:083111ae2a11 700 return(result);
saloutos 0:083111ae2a11 701 #else
saloutos 0:083111ae2a11 702 return(0U);
saloutos 0:083111ae2a11 703 #endif
saloutos 0:083111ae2a11 704 }
saloutos 0:083111ae2a11 705
saloutos 0:083111ae2a11 706
saloutos 0:083111ae2a11 707 /**
saloutos 0:083111ae2a11 708 \brief Set FPSCR
saloutos 0:083111ae2a11 709 \details Assigns the given value to the Floating Point Status/Control register.
saloutos 0:083111ae2a11 710 \param [in] fpscr Floating Point Status/Control value to set
saloutos 0:083111ae2a11 711 */
saloutos 0:083111ae2a11 712 __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
saloutos 0:083111ae2a11 713 {
saloutos 0:083111ae2a11 714 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
saloutos 0:083111ae2a11 715 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
saloutos 0:083111ae2a11 716 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
saloutos 0:083111ae2a11 717 #else
saloutos 0:083111ae2a11 718 (void)fpscr;
saloutos 0:083111ae2a11 719 #endif
saloutos 0:083111ae2a11 720 }
saloutos 0:083111ae2a11 721
saloutos 0:083111ae2a11 722 #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
saloutos 0:083111ae2a11 723 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
saloutos 0:083111ae2a11 724
saloutos 0:083111ae2a11 725
saloutos 0:083111ae2a11 726
saloutos 0:083111ae2a11 727 /*@} end of CMSIS_Core_RegAccFunctions */
saloutos 0:083111ae2a11 728
saloutos 0:083111ae2a11 729
saloutos 0:083111ae2a11 730 /* ########################## Core Instruction Access ######################### */
saloutos 0:083111ae2a11 731 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
saloutos 0:083111ae2a11 732 Access to dedicated instructions
saloutos 0:083111ae2a11 733 @{
saloutos 0:083111ae2a11 734 */
saloutos 0:083111ae2a11 735
saloutos 0:083111ae2a11 736 /* Define macros for porting to both thumb1 and thumb2.
saloutos 0:083111ae2a11 737 * For thumb1, use low register (r0-r7), specified by constraint "l"
saloutos 0:083111ae2a11 738 * Otherwise, use general registers, specified by constraint "r" */
saloutos 0:083111ae2a11 739 #if defined (__thumb__) && !defined (__thumb2__)
saloutos 0:083111ae2a11 740 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
saloutos 0:083111ae2a11 741 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
saloutos 0:083111ae2a11 742 #define __CMSIS_GCC_USE_REG(r) "l" (r)
saloutos 0:083111ae2a11 743 #else
saloutos 0:083111ae2a11 744 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
saloutos 0:083111ae2a11 745 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
saloutos 0:083111ae2a11 746 #define __CMSIS_GCC_USE_REG(r) "r" (r)
saloutos 0:083111ae2a11 747 #endif
saloutos 0:083111ae2a11 748
saloutos 0:083111ae2a11 749 /**
saloutos 0:083111ae2a11 750 \brief No Operation
saloutos 0:083111ae2a11 751 \details No Operation does nothing. This instruction can be used for code alignment purposes.
saloutos 0:083111ae2a11 752 */
saloutos 0:083111ae2a11 753 //__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
saloutos 0:083111ae2a11 754 //{
saloutos 0:083111ae2a11 755 // __ASM volatile ("nop");
saloutos 0:083111ae2a11 756 //}
saloutos 0:083111ae2a11 757 #define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
saloutos 0:083111ae2a11 758
saloutos 0:083111ae2a11 759 /**
saloutos 0:083111ae2a11 760 \brief Wait For Interrupt
saloutos 0:083111ae2a11 761 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
saloutos 0:083111ae2a11 762 */
saloutos 0:083111ae2a11 763 //__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
saloutos 0:083111ae2a11 764 //{
saloutos 0:083111ae2a11 765 // __ASM volatile ("wfi");
saloutos 0:083111ae2a11 766 //}
saloutos 0:083111ae2a11 767 #define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
saloutos 0:083111ae2a11 768
saloutos 0:083111ae2a11 769
saloutos 0:083111ae2a11 770 /**
saloutos 0:083111ae2a11 771 \brief Wait For Event
saloutos 0:083111ae2a11 772 \details Wait For Event is a hint instruction that permits the processor to enter
saloutos 0:083111ae2a11 773 a low-power state until one of a number of events occurs.
saloutos 0:083111ae2a11 774 */
saloutos 0:083111ae2a11 775 //__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
saloutos 0:083111ae2a11 776 //{
saloutos 0:083111ae2a11 777 // __ASM volatile ("wfe");
saloutos 0:083111ae2a11 778 //}
saloutos 0:083111ae2a11 779 #define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
saloutos 0:083111ae2a11 780
saloutos 0:083111ae2a11 781
saloutos 0:083111ae2a11 782 /**
saloutos 0:083111ae2a11 783 \brief Send Event
saloutos 0:083111ae2a11 784 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
saloutos 0:083111ae2a11 785 */
saloutos 0:083111ae2a11 786 //__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
saloutos 0:083111ae2a11 787 //{
saloutos 0:083111ae2a11 788 // __ASM volatile ("sev");
saloutos 0:083111ae2a11 789 //}
saloutos 0:083111ae2a11 790 #define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
saloutos 0:083111ae2a11 791
saloutos 0:083111ae2a11 792
saloutos 0:083111ae2a11 793 /**
saloutos 0:083111ae2a11 794 \brief Instruction Synchronization Barrier
saloutos 0:083111ae2a11 795 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
saloutos 0:083111ae2a11 796 so that all instructions following the ISB are fetched from cache or memory,
saloutos 0:083111ae2a11 797 after the instruction has been completed.
saloutos 0:083111ae2a11 798 */
saloutos 0:083111ae2a11 799 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
saloutos 0:083111ae2a11 800 {
saloutos 0:083111ae2a11 801 __ASM volatile ("isb 0xF":::"memory");
saloutos 0:083111ae2a11 802 }
saloutos 0:083111ae2a11 803
saloutos 0:083111ae2a11 804
saloutos 0:083111ae2a11 805 /**
saloutos 0:083111ae2a11 806 \brief Data Synchronization Barrier
saloutos 0:083111ae2a11 807 \details Acts as a special kind of Data Memory Barrier.
saloutos 0:083111ae2a11 808 It completes when all explicit memory accesses before this instruction complete.
saloutos 0:083111ae2a11 809 */
saloutos 0:083111ae2a11 810 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
saloutos 0:083111ae2a11 811 {
saloutos 0:083111ae2a11 812 __ASM volatile ("dsb 0xF":::"memory");
saloutos 0:083111ae2a11 813 }
saloutos 0:083111ae2a11 814
saloutos 0:083111ae2a11 815
saloutos 0:083111ae2a11 816 /**
saloutos 0:083111ae2a11 817 \brief Data Memory Barrier
saloutos 0:083111ae2a11 818 \details Ensures the apparent order of the explicit memory operations before
saloutos 0:083111ae2a11 819 and after the instruction, without ensuring their completion.
saloutos 0:083111ae2a11 820 */
saloutos 0:083111ae2a11 821 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
saloutos 0:083111ae2a11 822 {
saloutos 0:083111ae2a11 823 __ASM volatile ("dmb 0xF":::"memory");
saloutos 0:083111ae2a11 824 }
saloutos 0:083111ae2a11 825
saloutos 0:083111ae2a11 826
saloutos 0:083111ae2a11 827 /**
saloutos 0:083111ae2a11 828 \brief Reverse byte order (32 bit)
saloutos 0:083111ae2a11 829 \details Reverses the byte order in integer value.
saloutos 0:083111ae2a11 830 \param [in] value Value to reverse
saloutos 0:083111ae2a11 831 \return Reversed value
saloutos 0:083111ae2a11 832 */
saloutos 0:083111ae2a11 833 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
saloutos 0:083111ae2a11 834 {
saloutos 0:083111ae2a11 835 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
saloutos 0:083111ae2a11 836 return __builtin_bswap32(value);
saloutos 0:083111ae2a11 837 #else
saloutos 0:083111ae2a11 838 uint32_t result;
saloutos 0:083111ae2a11 839
saloutos 0:083111ae2a11 840 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
saloutos 0:083111ae2a11 841 return(result);
saloutos 0:083111ae2a11 842 #endif
saloutos 0:083111ae2a11 843 }
saloutos 0:083111ae2a11 844
saloutos 0:083111ae2a11 845
saloutos 0:083111ae2a11 846 /**
saloutos 0:083111ae2a11 847 \brief Reverse byte order (16 bit)
saloutos 0:083111ae2a11 848 \details Reverses the byte order in two unsigned short values.
saloutos 0:083111ae2a11 849 \param [in] value Value to reverse
saloutos 0:083111ae2a11 850 \return Reversed value
saloutos 0:083111ae2a11 851 */
saloutos 0:083111ae2a11 852 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
saloutos 0:083111ae2a11 853 {
saloutos 0:083111ae2a11 854 uint32_t result;
saloutos 0:083111ae2a11 855
saloutos 0:083111ae2a11 856 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
saloutos 0:083111ae2a11 857 return(result);
saloutos 0:083111ae2a11 858 }
saloutos 0:083111ae2a11 859
saloutos 0:083111ae2a11 860
saloutos 0:083111ae2a11 861 /**
saloutos 0:083111ae2a11 862 \brief Reverse byte order in signed short value
saloutos 0:083111ae2a11 863 \details Reverses the byte order in a signed short value with sign extension to integer.
saloutos 0:083111ae2a11 864 \param [in] value Value to reverse
saloutos 0:083111ae2a11 865 \return Reversed value
saloutos 0:083111ae2a11 866 */
saloutos 0:083111ae2a11 867 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
saloutos 0:083111ae2a11 868 {
saloutos 0:083111ae2a11 869 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
saloutos 0:083111ae2a11 870 return (short)__builtin_bswap16(value);
saloutos 0:083111ae2a11 871 #else
saloutos 0:083111ae2a11 872 int32_t result;
saloutos 0:083111ae2a11 873
saloutos 0:083111ae2a11 874 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
saloutos 0:083111ae2a11 875 return(result);
saloutos 0:083111ae2a11 876 #endif
saloutos 0:083111ae2a11 877 }
saloutos 0:083111ae2a11 878
saloutos 0:083111ae2a11 879
saloutos 0:083111ae2a11 880 /**
saloutos 0:083111ae2a11 881 \brief Rotate Right in unsigned value (32 bit)
saloutos 0:083111ae2a11 882 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
saloutos 0:083111ae2a11 883 \param [in] op1 Value to rotate
saloutos 0:083111ae2a11 884 \param [in] op2 Number of Bits to rotate
saloutos 0:083111ae2a11 885 \return Rotated value
saloutos 0:083111ae2a11 886 */
saloutos 0:083111ae2a11 887 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 888 {
saloutos 0:083111ae2a11 889 return (op1 >> op2) | (op1 << (32U - op2));
saloutos 0:083111ae2a11 890 }
saloutos 0:083111ae2a11 891
saloutos 0:083111ae2a11 892
saloutos 0:083111ae2a11 893 /**
saloutos 0:083111ae2a11 894 \brief Breakpoint
saloutos 0:083111ae2a11 895 \details Causes the processor to enter Debug state.
saloutos 0:083111ae2a11 896 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
saloutos 0:083111ae2a11 897 \param [in] value is ignored by the processor.
saloutos 0:083111ae2a11 898 If required, a debugger can use it to store additional information about the breakpoint.
saloutos 0:083111ae2a11 899 */
saloutos 0:083111ae2a11 900 #define __BKPT(value) __ASM volatile ("bkpt "#value)
saloutos 0:083111ae2a11 901
saloutos 0:083111ae2a11 902
saloutos 0:083111ae2a11 903 /**
saloutos 0:083111ae2a11 904 \brief Reverse bit order of value
saloutos 0:083111ae2a11 905 \details Reverses the bit order of the given value.
saloutos 0:083111ae2a11 906 \param [in] value Value to reverse
saloutos 0:083111ae2a11 907 \return Reversed value
saloutos 0:083111ae2a11 908 */
saloutos 0:083111ae2a11 909 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
saloutos 0:083111ae2a11 910 {
saloutos 0:083111ae2a11 911 uint32_t result;
saloutos 0:083111ae2a11 912
saloutos 0:083111ae2a11 913 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
saloutos 0:083111ae2a11 914 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
saloutos 0:083111ae2a11 915 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos 0:083111ae2a11 916 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
saloutos 0:083111ae2a11 917 #else
saloutos 0:083111ae2a11 918 int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
saloutos 0:083111ae2a11 919
saloutos 0:083111ae2a11 920 result = value; /* r will be reversed bits of v; first get LSB of v */
saloutos 0:083111ae2a11 921 for (value >>= 1U; value; value >>= 1U)
saloutos 0:083111ae2a11 922 {
saloutos 0:083111ae2a11 923 result <<= 1U;
saloutos 0:083111ae2a11 924 result |= value & 1U;
saloutos 0:083111ae2a11 925 s--;
saloutos 0:083111ae2a11 926 }
saloutos 0:083111ae2a11 927 result <<= s; /* shift when v's highest bits are zero */
saloutos 0:083111ae2a11 928 #endif
saloutos 0:083111ae2a11 929 return(result);
saloutos 0:083111ae2a11 930 }
saloutos 0:083111ae2a11 931
saloutos 0:083111ae2a11 932
saloutos 0:083111ae2a11 933 /**
saloutos 0:083111ae2a11 934 \brief Count leading zeros
saloutos 0:083111ae2a11 935 \details Counts the number of leading zeros of a data value.
saloutos 0:083111ae2a11 936 \param [in] value Value to count the leading zeros
saloutos 0:083111ae2a11 937 \return number of leading zeros in value
saloutos 0:083111ae2a11 938 */
saloutos 0:083111ae2a11 939 #define __CLZ __builtin_clz
saloutos 0:083111ae2a11 940
saloutos 0:083111ae2a11 941
saloutos 0:083111ae2a11 942 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
saloutos 0:083111ae2a11 943 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
saloutos 0:083111ae2a11 944 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
saloutos 0:083111ae2a11 945 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
saloutos 0:083111ae2a11 946 /**
saloutos 0:083111ae2a11 947 \brief LDR Exclusive (8 bit)
saloutos 0:083111ae2a11 948 \details Executes a exclusive LDR instruction for 8 bit value.
saloutos 0:083111ae2a11 949 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 950 \return value of type uint8_t at (*ptr)
saloutos 0:083111ae2a11 951 */
saloutos 0:083111ae2a11 952 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
saloutos 0:083111ae2a11 953 {
saloutos 0:083111ae2a11 954 uint32_t result;
saloutos 0:083111ae2a11 955
saloutos 0:083111ae2a11 956 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
saloutos 0:083111ae2a11 957 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
saloutos 0:083111ae2a11 958 #else
saloutos 0:083111ae2a11 959 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
saloutos 0:083111ae2a11 960 accepted by assembler. So has to use following less efficient pattern.
saloutos 0:083111ae2a11 961 */
saloutos 0:083111ae2a11 962 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
saloutos 0:083111ae2a11 963 #endif
saloutos 0:083111ae2a11 964 return ((uint8_t) result); /* Add explicit type cast here */
saloutos 0:083111ae2a11 965 }
saloutos 0:083111ae2a11 966
saloutos 0:083111ae2a11 967
saloutos 0:083111ae2a11 968 /**
saloutos 0:083111ae2a11 969 \brief LDR Exclusive (16 bit)
saloutos 0:083111ae2a11 970 \details Executes a exclusive LDR instruction for 16 bit values.
saloutos 0:083111ae2a11 971 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 972 \return value of type uint16_t at (*ptr)
saloutos 0:083111ae2a11 973 */
saloutos 0:083111ae2a11 974 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
saloutos 0:083111ae2a11 975 {
saloutos 0:083111ae2a11 976 uint32_t result;
saloutos 0:083111ae2a11 977
saloutos 0:083111ae2a11 978 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
saloutos 0:083111ae2a11 979 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
saloutos 0:083111ae2a11 980 #else
saloutos 0:083111ae2a11 981 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
saloutos 0:083111ae2a11 982 accepted by assembler. So has to use following less efficient pattern.
saloutos 0:083111ae2a11 983 */
saloutos 0:083111ae2a11 984 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
saloutos 0:083111ae2a11 985 #endif
saloutos 0:083111ae2a11 986 return ((uint16_t) result); /* Add explicit type cast here */
saloutos 0:083111ae2a11 987 }
saloutos 0:083111ae2a11 988
saloutos 0:083111ae2a11 989
saloutos 0:083111ae2a11 990 /**
saloutos 0:083111ae2a11 991 \brief LDR Exclusive (32 bit)
saloutos 0:083111ae2a11 992 \details Executes a exclusive LDR instruction for 32 bit values.
saloutos 0:083111ae2a11 993 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 994 \return value of type uint32_t at (*ptr)
saloutos 0:083111ae2a11 995 */
saloutos 0:083111ae2a11 996 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
saloutos 0:083111ae2a11 997 {
saloutos 0:083111ae2a11 998 uint32_t result;
saloutos 0:083111ae2a11 999
saloutos 0:083111ae2a11 1000 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
saloutos 0:083111ae2a11 1001 return(result);
saloutos 0:083111ae2a11 1002 }
saloutos 0:083111ae2a11 1003
saloutos 0:083111ae2a11 1004
saloutos 0:083111ae2a11 1005 /**
saloutos 0:083111ae2a11 1006 \brief STR Exclusive (8 bit)
saloutos 0:083111ae2a11 1007 \details Executes a exclusive STR instruction for 8 bit values.
saloutos 0:083111ae2a11 1008 \param [in] value Value to store
saloutos 0:083111ae2a11 1009 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 1010 \return 0 Function succeeded
saloutos 0:083111ae2a11 1011 \return 1 Function failed
saloutos 0:083111ae2a11 1012 */
saloutos 0:083111ae2a11 1013 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
saloutos 0:083111ae2a11 1014 {
saloutos 0:083111ae2a11 1015 uint32_t result;
saloutos 0:083111ae2a11 1016
saloutos 0:083111ae2a11 1017 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
saloutos 0:083111ae2a11 1018 return(result);
saloutos 0:083111ae2a11 1019 }
saloutos 0:083111ae2a11 1020
saloutos 0:083111ae2a11 1021
saloutos 0:083111ae2a11 1022 /**
saloutos 0:083111ae2a11 1023 \brief STR Exclusive (16 bit)
saloutos 0:083111ae2a11 1024 \details Executes a exclusive STR instruction for 16 bit values.
saloutos 0:083111ae2a11 1025 \param [in] value Value to store
saloutos 0:083111ae2a11 1026 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 1027 \return 0 Function succeeded
saloutos 0:083111ae2a11 1028 \return 1 Function failed
saloutos 0:083111ae2a11 1029 */
saloutos 0:083111ae2a11 1030 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
saloutos 0:083111ae2a11 1031 {
saloutos 0:083111ae2a11 1032 uint32_t result;
saloutos 0:083111ae2a11 1033
saloutos 0:083111ae2a11 1034 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
saloutos 0:083111ae2a11 1035 return(result);
saloutos 0:083111ae2a11 1036 }
saloutos 0:083111ae2a11 1037
saloutos 0:083111ae2a11 1038
saloutos 0:083111ae2a11 1039 /**
saloutos 0:083111ae2a11 1040 \brief STR Exclusive (32 bit)
saloutos 0:083111ae2a11 1041 \details Executes a exclusive STR instruction for 32 bit values.
saloutos 0:083111ae2a11 1042 \param [in] value Value to store
saloutos 0:083111ae2a11 1043 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 1044 \return 0 Function succeeded
saloutos 0:083111ae2a11 1045 \return 1 Function failed
saloutos 0:083111ae2a11 1046 */
saloutos 0:083111ae2a11 1047 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
saloutos 0:083111ae2a11 1048 {
saloutos 0:083111ae2a11 1049 uint32_t result;
saloutos 0:083111ae2a11 1050
saloutos 0:083111ae2a11 1051 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
saloutos 0:083111ae2a11 1052 return(result);
saloutos 0:083111ae2a11 1053 }
saloutos 0:083111ae2a11 1054
saloutos 0:083111ae2a11 1055
saloutos 0:083111ae2a11 1056 /**
saloutos 0:083111ae2a11 1057 \brief Remove the exclusive lock
saloutos 0:083111ae2a11 1058 \details Removes the exclusive lock which is created by LDREX.
saloutos 0:083111ae2a11 1059 */
saloutos 0:083111ae2a11 1060 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
saloutos 0:083111ae2a11 1061 {
saloutos 0:083111ae2a11 1062 __ASM volatile ("clrex" ::: "memory");
saloutos 0:083111ae2a11 1063 }
saloutos 0:083111ae2a11 1064
saloutos 0:083111ae2a11 1065 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
saloutos 0:083111ae2a11 1066 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
saloutos 0:083111ae2a11 1067 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
saloutos 0:083111ae2a11 1068 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
saloutos 0:083111ae2a11 1069
saloutos 0:083111ae2a11 1070
saloutos 0:083111ae2a11 1071 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
saloutos 0:083111ae2a11 1072 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
saloutos 0:083111ae2a11 1073 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos 0:083111ae2a11 1074 /**
saloutos 0:083111ae2a11 1075 \brief Signed Saturate
saloutos 0:083111ae2a11 1076 \details Saturates a signed value.
saloutos 0:083111ae2a11 1077 \param [in] value Value to be saturated
saloutos 0:083111ae2a11 1078 \param [in] sat Bit position to saturate to (1..32)
saloutos 0:083111ae2a11 1079 \return Saturated value
saloutos 0:083111ae2a11 1080 */
saloutos 0:083111ae2a11 1081 #define __SSAT(ARG1,ARG2) \
saloutos 0:083111ae2a11 1082 ({ \
saloutos 0:083111ae2a11 1083 int32_t __RES, __ARG1 = (ARG1); \
saloutos 0:083111ae2a11 1084 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
saloutos 0:083111ae2a11 1085 __RES; \
saloutos 0:083111ae2a11 1086 })
saloutos 0:083111ae2a11 1087
saloutos 0:083111ae2a11 1088
saloutos 0:083111ae2a11 1089 /**
saloutos 0:083111ae2a11 1090 \brief Unsigned Saturate
saloutos 0:083111ae2a11 1091 \details Saturates an unsigned value.
saloutos 0:083111ae2a11 1092 \param [in] value Value to be saturated
saloutos 0:083111ae2a11 1093 \param [in] sat Bit position to saturate to (0..31)
saloutos 0:083111ae2a11 1094 \return Saturated value
saloutos 0:083111ae2a11 1095 */
saloutos 0:083111ae2a11 1096 #define __USAT(ARG1,ARG2) \
saloutos 0:083111ae2a11 1097 ({ \
saloutos 0:083111ae2a11 1098 uint32_t __RES, __ARG1 = (ARG1); \
saloutos 0:083111ae2a11 1099 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
saloutos 0:083111ae2a11 1100 __RES; \
saloutos 0:083111ae2a11 1101 })
saloutos 0:083111ae2a11 1102
saloutos 0:083111ae2a11 1103
saloutos 0:083111ae2a11 1104 /**
saloutos 0:083111ae2a11 1105 \brief Rotate Right with Extend (32 bit)
saloutos 0:083111ae2a11 1106 \details Moves each bit of a bitstring right by one bit.
saloutos 0:083111ae2a11 1107 The carry input is shifted in at the left end of the bitstring.
saloutos 0:083111ae2a11 1108 \param [in] value Value to rotate
saloutos 0:083111ae2a11 1109 \return Rotated value
saloutos 0:083111ae2a11 1110 */
saloutos 0:083111ae2a11 1111 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
saloutos 0:083111ae2a11 1112 {
saloutos 0:083111ae2a11 1113 uint32_t result;
saloutos 0:083111ae2a11 1114
saloutos 0:083111ae2a11 1115 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
saloutos 0:083111ae2a11 1116 return(result);
saloutos 0:083111ae2a11 1117 }
saloutos 0:083111ae2a11 1118
saloutos 0:083111ae2a11 1119
saloutos 0:083111ae2a11 1120 /**
saloutos 0:083111ae2a11 1121 \brief LDRT Unprivileged (8 bit)
saloutos 0:083111ae2a11 1122 \details Executes a Unprivileged LDRT instruction for 8 bit value.
saloutos 0:083111ae2a11 1123 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 1124 \return value of type uint8_t at (*ptr)
saloutos 0:083111ae2a11 1125 */
saloutos 0:083111ae2a11 1126 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
saloutos 0:083111ae2a11 1127 {
saloutos 0:083111ae2a11 1128 uint32_t result;
saloutos 0:083111ae2a11 1129
saloutos 0:083111ae2a11 1130 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
saloutos 0:083111ae2a11 1131 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos 0:083111ae2a11 1132 #else
saloutos 0:083111ae2a11 1133 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
saloutos 0:083111ae2a11 1134 accepted by assembler. So has to use following less efficient pattern.
saloutos 0:083111ae2a11 1135 */
saloutos 0:083111ae2a11 1136 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
saloutos 0:083111ae2a11 1137 #endif
saloutos 0:083111ae2a11 1138 return ((uint8_t) result); /* Add explicit type cast here */
saloutos 0:083111ae2a11 1139 }
saloutos 0:083111ae2a11 1140
saloutos 0:083111ae2a11 1141
saloutos 0:083111ae2a11 1142 /**
saloutos 0:083111ae2a11 1143 \brief LDRT Unprivileged (16 bit)
saloutos 0:083111ae2a11 1144 \details Executes a Unprivileged LDRT instruction for 16 bit values.
saloutos 0:083111ae2a11 1145 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 1146 \return value of type uint16_t at (*ptr)
saloutos 0:083111ae2a11 1147 */
saloutos 0:083111ae2a11 1148 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
saloutos 0:083111ae2a11 1149 {
saloutos 0:083111ae2a11 1150 uint32_t result;
saloutos 0:083111ae2a11 1151
saloutos 0:083111ae2a11 1152 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
saloutos 0:083111ae2a11 1153 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos 0:083111ae2a11 1154 #else
saloutos 0:083111ae2a11 1155 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
saloutos 0:083111ae2a11 1156 accepted by assembler. So has to use following less efficient pattern.
saloutos 0:083111ae2a11 1157 */
saloutos 0:083111ae2a11 1158 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
saloutos 0:083111ae2a11 1159 #endif
saloutos 0:083111ae2a11 1160 return ((uint16_t) result); /* Add explicit type cast here */
saloutos 0:083111ae2a11 1161 }
saloutos 0:083111ae2a11 1162
saloutos 0:083111ae2a11 1163
saloutos 0:083111ae2a11 1164 /**
saloutos 0:083111ae2a11 1165 \brief LDRT Unprivileged (32 bit)
saloutos 0:083111ae2a11 1166 \details Executes a Unprivileged LDRT instruction for 32 bit values.
saloutos 0:083111ae2a11 1167 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 1168 \return value of type uint32_t at (*ptr)
saloutos 0:083111ae2a11 1169 */
saloutos 0:083111ae2a11 1170 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
saloutos 0:083111ae2a11 1171 {
saloutos 0:083111ae2a11 1172 uint32_t result;
saloutos 0:083111ae2a11 1173
saloutos 0:083111ae2a11 1174 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos 0:083111ae2a11 1175 return(result);
saloutos 0:083111ae2a11 1176 }
saloutos 0:083111ae2a11 1177
saloutos 0:083111ae2a11 1178
saloutos 0:083111ae2a11 1179 /**
saloutos 0:083111ae2a11 1180 \brief STRT Unprivileged (8 bit)
saloutos 0:083111ae2a11 1181 \details Executes a Unprivileged STRT instruction for 8 bit values.
saloutos 0:083111ae2a11 1182 \param [in] value Value to store
saloutos 0:083111ae2a11 1183 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 1184 */
saloutos 0:083111ae2a11 1185 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
saloutos 0:083111ae2a11 1186 {
saloutos 0:083111ae2a11 1187 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
saloutos 0:083111ae2a11 1188 }
saloutos 0:083111ae2a11 1189
saloutos 0:083111ae2a11 1190
saloutos 0:083111ae2a11 1191 /**
saloutos 0:083111ae2a11 1192 \brief STRT Unprivileged (16 bit)
saloutos 0:083111ae2a11 1193 \details Executes a Unprivileged STRT instruction for 16 bit values.
saloutos 0:083111ae2a11 1194 \param [in] value Value to store
saloutos 0:083111ae2a11 1195 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 1196 */
saloutos 0:083111ae2a11 1197 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
saloutos 0:083111ae2a11 1198 {
saloutos 0:083111ae2a11 1199 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
saloutos 0:083111ae2a11 1200 }
saloutos 0:083111ae2a11 1201
saloutos 0:083111ae2a11 1202
saloutos 0:083111ae2a11 1203 /**
saloutos 0:083111ae2a11 1204 \brief STRT Unprivileged (32 bit)
saloutos 0:083111ae2a11 1205 \details Executes a Unprivileged STRT instruction for 32 bit values.
saloutos 0:083111ae2a11 1206 \param [in] value Value to store
saloutos 0:083111ae2a11 1207 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 1208 */
saloutos 0:083111ae2a11 1209 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
saloutos 0:083111ae2a11 1210 {
saloutos 0:083111ae2a11 1211 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
saloutos 0:083111ae2a11 1212 }
saloutos 0:083111ae2a11 1213
saloutos 0:083111ae2a11 1214 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
saloutos 0:083111ae2a11 1215 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
saloutos 0:083111ae2a11 1216 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
saloutos 0:083111ae2a11 1217
saloutos 0:083111ae2a11 1218
saloutos 0:083111ae2a11 1219 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
saloutos 0:083111ae2a11 1220 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
saloutos 0:083111ae2a11 1221 /**
saloutos 0:083111ae2a11 1222 \brief Load-Acquire (8 bit)
saloutos 0:083111ae2a11 1223 \details Executes a LDAB instruction for 8 bit value.
saloutos 0:083111ae2a11 1224 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 1225 \return value of type uint8_t at (*ptr)
saloutos 0:083111ae2a11 1226 */
saloutos 0:083111ae2a11 1227 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
saloutos 0:083111ae2a11 1228 {
saloutos 0:083111ae2a11 1229 uint32_t result;
saloutos 0:083111ae2a11 1230
saloutos 0:083111ae2a11 1231 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos 0:083111ae2a11 1232 return ((uint8_t) result);
saloutos 0:083111ae2a11 1233 }
saloutos 0:083111ae2a11 1234
saloutos 0:083111ae2a11 1235
saloutos 0:083111ae2a11 1236 /**
saloutos 0:083111ae2a11 1237 \brief Load-Acquire (16 bit)
saloutos 0:083111ae2a11 1238 \details Executes a LDAH instruction for 16 bit values.
saloutos 0:083111ae2a11 1239 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 1240 \return value of type uint16_t at (*ptr)
saloutos 0:083111ae2a11 1241 */
saloutos 0:083111ae2a11 1242 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
saloutos 0:083111ae2a11 1243 {
saloutos 0:083111ae2a11 1244 uint32_t result;
saloutos 0:083111ae2a11 1245
saloutos 0:083111ae2a11 1246 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos 0:083111ae2a11 1247 return ((uint16_t) result);
saloutos 0:083111ae2a11 1248 }
saloutos 0:083111ae2a11 1249
saloutos 0:083111ae2a11 1250
saloutos 0:083111ae2a11 1251 /**
saloutos 0:083111ae2a11 1252 \brief Load-Acquire (32 bit)
saloutos 0:083111ae2a11 1253 \details Executes a LDA instruction for 32 bit values.
saloutos 0:083111ae2a11 1254 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 1255 \return value of type uint32_t at (*ptr)
saloutos 0:083111ae2a11 1256 */
saloutos 0:083111ae2a11 1257 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
saloutos 0:083111ae2a11 1258 {
saloutos 0:083111ae2a11 1259 uint32_t result;
saloutos 0:083111ae2a11 1260
saloutos 0:083111ae2a11 1261 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos 0:083111ae2a11 1262 return(result);
saloutos 0:083111ae2a11 1263 }
saloutos 0:083111ae2a11 1264
saloutos 0:083111ae2a11 1265
saloutos 0:083111ae2a11 1266 /**
saloutos 0:083111ae2a11 1267 \brief Store-Release (8 bit)
saloutos 0:083111ae2a11 1268 \details Executes a STLB instruction for 8 bit values.
saloutos 0:083111ae2a11 1269 \param [in] value Value to store
saloutos 0:083111ae2a11 1270 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 1271 */
saloutos 0:083111ae2a11 1272 __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
saloutos 0:083111ae2a11 1273 {
saloutos 0:083111ae2a11 1274 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
saloutos 0:083111ae2a11 1275 }
saloutos 0:083111ae2a11 1276
saloutos 0:083111ae2a11 1277
saloutos 0:083111ae2a11 1278 /**
saloutos 0:083111ae2a11 1279 \brief Store-Release (16 bit)
saloutos 0:083111ae2a11 1280 \details Executes a STLH instruction for 16 bit values.
saloutos 0:083111ae2a11 1281 \param [in] value Value to store
saloutos 0:083111ae2a11 1282 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 1283 */
saloutos 0:083111ae2a11 1284 __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
saloutos 0:083111ae2a11 1285 {
saloutos 0:083111ae2a11 1286 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
saloutos 0:083111ae2a11 1287 }
saloutos 0:083111ae2a11 1288
saloutos 0:083111ae2a11 1289
saloutos 0:083111ae2a11 1290 /**
saloutos 0:083111ae2a11 1291 \brief Store-Release (32 bit)
saloutos 0:083111ae2a11 1292 \details Executes a STL instruction for 32 bit values.
saloutos 0:083111ae2a11 1293 \param [in] value Value to store
saloutos 0:083111ae2a11 1294 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 1295 */
saloutos 0:083111ae2a11 1296 __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
saloutos 0:083111ae2a11 1297 {
saloutos 0:083111ae2a11 1298 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
saloutos 0:083111ae2a11 1299 }
saloutos 0:083111ae2a11 1300
saloutos 0:083111ae2a11 1301
saloutos 0:083111ae2a11 1302 /**
saloutos 0:083111ae2a11 1303 \brief Load-Acquire Exclusive (8 bit)
saloutos 0:083111ae2a11 1304 \details Executes a LDAB exclusive instruction for 8 bit value.
saloutos 0:083111ae2a11 1305 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 1306 \return value of type uint8_t at (*ptr)
saloutos 0:083111ae2a11 1307 */
saloutos 0:083111ae2a11 1308 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
saloutos 0:083111ae2a11 1309 {
saloutos 0:083111ae2a11 1310 uint32_t result;
saloutos 0:083111ae2a11 1311
saloutos 0:083111ae2a11 1312 __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos 0:083111ae2a11 1313 return ((uint8_t) result);
saloutos 0:083111ae2a11 1314 }
saloutos 0:083111ae2a11 1315
saloutos 0:083111ae2a11 1316
saloutos 0:083111ae2a11 1317 /**
saloutos 0:083111ae2a11 1318 \brief Load-Acquire Exclusive (16 bit)
saloutos 0:083111ae2a11 1319 \details Executes a LDAH exclusive instruction for 16 bit values.
saloutos 0:083111ae2a11 1320 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 1321 \return value of type uint16_t at (*ptr)
saloutos 0:083111ae2a11 1322 */
saloutos 0:083111ae2a11 1323 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
saloutos 0:083111ae2a11 1324 {
saloutos 0:083111ae2a11 1325 uint32_t result;
saloutos 0:083111ae2a11 1326
saloutos 0:083111ae2a11 1327 __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos 0:083111ae2a11 1328 return ((uint16_t) result);
saloutos 0:083111ae2a11 1329 }
saloutos 0:083111ae2a11 1330
saloutos 0:083111ae2a11 1331
saloutos 0:083111ae2a11 1332 /**
saloutos 0:083111ae2a11 1333 \brief Load-Acquire Exclusive (32 bit)
saloutos 0:083111ae2a11 1334 \details Executes a LDA exclusive instruction for 32 bit values.
saloutos 0:083111ae2a11 1335 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 1336 \return value of type uint32_t at (*ptr)
saloutos 0:083111ae2a11 1337 */
saloutos 0:083111ae2a11 1338 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
saloutos 0:083111ae2a11 1339 {
saloutos 0:083111ae2a11 1340 uint32_t result;
saloutos 0:083111ae2a11 1341
saloutos 0:083111ae2a11 1342 __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos 0:083111ae2a11 1343 return(result);
saloutos 0:083111ae2a11 1344 }
saloutos 0:083111ae2a11 1345
saloutos 0:083111ae2a11 1346
saloutos 0:083111ae2a11 1347 /**
saloutos 0:083111ae2a11 1348 \brief Store-Release Exclusive (8 bit)
saloutos 0:083111ae2a11 1349 \details Executes a STLB exclusive instruction for 8 bit values.
saloutos 0:083111ae2a11 1350 \param [in] value Value to store
saloutos 0:083111ae2a11 1351 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 1352 \return 0 Function succeeded
saloutos 0:083111ae2a11 1353 \return 1 Function failed
saloutos 0:083111ae2a11 1354 */
saloutos 0:083111ae2a11 1355 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
saloutos 0:083111ae2a11 1356 {
saloutos 0:083111ae2a11 1357 uint32_t result;
saloutos 0:083111ae2a11 1358
saloutos 0:083111ae2a11 1359 __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
saloutos 0:083111ae2a11 1360 return(result);
saloutos 0:083111ae2a11 1361 }
saloutos 0:083111ae2a11 1362
saloutos 0:083111ae2a11 1363
saloutos 0:083111ae2a11 1364 /**
saloutos 0:083111ae2a11 1365 \brief Store-Release Exclusive (16 bit)
saloutos 0:083111ae2a11 1366 \details Executes a STLH exclusive instruction for 16 bit values.
saloutos 0:083111ae2a11 1367 \param [in] value Value to store
saloutos 0:083111ae2a11 1368 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 1369 \return 0 Function succeeded
saloutos 0:083111ae2a11 1370 \return 1 Function failed
saloutos 0:083111ae2a11 1371 */
saloutos 0:083111ae2a11 1372 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
saloutos 0:083111ae2a11 1373 {
saloutos 0:083111ae2a11 1374 uint32_t result;
saloutos 0:083111ae2a11 1375
saloutos 0:083111ae2a11 1376 __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
saloutos 0:083111ae2a11 1377 return(result);
saloutos 0:083111ae2a11 1378 }
saloutos 0:083111ae2a11 1379
saloutos 0:083111ae2a11 1380
saloutos 0:083111ae2a11 1381 /**
saloutos 0:083111ae2a11 1382 \brief Store-Release Exclusive (32 bit)
saloutos 0:083111ae2a11 1383 \details Executes a STL exclusive instruction for 32 bit values.
saloutos 0:083111ae2a11 1384 \param [in] value Value to store
saloutos 0:083111ae2a11 1385 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 1386 \return 0 Function succeeded
saloutos 0:083111ae2a11 1387 \return 1 Function failed
saloutos 0:083111ae2a11 1388 */
saloutos 0:083111ae2a11 1389 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
saloutos 0:083111ae2a11 1390 {
saloutos 0:083111ae2a11 1391 uint32_t result;
saloutos 0:083111ae2a11 1392
saloutos 0:083111ae2a11 1393 __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
saloutos 0:083111ae2a11 1394 return(result);
saloutos 0:083111ae2a11 1395 }
saloutos 0:083111ae2a11 1396
saloutos 0:083111ae2a11 1397 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
saloutos 0:083111ae2a11 1398 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
saloutos 0:083111ae2a11 1399
saloutos 0:083111ae2a11 1400 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
saloutos 0:083111ae2a11 1401
saloutos 0:083111ae2a11 1402
saloutos 0:083111ae2a11 1403 /* ################### Compiler specific Intrinsics ########################### */
saloutos 0:083111ae2a11 1404 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
saloutos 0:083111ae2a11 1405 Access to dedicated SIMD instructions
saloutos 0:083111ae2a11 1406 @{
saloutos 0:083111ae2a11 1407 */
saloutos 0:083111ae2a11 1408
saloutos 0:083111ae2a11 1409 #if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
saloutos 0:083111ae2a11 1410
saloutos 0:083111ae2a11 1411 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1412 {
saloutos 0:083111ae2a11 1413 uint32_t result;
saloutos 0:083111ae2a11 1414
saloutos 0:083111ae2a11 1415 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1416 return(result);
saloutos 0:083111ae2a11 1417 }
saloutos 0:083111ae2a11 1418
saloutos 0:083111ae2a11 1419 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1420 {
saloutos 0:083111ae2a11 1421 uint32_t result;
saloutos 0:083111ae2a11 1422
saloutos 0:083111ae2a11 1423 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1424 return(result);
saloutos 0:083111ae2a11 1425 }
saloutos 0:083111ae2a11 1426
saloutos 0:083111ae2a11 1427 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1428 {
saloutos 0:083111ae2a11 1429 uint32_t result;
saloutos 0:083111ae2a11 1430
saloutos 0:083111ae2a11 1431 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1432 return(result);
saloutos 0:083111ae2a11 1433 }
saloutos 0:083111ae2a11 1434
saloutos 0:083111ae2a11 1435 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1436 {
saloutos 0:083111ae2a11 1437 uint32_t result;
saloutos 0:083111ae2a11 1438
saloutos 0:083111ae2a11 1439 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1440 return(result);
saloutos 0:083111ae2a11 1441 }
saloutos 0:083111ae2a11 1442
saloutos 0:083111ae2a11 1443 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1444 {
saloutos 0:083111ae2a11 1445 uint32_t result;
saloutos 0:083111ae2a11 1446
saloutos 0:083111ae2a11 1447 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1448 return(result);
saloutos 0:083111ae2a11 1449 }
saloutos 0:083111ae2a11 1450
saloutos 0:083111ae2a11 1451 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1452 {
saloutos 0:083111ae2a11 1453 uint32_t result;
saloutos 0:083111ae2a11 1454
saloutos 0:083111ae2a11 1455 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1456 return(result);
saloutos 0:083111ae2a11 1457 }
saloutos 0:083111ae2a11 1458
saloutos 0:083111ae2a11 1459
saloutos 0:083111ae2a11 1460 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1461 {
saloutos 0:083111ae2a11 1462 uint32_t result;
saloutos 0:083111ae2a11 1463
saloutos 0:083111ae2a11 1464 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1465 return(result);
saloutos 0:083111ae2a11 1466 }
saloutos 0:083111ae2a11 1467
saloutos 0:083111ae2a11 1468 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1469 {
saloutos 0:083111ae2a11 1470 uint32_t result;
saloutos 0:083111ae2a11 1471
saloutos 0:083111ae2a11 1472 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1473 return(result);
saloutos 0:083111ae2a11 1474 }
saloutos 0:083111ae2a11 1475
saloutos 0:083111ae2a11 1476 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1477 {
saloutos 0:083111ae2a11 1478 uint32_t result;
saloutos 0:083111ae2a11 1479
saloutos 0:083111ae2a11 1480 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1481 return(result);
saloutos 0:083111ae2a11 1482 }
saloutos 0:083111ae2a11 1483
saloutos 0:083111ae2a11 1484 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1485 {
saloutos 0:083111ae2a11 1486 uint32_t result;
saloutos 0:083111ae2a11 1487
saloutos 0:083111ae2a11 1488 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1489 return(result);
saloutos 0:083111ae2a11 1490 }
saloutos 0:083111ae2a11 1491
saloutos 0:083111ae2a11 1492 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1493 {
saloutos 0:083111ae2a11 1494 uint32_t result;
saloutos 0:083111ae2a11 1495
saloutos 0:083111ae2a11 1496 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1497 return(result);
saloutos 0:083111ae2a11 1498 }
saloutos 0:083111ae2a11 1499
saloutos 0:083111ae2a11 1500 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1501 {
saloutos 0:083111ae2a11 1502 uint32_t result;
saloutos 0:083111ae2a11 1503
saloutos 0:083111ae2a11 1504 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1505 return(result);
saloutos 0:083111ae2a11 1506 }
saloutos 0:083111ae2a11 1507
saloutos 0:083111ae2a11 1508
saloutos 0:083111ae2a11 1509 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1510 {
saloutos 0:083111ae2a11 1511 uint32_t result;
saloutos 0:083111ae2a11 1512
saloutos 0:083111ae2a11 1513 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1514 return(result);
saloutos 0:083111ae2a11 1515 }
saloutos 0:083111ae2a11 1516
saloutos 0:083111ae2a11 1517 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1518 {
saloutos 0:083111ae2a11 1519 uint32_t result;
saloutos 0:083111ae2a11 1520
saloutos 0:083111ae2a11 1521 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1522 return(result);
saloutos 0:083111ae2a11 1523 }
saloutos 0:083111ae2a11 1524
saloutos 0:083111ae2a11 1525 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1526 {
saloutos 0:083111ae2a11 1527 uint32_t result;
saloutos 0:083111ae2a11 1528
saloutos 0:083111ae2a11 1529 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1530 return(result);
saloutos 0:083111ae2a11 1531 }
saloutos 0:083111ae2a11 1532
saloutos 0:083111ae2a11 1533 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1534 {
saloutos 0:083111ae2a11 1535 uint32_t result;
saloutos 0:083111ae2a11 1536
saloutos 0:083111ae2a11 1537 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1538 return(result);
saloutos 0:083111ae2a11 1539 }
saloutos 0:083111ae2a11 1540
saloutos 0:083111ae2a11 1541 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1542 {
saloutos 0:083111ae2a11 1543 uint32_t result;
saloutos 0:083111ae2a11 1544
saloutos 0:083111ae2a11 1545 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1546 return(result);
saloutos 0:083111ae2a11 1547 }
saloutos 0:083111ae2a11 1548
saloutos 0:083111ae2a11 1549 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1550 {
saloutos 0:083111ae2a11 1551 uint32_t result;
saloutos 0:083111ae2a11 1552
saloutos 0:083111ae2a11 1553 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1554 return(result);
saloutos 0:083111ae2a11 1555 }
saloutos 0:083111ae2a11 1556
saloutos 0:083111ae2a11 1557 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1558 {
saloutos 0:083111ae2a11 1559 uint32_t result;
saloutos 0:083111ae2a11 1560
saloutos 0:083111ae2a11 1561 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1562 return(result);
saloutos 0:083111ae2a11 1563 }
saloutos 0:083111ae2a11 1564
saloutos 0:083111ae2a11 1565 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1566 {
saloutos 0:083111ae2a11 1567 uint32_t result;
saloutos 0:083111ae2a11 1568
saloutos 0:083111ae2a11 1569 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1570 return(result);
saloutos 0:083111ae2a11 1571 }
saloutos 0:083111ae2a11 1572
saloutos 0:083111ae2a11 1573 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1574 {
saloutos 0:083111ae2a11 1575 uint32_t result;
saloutos 0:083111ae2a11 1576
saloutos 0:083111ae2a11 1577 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1578 return(result);
saloutos 0:083111ae2a11 1579 }
saloutos 0:083111ae2a11 1580
saloutos 0:083111ae2a11 1581 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1582 {
saloutos 0:083111ae2a11 1583 uint32_t result;
saloutos 0:083111ae2a11 1584
saloutos 0:083111ae2a11 1585 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1586 return(result);
saloutos 0:083111ae2a11 1587 }
saloutos 0:083111ae2a11 1588
saloutos 0:083111ae2a11 1589 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1590 {
saloutos 0:083111ae2a11 1591 uint32_t result;
saloutos 0:083111ae2a11 1592
saloutos 0:083111ae2a11 1593 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1594 return(result);
saloutos 0:083111ae2a11 1595 }
saloutos 0:083111ae2a11 1596
saloutos 0:083111ae2a11 1597 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1598 {
saloutos 0:083111ae2a11 1599 uint32_t result;
saloutos 0:083111ae2a11 1600
saloutos 0:083111ae2a11 1601 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1602 return(result);
saloutos 0:083111ae2a11 1603 }
saloutos 0:083111ae2a11 1604
saloutos 0:083111ae2a11 1605 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1606 {
saloutos 0:083111ae2a11 1607 uint32_t result;
saloutos 0:083111ae2a11 1608
saloutos 0:083111ae2a11 1609 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1610 return(result);
saloutos 0:083111ae2a11 1611 }
saloutos 0:083111ae2a11 1612
saloutos 0:083111ae2a11 1613 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1614 {
saloutos 0:083111ae2a11 1615 uint32_t result;
saloutos 0:083111ae2a11 1616
saloutos 0:083111ae2a11 1617 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1618 return(result);
saloutos 0:083111ae2a11 1619 }
saloutos 0:083111ae2a11 1620
saloutos 0:083111ae2a11 1621 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1622 {
saloutos 0:083111ae2a11 1623 uint32_t result;
saloutos 0:083111ae2a11 1624
saloutos 0:083111ae2a11 1625 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1626 return(result);
saloutos 0:083111ae2a11 1627 }
saloutos 0:083111ae2a11 1628
saloutos 0:083111ae2a11 1629 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1630 {
saloutos 0:083111ae2a11 1631 uint32_t result;
saloutos 0:083111ae2a11 1632
saloutos 0:083111ae2a11 1633 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1634 return(result);
saloutos 0:083111ae2a11 1635 }
saloutos 0:083111ae2a11 1636
saloutos 0:083111ae2a11 1637 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1638 {
saloutos 0:083111ae2a11 1639 uint32_t result;
saloutos 0:083111ae2a11 1640
saloutos 0:083111ae2a11 1641 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1642 return(result);
saloutos 0:083111ae2a11 1643 }
saloutos 0:083111ae2a11 1644
saloutos 0:083111ae2a11 1645 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1646 {
saloutos 0:083111ae2a11 1647 uint32_t result;
saloutos 0:083111ae2a11 1648
saloutos 0:083111ae2a11 1649 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1650 return(result);
saloutos 0:083111ae2a11 1651 }
saloutos 0:083111ae2a11 1652
saloutos 0:083111ae2a11 1653 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1654 {
saloutos 0:083111ae2a11 1655 uint32_t result;
saloutos 0:083111ae2a11 1656
saloutos 0:083111ae2a11 1657 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1658 return(result);
saloutos 0:083111ae2a11 1659 }
saloutos 0:083111ae2a11 1660
saloutos 0:083111ae2a11 1661 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1662 {
saloutos 0:083111ae2a11 1663 uint32_t result;
saloutos 0:083111ae2a11 1664
saloutos 0:083111ae2a11 1665 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1666 return(result);
saloutos 0:083111ae2a11 1667 }
saloutos 0:083111ae2a11 1668
saloutos 0:083111ae2a11 1669 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1670 {
saloutos 0:083111ae2a11 1671 uint32_t result;
saloutos 0:083111ae2a11 1672
saloutos 0:083111ae2a11 1673 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1674 return(result);
saloutos 0:083111ae2a11 1675 }
saloutos 0:083111ae2a11 1676
saloutos 0:083111ae2a11 1677 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1678 {
saloutos 0:083111ae2a11 1679 uint32_t result;
saloutos 0:083111ae2a11 1680
saloutos 0:083111ae2a11 1681 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1682 return(result);
saloutos 0:083111ae2a11 1683 }
saloutos 0:083111ae2a11 1684
saloutos 0:083111ae2a11 1685 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1686 {
saloutos 0:083111ae2a11 1687 uint32_t result;
saloutos 0:083111ae2a11 1688
saloutos 0:083111ae2a11 1689 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1690 return(result);
saloutos 0:083111ae2a11 1691 }
saloutos 0:083111ae2a11 1692
saloutos 0:083111ae2a11 1693 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1694 {
saloutos 0:083111ae2a11 1695 uint32_t result;
saloutos 0:083111ae2a11 1696
saloutos 0:083111ae2a11 1697 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1698 return(result);
saloutos 0:083111ae2a11 1699 }
saloutos 0:083111ae2a11 1700
saloutos 0:083111ae2a11 1701 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1702 {
saloutos 0:083111ae2a11 1703 uint32_t result;
saloutos 0:083111ae2a11 1704
saloutos 0:083111ae2a11 1705 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1706 return(result);
saloutos 0:083111ae2a11 1707 }
saloutos 0:083111ae2a11 1708
saloutos 0:083111ae2a11 1709 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
saloutos 0:083111ae2a11 1710 {
saloutos 0:083111ae2a11 1711 uint32_t result;
saloutos 0:083111ae2a11 1712
saloutos 0:083111ae2a11 1713 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
saloutos 0:083111ae2a11 1714 return(result);
saloutos 0:083111ae2a11 1715 }
saloutos 0:083111ae2a11 1716
saloutos 0:083111ae2a11 1717 #define __SSAT16(ARG1,ARG2) \
saloutos 0:083111ae2a11 1718 ({ \
saloutos 0:083111ae2a11 1719 int32_t __RES, __ARG1 = (ARG1); \
saloutos 0:083111ae2a11 1720 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
saloutos 0:083111ae2a11 1721 __RES; \
saloutos 0:083111ae2a11 1722 })
saloutos 0:083111ae2a11 1723
saloutos 0:083111ae2a11 1724 #define __USAT16(ARG1,ARG2) \
saloutos 0:083111ae2a11 1725 ({ \
saloutos 0:083111ae2a11 1726 uint32_t __RES, __ARG1 = (ARG1); \
saloutos 0:083111ae2a11 1727 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
saloutos 0:083111ae2a11 1728 __RES; \
saloutos 0:083111ae2a11 1729 })
saloutos 0:083111ae2a11 1730
saloutos 0:083111ae2a11 1731 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
saloutos 0:083111ae2a11 1732 {
saloutos 0:083111ae2a11 1733 uint32_t result;
saloutos 0:083111ae2a11 1734
saloutos 0:083111ae2a11 1735 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
saloutos 0:083111ae2a11 1736 return(result);
saloutos 0:083111ae2a11 1737 }
saloutos 0:083111ae2a11 1738
saloutos 0:083111ae2a11 1739 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1740 {
saloutos 0:083111ae2a11 1741 uint32_t result;
saloutos 0:083111ae2a11 1742
saloutos 0:083111ae2a11 1743 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1744 return(result);
saloutos 0:083111ae2a11 1745 }
saloutos 0:083111ae2a11 1746
saloutos 0:083111ae2a11 1747 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
saloutos 0:083111ae2a11 1748 {
saloutos 0:083111ae2a11 1749 uint32_t result;
saloutos 0:083111ae2a11 1750
saloutos 0:083111ae2a11 1751 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
saloutos 0:083111ae2a11 1752 return(result);
saloutos 0:083111ae2a11 1753 }
saloutos 0:083111ae2a11 1754
saloutos 0:083111ae2a11 1755 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1756 {
saloutos 0:083111ae2a11 1757 uint32_t result;
saloutos 0:083111ae2a11 1758
saloutos 0:083111ae2a11 1759 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1760 return(result);
saloutos 0:083111ae2a11 1761 }
saloutos 0:083111ae2a11 1762
saloutos 0:083111ae2a11 1763 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1764 {
saloutos 0:083111ae2a11 1765 uint32_t result;
saloutos 0:083111ae2a11 1766
saloutos 0:083111ae2a11 1767 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1768 return(result);
saloutos 0:083111ae2a11 1769 }
saloutos 0:083111ae2a11 1770
saloutos 0:083111ae2a11 1771 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1772 {
saloutos 0:083111ae2a11 1773 uint32_t result;
saloutos 0:083111ae2a11 1774
saloutos 0:083111ae2a11 1775 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1776 return(result);
saloutos 0:083111ae2a11 1777 }
saloutos 0:083111ae2a11 1778
saloutos 0:083111ae2a11 1779 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
saloutos 0:083111ae2a11 1780 {
saloutos 0:083111ae2a11 1781 uint32_t result;
saloutos 0:083111ae2a11 1782
saloutos 0:083111ae2a11 1783 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
saloutos 0:083111ae2a11 1784 return(result);
saloutos 0:083111ae2a11 1785 }
saloutos 0:083111ae2a11 1786
saloutos 0:083111ae2a11 1787 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
saloutos 0:083111ae2a11 1788 {
saloutos 0:083111ae2a11 1789 uint32_t result;
saloutos 0:083111ae2a11 1790
saloutos 0:083111ae2a11 1791 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
saloutos 0:083111ae2a11 1792 return(result);
saloutos 0:083111ae2a11 1793 }
saloutos 0:083111ae2a11 1794
saloutos 0:083111ae2a11 1795 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
saloutos 0:083111ae2a11 1796 {
saloutos 0:083111ae2a11 1797 union llreg_u{
saloutos 0:083111ae2a11 1798 uint32_t w32[2];
saloutos 0:083111ae2a11 1799 uint64_t w64;
saloutos 0:083111ae2a11 1800 } llr;
saloutos 0:083111ae2a11 1801 llr.w64 = acc;
saloutos 0:083111ae2a11 1802
saloutos 0:083111ae2a11 1803 #ifndef __ARMEB__ /* Little endian */
saloutos 0:083111ae2a11 1804 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
saloutos 0:083111ae2a11 1805 #else /* Big endian */
saloutos 0:083111ae2a11 1806 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
saloutos 0:083111ae2a11 1807 #endif
saloutos 0:083111ae2a11 1808
saloutos 0:083111ae2a11 1809 return(llr.w64);
saloutos 0:083111ae2a11 1810 }
saloutos 0:083111ae2a11 1811
saloutos 0:083111ae2a11 1812 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
saloutos 0:083111ae2a11 1813 {
saloutos 0:083111ae2a11 1814 union llreg_u{
saloutos 0:083111ae2a11 1815 uint32_t w32[2];
saloutos 0:083111ae2a11 1816 uint64_t w64;
saloutos 0:083111ae2a11 1817 } llr;
saloutos 0:083111ae2a11 1818 llr.w64 = acc;
saloutos 0:083111ae2a11 1819
saloutos 0:083111ae2a11 1820 #ifndef __ARMEB__ /* Little endian */
saloutos 0:083111ae2a11 1821 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
saloutos 0:083111ae2a11 1822 #else /* Big endian */
saloutos 0:083111ae2a11 1823 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
saloutos 0:083111ae2a11 1824 #endif
saloutos 0:083111ae2a11 1825
saloutos 0:083111ae2a11 1826 return(llr.w64);
saloutos 0:083111ae2a11 1827 }
saloutos 0:083111ae2a11 1828
saloutos 0:083111ae2a11 1829 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1830 {
saloutos 0:083111ae2a11 1831 uint32_t result;
saloutos 0:083111ae2a11 1832
saloutos 0:083111ae2a11 1833 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1834 return(result);
saloutos 0:083111ae2a11 1835 }
saloutos 0:083111ae2a11 1836
saloutos 0:083111ae2a11 1837 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1838 {
saloutos 0:083111ae2a11 1839 uint32_t result;
saloutos 0:083111ae2a11 1840
saloutos 0:083111ae2a11 1841 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1842 return(result);
saloutos 0:083111ae2a11 1843 }
saloutos 0:083111ae2a11 1844
saloutos 0:083111ae2a11 1845 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
saloutos 0:083111ae2a11 1846 {
saloutos 0:083111ae2a11 1847 uint32_t result;
saloutos 0:083111ae2a11 1848
saloutos 0:083111ae2a11 1849 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
saloutos 0:083111ae2a11 1850 return(result);
saloutos 0:083111ae2a11 1851 }
saloutos 0:083111ae2a11 1852
saloutos 0:083111ae2a11 1853 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
saloutos 0:083111ae2a11 1854 {
saloutos 0:083111ae2a11 1855 uint32_t result;
saloutos 0:083111ae2a11 1856
saloutos 0:083111ae2a11 1857 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
saloutos 0:083111ae2a11 1858 return(result);
saloutos 0:083111ae2a11 1859 }
saloutos 0:083111ae2a11 1860
saloutos 0:083111ae2a11 1861 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
saloutos 0:083111ae2a11 1862 {
saloutos 0:083111ae2a11 1863 union llreg_u{
saloutos 0:083111ae2a11 1864 uint32_t w32[2];
saloutos 0:083111ae2a11 1865 uint64_t w64;
saloutos 0:083111ae2a11 1866 } llr;
saloutos 0:083111ae2a11 1867 llr.w64 = acc;
saloutos 0:083111ae2a11 1868
saloutos 0:083111ae2a11 1869 #ifndef __ARMEB__ /* Little endian */
saloutos 0:083111ae2a11 1870 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
saloutos 0:083111ae2a11 1871 #else /* Big endian */
saloutos 0:083111ae2a11 1872 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
saloutos 0:083111ae2a11 1873 #endif
saloutos 0:083111ae2a11 1874
saloutos 0:083111ae2a11 1875 return(llr.w64);
saloutos 0:083111ae2a11 1876 }
saloutos 0:083111ae2a11 1877
saloutos 0:083111ae2a11 1878 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
saloutos 0:083111ae2a11 1879 {
saloutos 0:083111ae2a11 1880 union llreg_u{
saloutos 0:083111ae2a11 1881 uint32_t w32[2];
saloutos 0:083111ae2a11 1882 uint64_t w64;
saloutos 0:083111ae2a11 1883 } llr;
saloutos 0:083111ae2a11 1884 llr.w64 = acc;
saloutos 0:083111ae2a11 1885
saloutos 0:083111ae2a11 1886 #ifndef __ARMEB__ /* Little endian */
saloutos 0:083111ae2a11 1887 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
saloutos 0:083111ae2a11 1888 #else /* Big endian */
saloutos 0:083111ae2a11 1889 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
saloutos 0:083111ae2a11 1890 #endif
saloutos 0:083111ae2a11 1891
saloutos 0:083111ae2a11 1892 return(llr.w64);
saloutos 0:083111ae2a11 1893 }
saloutos 0:083111ae2a11 1894
saloutos 0:083111ae2a11 1895 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 1896 {
saloutos 0:083111ae2a11 1897 uint32_t result;
saloutos 0:083111ae2a11 1898
saloutos 0:083111ae2a11 1899 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1900 return(result);
saloutos 0:083111ae2a11 1901 }
saloutos 0:083111ae2a11 1902
saloutos 0:083111ae2a11 1903 __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
saloutos 0:083111ae2a11 1904 {
saloutos 0:083111ae2a11 1905 int32_t result;
saloutos 0:083111ae2a11 1906
saloutos 0:083111ae2a11 1907 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1908 return(result);
saloutos 0:083111ae2a11 1909 }
saloutos 0:083111ae2a11 1910
saloutos 0:083111ae2a11 1911 __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
saloutos 0:083111ae2a11 1912 {
saloutos 0:083111ae2a11 1913 int32_t result;
saloutos 0:083111ae2a11 1914
saloutos 0:083111ae2a11 1915 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos 0:083111ae2a11 1916 return(result);
saloutos 0:083111ae2a11 1917 }
saloutos 0:083111ae2a11 1918
saloutos 0:083111ae2a11 1919 #if 0
saloutos 0:083111ae2a11 1920 #define __PKHBT(ARG1,ARG2,ARG3) \
saloutos 0:083111ae2a11 1921 ({ \
saloutos 0:083111ae2a11 1922 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
saloutos 0:083111ae2a11 1923 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
saloutos 0:083111ae2a11 1924 __RES; \
saloutos 0:083111ae2a11 1925 })
saloutos 0:083111ae2a11 1926
saloutos 0:083111ae2a11 1927 #define __PKHTB(ARG1,ARG2,ARG3) \
saloutos 0:083111ae2a11 1928 ({ \
saloutos 0:083111ae2a11 1929 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
saloutos 0:083111ae2a11 1930 if (ARG3 == 0) \
saloutos 0:083111ae2a11 1931 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
saloutos 0:083111ae2a11 1932 else \
saloutos 0:083111ae2a11 1933 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
saloutos 0:083111ae2a11 1934 __RES; \
saloutos 0:083111ae2a11 1935 })
saloutos 0:083111ae2a11 1936 #endif
saloutos 0:083111ae2a11 1937
saloutos 0:083111ae2a11 1938 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
saloutos 0:083111ae2a11 1939 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
saloutos 0:083111ae2a11 1940
saloutos 0:083111ae2a11 1941 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
saloutos 0:083111ae2a11 1942 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
saloutos 0:083111ae2a11 1943
saloutos 0:083111ae2a11 1944 __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
saloutos 0:083111ae2a11 1945 {
saloutos 0:083111ae2a11 1946 int32_t result;
saloutos 0:083111ae2a11 1947
saloutos 0:083111ae2a11 1948 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
saloutos 0:083111ae2a11 1949 return(result);
saloutos 0:083111ae2a11 1950 }
saloutos 0:083111ae2a11 1951
saloutos 0:083111ae2a11 1952 #endif /* (__ARM_FEATURE_DSP == 1) */
saloutos 0:083111ae2a11 1953 /*@} end of group CMSIS_SIMD_intrinsics */
saloutos 0:083111ae2a11 1954
saloutos 0:083111ae2a11 1955
saloutos 0:083111ae2a11 1956 #pragma GCC diagnostic pop
saloutos 0:083111ae2a11 1957
saloutos 0:083111ae2a11 1958 #endif /* __CMSIS_GCC_H */