Aditya Mehrotra / mbed-dev

Biomimetics MBED Library w/ Added Support for CAN3

Dependents:   CAN_TEST SPIne_Plus_DYNO_SENSORS SPIne_Plus_v2 SPIne_Plus_Dyno_v2

cmsis/TARGET_CORTEX_A/core_caFunc.h@3:993b4d6ff61e, 2021-03-09 (annotated)

Committer:
adimmit
Date:
Tue Mar 09 20:33:24 2021 +0000
Revision:
3:993b4d6ff61e
Parent:
0:083111ae2a11 
added CAN3

Who changed what in which revision?

UserRevisionLine numberNew contents of line
saloutos 0:083111ae2a11 1 /**************************************************************************//**
saloutos 0:083111ae2a11 2 * @file core_caFunc.h
saloutos 0:083111ae2a11 3 * @brief CMSIS Cortex-A Core Function Access Header File
saloutos 0:083111ae2a11 4 * @version V3.10
saloutos 0:083111ae2a11 5 * @date 30 Oct 2013
saloutos 0:083111ae2a11 6 *
saloutos 0:083111ae2a11 7 * @note
saloutos 0:083111ae2a11 8 *
saloutos 0:083111ae2a11 9 ******************************************************************************/
saloutos 0:083111ae2a11 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
saloutos 0:083111ae2a11 11
saloutos 0:083111ae2a11 12 All rights reserved.
saloutos 0:083111ae2a11 13 Redistribution and use in source and binary forms, with or without
saloutos 0:083111ae2a11 14 modification, are permitted provided that the following conditions are met:
saloutos 0:083111ae2a11 15 - Redistributions of source code must retain the above copyright
saloutos 0:083111ae2a11 16 notice, this list of conditions and the following disclaimer.
saloutos 0:083111ae2a11 17 - Redistributions in binary form must reproduce the above copyright
saloutos 0:083111ae2a11 18 notice, this list of conditions and the following disclaimer in the
saloutos 0:083111ae2a11 19 documentation and/or other materials provided with the distribution.
saloutos 0:083111ae2a11 20 - Neither the name of ARM nor the names of its contributors may be used
saloutos 0:083111ae2a11 21 to endorse or promote products derived from this software without
saloutos 0:083111ae2a11 22 specific prior written permission.
saloutos 0:083111ae2a11 23 *
saloutos 0:083111ae2a11 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
saloutos 0:083111ae2a11 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
saloutos 0:083111ae2a11 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
saloutos 0:083111ae2a11 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
saloutos 0:083111ae2a11 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
saloutos 0:083111ae2a11 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
saloutos 0:083111ae2a11 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
saloutos 0:083111ae2a11 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
saloutos 0:083111ae2a11 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
saloutos 0:083111ae2a11 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
saloutos 0:083111ae2a11 34 POSSIBILITY OF SUCH DAMAGE.
saloutos 0:083111ae2a11 35 ---------------------------------------------------------------------------*/
saloutos 0:083111ae2a11 36
saloutos 0:083111ae2a11 37
saloutos 0:083111ae2a11 38 #ifndef __CORE_CAFUNC_H__
saloutos 0:083111ae2a11 39 #define __CORE_CAFUNC_H__
saloutos 0:083111ae2a11 40
saloutos 0:083111ae2a11 41
saloutos 0:083111ae2a11 42 /* ########################### Core Function Access ########################### */
saloutos 0:083111ae2a11 43 /** \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
saloutos 0:083111ae2a11 45 @{
saloutos 0:083111ae2a11 46 */
saloutos 0:083111ae2a11 47
saloutos 0:083111ae2a11 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
saloutos 0:083111ae2a11 49 /* ARM armcc specific functions */
saloutos 0:083111ae2a11 50
saloutos 0:083111ae2a11 51 #if (__ARMCC_VERSION < 400677)
saloutos 0:083111ae2a11 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
saloutos 0:083111ae2a11 53 #endif
saloutos 0:083111ae2a11 54
saloutos 0:083111ae2a11 55 #define MODE_USR 0x10
saloutos 0:083111ae2a11 56 #define MODE_FIQ 0x11
saloutos 0:083111ae2a11 57 #define MODE_IRQ 0x12
saloutos 0:083111ae2a11 58 #define MODE_SVC 0x13
saloutos 0:083111ae2a11 59 #define MODE_MON 0x16
saloutos 0:083111ae2a11 60 #define MODE_ABT 0x17
saloutos 0:083111ae2a11 61 #define MODE_HYP 0x1A
saloutos 0:083111ae2a11 62 #define MODE_UND 0x1B
saloutos 0:083111ae2a11 63 #define MODE_SYS 0x1F
saloutos 0:083111ae2a11 64
saloutos 0:083111ae2a11 65 /** \brief Get APSR Register
saloutos 0:083111ae2a11 66
saloutos 0:083111ae2a11 67 This function returns the content of the APSR Register.
saloutos 0:083111ae2a11 68
saloutos 0:083111ae2a11 69 \return APSR Register value
saloutos 0:083111ae2a11 70 */
saloutos 0:083111ae2a11 71 __STATIC_INLINE uint32_t __get_APSR(void)
saloutos 0:083111ae2a11 72 {
saloutos 0:083111ae2a11 73 register uint32_t __regAPSR __ASM("apsr");
saloutos 0:083111ae2a11 74 return(__regAPSR);
saloutos 0:083111ae2a11 75 }
saloutos 0:083111ae2a11 76
saloutos 0:083111ae2a11 77
saloutos 0:083111ae2a11 78 /** \brief Get CPSR Register
saloutos 0:083111ae2a11 79
saloutos 0:083111ae2a11 80 This function returns the content of the CPSR Register.
saloutos 0:083111ae2a11 81
saloutos 0:083111ae2a11 82 \return CPSR Register value
saloutos 0:083111ae2a11 83 */
saloutos 0:083111ae2a11 84 __STATIC_INLINE uint32_t __get_CPSR(void)
saloutos 0:083111ae2a11 85 {
saloutos 0:083111ae2a11 86 register uint32_t __regCPSR __ASM("cpsr");
saloutos 0:083111ae2a11 87 return(__regCPSR);
saloutos 0:083111ae2a11 88 }
saloutos 0:083111ae2a11 89
saloutos 0:083111ae2a11 90 /** \brief Set Stack Pointer
saloutos 0:083111ae2a11 91
saloutos 0:083111ae2a11 92 This function assigns the given value to the current stack pointer.
saloutos 0:083111ae2a11 93
saloutos 0:083111ae2a11 94 \param [in] topOfStack Stack Pointer value to set
saloutos 0:083111ae2a11 95 */
saloutos 0:083111ae2a11 96 register uint32_t __regSP __ASM("sp");
saloutos 0:083111ae2a11 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
saloutos 0:083111ae2a11 98 {
saloutos 0:083111ae2a11 99 __regSP = topOfStack;
saloutos 0:083111ae2a11 100 }
saloutos 0:083111ae2a11 101
saloutos 0:083111ae2a11 102
saloutos 0:083111ae2a11 103 /** \brief Get link register
saloutos 0:083111ae2a11 104
saloutos 0:083111ae2a11 105 This function returns the value of the link register
saloutos 0:083111ae2a11 106
saloutos 0:083111ae2a11 107 \return Value of link register
saloutos 0:083111ae2a11 108 */
saloutos 0:083111ae2a11 109 register uint32_t __reglr __ASM("lr");
saloutos 0:083111ae2a11 110 __STATIC_INLINE uint32_t __get_LR(void)
saloutos 0:083111ae2a11 111 {
saloutos 0:083111ae2a11 112 return(__reglr);
saloutos 0:083111ae2a11 113 }
saloutos 0:083111ae2a11 114
saloutos 0:083111ae2a11 115 /** \brief Set link register
saloutos 0:083111ae2a11 116
saloutos 0:083111ae2a11 117 This function sets the value of the link register
saloutos 0:083111ae2a11 118
saloutos 0:083111ae2a11 119 \param [in] lr LR value to set
saloutos 0:083111ae2a11 120 */
saloutos 0:083111ae2a11 121 __STATIC_INLINE void __set_LR(uint32_t lr)
saloutos 0:083111ae2a11 122 {
saloutos 0:083111ae2a11 123 __reglr = lr;
saloutos 0:083111ae2a11 124 }
saloutos 0:083111ae2a11 125
saloutos 0:083111ae2a11 126 /** \brief Set Process Stack Pointer
saloutos 0:083111ae2a11 127
saloutos 0:083111ae2a11 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
saloutos 0:083111ae2a11 129
saloutos 0:083111ae2a11 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
saloutos 0:083111ae2a11 131 */
saloutos 0:083111ae2a11 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
saloutos 0:083111ae2a11 133 {
saloutos 0:083111ae2a11 134 ARM
saloutos 0:083111ae2a11 135 PRESERVE8
saloutos 0:083111ae2a11 136
saloutos 0:083111ae2a11 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
saloutos 0:083111ae2a11 138 MRS R1, CPSR
saloutos 0:083111ae2a11 139 CPS #MODE_SYS ;no effect in USR mode
saloutos 0:083111ae2a11 140 MOV SP, R0
saloutos 0:083111ae2a11 141 MSR CPSR_c, R1 ;no effect in USR mode
saloutos 0:083111ae2a11 142 ISB
saloutos 0:083111ae2a11 143 BX LR
saloutos 0:083111ae2a11 144
saloutos 0:083111ae2a11 145 }
saloutos 0:083111ae2a11 146
saloutos 0:083111ae2a11 147 /** \brief Set User Mode
saloutos 0:083111ae2a11 148
saloutos 0:083111ae2a11 149 This function changes the processor state to User Mode
saloutos 0:083111ae2a11 150 */
saloutos 0:083111ae2a11 151 __STATIC_ASM void __set_CPS_USR(void)
saloutos 0:083111ae2a11 152 {
saloutos 0:083111ae2a11 153 ARM
saloutos 0:083111ae2a11 154
saloutos 0:083111ae2a11 155 CPS #MODE_USR
saloutos 0:083111ae2a11 156 BX LR
saloutos 0:083111ae2a11 157 }
saloutos 0:083111ae2a11 158
saloutos 0:083111ae2a11 159
saloutos 0:083111ae2a11 160 /** \brief Enable FIQ
saloutos 0:083111ae2a11 161
saloutos 0:083111ae2a11 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
saloutos 0:083111ae2a11 163 Can only be executed in Privileged modes.
saloutos 0:083111ae2a11 164 */
saloutos 0:083111ae2a11 165 #define __enable_fault_irq __enable_fiq
saloutos 0:083111ae2a11 166
saloutos 0:083111ae2a11 167
saloutos 0:083111ae2a11 168 /** \brief Disable FIQ
saloutos 0:083111ae2a11 169
saloutos 0:083111ae2a11 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
saloutos 0:083111ae2a11 171 Can only be executed in Privileged modes.
saloutos 0:083111ae2a11 172 */
saloutos 0:083111ae2a11 173 #define __disable_fault_irq __disable_fiq
saloutos 0:083111ae2a11 174
saloutos 0:083111ae2a11 175
saloutos 0:083111ae2a11 176 /** \brief Get FPSCR
saloutos 0:083111ae2a11 177
saloutos 0:083111ae2a11 178 This function returns the current value of the Floating Point Status/Control register.
saloutos 0:083111ae2a11 179
saloutos 0:083111ae2a11 180 \return Floating Point Status/Control register value
saloutos 0:083111ae2a11 181 */
saloutos 0:083111ae2a11 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
saloutos 0:083111ae2a11 183 {
saloutos 0:083111ae2a11 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
saloutos 0:083111ae2a11 185 register uint32_t __regfpscr __ASM("fpscr");
saloutos 0:083111ae2a11 186 return(__regfpscr);
saloutos 0:083111ae2a11 187 #else
saloutos 0:083111ae2a11 188 return(0);
saloutos 0:083111ae2a11 189 #endif
saloutos 0:083111ae2a11 190 }
saloutos 0:083111ae2a11 191
saloutos 0:083111ae2a11 192
saloutos 0:083111ae2a11 193 /** \brief Set FPSCR
saloutos 0:083111ae2a11 194
saloutos 0:083111ae2a11 195 This function assigns the given value to the Floating Point Status/Control register.
saloutos 0:083111ae2a11 196
saloutos 0:083111ae2a11 197 \param [in] fpscr Floating Point Status/Control value to set
saloutos 0:083111ae2a11 198 */
saloutos 0:083111ae2a11 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
saloutos 0:083111ae2a11 200 {
saloutos 0:083111ae2a11 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
saloutos 0:083111ae2a11 202 register uint32_t __regfpscr __ASM("fpscr");
saloutos 0:083111ae2a11 203 __regfpscr = (fpscr);
saloutos 0:083111ae2a11 204 #endif
saloutos 0:083111ae2a11 205 }
saloutos 0:083111ae2a11 206
saloutos 0:083111ae2a11 207 /** \brief Get FPEXC
saloutos 0:083111ae2a11 208
saloutos 0:083111ae2a11 209 This function returns the current value of the Floating Point Exception Control register.
saloutos 0:083111ae2a11 210
saloutos 0:083111ae2a11 211 \return Floating Point Exception Control register value
saloutos 0:083111ae2a11 212 */
saloutos 0:083111ae2a11 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
saloutos 0:083111ae2a11 214 {
saloutos 0:083111ae2a11 215 #if (__FPU_PRESENT == 1)
saloutos 0:083111ae2a11 216 register uint32_t __regfpexc __ASM("fpexc");
saloutos 0:083111ae2a11 217 return(__regfpexc);
saloutos 0:083111ae2a11 218 #else
saloutos 0:083111ae2a11 219 return(0);
saloutos 0:083111ae2a11 220 #endif
saloutos 0:083111ae2a11 221 }
saloutos 0:083111ae2a11 222
saloutos 0:083111ae2a11 223
saloutos 0:083111ae2a11 224 /** \brief Set FPEXC
saloutos 0:083111ae2a11 225
saloutos 0:083111ae2a11 226 This function assigns the given value to the Floating Point Exception Control register.
saloutos 0:083111ae2a11 227
saloutos 0:083111ae2a11 228 \param [in] fpscr Floating Point Exception Control value to set
saloutos 0:083111ae2a11 229 */
saloutos 0:083111ae2a11 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
saloutos 0:083111ae2a11 231 {
saloutos 0:083111ae2a11 232 #if (__FPU_PRESENT == 1)
saloutos 0:083111ae2a11 233 register uint32_t __regfpexc __ASM("fpexc");
saloutos 0:083111ae2a11 234 __regfpexc = (fpexc);
saloutos 0:083111ae2a11 235 #endif
saloutos 0:083111ae2a11 236 }
saloutos 0:083111ae2a11 237
saloutos 0:083111ae2a11 238 /** \brief Get CPACR
saloutos 0:083111ae2a11 239
saloutos 0:083111ae2a11 240 This function returns the current value of the Coprocessor Access Control register.
saloutos 0:083111ae2a11 241
saloutos 0:083111ae2a11 242 \return Coprocessor Access Control register value
saloutos 0:083111ae2a11 243 */
saloutos 0:083111ae2a11 244 __STATIC_INLINE uint32_t __get_CPACR(void)
saloutos 0:083111ae2a11 245 {
saloutos 0:083111ae2a11 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
saloutos 0:083111ae2a11 247 return __regCPACR;
saloutos 0:083111ae2a11 248 }
saloutos 0:083111ae2a11 249
saloutos 0:083111ae2a11 250 /** \brief Set CPACR
saloutos 0:083111ae2a11 251
saloutos 0:083111ae2a11 252 This function assigns the given value to the Coprocessor Access Control register.
saloutos 0:083111ae2a11 253
saloutos 0:083111ae2a11 254 \param [in] cpacr Coprocessor Acccess Control value to set
saloutos 0:083111ae2a11 255 */
saloutos 0:083111ae2a11 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
saloutos 0:083111ae2a11 257 {
saloutos 0:083111ae2a11 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
saloutos 0:083111ae2a11 259 __regCPACR = cpacr;
saloutos 0:083111ae2a11 260 __ISB();
saloutos 0:083111ae2a11 261 }
saloutos 0:083111ae2a11 262
saloutos 0:083111ae2a11 263 /** \brief Get CBAR
saloutos 0:083111ae2a11 264
saloutos 0:083111ae2a11 265 This function returns the value of the Configuration Base Address register.
saloutos 0:083111ae2a11 266
saloutos 0:083111ae2a11 267 \return Configuration Base Address register value
saloutos 0:083111ae2a11 268 */
saloutos 0:083111ae2a11 269 __STATIC_INLINE uint32_t __get_CBAR() {
saloutos 0:083111ae2a11 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
saloutos 0:083111ae2a11 271 return(__regCBAR);
saloutos 0:083111ae2a11 272 }
saloutos 0:083111ae2a11 273
saloutos 0:083111ae2a11 274 /** \brief Get TTBR0
saloutos 0:083111ae2a11 275
saloutos 0:083111ae2a11 276 This function returns the value of the Translation Table Base Register 0.
saloutos 0:083111ae2a11 277
saloutos 0:083111ae2a11 278 \return Translation Table Base Register 0 value
saloutos 0:083111ae2a11 279 */
saloutos 0:083111ae2a11 280 __STATIC_INLINE uint32_t __get_TTBR0() {
saloutos 0:083111ae2a11 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
saloutos 0:083111ae2a11 282 return(__regTTBR0);
saloutos 0:083111ae2a11 283 }
saloutos 0:083111ae2a11 284
saloutos 0:083111ae2a11 285 /** \brief Set TTBR0
saloutos 0:083111ae2a11 286
saloutos 0:083111ae2a11 287 This function assigns the given value to the Translation Table Base Register 0.
saloutos 0:083111ae2a11 288
saloutos 0:083111ae2a11 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
saloutos 0:083111ae2a11 290 */
saloutos 0:083111ae2a11 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
saloutos 0:083111ae2a11 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
saloutos 0:083111ae2a11 293 __regTTBR0 = ttbr0;
saloutos 0:083111ae2a11 294 __ISB();
saloutos 0:083111ae2a11 295 }
saloutos 0:083111ae2a11 296
saloutos 0:083111ae2a11 297 /** \brief Get DACR
saloutos 0:083111ae2a11 298
saloutos 0:083111ae2a11 299 This function returns the value of the Domain Access Control Register.
saloutos 0:083111ae2a11 300
saloutos 0:083111ae2a11 301 \return Domain Access Control Register value
saloutos 0:083111ae2a11 302 */
saloutos 0:083111ae2a11 303 __STATIC_INLINE uint32_t __get_DACR() {
saloutos 0:083111ae2a11 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
saloutos 0:083111ae2a11 305 return(__regDACR);
saloutos 0:083111ae2a11 306 }
saloutos 0:083111ae2a11 307
saloutos 0:083111ae2a11 308 /** \brief Set DACR
saloutos 0:083111ae2a11 309
saloutos 0:083111ae2a11 310 This function assigns the given value to the Domain Access Control Register.
saloutos 0:083111ae2a11 311
saloutos 0:083111ae2a11 312 \param [in] dacr Domain Access Control Register value to set
saloutos 0:083111ae2a11 313 */
saloutos 0:083111ae2a11 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
saloutos 0:083111ae2a11 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
saloutos 0:083111ae2a11 316 __regDACR = dacr;
saloutos 0:083111ae2a11 317 __ISB();
saloutos 0:083111ae2a11 318 }
saloutos 0:083111ae2a11 319
saloutos 0:083111ae2a11 320 /******************************** Cache and BTAC enable ****************************************************/
saloutos 0:083111ae2a11 321
saloutos 0:083111ae2a11 322 /** \brief Set SCTLR
saloutos 0:083111ae2a11 323
saloutos 0:083111ae2a11 324 This function assigns the given value to the System Control Register.
saloutos 0:083111ae2a11 325
saloutos 0:083111ae2a11 326 \param [in] sctlr System Control Register value to set
saloutos 0:083111ae2a11 327 */
saloutos 0:083111ae2a11 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
saloutos 0:083111ae2a11 329 {
saloutos 0:083111ae2a11 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
saloutos 0:083111ae2a11 331 __regSCTLR = sctlr;
saloutos 0:083111ae2a11 332 }
saloutos 0:083111ae2a11 333
saloutos 0:083111ae2a11 334 /** \brief Get SCTLR
saloutos 0:083111ae2a11 335
saloutos 0:083111ae2a11 336 This function returns the value of the System Control Register.
saloutos 0:083111ae2a11 337
saloutos 0:083111ae2a11 338 \return System Control Register value
saloutos 0:083111ae2a11 339 */
saloutos 0:083111ae2a11 340 __STATIC_INLINE uint32_t __get_SCTLR() {
saloutos 0:083111ae2a11 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
saloutos 0:083111ae2a11 342 return(__regSCTLR);
saloutos 0:083111ae2a11 343 }
saloutos 0:083111ae2a11 344
saloutos 0:083111ae2a11 345 /** \brief Enable Caches
saloutos 0:083111ae2a11 346
saloutos 0:083111ae2a11 347 Enable Caches
saloutos 0:083111ae2a11 348 */
saloutos 0:083111ae2a11 349 __STATIC_INLINE void __enable_caches(void) {
saloutos 0:083111ae2a11 350 // Set I bit 12 to enable I Cache
saloutos 0:083111ae2a11 351 // Set C bit 2 to enable D Cache
saloutos 0:083111ae2a11 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
saloutos 0:083111ae2a11 353 }
saloutos 0:083111ae2a11 354
saloutos 0:083111ae2a11 355 /** \brief Disable Caches
saloutos 0:083111ae2a11 356
saloutos 0:083111ae2a11 357 Disable Caches
saloutos 0:083111ae2a11 358 */
saloutos 0:083111ae2a11 359 __STATIC_INLINE void __disable_caches(void) {
saloutos 0:083111ae2a11 360 // Clear I bit 12 to disable I Cache
saloutos 0:083111ae2a11 361 // Clear C bit 2 to disable D Cache
saloutos 0:083111ae2a11 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
saloutos 0:083111ae2a11 363 __ISB();
saloutos 0:083111ae2a11 364 }
saloutos 0:083111ae2a11 365
saloutos 0:083111ae2a11 366 /** \brief Enable BTAC
saloutos 0:083111ae2a11 367
saloutos 0:083111ae2a11 368 Enable BTAC
saloutos 0:083111ae2a11 369 */
saloutos 0:083111ae2a11 370 __STATIC_INLINE void __enable_btac(void) {
saloutos 0:083111ae2a11 371 // Set Z bit 11 to enable branch prediction
saloutos 0:083111ae2a11 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
saloutos 0:083111ae2a11 373 __ISB();
saloutos 0:083111ae2a11 374 }
saloutos 0:083111ae2a11 375
saloutos 0:083111ae2a11 376 /** \brief Disable BTAC
saloutos 0:083111ae2a11 377
saloutos 0:083111ae2a11 378 Disable BTAC
saloutos 0:083111ae2a11 379 */
saloutos 0:083111ae2a11 380 __STATIC_INLINE void __disable_btac(void) {
saloutos 0:083111ae2a11 381 // Clear Z bit 11 to disable branch prediction
saloutos 0:083111ae2a11 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
saloutos 0:083111ae2a11 383 }
saloutos 0:083111ae2a11 384
saloutos 0:083111ae2a11 385
saloutos 0:083111ae2a11 386 /** \brief Enable MMU
saloutos 0:083111ae2a11 387
saloutos 0:083111ae2a11 388 Enable MMU
saloutos 0:083111ae2a11 389 */
saloutos 0:083111ae2a11 390 __STATIC_INLINE void __enable_mmu(void) {
saloutos 0:083111ae2a11 391 // Set M bit 0 to enable the MMU
saloutos 0:083111ae2a11 392 // Set AFE bit to enable simplified access permissions model
saloutos 0:083111ae2a11 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
saloutos 0:083111ae2a11 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
saloutos 0:083111ae2a11 395 __ISB();
saloutos 0:083111ae2a11 396 }
saloutos 0:083111ae2a11 397
saloutos 0:083111ae2a11 398 /** \brief Disable MMU
saloutos 0:083111ae2a11 399
saloutos 0:083111ae2a11 400 Disable MMU
saloutos 0:083111ae2a11 401 */
saloutos 0:083111ae2a11 402 __STATIC_INLINE void __disable_mmu(void) {
saloutos 0:083111ae2a11 403 // Clear M bit 0 to disable the MMU
saloutos 0:083111ae2a11 404 __set_SCTLR( __get_SCTLR() & ~1);
saloutos 0:083111ae2a11 405 __ISB();
saloutos 0:083111ae2a11 406 }
saloutos 0:083111ae2a11 407
saloutos 0:083111ae2a11 408 /******************************** TLB maintenance operations ************************************************/
saloutos 0:083111ae2a11 409 /** \brief Invalidate the whole tlb
saloutos 0:083111ae2a11 410
saloutos 0:083111ae2a11 411 TLBIALL. Invalidate the whole tlb
saloutos 0:083111ae2a11 412 */
saloutos 0:083111ae2a11 413
saloutos 0:083111ae2a11 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
saloutos 0:083111ae2a11 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
saloutos 0:083111ae2a11 416 __TLBIALL = 0;
saloutos 0:083111ae2a11 417 __DSB();
saloutos 0:083111ae2a11 418 __ISB();
saloutos 0:083111ae2a11 419 }
saloutos 0:083111ae2a11 420
saloutos 0:083111ae2a11 421 /******************************** BTB maintenance operations ************************************************/
saloutos 0:083111ae2a11 422 /** \brief Invalidate entire branch predictor array
saloutos 0:083111ae2a11 423
saloutos 0:083111ae2a11 424 BPIALL. Branch Predictor Invalidate All.
saloutos 0:083111ae2a11 425 */
saloutos 0:083111ae2a11 426
saloutos 0:083111ae2a11 427 __STATIC_INLINE void __v7_inv_btac(void) {
saloutos 0:083111ae2a11 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
saloutos 0:083111ae2a11 429 __BPIALL = 0;
saloutos 0:083111ae2a11 430 __DSB(); //ensure completion of the invalidation
saloutos 0:083111ae2a11 431 __ISB(); //ensure instruction fetch path sees new state
saloutos 0:083111ae2a11 432 }
saloutos 0:083111ae2a11 433
saloutos 0:083111ae2a11 434
saloutos 0:083111ae2a11 435 /******************************** L1 cache operations ******************************************************/
saloutos 0:083111ae2a11 436
saloutos 0:083111ae2a11 437 /** \brief Invalidate the whole I$
saloutos 0:083111ae2a11 438
saloutos 0:083111ae2a11 439 ICIALLU. Instruction Cache Invalidate All to PoU
saloutos 0:083111ae2a11 440 */
saloutos 0:083111ae2a11 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
saloutos 0:083111ae2a11 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
saloutos 0:083111ae2a11 443 __ICIALLU = 0;
saloutos 0:083111ae2a11 444 __DSB(); //ensure completion of the invalidation
saloutos 0:083111ae2a11 445 __ISB(); //ensure instruction fetch path sees new I cache state
saloutos 0:083111ae2a11 446 }
saloutos 0:083111ae2a11 447
saloutos 0:083111ae2a11 448 /** \brief Clean D$ by MVA
saloutos 0:083111ae2a11 449
saloutos 0:083111ae2a11 450 DCCMVAC. Data cache clean by MVA to PoC
saloutos 0:083111ae2a11 451 */
saloutos 0:083111ae2a11 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
saloutos 0:083111ae2a11 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
saloutos 0:083111ae2a11 454 __DCCMVAC = (uint32_t)va;
saloutos 0:083111ae2a11 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
saloutos 0:083111ae2a11 456 }
saloutos 0:083111ae2a11 457
saloutos 0:083111ae2a11 458 /** \brief Invalidate D$ by MVA
saloutos 0:083111ae2a11 459
saloutos 0:083111ae2a11 460 DCIMVAC. Data cache invalidate by MVA to PoC
saloutos 0:083111ae2a11 461 */
saloutos 0:083111ae2a11 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
saloutos 0:083111ae2a11 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
saloutos 0:083111ae2a11 464 __DCIMVAC = (uint32_t)va;
saloutos 0:083111ae2a11 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
saloutos 0:083111ae2a11 466 }
saloutos 0:083111ae2a11 467
saloutos 0:083111ae2a11 468 /** \brief Clean and Invalidate D$ by MVA
saloutos 0:083111ae2a11 469
saloutos 0:083111ae2a11 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
saloutos 0:083111ae2a11 471 */
saloutos 0:083111ae2a11 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
saloutos 0:083111ae2a11 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
saloutos 0:083111ae2a11 474 __DCCIMVAC = (uint32_t)va;
saloutos 0:083111ae2a11 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
saloutos 0:083111ae2a11 476 }
saloutos 0:083111ae2a11 477
saloutos 0:083111ae2a11 478 /** \brief Clean and Invalidate the entire data or unified cache
saloutos 0:083111ae2a11 479
saloutos 0:083111ae2a11 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
saloutos 0:083111ae2a11 481 */
saloutos 0:083111ae2a11 482 #pragma push
saloutos 0:083111ae2a11 483 #pragma arm
saloutos 0:083111ae2a11 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
saloutos 0:083111ae2a11 485 ARM
saloutos 0:083111ae2a11 486
saloutos 0:083111ae2a11 487 PUSH {R4-R11}
saloutos 0:083111ae2a11 488
saloutos 0:083111ae2a11 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
saloutos 0:083111ae2a11 490 ANDS R3, R6, #0x07000000 // Extract coherency level
saloutos 0:083111ae2a11 491 MOV R3, R3, LSR #23 // Total cache levels << 1
saloutos 0:083111ae2a11 492 BEQ Finished // If 0, no need to clean
saloutos 0:083111ae2a11 493
saloutos 0:083111ae2a11 494 MOV R10, #0 // R10 holds current cache level << 1
saloutos 0:083111ae2a11 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
saloutos 0:083111ae2a11 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
saloutos 0:083111ae2a11 497 AND R1, R1, #7 // Isolate those lower 3 bits
saloutos 0:083111ae2a11 498 CMP R1, #2
saloutos 0:083111ae2a11 499 BLT Skip // No cache or only instruction cache at this level
saloutos 0:083111ae2a11 500
saloutos 0:083111ae2a11 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
saloutos 0:083111ae2a11 502 ISB // ISB to sync the change to the CacheSizeID reg
saloutos 0:083111ae2a11 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
saloutos 0:083111ae2a11 504 AND R2, R1, #7 // Extract the line length field
saloutos 0:083111ae2a11 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
saloutos 0:083111ae2a11 506 LDR R4, =0x3FF
saloutos 0:083111ae2a11 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
saloutos 0:083111ae2a11 508 CLZ R5, R4 // R5 is the bit position of the way size increment
saloutos 0:083111ae2a11 509 LDR R7, =0x7FFF
saloutos 0:083111ae2a11 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
saloutos 0:083111ae2a11 511
saloutos 0:083111ae2a11 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
saloutos 0:083111ae2a11 513
saloutos 0:083111ae2a11 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
saloutos 0:083111ae2a11 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
saloutos 0:083111ae2a11 516 CMP R0, #0
saloutos 0:083111ae2a11 517 BNE Dccsw
saloutos 0:083111ae2a11 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
saloutos 0:083111ae2a11 519 B cont
saloutos 0:083111ae2a11 520 Dccsw CMP R0, #1
saloutos 0:083111ae2a11 521 BNE Dccisw
saloutos 0:083111ae2a11 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
saloutos 0:083111ae2a11 523 B cont
saloutos 0:083111ae2a11 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
saloutos 0:083111ae2a11 525 cont SUBS R9, R9, #1 // Decrement the Way number
saloutos 0:083111ae2a11 526 BGE Loop3
saloutos 0:083111ae2a11 527 SUBS R7, R7, #1 // Decrement the Set number
saloutos 0:083111ae2a11 528 BGE Loop2
saloutos 0:083111ae2a11 529 Skip ADD R10, R10, #2 // Increment the cache number
saloutos 0:083111ae2a11 530 CMP R3, R10
saloutos 0:083111ae2a11 531 BGT Loop1
saloutos 0:083111ae2a11 532
saloutos 0:083111ae2a11 533 Finished
saloutos 0:083111ae2a11 534 DSB
saloutos 0:083111ae2a11 535 POP {R4-R11}
saloutos 0:083111ae2a11 536 BX lr
saloutos 0:083111ae2a11 537
saloutos 0:083111ae2a11 538 }
saloutos 0:083111ae2a11 539 #pragma pop
saloutos 0:083111ae2a11 540
saloutos 0:083111ae2a11 541
saloutos 0:083111ae2a11 542 /** \brief Invalidate the whole D$
saloutos 0:083111ae2a11 543
saloutos 0:083111ae2a11 544 DCISW. Invalidate by Set/Way
saloutos 0:083111ae2a11 545 */
saloutos 0:083111ae2a11 546
saloutos 0:083111ae2a11 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
saloutos 0:083111ae2a11 548 __v7_all_cache(0);
saloutos 0:083111ae2a11 549 }
saloutos 0:083111ae2a11 550
saloutos 0:083111ae2a11 551 /** \brief Clean the whole D$
saloutos 0:083111ae2a11 552
saloutos 0:083111ae2a11 553 DCCSW. Clean by Set/Way
saloutos 0:083111ae2a11 554 */
saloutos 0:083111ae2a11 555
saloutos 0:083111ae2a11 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
saloutos 0:083111ae2a11 557 __v7_all_cache(1);
saloutos 0:083111ae2a11 558 }
saloutos 0:083111ae2a11 559
saloutos 0:083111ae2a11 560 /** \brief Clean and invalidate the whole D$
saloutos 0:083111ae2a11 561
saloutos 0:083111ae2a11 562 DCCISW. Clean and Invalidate by Set/Way
saloutos 0:083111ae2a11 563 */
saloutos 0:083111ae2a11 564
saloutos 0:083111ae2a11 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
saloutos 0:083111ae2a11 566 __v7_all_cache(2);
saloutos 0:083111ae2a11 567 }
saloutos 0:083111ae2a11 568
saloutos 0:083111ae2a11 569 #include "core_ca_mmu.h"
saloutos 0:083111ae2a11 570
saloutos 0:083111ae2a11 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
saloutos 0:083111ae2a11 572
saloutos 0:083111ae2a11 573 #define __inline inline
saloutos 0:083111ae2a11 574
saloutos 0:083111ae2a11 575 inline static uint32_t __disable_irq_iar() {
saloutos 0:083111ae2a11 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
saloutos 0:083111ae2a11 577 __disable_irq();
saloutos 0:083111ae2a11 578 return irq_dis;
saloutos 0:083111ae2a11 579 }
saloutos 0:083111ae2a11 580
saloutos 0:083111ae2a11 581 #define MODE_USR 0x10
saloutos 0:083111ae2a11 582 #define MODE_FIQ 0x11
saloutos 0:083111ae2a11 583 #define MODE_IRQ 0x12
saloutos 0:083111ae2a11 584 #define MODE_SVC 0x13
saloutos 0:083111ae2a11 585 #define MODE_MON 0x16
saloutos 0:083111ae2a11 586 #define MODE_ABT 0x17
saloutos 0:083111ae2a11 587 #define MODE_HYP 0x1A
saloutos 0:083111ae2a11 588 #define MODE_UND 0x1B
saloutos 0:083111ae2a11 589 #define MODE_SYS 0x1F
saloutos 0:083111ae2a11 590
saloutos 0:083111ae2a11 591 /** \brief Set Process Stack Pointer
saloutos 0:083111ae2a11 592
saloutos 0:083111ae2a11 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
saloutos 0:083111ae2a11 594
saloutos 0:083111ae2a11 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
saloutos 0:083111ae2a11 596 */
saloutos 0:083111ae2a11 597 // from rt_CMSIS.c
saloutos 0:083111ae2a11 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
saloutos 0:083111ae2a11 599 __asm(
saloutos 0:083111ae2a11 600 " ARM\n"
saloutos 0:083111ae2a11 601 // " PRESERVE8\n"
saloutos 0:083111ae2a11 602
saloutos 0:083111ae2a11 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
saloutos 0:083111ae2a11 604 " MRS R1, CPSR \n"
saloutos 0:083111ae2a11 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
saloutos 0:083111ae2a11 606 " MOV SP, R0 \n"
saloutos 0:083111ae2a11 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
saloutos 0:083111ae2a11 608 " ISB \n"
saloutos 0:083111ae2a11 609 " BX LR \n");
saloutos 0:083111ae2a11 610 }
saloutos 0:083111ae2a11 611
saloutos 0:083111ae2a11 612 /** \brief Set User Mode
saloutos 0:083111ae2a11 613
saloutos 0:083111ae2a11 614 This function changes the processor state to User Mode
saloutos 0:083111ae2a11 615 */
saloutos 0:083111ae2a11 616 // from rt_CMSIS.c
saloutos 0:083111ae2a11 617 __arm static inline void __set_CPS_USR(void) {
saloutos 0:083111ae2a11 618 __asm(
saloutos 0:083111ae2a11 619 " ARM \n"
saloutos 0:083111ae2a11 620
saloutos 0:083111ae2a11 621 " CPS #0x10 \n" // MODE_USR
saloutos 0:083111ae2a11 622 " BX LR\n");
saloutos 0:083111ae2a11 623 }
saloutos 0:083111ae2a11 624
saloutos 0:083111ae2a11 625 /** \brief Set TTBR0
saloutos 0:083111ae2a11 626
saloutos 0:083111ae2a11 627 This function assigns the given value to the Translation Table Base Register 0.
saloutos 0:083111ae2a11 628
saloutos 0:083111ae2a11 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
saloutos 0:083111ae2a11 630 */
saloutos 0:083111ae2a11 631 // from mmu_Renesas_RZ_A1.c
saloutos 0:083111ae2a11 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
saloutos 0:083111ae2a11 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
saloutos 0:083111ae2a11 634 __ISB();
saloutos 0:083111ae2a11 635 }
saloutos 0:083111ae2a11 636
saloutos 0:083111ae2a11 637 /** \brief Set DACR
saloutos 0:083111ae2a11 638
saloutos 0:083111ae2a11 639 This function assigns the given value to the Domain Access Control Register.
saloutos 0:083111ae2a11 640
saloutos 0:083111ae2a11 641 \param [in] dacr Domain Access Control Register value to set
saloutos 0:083111ae2a11 642 */
saloutos 0:083111ae2a11 643 // from mmu_Renesas_RZ_A1.c
saloutos 0:083111ae2a11 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
saloutos 0:083111ae2a11 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
saloutos 0:083111ae2a11 646 __ISB();
saloutos 0:083111ae2a11 647 }
saloutos 0:083111ae2a11 648
saloutos 0:083111ae2a11 649
saloutos 0:083111ae2a11 650 /******************************** Cache and BTAC enable ****************************************************/
saloutos 0:083111ae2a11 651 /** \brief Set SCTLR
saloutos 0:083111ae2a11 652
saloutos 0:083111ae2a11 653 This function assigns the given value to the System Control Register.
saloutos 0:083111ae2a11 654
saloutos 0:083111ae2a11 655 \param [in] sctlr System Control Register value to set
saloutos 0:083111ae2a11 656 */
saloutos 0:083111ae2a11 657 // from __enable_mmu()
saloutos 0:083111ae2a11 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
saloutos 0:083111ae2a11 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
saloutos 0:083111ae2a11 660 }
saloutos 0:083111ae2a11 661
saloutos 0:083111ae2a11 662 /** \brief Get SCTLR
saloutos 0:083111ae2a11 663
saloutos 0:083111ae2a11 664 This function returns the value of the System Control Register.
saloutos 0:083111ae2a11 665
saloutos 0:083111ae2a11 666 \return System Control Register value
saloutos 0:083111ae2a11 667 */
saloutos 0:083111ae2a11 668 // from __enable_mmu()
saloutos 0:083111ae2a11 669 __STATIC_INLINE uint32_t __get_SCTLR() {
saloutos 0:083111ae2a11 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
saloutos 0:083111ae2a11 671 return __regSCTLR;
saloutos 0:083111ae2a11 672 }
saloutos 0:083111ae2a11 673
saloutos 0:083111ae2a11 674 /** \brief Enable Caches
saloutos 0:083111ae2a11 675
saloutos 0:083111ae2a11 676 Enable Caches
saloutos 0:083111ae2a11 677 */
saloutos 0:083111ae2a11 678 // from system_Renesas_RZ_A1.c
saloutos 0:083111ae2a11 679 __STATIC_INLINE void __enable_caches(void) {
saloutos 0:083111ae2a11 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
saloutos 0:083111ae2a11 681 }
saloutos 0:083111ae2a11 682
saloutos 0:083111ae2a11 683 /** \brief Enable BTAC
saloutos 0:083111ae2a11 684
saloutos 0:083111ae2a11 685 Enable BTAC
saloutos 0:083111ae2a11 686 */
saloutos 0:083111ae2a11 687 // from system_Renesas_RZ_A1.c
saloutos 0:083111ae2a11 688 __STATIC_INLINE void __enable_btac(void) {
saloutos 0:083111ae2a11 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
saloutos 0:083111ae2a11 690 __ISB();
saloutos 0:083111ae2a11 691 }
saloutos 0:083111ae2a11 692
saloutos 0:083111ae2a11 693 /** \brief Enable MMU
saloutos 0:083111ae2a11 694
saloutos 0:083111ae2a11 695 Enable MMU
saloutos 0:083111ae2a11 696 */
saloutos 0:083111ae2a11 697 // from system_Renesas_RZ_A1.c
saloutos 0:083111ae2a11 698 __STATIC_INLINE void __enable_mmu(void) {
saloutos 0:083111ae2a11 699 // Set M bit 0 to enable the MMU
saloutos 0:083111ae2a11 700 // Set AFE bit to enable simplified access permissions model
saloutos 0:083111ae2a11 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
saloutos 0:083111ae2a11 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
saloutos 0:083111ae2a11 703 __ISB();
saloutos 0:083111ae2a11 704 }
saloutos 0:083111ae2a11 705
saloutos 0:083111ae2a11 706 /******************************** TLB maintenance operations ************************************************/
saloutos 0:083111ae2a11 707 /** \brief Invalidate the whole tlb
saloutos 0:083111ae2a11 708
saloutos 0:083111ae2a11 709 TLBIALL. Invalidate the whole tlb
saloutos 0:083111ae2a11 710 */
saloutos 0:083111ae2a11 711 // from system_Renesas_RZ_A1.c
saloutos 0:083111ae2a11 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
saloutos 0:083111ae2a11 713 uint32_t val = 0;
saloutos 0:083111ae2a11 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
saloutos 0:083111ae2a11 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
saloutos 0:083111ae2a11 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
saloutos 0:083111ae2a11 717 __DSB();
saloutos 0:083111ae2a11 718 __ISB();
saloutos 0:083111ae2a11 719 }
saloutos 0:083111ae2a11 720
saloutos 0:083111ae2a11 721 /******************************** BTB maintenance operations ************************************************/
saloutos 0:083111ae2a11 722 /** \brief Invalidate entire branch predictor array
saloutos 0:083111ae2a11 723
saloutos 0:083111ae2a11 724 BPIALL. Branch Predictor Invalidate All.
saloutos 0:083111ae2a11 725 */
saloutos 0:083111ae2a11 726 // from system_Renesas_RZ_A1.c
saloutos 0:083111ae2a11 727 __STATIC_INLINE void __v7_inv_btac(void) {
saloutos 0:083111ae2a11 728 uint32_t val = 0;
saloutos 0:083111ae2a11 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
saloutos 0:083111ae2a11 730 __DSB(); //ensure completion of the invalidation
saloutos 0:083111ae2a11 731 __ISB(); //ensure instruction fetch path sees new state
saloutos 0:083111ae2a11 732 }
saloutos 0:083111ae2a11 733
saloutos 0:083111ae2a11 734
saloutos 0:083111ae2a11 735 /******************************** L1 cache operations ******************************************************/
saloutos 0:083111ae2a11 736
saloutos 0:083111ae2a11 737 /** \brief Invalidate the whole I$
saloutos 0:083111ae2a11 738
saloutos 0:083111ae2a11 739 ICIALLU. Instruction Cache Invalidate All to PoU
saloutos 0:083111ae2a11 740 */
saloutos 0:083111ae2a11 741 // from system_Renesas_RZ_A1.c
saloutos 0:083111ae2a11 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
saloutos 0:083111ae2a11 743 uint32_t val = 0;
saloutos 0:083111ae2a11 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
saloutos 0:083111ae2a11 745 __DSB(); //ensure completion of the invalidation
saloutos 0:083111ae2a11 746 __ISB(); //ensure instruction fetch path sees new I cache state
saloutos 0:083111ae2a11 747 }
saloutos 0:083111ae2a11 748
saloutos 0:083111ae2a11 749 // from __v7_inv_dcache_all()
saloutos 0:083111ae2a11 750 __arm static inline void __v7_all_cache(uint32_t op) {
saloutos 0:083111ae2a11 751 __asm(
saloutos 0:083111ae2a11 752 " ARM \n"
saloutos 0:083111ae2a11 753
saloutos 0:083111ae2a11 754 " PUSH {R4-R11} \n"
saloutos 0:083111ae2a11 755
saloutos 0:083111ae2a11 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
saloutos 0:083111ae2a11 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
saloutos 0:083111ae2a11 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
saloutos 0:083111ae2a11 759 " BEQ Finished\n" // If 0, no need to clean
saloutos 0:083111ae2a11 760
saloutos 0:083111ae2a11 761 " MOV R10, #0\n" // R10 holds current cache level << 1
saloutos 0:083111ae2a11 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
saloutos 0:083111ae2a11 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
saloutos 0:083111ae2a11 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
saloutos 0:083111ae2a11 765 " CMP R1, #2 \n"
saloutos 0:083111ae2a11 766 " BLT Skip \n" // No cache or only instruction cache at this level
saloutos 0:083111ae2a11 767
saloutos 0:083111ae2a11 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
saloutos 0:083111ae2a11 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
saloutos 0:083111ae2a11 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
saloutos 0:083111ae2a11 771 " AND R2, R1, #7 \n" // Extract the line length field
saloutos 0:083111ae2a11 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
saloutos 0:083111ae2a11 773 " movw R4, #0x3FF \n"
saloutos 0:083111ae2a11 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
saloutos 0:083111ae2a11 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
saloutos 0:083111ae2a11 776 " movw R7, #0x7FFF \n"
saloutos 0:083111ae2a11 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
saloutos 0:083111ae2a11 778
saloutos 0:083111ae2a11 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
saloutos 0:083111ae2a11 780
saloutos 0:083111ae2a11 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
saloutos 0:083111ae2a11 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
saloutos 0:083111ae2a11 783 " CMP R0, #0 \n"
saloutos 0:083111ae2a11 784 " BNE Dccsw \n"
saloutos 0:083111ae2a11 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
saloutos 0:083111ae2a11 786 " B cont \n"
saloutos 0:083111ae2a11 787 "Dccsw: CMP R0, #1 \n"
saloutos 0:083111ae2a11 788 " BNE Dccisw \n"
saloutos 0:083111ae2a11 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
saloutos 0:083111ae2a11 790 " B cont \n"
saloutos 0:083111ae2a11 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
saloutos 0:083111ae2a11 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
saloutos 0:083111ae2a11 793 " BGE Loop3 \n"
saloutos 0:083111ae2a11 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
saloutos 0:083111ae2a11 795 " BGE Loop2 \n"
saloutos 0:083111ae2a11 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
saloutos 0:083111ae2a11 797 " CMP R3, R10 \n"
saloutos 0:083111ae2a11 798 " BGT Loop1 \n"
saloutos 0:083111ae2a11 799
saloutos 0:083111ae2a11 800 "Finished: \n"
saloutos 0:083111ae2a11 801 " DSB \n"
saloutos 0:083111ae2a11 802 " POP {R4-R11} \n"
saloutos 0:083111ae2a11 803 " BX lr \n" );
saloutos 0:083111ae2a11 804 }
saloutos 0:083111ae2a11 805
saloutos 0:083111ae2a11 806 /** \brief Invalidate the whole D$
saloutos 0:083111ae2a11 807
saloutos 0:083111ae2a11 808 DCISW. Invalidate by Set/Way
saloutos 0:083111ae2a11 809 */
saloutos 0:083111ae2a11 810 // from system_Renesas_RZ_A1.c
saloutos 0:083111ae2a11 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
saloutos 0:083111ae2a11 812 __v7_all_cache(0);
saloutos 0:083111ae2a11 813 }
saloutos 0:083111ae2a11 814 /** \brief Clean the whole D$
saloutos 0:083111ae2a11 815
saloutos 0:083111ae2a11 816 DCCSW. Clean by Set/Way
saloutos 0:083111ae2a11 817 */
saloutos 0:083111ae2a11 818
saloutos 0:083111ae2a11 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
saloutos 0:083111ae2a11 820 __v7_all_cache(1);
saloutos 0:083111ae2a11 821 }
saloutos 0:083111ae2a11 822
saloutos 0:083111ae2a11 823 /** \brief Clean and invalidate the whole D$
saloutos 0:083111ae2a11 824
saloutos 0:083111ae2a11 825 DCCISW. Clean and Invalidate by Set/Way
saloutos 0:083111ae2a11 826 */
saloutos 0:083111ae2a11 827
saloutos 0:083111ae2a11 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
saloutos 0:083111ae2a11 829 __v7_all_cache(2);
saloutos 0:083111ae2a11 830 }
saloutos 0:083111ae2a11 831 /** \brief Clean and Invalidate D$ by MVA
saloutos 0:083111ae2a11 832
saloutos 0:083111ae2a11 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
saloutos 0:083111ae2a11 834 */
saloutos 0:083111ae2a11 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
saloutos 0:083111ae2a11 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
saloutos 0:083111ae2a11 837 __DMB();
saloutos 0:083111ae2a11 838 }
saloutos 0:083111ae2a11 839
saloutos 0:083111ae2a11 840 #include "core_ca_mmu.h"
saloutos 0:083111ae2a11 841
saloutos 0:083111ae2a11 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
saloutos 0:083111ae2a11 843 /* GNU gcc specific functions */
saloutos 0:083111ae2a11 844
saloutos 0:083111ae2a11 845 #define MODE_USR 0x10
saloutos 0:083111ae2a11 846 #define MODE_FIQ 0x11
saloutos 0:083111ae2a11 847 #define MODE_IRQ 0x12
saloutos 0:083111ae2a11 848 #define MODE_SVC 0x13
saloutos 0:083111ae2a11 849 #define MODE_MON 0x16
saloutos 0:083111ae2a11 850 #define MODE_ABT 0x17
saloutos 0:083111ae2a11 851 #define MODE_HYP 0x1A
saloutos 0:083111ae2a11 852 #define MODE_UND 0x1B
saloutos 0:083111ae2a11 853 #define MODE_SYS 0x1F
saloutos 0:083111ae2a11 854
saloutos 0:083111ae2a11 855
saloutos 0:083111ae2a11 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
saloutos 0:083111ae2a11 857 {
saloutos 0:083111ae2a11 858 __ASM volatile ("cpsie i");
saloutos 0:083111ae2a11 859 }
saloutos 0:083111ae2a11 860
saloutos 0:083111ae2a11 861 /** \brief Disable IRQ Interrupts
saloutos 0:083111ae2a11 862
saloutos 0:083111ae2a11 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
saloutos 0:083111ae2a11 864 Can only be executed in Privileged modes.
saloutos 0:083111ae2a11 865 */
saloutos 0:083111ae2a11 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
saloutos 0:083111ae2a11 867 {
saloutos 0:083111ae2a11 868 uint32_t result;
saloutos 0:083111ae2a11 869
saloutos 0:083111ae2a11 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
saloutos 0:083111ae2a11 871 __ASM volatile ("cpsid i");
saloutos 0:083111ae2a11 872 return(result & 0x80);
saloutos 0:083111ae2a11 873 }
saloutos 0:083111ae2a11 874
saloutos 0:083111ae2a11 875
saloutos 0:083111ae2a11 876 /** \brief Get APSR Register
saloutos 0:083111ae2a11 877
saloutos 0:083111ae2a11 878 This function returns the content of the APSR Register.
saloutos 0:083111ae2a11 879
saloutos 0:083111ae2a11 880 \return APSR Register value
saloutos 0:083111ae2a11 881 */
saloutos 0:083111ae2a11 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
saloutos 0:083111ae2a11 883 {
saloutos 0:083111ae2a11 884 #if 1
saloutos 0:083111ae2a11 885 register uint32_t __regAPSR;
saloutos 0:083111ae2a11 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
saloutos 0:083111ae2a11 887 #else
saloutos 0:083111ae2a11 888 register uint32_t __regAPSR __ASM("apsr");
saloutos 0:083111ae2a11 889 #endif
saloutos 0:083111ae2a11 890 return(__regAPSR);
saloutos 0:083111ae2a11 891 }
saloutos 0:083111ae2a11 892
saloutos 0:083111ae2a11 893
saloutos 0:083111ae2a11 894 /** \brief Get CPSR Register
saloutos 0:083111ae2a11 895
saloutos 0:083111ae2a11 896 This function returns the content of the CPSR Register.
saloutos 0:083111ae2a11 897
saloutos 0:083111ae2a11 898 \return CPSR Register value
saloutos 0:083111ae2a11 899 */
saloutos 0:083111ae2a11 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
saloutos 0:083111ae2a11 901 {
saloutos 0:083111ae2a11 902 #if 1
saloutos 0:083111ae2a11 903 register uint32_t __regCPSR;
saloutos 0:083111ae2a11 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
saloutos 0:083111ae2a11 905 #else
saloutos 0:083111ae2a11 906 register uint32_t __regCPSR __ASM("cpsr");
saloutos 0:083111ae2a11 907 #endif
saloutos 0:083111ae2a11 908 return(__regCPSR);
saloutos 0:083111ae2a11 909 }
saloutos 0:083111ae2a11 910
saloutos 0:083111ae2a11 911 #if 0
saloutos 0:083111ae2a11 912 /** \brief Set Stack Pointer
saloutos 0:083111ae2a11 913
saloutos 0:083111ae2a11 914 This function assigns the given value to the current stack pointer.
saloutos 0:083111ae2a11 915
saloutos 0:083111ae2a11 916 \param [in] topOfStack Stack Pointer value to set
saloutos 0:083111ae2a11 917 */
saloutos 0:083111ae2a11 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
saloutos 0:083111ae2a11 919 {
saloutos 0:083111ae2a11 920 register uint32_t __regSP __ASM("sp");
saloutos 0:083111ae2a11 921 __regSP = topOfStack;
saloutos 0:083111ae2a11 922 }
saloutos 0:083111ae2a11 923 #endif
saloutos 0:083111ae2a11 924
saloutos 0:083111ae2a11 925 /** \brief Get link register
saloutos 0:083111ae2a11 926
saloutos 0:083111ae2a11 927 This function returns the value of the link register
saloutos 0:083111ae2a11 928
saloutos 0:083111ae2a11 929 \return Value of link register
saloutos 0:083111ae2a11 930 */
saloutos 0:083111ae2a11 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
saloutos 0:083111ae2a11 932 {
saloutos 0:083111ae2a11 933 register uint32_t __reglr __ASM("lr");
saloutos 0:083111ae2a11 934 return(__reglr);
saloutos 0:083111ae2a11 935 }
saloutos 0:083111ae2a11 936
saloutos 0:083111ae2a11 937 #if 0
saloutos 0:083111ae2a11 938 /** \brief Set link register
saloutos 0:083111ae2a11 939
saloutos 0:083111ae2a11 940 This function sets the value of the link register
saloutos 0:083111ae2a11 941
saloutos 0:083111ae2a11 942 \param [in] lr LR value to set
saloutos 0:083111ae2a11 943 */
saloutos 0:083111ae2a11 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
saloutos 0:083111ae2a11 945 {
saloutos 0:083111ae2a11 946 register uint32_t __reglr __ASM("lr");
saloutos 0:083111ae2a11 947 __reglr = lr;
saloutos 0:083111ae2a11 948 }
saloutos 0:083111ae2a11 949 #endif
saloutos 0:083111ae2a11 950
saloutos 0:083111ae2a11 951 /** \brief Set Process Stack Pointer
saloutos 0:083111ae2a11 952
saloutos 0:083111ae2a11 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
saloutos 0:083111ae2a11 954
saloutos 0:083111ae2a11 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
saloutos 0:083111ae2a11 956 */
saloutos 0:083111ae2a11 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
saloutos 0:083111ae2a11 958 {
saloutos 0:083111ae2a11 959 __asm__ volatile (
saloutos 0:083111ae2a11 960 ".ARM;"
saloutos 0:083111ae2a11 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
saloutos 0:083111ae2a11 962
saloutos 0:083111ae2a11 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
saloutos 0:083111ae2a11 964 "MRS R1, CPSR;"
saloutos 0:083111ae2a11 965 "CPS %0;" /* ;no effect in USR mode */
saloutos 0:083111ae2a11 966 "MOV SP, R0;"
saloutos 0:083111ae2a11 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
saloutos 0:083111ae2a11 968 "ISB;"
saloutos 0:083111ae2a11 969 //"BX LR;"
saloutos 0:083111ae2a11 970 :
saloutos 0:083111ae2a11 971 : "i"(MODE_SYS)
saloutos 0:083111ae2a11 972 : "r0", "r1");
saloutos 0:083111ae2a11 973 return;
saloutos 0:083111ae2a11 974 }
saloutos 0:083111ae2a11 975
saloutos 0:083111ae2a11 976 /** \brief Set User Mode
saloutos 0:083111ae2a11 977
saloutos 0:083111ae2a11 978 This function changes the processor state to User Mode
saloutos 0:083111ae2a11 979 */
saloutos 0:083111ae2a11 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
saloutos 0:083111ae2a11 981 {
saloutos 0:083111ae2a11 982 __asm__ volatile (
saloutos 0:083111ae2a11 983 ".ARM;"
saloutos 0:083111ae2a11 984
saloutos 0:083111ae2a11 985 "CPS %0;"
saloutos 0:083111ae2a11 986 //"BX LR;"
saloutos 0:083111ae2a11 987 :
saloutos 0:083111ae2a11 988 : "i"(MODE_USR)
saloutos 0:083111ae2a11 989 : );
saloutos 0:083111ae2a11 990 return;
saloutos 0:083111ae2a11 991 }
saloutos 0:083111ae2a11 992
saloutos 0:083111ae2a11 993
saloutos 0:083111ae2a11 994 /** \brief Enable FIQ
saloutos 0:083111ae2a11 995
saloutos 0:083111ae2a11 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
saloutos 0:083111ae2a11 997 Can only be executed in Privileged modes.
saloutos 0:083111ae2a11 998 */
saloutos 0:083111ae2a11 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
saloutos 0:083111ae2a11 1000
saloutos 0:083111ae2a11 1001
saloutos 0:083111ae2a11 1002 /** \brief Disable FIQ
saloutos 0:083111ae2a11 1003
saloutos 0:083111ae2a11 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
saloutos 0:083111ae2a11 1005 Can only be executed in Privileged modes.
saloutos 0:083111ae2a11 1006 */
saloutos 0:083111ae2a11 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
saloutos 0:083111ae2a11 1008
saloutos 0:083111ae2a11 1009
saloutos 0:083111ae2a11 1010 /** \brief Get FPSCR
saloutos 0:083111ae2a11 1011
saloutos 0:083111ae2a11 1012 This function returns the current value of the Floating Point Status/Control register.
saloutos 0:083111ae2a11 1013
saloutos 0:083111ae2a11 1014 \return Floating Point Status/Control register value
saloutos 0:083111ae2a11 1015 */
saloutos 0:083111ae2a11 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
saloutos 0:083111ae2a11 1017 {
saloutos 0:083111ae2a11 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
saloutos 0:083111ae2a11 1019 #if 1
saloutos 0:083111ae2a11 1020 uint32_t result;
saloutos 0:083111ae2a11 1021
saloutos 0:083111ae2a11 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
saloutos 0:083111ae2a11 1023 return (result);
saloutos 0:083111ae2a11 1024 #else
saloutos 0:083111ae2a11 1025 register uint32_t __regfpscr __ASM("fpscr");
saloutos 0:083111ae2a11 1026 return(__regfpscr);
saloutos 0:083111ae2a11 1027 #endif
saloutos 0:083111ae2a11 1028 #else
saloutos 0:083111ae2a11 1029 return(0);
saloutos 0:083111ae2a11 1030 #endif
saloutos 0:083111ae2a11 1031 }
saloutos 0:083111ae2a11 1032
saloutos 0:083111ae2a11 1033
saloutos 0:083111ae2a11 1034 /** \brief Set FPSCR
saloutos 0:083111ae2a11 1035
saloutos 0:083111ae2a11 1036 This function assigns the given value to the Floating Point Status/Control register.
saloutos 0:083111ae2a11 1037
saloutos 0:083111ae2a11 1038 \param [in] fpscr Floating Point Status/Control value to set
saloutos 0:083111ae2a11 1039 */
saloutos 0:083111ae2a11 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
saloutos 0:083111ae2a11 1041 {
saloutos 0:083111ae2a11 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
saloutos 0:083111ae2a11 1043 #if 1
saloutos 0:083111ae2a11 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
saloutos 0:083111ae2a11 1045 #else
saloutos 0:083111ae2a11 1046 register uint32_t __regfpscr __ASM("fpscr");
saloutos 0:083111ae2a11 1047 __regfpscr = (fpscr);
saloutos 0:083111ae2a11 1048 #endif
saloutos 0:083111ae2a11 1049 #endif
saloutos 0:083111ae2a11 1050 }
saloutos 0:083111ae2a11 1051
saloutos 0:083111ae2a11 1052 /** \brief Get FPEXC
saloutos 0:083111ae2a11 1053
saloutos 0:083111ae2a11 1054 This function returns the current value of the Floating Point Exception Control register.
saloutos 0:083111ae2a11 1055
saloutos 0:083111ae2a11 1056 \return Floating Point Exception Control register value
saloutos 0:083111ae2a11 1057 */
saloutos 0:083111ae2a11 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
saloutos 0:083111ae2a11 1059 {
saloutos 0:083111ae2a11 1060 #if (__FPU_PRESENT == 1)
saloutos 0:083111ae2a11 1061 #if 1
saloutos 0:083111ae2a11 1062 uint32_t result;
saloutos 0:083111ae2a11 1063
saloutos 0:083111ae2a11 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
saloutos 0:083111ae2a11 1065 return (result);
saloutos 0:083111ae2a11 1066 #else
saloutos 0:083111ae2a11 1067 register uint32_t __regfpexc __ASM("fpexc");
saloutos 0:083111ae2a11 1068 return(__regfpexc);
saloutos 0:083111ae2a11 1069 #endif
saloutos 0:083111ae2a11 1070 #else
saloutos 0:083111ae2a11 1071 return(0);
saloutos 0:083111ae2a11 1072 #endif
saloutos 0:083111ae2a11 1073 }
saloutos 0:083111ae2a11 1074
saloutos 0:083111ae2a11 1075
saloutos 0:083111ae2a11 1076 /** \brief Set FPEXC
saloutos 0:083111ae2a11 1077
saloutos 0:083111ae2a11 1078 This function assigns the given value to the Floating Point Exception Control register.
saloutos 0:083111ae2a11 1079
saloutos 0:083111ae2a11 1080 \param [in] fpscr Floating Point Exception Control value to set
saloutos 0:083111ae2a11 1081 */
saloutos 0:083111ae2a11 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
saloutos 0:083111ae2a11 1083 {
saloutos 0:083111ae2a11 1084 #if (__FPU_PRESENT == 1)
saloutos 0:083111ae2a11 1085 #if 1
saloutos 0:083111ae2a11 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
saloutos 0:083111ae2a11 1087 #else
saloutos 0:083111ae2a11 1088 register uint32_t __regfpexc __ASM("fpexc");
saloutos 0:083111ae2a11 1089 __regfpexc = (fpexc);
saloutos 0:083111ae2a11 1090 #endif
saloutos 0:083111ae2a11 1091 #endif
saloutos 0:083111ae2a11 1092 }
saloutos 0:083111ae2a11 1093
saloutos 0:083111ae2a11 1094 /** \brief Get CPACR
saloutos 0:083111ae2a11 1095
saloutos 0:083111ae2a11 1096 This function returns the current value of the Coprocessor Access Control register.
saloutos 0:083111ae2a11 1097
saloutos 0:083111ae2a11 1098 \return Coprocessor Access Control register value
saloutos 0:083111ae2a11 1099 */
saloutos 0:083111ae2a11 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
saloutos 0:083111ae2a11 1101 {
saloutos 0:083111ae2a11 1102 #if 1
saloutos 0:083111ae2a11 1103 register uint32_t __regCPACR;
saloutos 0:083111ae2a11 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
saloutos 0:083111ae2a11 1105 #else
saloutos 0:083111ae2a11 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
saloutos 0:083111ae2a11 1107 #endif
saloutos 0:083111ae2a11 1108 return __regCPACR;
saloutos 0:083111ae2a11 1109 }
saloutos 0:083111ae2a11 1110
saloutos 0:083111ae2a11 1111 /** \brief Set CPACR
saloutos 0:083111ae2a11 1112
saloutos 0:083111ae2a11 1113 This function assigns the given value to the Coprocessor Access Control register.
saloutos 0:083111ae2a11 1114
saloutos 0:083111ae2a11 1115 \param [in] cpacr Coprocessor Acccess Control value to set
saloutos 0:083111ae2a11 1116 */
saloutos 0:083111ae2a11 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
saloutos 0:083111ae2a11 1118 {
saloutos 0:083111ae2a11 1119 #if 1
saloutos 0:083111ae2a11 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
saloutos 0:083111ae2a11 1121 #else
saloutos 0:083111ae2a11 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
saloutos 0:083111ae2a11 1123 __regCPACR = cpacr;
saloutos 0:083111ae2a11 1124 #endif
saloutos 0:083111ae2a11 1125 __ISB();
saloutos 0:083111ae2a11 1126 }
saloutos 0:083111ae2a11 1127
saloutos 0:083111ae2a11 1128 /** \brief Get CBAR
saloutos 0:083111ae2a11 1129
saloutos 0:083111ae2a11 1130 This function returns the value of the Configuration Base Address register.
saloutos 0:083111ae2a11 1131
saloutos 0:083111ae2a11 1132 \return Configuration Base Address register value
saloutos 0:083111ae2a11 1133 */
saloutos 0:083111ae2a11 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
saloutos 0:083111ae2a11 1135 #if 1
saloutos 0:083111ae2a11 1136 register uint32_t __regCBAR;
saloutos 0:083111ae2a11 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
saloutos 0:083111ae2a11 1138 #else
saloutos 0:083111ae2a11 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
saloutos 0:083111ae2a11 1140 #endif
saloutos 0:083111ae2a11 1141 return(__regCBAR);
saloutos 0:083111ae2a11 1142 }
saloutos 0:083111ae2a11 1143
saloutos 0:083111ae2a11 1144 /** \brief Get TTBR0
saloutos 0:083111ae2a11 1145
saloutos 0:083111ae2a11 1146 This function returns the value of the Translation Table Base Register 0.
saloutos 0:083111ae2a11 1147
saloutos 0:083111ae2a11 1148 \return Translation Table Base Register 0 value
saloutos 0:083111ae2a11 1149 */
saloutos 0:083111ae2a11 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
saloutos 0:083111ae2a11 1151 #if 1
saloutos 0:083111ae2a11 1152 register uint32_t __regTTBR0;
saloutos 0:083111ae2a11 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
saloutos 0:083111ae2a11 1154 #else
saloutos 0:083111ae2a11 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
saloutos 0:083111ae2a11 1156 #endif
saloutos 0:083111ae2a11 1157 return(__regTTBR0);
saloutos 0:083111ae2a11 1158 }
saloutos 0:083111ae2a11 1159
saloutos 0:083111ae2a11 1160 /** \brief Set TTBR0
saloutos 0:083111ae2a11 1161
saloutos 0:083111ae2a11 1162 This function assigns the given value to the Translation Table Base Register 0.
saloutos 0:083111ae2a11 1163
saloutos 0:083111ae2a11 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
saloutos 0:083111ae2a11 1165 */
saloutos 0:083111ae2a11 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
saloutos 0:083111ae2a11 1167 #if 1
saloutos 0:083111ae2a11 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
saloutos 0:083111ae2a11 1169 #else
saloutos 0:083111ae2a11 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
saloutos 0:083111ae2a11 1171 __regTTBR0 = ttbr0;
saloutos 0:083111ae2a11 1172 #endif
saloutos 0:083111ae2a11 1173 __ISB();
saloutos 0:083111ae2a11 1174 }
saloutos 0:083111ae2a11 1175
saloutos 0:083111ae2a11 1176 /** \brief Get DACR
saloutos 0:083111ae2a11 1177
saloutos 0:083111ae2a11 1178 This function returns the value of the Domain Access Control Register.
saloutos 0:083111ae2a11 1179
saloutos 0:083111ae2a11 1180 \return Domain Access Control Register value
saloutos 0:083111ae2a11 1181 */
saloutos 0:083111ae2a11 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
saloutos 0:083111ae2a11 1183 #if 1
saloutos 0:083111ae2a11 1184 register uint32_t __regDACR;
saloutos 0:083111ae2a11 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
saloutos 0:083111ae2a11 1186 #else
saloutos 0:083111ae2a11 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
saloutos 0:083111ae2a11 1188 #endif
saloutos 0:083111ae2a11 1189 return(__regDACR);
saloutos 0:083111ae2a11 1190 }
saloutos 0:083111ae2a11 1191
saloutos 0:083111ae2a11 1192 /** \brief Set DACR
saloutos 0:083111ae2a11 1193
saloutos 0:083111ae2a11 1194 This function assigns the given value to the Domain Access Control Register.
saloutos 0:083111ae2a11 1195
saloutos 0:083111ae2a11 1196 \param [in] dacr Domain Access Control Register value to set
saloutos 0:083111ae2a11 1197 */
saloutos 0:083111ae2a11 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
saloutos 0:083111ae2a11 1199 #if 1
saloutos 0:083111ae2a11 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
saloutos 0:083111ae2a11 1201 #else
saloutos 0:083111ae2a11 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
saloutos 0:083111ae2a11 1203 __regDACR = dacr;
saloutos 0:083111ae2a11 1204 #endif
saloutos 0:083111ae2a11 1205 __ISB();
saloutos 0:083111ae2a11 1206 }
saloutos 0:083111ae2a11 1207
saloutos 0:083111ae2a11 1208 /******************************** Cache and BTAC enable ****************************************************/
saloutos 0:083111ae2a11 1209
saloutos 0:083111ae2a11 1210 /** \brief Set SCTLR
saloutos 0:083111ae2a11 1211
saloutos 0:083111ae2a11 1212 This function assigns the given value to the System Control Register.
saloutos 0:083111ae2a11 1213
saloutos 0:083111ae2a11 1214 \param [in] sctlr System Control Register value to set
saloutos 0:083111ae2a11 1215 */
saloutos 0:083111ae2a11 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
saloutos 0:083111ae2a11 1217 {
saloutos 0:083111ae2a11 1218 #if 1
saloutos 0:083111ae2a11 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
saloutos 0:083111ae2a11 1220 #else
saloutos 0:083111ae2a11 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
saloutos 0:083111ae2a11 1222 __regSCTLR = sctlr;
saloutos 0:083111ae2a11 1223 #endif
saloutos 0:083111ae2a11 1224 }
saloutos 0:083111ae2a11 1225
saloutos 0:083111ae2a11 1226 /** \brief Get SCTLR
saloutos 0:083111ae2a11 1227
saloutos 0:083111ae2a11 1228 This function returns the value of the System Control Register.
saloutos 0:083111ae2a11 1229
saloutos 0:083111ae2a11 1230 \return System Control Register value
saloutos 0:083111ae2a11 1231 */
saloutos 0:083111ae2a11 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
saloutos 0:083111ae2a11 1233 #if 1
saloutos 0:083111ae2a11 1234 register uint32_t __regSCTLR;
saloutos 0:083111ae2a11 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
saloutos 0:083111ae2a11 1236 #else
saloutos 0:083111ae2a11 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
saloutos 0:083111ae2a11 1238 #endif
saloutos 0:083111ae2a11 1239 return(__regSCTLR);
saloutos 0:083111ae2a11 1240 }
saloutos 0:083111ae2a11 1241
saloutos 0:083111ae2a11 1242 /** \brief Enable Caches
saloutos 0:083111ae2a11 1243
saloutos 0:083111ae2a11 1244 Enable Caches
saloutos 0:083111ae2a11 1245 */
saloutos 0:083111ae2a11 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
saloutos 0:083111ae2a11 1247 // Set I bit 12 to enable I Cache
saloutos 0:083111ae2a11 1248 // Set C bit 2 to enable D Cache
saloutos 0:083111ae2a11 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
saloutos 0:083111ae2a11 1250 }
saloutos 0:083111ae2a11 1251
saloutos 0:083111ae2a11 1252 /** \brief Disable Caches
saloutos 0:083111ae2a11 1253
saloutos 0:083111ae2a11 1254 Disable Caches
saloutos 0:083111ae2a11 1255 */
saloutos 0:083111ae2a11 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
saloutos 0:083111ae2a11 1257 // Clear I bit 12 to disable I Cache
saloutos 0:083111ae2a11 1258 // Clear C bit 2 to disable D Cache
saloutos 0:083111ae2a11 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
saloutos 0:083111ae2a11 1260 __ISB();
saloutos 0:083111ae2a11 1261 }
saloutos 0:083111ae2a11 1262
saloutos 0:083111ae2a11 1263 /** \brief Enable BTAC
saloutos 0:083111ae2a11 1264
saloutos 0:083111ae2a11 1265 Enable BTAC
saloutos 0:083111ae2a11 1266 */
saloutos 0:083111ae2a11 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
saloutos 0:083111ae2a11 1268 // Set Z bit 11 to enable branch prediction
saloutos 0:083111ae2a11 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
saloutos 0:083111ae2a11 1270 __ISB();
saloutos 0:083111ae2a11 1271 }
saloutos 0:083111ae2a11 1272
saloutos 0:083111ae2a11 1273 /** \brief Disable BTAC
saloutos 0:083111ae2a11 1274
saloutos 0:083111ae2a11 1275 Disable BTAC
saloutos 0:083111ae2a11 1276 */
saloutos 0:083111ae2a11 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
saloutos 0:083111ae2a11 1278 // Clear Z bit 11 to disable branch prediction
saloutos 0:083111ae2a11 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
saloutos 0:083111ae2a11 1280 }
saloutos 0:083111ae2a11 1281
saloutos 0:083111ae2a11 1282
saloutos 0:083111ae2a11 1283 /** \brief Enable MMU
saloutos 0:083111ae2a11 1284
saloutos 0:083111ae2a11 1285 Enable MMU
saloutos 0:083111ae2a11 1286 */
saloutos 0:083111ae2a11 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
saloutos 0:083111ae2a11 1288 // Set M bit 0 to enable the MMU
saloutos 0:083111ae2a11 1289 // Set AFE bit to enable simplified access permissions model
saloutos 0:083111ae2a11 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
saloutos 0:083111ae2a11 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
saloutos 0:083111ae2a11 1292 __ISB();
saloutos 0:083111ae2a11 1293 }
saloutos 0:083111ae2a11 1294
saloutos 0:083111ae2a11 1295 /** \brief Disable MMU
saloutos 0:083111ae2a11 1296
saloutos 0:083111ae2a11 1297 Disable MMU
saloutos 0:083111ae2a11 1298 */
saloutos 0:083111ae2a11 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
saloutos 0:083111ae2a11 1300 // Clear M bit 0 to disable the MMU
saloutos 0:083111ae2a11 1301 __set_SCTLR( __get_SCTLR() & ~1);
saloutos 0:083111ae2a11 1302 __ISB();
saloutos 0:083111ae2a11 1303 }
saloutos 0:083111ae2a11 1304
saloutos 0:083111ae2a11 1305 /******************************** TLB maintenance operations ************************************************/
saloutos 0:083111ae2a11 1306 /** \brief Invalidate the whole tlb
saloutos 0:083111ae2a11 1307
saloutos 0:083111ae2a11 1308 TLBIALL. Invalidate the whole tlb
saloutos 0:083111ae2a11 1309 */
saloutos 0:083111ae2a11 1310
saloutos 0:083111ae2a11 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
saloutos 0:083111ae2a11 1312 #if 1
saloutos 0:083111ae2a11 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
saloutos 0:083111ae2a11 1314 #else
saloutos 0:083111ae2a11 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
saloutos 0:083111ae2a11 1316 __TLBIALL = 0;
saloutos 0:083111ae2a11 1317 #endif
saloutos 0:083111ae2a11 1318 __DSB();
saloutos 0:083111ae2a11 1319 __ISB();
saloutos 0:083111ae2a11 1320 }
saloutos 0:083111ae2a11 1321
saloutos 0:083111ae2a11 1322 /******************************** BTB maintenance operations ************************************************/
saloutos 0:083111ae2a11 1323 /** \brief Invalidate entire branch predictor array
saloutos 0:083111ae2a11 1324
saloutos 0:083111ae2a11 1325 BPIALL. Branch Predictor Invalidate All.
saloutos 0:083111ae2a11 1326 */
saloutos 0:083111ae2a11 1327
saloutos 0:083111ae2a11 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
saloutos 0:083111ae2a11 1329 #if 1
saloutos 0:083111ae2a11 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
saloutos 0:083111ae2a11 1331 #else
saloutos 0:083111ae2a11 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
saloutos 0:083111ae2a11 1333 __BPIALL = 0;
saloutos 0:083111ae2a11 1334 #endif
saloutos 0:083111ae2a11 1335 __DSB(); //ensure completion of the invalidation
saloutos 0:083111ae2a11 1336 __ISB(); //ensure instruction fetch path sees new state
saloutos 0:083111ae2a11 1337 }
saloutos 0:083111ae2a11 1338
saloutos 0:083111ae2a11 1339
saloutos 0:083111ae2a11 1340 /******************************** L1 cache operations ******************************************************/
saloutos 0:083111ae2a11 1341
saloutos 0:083111ae2a11 1342 /** \brief Invalidate the whole I$
saloutos 0:083111ae2a11 1343
saloutos 0:083111ae2a11 1344 ICIALLU. Instruction Cache Invalidate All to PoU
saloutos 0:083111ae2a11 1345 */
saloutos 0:083111ae2a11 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
saloutos 0:083111ae2a11 1347 #if 1
saloutos 0:083111ae2a11 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
saloutos 0:083111ae2a11 1349 #else
saloutos 0:083111ae2a11 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
saloutos 0:083111ae2a11 1351 __ICIALLU = 0;
saloutos 0:083111ae2a11 1352 #endif
saloutos 0:083111ae2a11 1353 __DSB(); //ensure completion of the invalidation
saloutos 0:083111ae2a11 1354 __ISB(); //ensure instruction fetch path sees new I cache state
saloutos 0:083111ae2a11 1355 }
saloutos 0:083111ae2a11 1356
saloutos 0:083111ae2a11 1357 /** \brief Clean D$ by MVA
saloutos 0:083111ae2a11 1358
saloutos 0:083111ae2a11 1359 DCCMVAC. Data cache clean by MVA to PoC
saloutos 0:083111ae2a11 1360 */
saloutos 0:083111ae2a11 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
saloutos 0:083111ae2a11 1362 #if 1
saloutos 0:083111ae2a11 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
saloutos 0:083111ae2a11 1364 #else
saloutos 0:083111ae2a11 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
saloutos 0:083111ae2a11 1366 __DCCMVAC = (uint32_t)va;
saloutos 0:083111ae2a11 1367 #endif
saloutos 0:083111ae2a11 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
saloutos 0:083111ae2a11 1369 }
saloutos 0:083111ae2a11 1370
saloutos 0:083111ae2a11 1371 /** \brief Invalidate D$ by MVA
saloutos 0:083111ae2a11 1372
saloutos 0:083111ae2a11 1373 DCIMVAC. Data cache invalidate by MVA to PoC
saloutos 0:083111ae2a11 1374 */
saloutos 0:083111ae2a11 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
saloutos 0:083111ae2a11 1376 #if 1
saloutos 0:083111ae2a11 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
saloutos 0:083111ae2a11 1378 #else
saloutos 0:083111ae2a11 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
saloutos 0:083111ae2a11 1380 __DCIMVAC = (uint32_t)va;
saloutos 0:083111ae2a11 1381 #endif
saloutos 0:083111ae2a11 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
saloutos 0:083111ae2a11 1383 }
saloutos 0:083111ae2a11 1384
saloutos 0:083111ae2a11 1385 /** \brief Clean and Invalidate D$ by MVA
saloutos 0:083111ae2a11 1386
saloutos 0:083111ae2a11 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
saloutos 0:083111ae2a11 1388 */
saloutos 0:083111ae2a11 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
saloutos 0:083111ae2a11 1390 #if 1
saloutos 0:083111ae2a11 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
saloutos 0:083111ae2a11 1392 #else
saloutos 0:083111ae2a11 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
saloutos 0:083111ae2a11 1394 __DCCIMVAC = (uint32_t)va;
saloutos 0:083111ae2a11 1395 #endif
saloutos 0:083111ae2a11 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
saloutos 0:083111ae2a11 1397 }
saloutos 0:083111ae2a11 1398
saloutos 0:083111ae2a11 1399 /** \brief Clean and Invalidate the entire data or unified cache
saloutos 0:083111ae2a11 1400
saloutos 0:083111ae2a11 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
saloutos 0:083111ae2a11 1402 */
saloutos 0:083111ae2a11 1403 extern void __v7_all_cache(uint32_t op);
saloutos 0:083111ae2a11 1404
saloutos 0:083111ae2a11 1405
saloutos 0:083111ae2a11 1406 /** \brief Invalidate the whole D$
saloutos 0:083111ae2a11 1407
saloutos 0:083111ae2a11 1408 DCISW. Invalidate by Set/Way
saloutos 0:083111ae2a11 1409 */
saloutos 0:083111ae2a11 1410
saloutos 0:083111ae2a11 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
saloutos 0:083111ae2a11 1412 __v7_all_cache(0);
saloutos 0:083111ae2a11 1413 }
saloutos 0:083111ae2a11 1414
saloutos 0:083111ae2a11 1415 /** \brief Clean the whole D$
saloutos 0:083111ae2a11 1416
saloutos 0:083111ae2a11 1417 DCCSW. Clean by Set/Way
saloutos 0:083111ae2a11 1418 */
saloutos 0:083111ae2a11 1419
saloutos 0:083111ae2a11 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
saloutos 0:083111ae2a11 1421 __v7_all_cache(1);
saloutos 0:083111ae2a11 1422 }
saloutos 0:083111ae2a11 1423
saloutos 0:083111ae2a11 1424 /** \brief Clean and invalidate the whole D$
saloutos 0:083111ae2a11 1425
saloutos 0:083111ae2a11 1426 DCCISW. Clean and Invalidate by Set/Way
saloutos 0:083111ae2a11 1427 */
saloutos 0:083111ae2a11 1428
saloutos 0:083111ae2a11 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
saloutos 0:083111ae2a11 1430 __v7_all_cache(2);
saloutos 0:083111ae2a11 1431 }
saloutos 0:083111ae2a11 1432
saloutos 0:083111ae2a11 1433 #include "core_ca_mmu.h"
saloutos 0:083111ae2a11 1434
saloutos 0:083111ae2a11 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
saloutos 0:083111ae2a11 1436
saloutos 0:083111ae2a11 1437 #error TASKING Compiler support not implemented for Cortex-A
saloutos 0:083111ae2a11 1438
saloutos 0:083111ae2a11 1439 #endif
saloutos 0:083111ae2a11 1440
saloutos 0:083111ae2a11 1441 /*@} end of CMSIS_Core_RegAccFunctions */
saloutos 0:083111ae2a11 1442
saloutos 0:083111ae2a11 1443
saloutos 0:083111ae2a11 1444 #endif /* __CORE_CAFUNC_H__ */