Aditya Mehrotra / mbed-dev

Biomimetics MBED Library w/ Added Support for CAN3

Dependents:   CAN_TEST SPIne_Plus_DYNO_SENSORS SPIne_Plus_v2 SPIne_Plus_Dyno_v2

cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armcc.h@3:993b4d6ff61e, 2021-03-09 (annotated)

Committer:
adimmit
Date:
Tue Mar 09 20:33:24 2021 +0000
Revision:
3:993b4d6ff61e
Parent:
0:083111ae2a11 
added CAN3

Who changed what in which revision?

UserRevisionLine numberNew contents of line
saloutos 0:083111ae2a11 1 /**************************************************************************//**
saloutos 0:083111ae2a11 2 * @file cmsis_armcc.h
saloutos 0:083111ae2a11 3 * @brief CMSIS compiler specific macros, functions, instructions
saloutos 0:083111ae2a11 4 * @version V1.00
saloutos 0:083111ae2a11 5 * @date 22. Feb 2017
saloutos 0:083111ae2a11 6 ******************************************************************************/
saloutos 0:083111ae2a11 7 /*
saloutos 0:083111ae2a11 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
saloutos 0:083111ae2a11 9 *
saloutos 0:083111ae2a11 10 * SPDX-License-Identifier: Apache-2.0
saloutos 0:083111ae2a11 11 *
saloutos 0:083111ae2a11 12 * Licensed under the Apache License, Version 2.0 (the License); you may
saloutos 0:083111ae2a11 13 * not use this file except in compliance with the License.
saloutos 0:083111ae2a11 14 * You may obtain a copy of the License at
saloutos 0:083111ae2a11 15 *
saloutos 0:083111ae2a11 16 * www.apache.org/licenses/LICENSE-2.0
saloutos 0:083111ae2a11 17 *
saloutos 0:083111ae2a11 18 * Unless required by applicable law or agreed to in writing, software
saloutos 0:083111ae2a11 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
saloutos 0:083111ae2a11 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
saloutos 0:083111ae2a11 21 * See the License for the specific language governing permissions and
saloutos 0:083111ae2a11 22 * limitations under the License.
saloutos 0:083111ae2a11 23 */
saloutos 0:083111ae2a11 24
saloutos 0:083111ae2a11 25 #ifndef __CMSIS_ARMCC_H
saloutos 0:083111ae2a11 26 #define __CMSIS_ARMCC_H
saloutos 0:083111ae2a11 27
saloutos 0:083111ae2a11 28 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
saloutos 0:083111ae2a11 29 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
saloutos 0:083111ae2a11 30 #endif
saloutos 0:083111ae2a11 31
saloutos 0:083111ae2a11 32 /* CMSIS compiler control architecture macros */
saloutos 0:083111ae2a11 33 #if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1))
saloutos 0:083111ae2a11 34 #define __ARM_ARCH_7A__ 1
saloutos 0:083111ae2a11 35 #endif
saloutos 0:083111ae2a11 36
saloutos 0:083111ae2a11 37 /* CMSIS compiler specific defines */
saloutos 0:083111ae2a11 38 #ifndef __ASM
saloutos 0:083111ae2a11 39 #define __ASM __asm
saloutos 0:083111ae2a11 40 #endif
saloutos 0:083111ae2a11 41 #ifndef __INLINE
saloutos 0:083111ae2a11 42 #define __INLINE __inline
saloutos 0:083111ae2a11 43 #endif
saloutos 0:083111ae2a11 44 #ifndef __STATIC_INLINE
saloutos 0:083111ae2a11 45 #define __STATIC_INLINE static __inline
saloutos 0:083111ae2a11 46 #endif
saloutos 0:083111ae2a11 47 #ifndef __STATIC_ASM
saloutos 0:083111ae2a11 48 #define __STATIC_ASM static __asm
saloutos 0:083111ae2a11 49 #endif
saloutos 0:083111ae2a11 50 #ifndef __NO_RETURN
saloutos 0:083111ae2a11 51 #define __NO_RETURN __declspec(noreturn)
saloutos 0:083111ae2a11 52 #endif
saloutos 0:083111ae2a11 53 #ifndef __USED
saloutos 0:083111ae2a11 54 #define __USED __attribute__((used))
saloutos 0:083111ae2a11 55 #endif
saloutos 0:083111ae2a11 56 #ifndef __WEAK
saloutos 0:083111ae2a11 57 #define __WEAK __attribute__((weak))
saloutos 0:083111ae2a11 58 #endif
saloutos 0:083111ae2a11 59 #ifndef __UNALIGNED_UINT32
saloutos 0:083111ae2a11 60 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
saloutos 0:083111ae2a11 61 #endif
saloutos 0:083111ae2a11 62 #ifndef __ALIGNED
saloutos 0:083111ae2a11 63 #define __ALIGNED(x) __attribute__((aligned(x)))
saloutos 0:083111ae2a11 64 #endif
saloutos 0:083111ae2a11 65 #ifndef __PACKED
saloutos 0:083111ae2a11 66 #define __PACKED __attribute__((packed))
saloutos 0:083111ae2a11 67 #endif
saloutos 0:083111ae2a11 68
saloutos 0:083111ae2a11 69
saloutos 0:083111ae2a11 70 /* ########################### Core Function Access ########################### */
saloutos 0:083111ae2a11 71
saloutos 0:083111ae2a11 72 /**
saloutos 0:083111ae2a11 73 \brief Get FPSCR
saloutos 0:083111ae2a11 74 \return Floating Point Status/Control register value
saloutos 0:083111ae2a11 75 */
saloutos 0:083111ae2a11 76 __STATIC_INLINE uint32_t __get_FPSCR(void)
saloutos 0:083111ae2a11 77 {
saloutos 0:083111ae2a11 78 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
saloutos 0:083111ae2a11 79 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
saloutos 0:083111ae2a11 80 register uint32_t __regfpscr __ASM("fpscr");
saloutos 0:083111ae2a11 81 return(__regfpscr);
saloutos 0:083111ae2a11 82 #else
saloutos 0:083111ae2a11 83 return(0U);
saloutos 0:083111ae2a11 84 #endif
saloutos 0:083111ae2a11 85 }
saloutos 0:083111ae2a11 86
saloutos 0:083111ae2a11 87 /**
saloutos 0:083111ae2a11 88 \brief Set FPSCR
saloutos 0:083111ae2a11 89 \param [in] fpscr Floating Point Status/Control value to set
saloutos 0:083111ae2a11 90 */
saloutos 0:083111ae2a11 91 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
saloutos 0:083111ae2a11 92 {
saloutos 0:083111ae2a11 93 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
saloutos 0:083111ae2a11 94 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
saloutos 0:083111ae2a11 95 register uint32_t __regfpscr __ASM("fpscr");
saloutos 0:083111ae2a11 96 __regfpscr = (fpscr);
saloutos 0:083111ae2a11 97 #else
saloutos 0:083111ae2a11 98 (void)fpscr;
saloutos 0:083111ae2a11 99 #endif
saloutos 0:083111ae2a11 100 }
saloutos 0:083111ae2a11 101
saloutos 0:083111ae2a11 102 /* ########################## Core Instruction Access ######################### */
saloutos 0:083111ae2a11 103 /**
saloutos 0:083111ae2a11 104 \brief No Operation
saloutos 0:083111ae2a11 105 */
saloutos 0:083111ae2a11 106 #define __NOP __nop
saloutos 0:083111ae2a11 107
saloutos 0:083111ae2a11 108 /**
saloutos 0:083111ae2a11 109 \brief Wait For Interrupt
saloutos 0:083111ae2a11 110 */
saloutos 0:083111ae2a11 111 #define __WFI __wfi
saloutos 0:083111ae2a11 112
saloutos 0:083111ae2a11 113 /**
saloutos 0:083111ae2a11 114 \brief Wait For Event
saloutos 0:083111ae2a11 115 */
saloutos 0:083111ae2a11 116 #define __WFE __wfe
saloutos 0:083111ae2a11 117
saloutos 0:083111ae2a11 118 /**
saloutos 0:083111ae2a11 119 \brief Send Event
saloutos 0:083111ae2a11 120 */
saloutos 0:083111ae2a11 121 #define __SEV __sev
saloutos 0:083111ae2a11 122
saloutos 0:083111ae2a11 123 /**
saloutos 0:083111ae2a11 124 \brief Instruction Synchronization Barrier
saloutos 0:083111ae2a11 125 */
saloutos 0:083111ae2a11 126 #define __ISB() do {\
saloutos 0:083111ae2a11 127 __schedule_barrier();\
saloutos 0:083111ae2a11 128 __isb(0xF);\
saloutos 0:083111ae2a11 129 __schedule_barrier();\
saloutos 0:083111ae2a11 130 } while (0U)
saloutos 0:083111ae2a11 131
saloutos 0:083111ae2a11 132 /**
saloutos 0:083111ae2a11 133 \brief Data Synchronization Barrier
saloutos 0:083111ae2a11 134 */
saloutos 0:083111ae2a11 135 #define __DSB() do {\
saloutos 0:083111ae2a11 136 __schedule_barrier();\
saloutos 0:083111ae2a11 137 __dsb(0xF);\
saloutos 0:083111ae2a11 138 __schedule_barrier();\
saloutos 0:083111ae2a11 139 } while (0U)
saloutos 0:083111ae2a11 140
saloutos 0:083111ae2a11 141 /**
saloutos 0:083111ae2a11 142 \brief Data Memory Barrier
saloutos 0:083111ae2a11 143 */
saloutos 0:083111ae2a11 144 #define __DMB() do {\
saloutos 0:083111ae2a11 145 __schedule_barrier();\
saloutos 0:083111ae2a11 146 __dmb(0xF);\
saloutos 0:083111ae2a11 147 __schedule_barrier();\
saloutos 0:083111ae2a11 148 } while (0U)
saloutos 0:083111ae2a11 149
saloutos 0:083111ae2a11 150 /**
saloutos 0:083111ae2a11 151 \brief Reverse byte order (32 bit)
saloutos 0:083111ae2a11 152 \param [in] value Value to reverse
saloutos 0:083111ae2a11 153 \return Reversed value
saloutos 0:083111ae2a11 154 */
saloutos 0:083111ae2a11 155 #define __REV __rev
saloutos 0:083111ae2a11 156
saloutos 0:083111ae2a11 157 /**
saloutos 0:083111ae2a11 158 \brief Reverse byte order (16 bit)
saloutos 0:083111ae2a11 159 \param [in] value Value to reverse
saloutos 0:083111ae2a11 160 \return Reversed value
saloutos 0:083111ae2a11 161 */
saloutos 0:083111ae2a11 162 #ifndef __NO_EMBEDDED_ASM
saloutos 0:083111ae2a11 163 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
saloutos 0:083111ae2a11 164 {
saloutos 0:083111ae2a11 165 rev16 r0, r0
saloutos 0:083111ae2a11 166 bx lr
saloutos 0:083111ae2a11 167 }
saloutos 0:083111ae2a11 168 #endif
saloutos 0:083111ae2a11 169
saloutos 0:083111ae2a11 170 /**
saloutos 0:083111ae2a11 171 \brief Reverse byte order in signed short value
saloutos 0:083111ae2a11 172 \param [in] value Value to reverse
saloutos 0:083111ae2a11 173 \return Reversed value
saloutos 0:083111ae2a11 174 */
saloutos 0:083111ae2a11 175 #ifndef __NO_EMBEDDED_ASM
saloutos 0:083111ae2a11 176 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
saloutos 0:083111ae2a11 177 {
saloutos 0:083111ae2a11 178 revsh r0, r0
saloutos 0:083111ae2a11 179 bx lr
saloutos 0:083111ae2a11 180 }
saloutos 0:083111ae2a11 181 #endif
saloutos 0:083111ae2a11 182
saloutos 0:083111ae2a11 183 /**
saloutos 0:083111ae2a11 184 \brief Rotate Right in unsigned value (32 bit)
saloutos 0:083111ae2a11 185 \param [in] op1 Value to rotate
saloutos 0:083111ae2a11 186 \param [in] op2 Number of Bits to rotate
saloutos 0:083111ae2a11 187 \return Rotated value
saloutos 0:083111ae2a11 188 */
saloutos 0:083111ae2a11 189 #define __ROR __ror
saloutos 0:083111ae2a11 190
saloutos 0:083111ae2a11 191 /**
saloutos 0:083111ae2a11 192 \brief Breakpoint
saloutos 0:083111ae2a11 193 \param [in] value is ignored by the processor.
saloutos 0:083111ae2a11 194 If required, a debugger can use it to store additional information about the breakpoint.
saloutos 0:083111ae2a11 195 */
saloutos 0:083111ae2a11 196 #define __BKPT(value) __breakpoint(value)
saloutos 0:083111ae2a11 197
saloutos 0:083111ae2a11 198 /**
saloutos 0:083111ae2a11 199 \brief Reverse bit order of value
saloutos 0:083111ae2a11 200 \param [in] value Value to reverse
saloutos 0:083111ae2a11 201 \return Reversed value
saloutos 0:083111ae2a11 202 */
saloutos 0:083111ae2a11 203 #define __RBIT __rbit
saloutos 0:083111ae2a11 204
saloutos 0:083111ae2a11 205 /**
saloutos 0:083111ae2a11 206 \brief Count leading zeros
saloutos 0:083111ae2a11 207 \param [in] value Value to count the leading zeros
saloutos 0:083111ae2a11 208 \return number of leading zeros in value
saloutos 0:083111ae2a11 209 */
saloutos 0:083111ae2a11 210 #define __CLZ __clz
saloutos 0:083111ae2a11 211
saloutos 0:083111ae2a11 212 /** \brief Get CPSR Register
saloutos 0:083111ae2a11 213 \return CPSR Register value
saloutos 0:083111ae2a11 214 */
saloutos 0:083111ae2a11 215 __STATIC_INLINE uint32_t __get_CPSR(void)
saloutos 0:083111ae2a11 216 {
saloutos 0:083111ae2a11 217 register uint32_t __regCPSR __ASM("cpsr");
saloutos 0:083111ae2a11 218 return(__regCPSR);
saloutos 0:083111ae2a11 219 }
saloutos 0:083111ae2a11 220
saloutos 0:083111ae2a11 221
saloutos 0:083111ae2a11 222 /** \brief Set CPSR Register
saloutos 0:083111ae2a11 223 \param [in] cpsr CPSR value to set
saloutos 0:083111ae2a11 224 */
saloutos 0:083111ae2a11 225 __STATIC_INLINE void __set_CPSR(uint32_t cpsr)
saloutos 0:083111ae2a11 226 {
saloutos 0:083111ae2a11 227 register uint32_t __regCPSR __ASM("cpsr");
saloutos 0:083111ae2a11 228 __regCPSR = cpsr;
saloutos 0:083111ae2a11 229 }
saloutos 0:083111ae2a11 230
saloutos 0:083111ae2a11 231 /** \brief Get Mode
saloutos 0:083111ae2a11 232 \return Processor Mode
saloutos 0:083111ae2a11 233 */
saloutos 0:083111ae2a11 234 __STATIC_INLINE uint32_t __get_mode(void) {
saloutos 0:083111ae2a11 235 return (__get_CPSR() & 0x1FU);
saloutos 0:083111ae2a11 236 }
saloutos 0:083111ae2a11 237
saloutos 0:083111ae2a11 238 /** \brief Set Mode
saloutos 0:083111ae2a11 239 \param [in] mode Mode value to set
saloutos 0:083111ae2a11 240 */
saloutos 0:083111ae2a11 241 __STATIC_INLINE __ASM void __set_mode(uint32_t mode) {
saloutos 0:083111ae2a11 242 MOV r1, lr
saloutos 0:083111ae2a11 243 MSR CPSR_C, r0
saloutos 0:083111ae2a11 244 BX r1
saloutos 0:083111ae2a11 245 }
saloutos 0:083111ae2a11 246
saloutos 0:083111ae2a11 247 /** \brief Set Stack Pointer
saloutos 0:083111ae2a11 248 \param [in] stack Stack Pointer value to set
saloutos 0:083111ae2a11 249 */
saloutos 0:083111ae2a11 250 __STATIC_INLINE __ASM void __set_SP(uint32_t stack)
saloutos 0:083111ae2a11 251 {
saloutos 0:083111ae2a11 252 MOV sp, r0
saloutos 0:083111ae2a11 253 BX lr
saloutos 0:083111ae2a11 254 }
saloutos 0:083111ae2a11 255
saloutos 0:083111ae2a11 256 /** \brief Set Process Stack Pointer
saloutos 0:083111ae2a11 257 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
saloutos 0:083111ae2a11 258 */
saloutos 0:083111ae2a11 259 __STATIC_INLINE __ASM void __set_PSP(uint32_t topOfProcStack)
saloutos 0:083111ae2a11 260 {
saloutos 0:083111ae2a11 261 ARM
saloutos 0:083111ae2a11 262 PRESERVE8
saloutos 0:083111ae2a11 263
saloutos 0:083111ae2a11 264 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
saloutos 0:083111ae2a11 265 MRS R1, CPSR
saloutos 0:083111ae2a11 266 CPS #0x1F ;no effect in USR mode
saloutos 0:083111ae2a11 267 MOV SP, R0
saloutos 0:083111ae2a11 268 MSR CPSR_c, R1 ;no effect in USR mode
saloutos 0:083111ae2a11 269 ISB
saloutos 0:083111ae2a11 270 BX LR
saloutos 0:083111ae2a11 271 }
saloutos 0:083111ae2a11 272
saloutos 0:083111ae2a11 273 /** \brief Set User Mode
saloutos 0:083111ae2a11 274 */
saloutos 0:083111ae2a11 275 __STATIC_INLINE __ASM void __set_CPS_USR(void)
saloutos 0:083111ae2a11 276 {
saloutos 0:083111ae2a11 277 ARM
saloutos 0:083111ae2a11 278
saloutos 0:083111ae2a11 279 CPS #0x10
saloutos 0:083111ae2a11 280 BX LR
saloutos 0:083111ae2a11 281 }
saloutos 0:083111ae2a11 282
saloutos 0:083111ae2a11 283 /** \brief Get FPEXC
saloutos 0:083111ae2a11 284 \return Floating Point Exception Control register value
saloutos 0:083111ae2a11 285 */
saloutos 0:083111ae2a11 286 __STATIC_INLINE uint32_t __get_FPEXC(void)
saloutos 0:083111ae2a11 287 {
saloutos 0:083111ae2a11 288 #if (__FPU_PRESENT == 1)
saloutos 0:083111ae2a11 289 register uint32_t __regfpexc __ASM("fpexc");
saloutos 0:083111ae2a11 290 return(__regfpexc);
saloutos 0:083111ae2a11 291 #else
saloutos 0:083111ae2a11 292 return(0);
saloutos 0:083111ae2a11 293 #endif
saloutos 0:083111ae2a11 294 }
saloutos 0:083111ae2a11 295
saloutos 0:083111ae2a11 296 /** \brief Set FPEXC
saloutos 0:083111ae2a11 297 \param [in] fpexc Floating Point Exception Control value to set
saloutos 0:083111ae2a11 298 */
saloutos 0:083111ae2a11 299 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
saloutos 0:083111ae2a11 300 {
saloutos 0:083111ae2a11 301 #if (__FPU_PRESENT == 1)
saloutos 0:083111ae2a11 302 register uint32_t __regfpexc __ASM("fpexc");
saloutos 0:083111ae2a11 303 __regfpexc = (fpexc);
saloutos 0:083111ae2a11 304 #endif
saloutos 0:083111ae2a11 305 }
saloutos 0:083111ae2a11 306
saloutos 0:083111ae2a11 307 /** \brief Get CPACR
saloutos 0:083111ae2a11 308 \return Coprocessor Access Control register value
saloutos 0:083111ae2a11 309 */
saloutos 0:083111ae2a11 310 __STATIC_INLINE uint32_t __get_CPACR(void)
saloutos 0:083111ae2a11 311 {
saloutos 0:083111ae2a11 312 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
saloutos 0:083111ae2a11 313 return __regCPACR;
saloutos 0:083111ae2a11 314 }
saloutos 0:083111ae2a11 315
saloutos 0:083111ae2a11 316 /** \brief Set CPACR
saloutos 0:083111ae2a11 317 \param [in] cpacr Coprocessor Acccess Control value to set
saloutos 0:083111ae2a11 318 */
saloutos 0:083111ae2a11 319 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
saloutos 0:083111ae2a11 320 {
saloutos 0:083111ae2a11 321 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
saloutos 0:083111ae2a11 322 __regCPACR = cpacr;
saloutos 0:083111ae2a11 323 }
saloutos 0:083111ae2a11 324
saloutos 0:083111ae2a11 325 /** \brief Get CBAR
saloutos 0:083111ae2a11 326 \return Configuration Base Address register value
saloutos 0:083111ae2a11 327 */
saloutos 0:083111ae2a11 328 __STATIC_INLINE uint32_t __get_CBAR() {
saloutos 0:083111ae2a11 329 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
saloutos 0:083111ae2a11 330 return(__regCBAR);
saloutos 0:083111ae2a11 331 }
saloutos 0:083111ae2a11 332
saloutos 0:083111ae2a11 333 /** \brief Get TTBR0
saloutos 0:083111ae2a11 334
saloutos 0:083111ae2a11 335 This function returns the value of the Translation Table Base Register 0.
saloutos 0:083111ae2a11 336
saloutos 0:083111ae2a11 337 \return Translation Table Base Register 0 value
saloutos 0:083111ae2a11 338 */
saloutos 0:083111ae2a11 339 __STATIC_INLINE uint32_t __get_TTBR0() {
saloutos 0:083111ae2a11 340 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
saloutos 0:083111ae2a11 341 return(__regTTBR0);
saloutos 0:083111ae2a11 342 }
saloutos 0:083111ae2a11 343
saloutos 0:083111ae2a11 344 /** \brief Set TTBR0
saloutos 0:083111ae2a11 345
saloutos 0:083111ae2a11 346 This function assigns the given value to the Translation Table Base Register 0.
saloutos 0:083111ae2a11 347
saloutos 0:083111ae2a11 348 \param [in] ttbr0 Translation Table Base Register 0 value to set
saloutos 0:083111ae2a11 349 */
saloutos 0:083111ae2a11 350 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
saloutos 0:083111ae2a11 351 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
saloutos 0:083111ae2a11 352 __regTTBR0 = ttbr0;
saloutos 0:083111ae2a11 353 }
saloutos 0:083111ae2a11 354
saloutos 0:083111ae2a11 355 /** \brief Get DACR
saloutos 0:083111ae2a11 356
saloutos 0:083111ae2a11 357 This function returns the value of the Domain Access Control Register.
saloutos 0:083111ae2a11 358
saloutos 0:083111ae2a11 359 \return Domain Access Control Register value
saloutos 0:083111ae2a11 360 */
saloutos 0:083111ae2a11 361 __STATIC_INLINE uint32_t __get_DACR() {
saloutos 0:083111ae2a11 362 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
saloutos 0:083111ae2a11 363 return(__regDACR);
saloutos 0:083111ae2a11 364 }
saloutos 0:083111ae2a11 365
saloutos 0:083111ae2a11 366 /** \brief Set DACR
saloutos 0:083111ae2a11 367
saloutos 0:083111ae2a11 368 This function assigns the given value to the Domain Access Control Register.
saloutos 0:083111ae2a11 369
saloutos 0:083111ae2a11 370 \param [in] dacr Domain Access Control Register value to set
saloutos 0:083111ae2a11 371 */
saloutos 0:083111ae2a11 372 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
saloutos 0:083111ae2a11 373 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
saloutos 0:083111ae2a11 374 __regDACR = dacr;
saloutos 0:083111ae2a11 375 }
saloutos 0:083111ae2a11 376
saloutos 0:083111ae2a11 377 /** \brief Set SCTLR
saloutos 0:083111ae2a11 378
saloutos 0:083111ae2a11 379 This function assigns the given value to the System Control Register.
saloutos 0:083111ae2a11 380
saloutos 0:083111ae2a11 381 \param [in] sctlr System Control Register value to set
saloutos 0:083111ae2a11 382 */
saloutos 0:083111ae2a11 383 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
saloutos 0:083111ae2a11 384 {
saloutos 0:083111ae2a11 385 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
saloutos 0:083111ae2a11 386 __regSCTLR = sctlr;
saloutos 0:083111ae2a11 387 }
saloutos 0:083111ae2a11 388
saloutos 0:083111ae2a11 389 /** \brief Get SCTLR
saloutos 0:083111ae2a11 390 \return System Control Register value
saloutos 0:083111ae2a11 391 */
saloutos 0:083111ae2a11 392 __STATIC_INLINE uint32_t __get_SCTLR() {
saloutos 0:083111ae2a11 393 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
saloutos 0:083111ae2a11 394 return(__regSCTLR);
saloutos 0:083111ae2a11 395 }
saloutos 0:083111ae2a11 396
saloutos 0:083111ae2a11 397 /** \brief Set ACTRL
saloutos 0:083111ae2a11 398 \param [in] actrl Auxiliary Control Register value to set
saloutos 0:083111ae2a11 399 */
saloutos 0:083111ae2a11 400 __STATIC_INLINE void __set_ACTRL(uint32_t actrl)
saloutos 0:083111ae2a11 401 {
saloutos 0:083111ae2a11 402 register uint32_t __regACTRL __ASM("cp15:0:c1:c0:1");
saloutos 0:083111ae2a11 403 __regACTRL = actrl;
saloutos 0:083111ae2a11 404 }
saloutos 0:083111ae2a11 405
saloutos 0:083111ae2a11 406 /** \brief Get ACTRL
saloutos 0:083111ae2a11 407 \return Auxiliary Control Register value
saloutos 0:083111ae2a11 408 */
saloutos 0:083111ae2a11 409 __STATIC_INLINE uint32_t __get_ACTRL(void)
saloutos 0:083111ae2a11 410 {
saloutos 0:083111ae2a11 411 register uint32_t __regACTRL __ASM("cp15:0:c1:c0:1");
saloutos 0:083111ae2a11 412 return(__regACTRL);
saloutos 0:083111ae2a11 413 }
saloutos 0:083111ae2a11 414
saloutos 0:083111ae2a11 415 /** \brief Get MPIDR
saloutos 0:083111ae2a11 416
saloutos 0:083111ae2a11 417 This function returns the value of the Multiprocessor Affinity Register.
saloutos 0:083111ae2a11 418
saloutos 0:083111ae2a11 419 \return Multiprocessor Affinity Register value
saloutos 0:083111ae2a11 420 */
saloutos 0:083111ae2a11 421 __STATIC_INLINE uint32_t __get_MPIDR(void)
saloutos 0:083111ae2a11 422 {
saloutos 0:083111ae2a11 423 register uint32_t __regMPIDR __ASM("cp15:0:c0:c0:5");
saloutos 0:083111ae2a11 424 return(__regMPIDR);
saloutos 0:083111ae2a11 425 }
saloutos 0:083111ae2a11 426
saloutos 0:083111ae2a11 427 /** \brief Get VBAR
saloutos 0:083111ae2a11 428
saloutos 0:083111ae2a11 429 This function returns the value of the Vector Base Address Register.
saloutos 0:083111ae2a11 430
saloutos 0:083111ae2a11 431 \return Vector Base Address Register
saloutos 0:083111ae2a11 432 */
saloutos 0:083111ae2a11 433 __STATIC_INLINE uint32_t __get_VBAR(void)
saloutos 0:083111ae2a11 434 {
saloutos 0:083111ae2a11 435 register uint32_t __regVBAR __ASM("cp15:0:c12:c0:0");
saloutos 0:083111ae2a11 436 return(__regVBAR);
saloutos 0:083111ae2a11 437 }
saloutos 0:083111ae2a11 438
saloutos 0:083111ae2a11 439 /** \brief Set VBAR
saloutos 0:083111ae2a11 440
saloutos 0:083111ae2a11 441 This function assigns the given value to the Vector Base Address Register.
saloutos 0:083111ae2a11 442
saloutos 0:083111ae2a11 443 \param [in] vbar Vector Base Address Register value to set
saloutos 0:083111ae2a11 444 */
saloutos 0:083111ae2a11 445 __STATIC_INLINE void __set_VBAR(uint32_t vbar)
saloutos 0:083111ae2a11 446 {
saloutos 0:083111ae2a11 447 register uint32_t __regVBAR __ASM("cp15:0:c12:c0:0");
saloutos 0:083111ae2a11 448 __regVBAR = vbar;
saloutos 0:083111ae2a11 449 }
saloutos 0:083111ae2a11 450
saloutos 0:083111ae2a11 451 /** \brief Set CNTP_TVAL
saloutos 0:083111ae2a11 452
saloutos 0:083111ae2a11 453 This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
saloutos 0:083111ae2a11 454
saloutos 0:083111ae2a11 455 \param [in] value CNTP_TVAL Register value to set
saloutos 0:083111ae2a11 456 */
saloutos 0:083111ae2a11 457 __STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
saloutos 0:083111ae2a11 458 register uint32_t __regCNTP_TVAL __ASM("cp15:0:c14:c2:0");
saloutos 0:083111ae2a11 459 __regCNTP_TVAL = value;
saloutos 0:083111ae2a11 460 }
saloutos 0:083111ae2a11 461
saloutos 0:083111ae2a11 462 /** \brief Get CNTP_TVAL
saloutos 0:083111ae2a11 463
saloutos 0:083111ae2a11 464 This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
saloutos 0:083111ae2a11 465
saloutos 0:083111ae2a11 466 \return CNTP_TVAL Register value
saloutos 0:083111ae2a11 467 */
saloutos 0:083111ae2a11 468 __STATIC_INLINE uint32_t __get_CNTP_TVAL() {
saloutos 0:083111ae2a11 469 register uint32_t __regCNTP_TVAL __ASM("cp15:0:c14:c2:0");
saloutos 0:083111ae2a11 470 return(__regCNTP_TVAL);
saloutos 0:083111ae2a11 471 }
saloutos 0:083111ae2a11 472
saloutos 0:083111ae2a11 473 /** \brief Set CNTP_CTL
saloutos 0:083111ae2a11 474
saloutos 0:083111ae2a11 475 This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
saloutos 0:083111ae2a11 476
saloutos 0:083111ae2a11 477 \param [in] value CNTP_CTL Register value to set
saloutos 0:083111ae2a11 478 */
saloutos 0:083111ae2a11 479 __STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
saloutos 0:083111ae2a11 480 register uint32_t __regCNTP_CTL __ASM("cp15:0:c14:c2:1");
saloutos 0:083111ae2a11 481 __regCNTP_CTL = value;
saloutos 0:083111ae2a11 482 }
saloutos 0:083111ae2a11 483
saloutos 0:083111ae2a11 484 /** \brief Set TLBIALL
saloutos 0:083111ae2a11 485
saloutos 0:083111ae2a11 486 TLB Invalidate All
saloutos 0:083111ae2a11 487 */
saloutos 0:083111ae2a11 488 __STATIC_INLINE void __set_TLBIALL(uint32_t value) {
saloutos 0:083111ae2a11 489 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
saloutos 0:083111ae2a11 490 __TLBIALL = value;
saloutos 0:083111ae2a11 491 }
saloutos 0:083111ae2a11 492
saloutos 0:083111ae2a11 493 /** \brief Set BPIALL.
saloutos 0:083111ae2a11 494
saloutos 0:083111ae2a11 495 Branch Predictor Invalidate All
saloutos 0:083111ae2a11 496 */
saloutos 0:083111ae2a11 497 __STATIC_INLINE void __set_BPIALL(uint32_t value) {
saloutos 0:083111ae2a11 498 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
saloutos 0:083111ae2a11 499 __BPIALL = value;
saloutos 0:083111ae2a11 500 }
saloutos 0:083111ae2a11 501
saloutos 0:083111ae2a11 502 /** \brief Set ICIALLU
saloutos 0:083111ae2a11 503
saloutos 0:083111ae2a11 504 Instruction Cache Invalidate All
saloutos 0:083111ae2a11 505 */
saloutos 0:083111ae2a11 506 __STATIC_INLINE void __set_ICIALLU(uint32_t value) {
saloutos 0:083111ae2a11 507 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
saloutos 0:083111ae2a11 508 __ICIALLU = value;
saloutos 0:083111ae2a11 509 }
saloutos 0:083111ae2a11 510
saloutos 0:083111ae2a11 511 /** \brief Set DCCMVAC
saloutos 0:083111ae2a11 512
saloutos 0:083111ae2a11 513 Data cache clean
saloutos 0:083111ae2a11 514 */
saloutos 0:083111ae2a11 515 __STATIC_INLINE void __set_DCCMVAC(uint32_t value) {
saloutos 0:083111ae2a11 516 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
saloutos 0:083111ae2a11 517 __DCCMVAC = value;
saloutos 0:083111ae2a11 518 }
saloutos 0:083111ae2a11 519
saloutos 0:083111ae2a11 520 /** \brief Set DCIMVAC
saloutos 0:083111ae2a11 521
saloutos 0:083111ae2a11 522 Data cache invalidate
saloutos 0:083111ae2a11 523 */
saloutos 0:083111ae2a11 524 __STATIC_INLINE void __set_DCIMVAC(uint32_t value) {
saloutos 0:083111ae2a11 525 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
saloutos 0:083111ae2a11 526 __DCIMVAC = value;
saloutos 0:083111ae2a11 527 }
saloutos 0:083111ae2a11 528
saloutos 0:083111ae2a11 529 /** \brief Set DCCIMVAC
saloutos 0:083111ae2a11 530
saloutos 0:083111ae2a11 531 Data cache clean and invalidate
saloutos 0:083111ae2a11 532 */
saloutos 0:083111ae2a11 533 __STATIC_INLINE void __set_DCCIMVAC(uint32_t value) {
saloutos 0:083111ae2a11 534 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
saloutos 0:083111ae2a11 535 __DCCIMVAC = value;
saloutos 0:083111ae2a11 536 }
saloutos 0:083111ae2a11 537
saloutos 0:083111ae2a11 538 /** \brief Clean and Invalidate the entire data or unified cache
saloutos 0:083111ae2a11 539
saloutos 0:083111ae2a11 540 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
saloutos 0:083111ae2a11 541 */
saloutos 0:083111ae2a11 542 #pragma push
saloutos 0:083111ae2a11 543 #pragma arm
saloutos 0:083111ae2a11 544 __STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) {
saloutos 0:083111ae2a11 545 ARM
saloutos 0:083111ae2a11 546
saloutos 0:083111ae2a11 547 PUSH {R4-R11}
saloutos 0:083111ae2a11 548
saloutos 0:083111ae2a11 549 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
saloutos 0:083111ae2a11 550 ANDS R3, R6, #0x07000000 // Extract coherency level
saloutos 0:083111ae2a11 551 MOV R3, R3, LSR #23 // Total cache levels << 1
saloutos 0:083111ae2a11 552 BEQ Finished // If 0, no need to clean
saloutos 0:083111ae2a11 553
saloutos 0:083111ae2a11 554 MOV R10, #0 // R10 holds current cache level << 1
saloutos 0:083111ae2a11 555 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
saloutos 0:083111ae2a11 556 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
saloutos 0:083111ae2a11 557 AND R1, R1, #7 // Isolate those lower 3 bits
saloutos 0:083111ae2a11 558 CMP R1, #2
saloutos 0:083111ae2a11 559 BLT Skip // No cache or only instruction cache at this level
saloutos 0:083111ae2a11 560
saloutos 0:083111ae2a11 561 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
saloutos 0:083111ae2a11 562 ISB // ISB to sync the change to the CacheSizeID reg
saloutos 0:083111ae2a11 563 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
saloutos 0:083111ae2a11 564 AND R2, R1, #7 // Extract the line length field
saloutos 0:083111ae2a11 565 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
saloutos 0:083111ae2a11 566 LDR R4, =0x3FF
saloutos 0:083111ae2a11 567 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
saloutos 0:083111ae2a11 568 CLZ R5, R4 // R5 is the bit position of the way size increment
saloutos 0:083111ae2a11 569 LDR R7, =0x7FFF
saloutos 0:083111ae2a11 570 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
saloutos 0:083111ae2a11 571
saloutos 0:083111ae2a11 572 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
saloutos 0:083111ae2a11 573
saloutos 0:083111ae2a11 574 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
saloutos 0:083111ae2a11 575 ORR R11, R11, R7, LSL R2 // Factor in the Set number
saloutos 0:083111ae2a11 576 CMP R0, #0
saloutos 0:083111ae2a11 577 BNE Dccsw
saloutos 0:083111ae2a11 578 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
saloutos 0:083111ae2a11 579 B cont
saloutos 0:083111ae2a11 580 Dccsw CMP R0, #1
saloutos 0:083111ae2a11 581 BNE Dccisw
saloutos 0:083111ae2a11 582 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
saloutos 0:083111ae2a11 583 B cont
saloutos 0:083111ae2a11 584 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
saloutos 0:083111ae2a11 585 cont SUBS R9, R9, #1 // Decrement the Way number
saloutos 0:083111ae2a11 586 BGE Loop3
saloutos 0:083111ae2a11 587 SUBS R7, R7, #1 // Decrement the Set number
saloutos 0:083111ae2a11 588 BGE Loop2
saloutos 0:083111ae2a11 589 Skip ADD R10, R10, #2 // Increment the cache number
saloutos 0:083111ae2a11 590 CMP R3, R10
saloutos 0:083111ae2a11 591 BGT Loop1
saloutos 0:083111ae2a11 592
saloutos 0:083111ae2a11 593 Finished
saloutos 0:083111ae2a11 594 DSB
saloutos 0:083111ae2a11 595 POP {R4-R11}
saloutos 0:083111ae2a11 596 BX lr
saloutos 0:083111ae2a11 597 }
saloutos 0:083111ae2a11 598 #pragma pop
saloutos 0:083111ae2a11 599
saloutos 0:083111ae2a11 600 /** \brief Enable Floating Point Unit
saloutos 0:083111ae2a11 601
saloutos 0:083111ae2a11 602 Critical section, called from undef handler, so systick is disabled
saloutos 0:083111ae2a11 603 */
saloutos 0:083111ae2a11 604 #pragma push
saloutos 0:083111ae2a11 605 #pragma arm
saloutos 0:083111ae2a11 606 __STATIC_INLINE __ASM void __FPU_Enable(void) {
saloutos 0:083111ae2a11 607 ARM
saloutos 0:083111ae2a11 608
saloutos 0:083111ae2a11 609 //Permit access to VFP/NEON, registers by modifying CPACR
saloutos 0:083111ae2a11 610 MRC p15,0,R1,c1,c0,2
saloutos 0:083111ae2a11 611 ORR R1,R1,#0x00F00000
saloutos 0:083111ae2a11 612 MCR p15,0,R1,c1,c0,2
saloutos 0:083111ae2a11 613
saloutos 0:083111ae2a11 614 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
saloutos 0:083111ae2a11 615 ISB
saloutos 0:083111ae2a11 616
saloutos 0:083111ae2a11 617 //Enable VFP/NEON
saloutos 0:083111ae2a11 618 VMRS R1,FPEXC
saloutos 0:083111ae2a11 619 ORR R1,R1,#0x40000000
saloutos 0:083111ae2a11 620 VMSR FPEXC,R1
saloutos 0:083111ae2a11 621
saloutos 0:083111ae2a11 622 //Initialise VFP/NEON registers to 0
saloutos 0:083111ae2a11 623 MOV R2,#0
saloutos 0:083111ae2a11 624 IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16
saloutos 0:083111ae2a11 625 //Initialise D16 registers to 0
saloutos 0:083111ae2a11 626 VMOV D0, R2,R2
saloutos 0:083111ae2a11 627 VMOV D1, R2,R2
saloutos 0:083111ae2a11 628 VMOV D2, R2,R2
saloutos 0:083111ae2a11 629 VMOV D3, R2,R2
saloutos 0:083111ae2a11 630 VMOV D4, R2,R2
saloutos 0:083111ae2a11 631 VMOV D5, R2,R2
saloutos 0:083111ae2a11 632 VMOV D6, R2,R2
saloutos 0:083111ae2a11 633 VMOV D7, R2,R2
saloutos 0:083111ae2a11 634 VMOV D8, R2,R2
saloutos 0:083111ae2a11 635 VMOV D9, R2,R2
saloutos 0:083111ae2a11 636 VMOV D10,R2,R2
saloutos 0:083111ae2a11 637 VMOV D11,R2,R2
saloutos 0:083111ae2a11 638 VMOV D12,R2,R2
saloutos 0:083111ae2a11 639 VMOV D13,R2,R2
saloutos 0:083111ae2a11 640 VMOV D14,R2,R2
saloutos 0:083111ae2a11 641 VMOV D15,R2,R2
saloutos 0:083111ae2a11 642 ENDIF
saloutos 0:083111ae2a11 643 IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
saloutos 0:083111ae2a11 644 //Initialise D32 registers to 0
saloutos 0:083111ae2a11 645 VMOV D16,R2,R2
saloutos 0:083111ae2a11 646 VMOV D17,R2,R2
saloutos 0:083111ae2a11 647 VMOV D18,R2,R2
saloutos 0:083111ae2a11 648 VMOV D19,R2,R2
saloutos 0:083111ae2a11 649 VMOV D20,R2,R2
saloutos 0:083111ae2a11 650 VMOV D21,R2,R2
saloutos 0:083111ae2a11 651 VMOV D22,R2,R2
saloutos 0:083111ae2a11 652 VMOV D23,R2,R2
saloutos 0:083111ae2a11 653 VMOV D24,R2,R2
saloutos 0:083111ae2a11 654 VMOV D25,R2,R2
saloutos 0:083111ae2a11 655 VMOV D26,R2,R2
saloutos 0:083111ae2a11 656 VMOV D27,R2,R2
saloutos 0:083111ae2a11 657 VMOV D28,R2,R2
saloutos 0:083111ae2a11 658 VMOV D29,R2,R2
saloutos 0:083111ae2a11 659 VMOV D30,R2,R2
saloutos 0:083111ae2a11 660 VMOV D31,R2,R2
saloutos 0:083111ae2a11 661 ENDIF
saloutos 0:083111ae2a11 662
saloutos 0:083111ae2a11 663 //Initialise FPSCR to a known state
saloutos 0:083111ae2a11 664 VMRS R2,FPSCR
saloutos 0:083111ae2a11 665 LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
saloutos 0:083111ae2a11 666 AND R2,R2,R3
saloutos 0:083111ae2a11 667 VMSR FPSCR,R2
saloutos 0:083111ae2a11 668
saloutos 0:083111ae2a11 669 BX LR
saloutos 0:083111ae2a11 670 }
saloutos 0:083111ae2a11 671 #pragma pop
saloutos 0:083111ae2a11 672
saloutos 0:083111ae2a11 673 #endif /* __CMSIS_ARMCC_H */