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Dependents: CAN_TEST SPIne_Plus_DYNO_SENSORS SPIne_Plus_v2 SPIne_Plus_Dyno_v2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h@0:083111ae2a11, 2020-11-26 (annotated)

Committer:: saloutos
Date:: Thu Nov 26 04:08:56 2020 +0000
Revision:: 0:083111ae2a11

first commit of leaned mbed dev lib

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saloutos	0:083111ae2a11	1	/**
saloutos	0:083111ae2a11	2	******************************************************************************
saloutos	0:083111ae2a11	3	* @file stm32f4xx_ll_fmc.h
saloutos	0:083111ae2a11	4	* @author MCD Application Team
saloutos	0:083111ae2a11	5	* @version V1.7.1
saloutos	0:083111ae2a11	6	* @date 14-April-2017
saloutos	0:083111ae2a11	7	* @brief Header file of FMC HAL module.
saloutos	0:083111ae2a11	8	******************************************************************************
saloutos	0:083111ae2a11	9	* @attention
saloutos	0:083111ae2a11	10	*
saloutos	0:083111ae2a11	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
saloutos	0:083111ae2a11	12	*
saloutos	0:083111ae2a11	13	* Redistribution and use in source and binary forms, with or without modification,
saloutos	0:083111ae2a11	14	* are permitted provided that the following conditions are met:
saloutos	0:083111ae2a11	15	* 1. Redistributions of source code must retain the above copyright notice,
saloutos	0:083111ae2a11	16	* this list of conditions and the following disclaimer.
saloutos	0:083111ae2a11	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
saloutos	0:083111ae2a11	18	* this list of conditions and the following disclaimer in the documentation
saloutos	0:083111ae2a11	19	* and/or other materials provided with the distribution.
saloutos	0:083111ae2a11	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
saloutos	0:083111ae2a11	21	* may be used to endorse or promote products derived from this software
saloutos	0:083111ae2a11	22	* without specific prior written permission.
saloutos	0:083111ae2a11	23	*
saloutos	0:083111ae2a11	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
saloutos	0:083111ae2a11	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
saloutos	0:083111ae2a11	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
saloutos	0:083111ae2a11	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
saloutos	0:083111ae2a11	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
saloutos	0:083111ae2a11	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
saloutos	0:083111ae2a11	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
saloutos	0:083111ae2a11	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
saloutos	0:083111ae2a11	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
saloutos	0:083111ae2a11	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
saloutos	0:083111ae2a11	34	*
saloutos	0:083111ae2a11	35	******************************************************************************
saloutos	0:083111ae2a11	36	*/
saloutos	0:083111ae2a11	37
saloutos	0:083111ae2a11	38	/* Define to prevent recursive inclusion -------------------------------------*/
saloutos	0:083111ae2a11	39	#ifndef __STM32F4xx_LL_FMC_H
saloutos	0:083111ae2a11	40	#define __STM32F4xx_LL_FMC_H
saloutos	0:083111ae2a11	41
saloutos	0:083111ae2a11	42	#ifdef __cplusplus
saloutos	0:083111ae2a11	43	extern "C" {
saloutos	0:083111ae2a11	44	#endif
saloutos	0:083111ae2a11	45
saloutos	0:083111ae2a11	46	/* Includes ------------------------------------------------------------------*/
saloutos	0:083111ae2a11	47	#include "stm32f4xx_hal_def.h"
saloutos	0:083111ae2a11	48
saloutos	0:083111ae2a11	49	/** @addtogroup STM32F4xx_HAL_Driver
saloutos	0:083111ae2a11	50	* @{
saloutos	0:083111ae2a11	51	*/
saloutos	0:083111ae2a11	52
saloutos	0:083111ae2a11	53	/** @addtogroup FMC_LL
saloutos	0:083111ae2a11	54	* @{
saloutos	0:083111ae2a11	55	*/
saloutos	0:083111ae2a11	56	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
saloutos	0:083111ae2a11	57	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
saloutos	0:083111ae2a11	58	/* Private types -------------------------------------------------------------*/
saloutos	0:083111ae2a11	59	/** @defgroup FMC_LL_Private_Types FMC Private Types
saloutos	0:083111ae2a11	60	* @{
saloutos	0:083111ae2a11	61	*/
saloutos	0:083111ae2a11	62
saloutos	0:083111ae2a11	63	/**
saloutos	0:083111ae2a11	64	* @brief FMC NORSRAM Configuration Structure definition
saloutos	0:083111ae2a11	65	*/
saloutos	0:083111ae2a11	66	typedef struct
saloutos	0:083111ae2a11	67	{
saloutos	0:083111ae2a11	68	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
saloutos	0:083111ae2a11	69	This parameter can be a value of @ref FMC_NORSRAM_Bank */
saloutos	0:083111ae2a11	70
saloutos	0:083111ae2a11	71	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
saloutos	0:083111ae2a11	72	multiplexed on the data bus or not.
saloutos	0:083111ae2a11	73	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
saloutos	0:083111ae2a11	74
saloutos	0:083111ae2a11	75	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
saloutos	0:083111ae2a11	76	the corresponding memory device.
saloutos	0:083111ae2a11	77	This parameter can be a value of @ref FMC_Memory_Type */
saloutos	0:083111ae2a11	78
saloutos	0:083111ae2a11	79	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
saloutos	0:083111ae2a11	80	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
saloutos	0:083111ae2a11	81
saloutos	0:083111ae2a11	82	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
saloutos	0:083111ae2a11	83	valid only with synchronous burst Flash memories.
saloutos	0:083111ae2a11	84	This parameter can be a value of @ref FMC_Burst_Access_Mode */
saloutos	0:083111ae2a11	85
saloutos	0:083111ae2a11	86	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
saloutos	0:083111ae2a11	87	the Flash memory in burst mode.
saloutos	0:083111ae2a11	88	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
saloutos	0:083111ae2a11	89
saloutos	0:083111ae2a11	90	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
saloutos	0:083111ae2a11	91	memory, valid only when accessing Flash memories in burst mode.
saloutos	0:083111ae2a11	92	This parameter can be a value of @ref FMC_Wrap_Mode
saloutos	0:083111ae2a11	93	This mode is not available for the STM32F446/467/479xx devices */
saloutos	0:083111ae2a11	94
saloutos	0:083111ae2a11	95	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
saloutos	0:083111ae2a11	96	clock cycle before the wait state or during the wait state,
saloutos	0:083111ae2a11	97	valid only when accessing memories in burst mode.
saloutos	0:083111ae2a11	98	This parameter can be a value of @ref FMC_Wait_Timing */
saloutos	0:083111ae2a11	99
saloutos	0:083111ae2a11	100	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
saloutos	0:083111ae2a11	101	This parameter can be a value of @ref FMC_Write_Operation */
saloutos	0:083111ae2a11	102
saloutos	0:083111ae2a11	103	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
saloutos	0:083111ae2a11	104	signal, valid for Flash memory access in burst mode.
saloutos	0:083111ae2a11	105	This parameter can be a value of @ref FMC_Wait_Signal */
saloutos	0:083111ae2a11	106
saloutos	0:083111ae2a11	107	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
saloutos	0:083111ae2a11	108	This parameter can be a value of @ref FMC_Extended_Mode */
saloutos	0:083111ae2a11	109
saloutos	0:083111ae2a11	110	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
saloutos	0:083111ae2a11	111	valid only with asynchronous Flash memories.
saloutos	0:083111ae2a11	112	This parameter can be a value of @ref FMC_AsynchronousWait */
saloutos	0:083111ae2a11	113
saloutos	0:083111ae2a11	114	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
saloutos	0:083111ae2a11	115	This parameter can be a value of @ref FMC_Write_Burst */
saloutos	0:083111ae2a11	116
saloutos	0:083111ae2a11	117	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
saloutos	0:083111ae2a11	118	This parameter is only enabled through the FMC_BCR1 register, and don't care
saloutos	0:083111ae2a11	119	through FMC_BCR2..4 registers.
saloutos	0:083111ae2a11	120	This parameter can be a value of @ref FMC_Continous_Clock */
saloutos	0:083111ae2a11	121
saloutos	0:083111ae2a11	122	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
saloutos	0:083111ae2a11	123	This parameter is only enabled through the FMC_BCR1 register, and don't care
saloutos	0:083111ae2a11	124	through FMC_BCR2..4 registers.
saloutos	0:083111ae2a11	125	This parameter can be a value of @ref FMC_Write_FIFO
saloutos	0:083111ae2a11	126	This mode is available only for the STM32F446/469/479xx devices */
saloutos	0:083111ae2a11	127
saloutos	0:083111ae2a11	128	uint32_t PageSize; /*!< Specifies the memory page size.
saloutos	0:083111ae2a11	129	This parameter can be a value of @ref FMC_Page_Size */
saloutos	0:083111ae2a11	130	}FMC_NORSRAM_InitTypeDef;
saloutos	0:083111ae2a11	131
saloutos	0:083111ae2a11	132	/**
saloutos	0:083111ae2a11	133	* @brief FMC NORSRAM Timing parameters structure definition
saloutos	0:083111ae2a11	134	*/
saloutos	0:083111ae2a11	135	typedef struct
saloutos	0:083111ae2a11	136	{
saloutos	0:083111ae2a11	137	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
saloutos	0:083111ae2a11	138	the duration of the address setup time.
saloutos	0:083111ae2a11	139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
saloutos	0:083111ae2a11	140	@note This parameter is not used with synchronous NOR Flash memories. */
saloutos	0:083111ae2a11	141
saloutos	0:083111ae2a11	142	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
saloutos	0:083111ae2a11	143	the duration of the address hold time.
saloutos	0:083111ae2a11	144	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
saloutos	0:083111ae2a11	145	@note This parameter is not used with synchronous NOR Flash memories. */
saloutos	0:083111ae2a11	146
saloutos	0:083111ae2a11	147	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
saloutos	0:083111ae2a11	148	the duration of the data setup time.
saloutos	0:083111ae2a11	149	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
saloutos	0:083111ae2a11	150	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
saloutos	0:083111ae2a11	151	NOR Flash memories. */
saloutos	0:083111ae2a11	152
saloutos	0:083111ae2a11	153	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
saloutos	0:083111ae2a11	154	the duration of the bus turnaround.
saloutos	0:083111ae2a11	155	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
saloutos	0:083111ae2a11	156	@note This parameter is only used for multiplexed NOR Flash memories. */
saloutos	0:083111ae2a11	157
saloutos	0:083111ae2a11	158	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
saloutos	0:083111ae2a11	159	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
saloutos	0:083111ae2a11	160	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
saloutos	0:083111ae2a11	161	accesses. */
saloutos	0:083111ae2a11	162
saloutos	0:083111ae2a11	163	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
saloutos	0:083111ae2a11	164	to the memory before getting the first data.
saloutos	0:083111ae2a11	165	The parameter value depends on the memory type as shown below:
saloutos	0:083111ae2a11	166	- It must be set to 0 in case of a CRAM
saloutos	0:083111ae2a11	167	- It is don't care in asynchronous NOR, SRAM or ROM accesses
saloutos	0:083111ae2a11	168	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
saloutos	0:083111ae2a11	169	with synchronous burst mode enable */
saloutos	0:083111ae2a11	170
saloutos	0:083111ae2a11	171	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
saloutos	0:083111ae2a11	172	This parameter can be a value of @ref FMC_Access_Mode */
saloutos	0:083111ae2a11	173	}FMC_NORSRAM_TimingTypeDef;
saloutos	0:083111ae2a11	174
saloutos	0:083111ae2a11	175	/**
saloutos	0:083111ae2a11	176	* @brief FMC NAND Configuration Structure definition
saloutos	0:083111ae2a11	177	*/
saloutos	0:083111ae2a11	178	typedef struct
saloutos	0:083111ae2a11	179	{
saloutos	0:083111ae2a11	180	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
saloutos	0:083111ae2a11	181	This parameter can be a value of @ref FMC_NAND_Bank */
saloutos	0:083111ae2a11	182
saloutos	0:083111ae2a11	183	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
saloutos	0:083111ae2a11	184	This parameter can be any value of @ref FMC_Wait_feature */
saloutos	0:083111ae2a11	185
saloutos	0:083111ae2a11	186	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
saloutos	0:083111ae2a11	187	This parameter can be any value of @ref FMC_NAND_Data_Width */
saloutos	0:083111ae2a11	188
saloutos	0:083111ae2a11	189	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
saloutos	0:083111ae2a11	190	This parameter can be any value of @ref FMC_ECC */
saloutos	0:083111ae2a11	191
saloutos	0:083111ae2a11	192	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
saloutos	0:083111ae2a11	193	This parameter can be any value of @ref FMC_ECC_Page_Size */
saloutos	0:083111ae2a11	194
saloutos	0:083111ae2a11	195	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
saloutos	0:083111ae2a11	196	delay between CLE low and RE low.
saloutos	0:083111ae2a11	197	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
saloutos	0:083111ae2a11	198
saloutos	0:083111ae2a11	199	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
saloutos	0:083111ae2a11	200	delay between ALE low and RE low.
saloutos	0:083111ae2a11	201	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
saloutos	0:083111ae2a11	202	}FMC_NAND_InitTypeDef;
saloutos	0:083111ae2a11	203
saloutos	0:083111ae2a11	204	/**
saloutos	0:083111ae2a11	205	* @brief FMC NAND/PCCARD Timing parameters structure definition
saloutos	0:083111ae2a11	206	*/
saloutos	0:083111ae2a11	207	typedef struct
saloutos	0:083111ae2a11	208	{
saloutos	0:083111ae2a11	209	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
saloutos	0:083111ae2a11	210	the command assertion for NAND-Flash read or write access
saloutos	0:083111ae2a11	211	to common/Attribute or I/O memory space (depending on
saloutos	0:083111ae2a11	212	the memory space timing to be configured).
saloutos	0:083111ae2a11	213	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
saloutos	0:083111ae2a11	214
saloutos	0:083111ae2a11	215	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
saloutos	0:083111ae2a11	216	command for NAND-Flash read or write access to
saloutos	0:083111ae2a11	217	common/Attribute or I/O memory space (depending on the
saloutos	0:083111ae2a11	218	memory space timing to be configured).
saloutos	0:083111ae2a11	219	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
saloutos	0:083111ae2a11	220
saloutos	0:083111ae2a11	221	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
saloutos	0:083111ae2a11	222	(and data for write access) after the command de-assertion
saloutos	0:083111ae2a11	223	for NAND-Flash read or write access to common/Attribute
saloutos	0:083111ae2a11	224	or I/O memory space (depending on the memory space timing
saloutos	0:083111ae2a11	225	to be configured).
saloutos	0:083111ae2a11	226	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
saloutos	0:083111ae2a11	227
saloutos	0:083111ae2a11	228	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
saloutos	0:083111ae2a11	229	data bus is kept in HiZ after the start of a NAND-Flash
saloutos	0:083111ae2a11	230	write access to common/Attribute or I/O memory space (depending
saloutos	0:083111ae2a11	231	on the memory space timing to be configured).
saloutos	0:083111ae2a11	232	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
saloutos	0:083111ae2a11	233	}FMC_NAND_PCC_TimingTypeDef;
saloutos	0:083111ae2a11	234
saloutos	0:083111ae2a11	235	/**
saloutos	0:083111ae2a11	236	* @brief FMC NAND Configuration Structure definition
saloutos	0:083111ae2a11	237	*/
saloutos	0:083111ae2a11	238	typedef struct
saloutos	0:083111ae2a11	239	{
saloutos	0:083111ae2a11	240	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
saloutos	0:083111ae2a11	241	This parameter can be any value of @ref FMC_Wait_feature */
saloutos	0:083111ae2a11	242
saloutos	0:083111ae2a11	243	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
saloutos	0:083111ae2a11	244	delay between CLE low and RE low.
saloutos	0:083111ae2a11	245	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
saloutos	0:083111ae2a11	246
saloutos	0:083111ae2a11	247	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
saloutos	0:083111ae2a11	248	delay between ALE low and RE low.
saloutos	0:083111ae2a11	249	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
saloutos	0:083111ae2a11	250	}FMC_PCCARD_InitTypeDef;
saloutos	0:083111ae2a11	251
saloutos	0:083111ae2a11	252	/**
saloutos	0:083111ae2a11	253	* @brief FMC SDRAM Configuration Structure definition
saloutos	0:083111ae2a11	254	*/
saloutos	0:083111ae2a11	255	typedef struct
saloutos	0:083111ae2a11	256	{
saloutos	0:083111ae2a11	257	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
saloutos	0:083111ae2a11	258	This parameter can be a value of @ref FMC_SDRAM_Bank */
saloutos	0:083111ae2a11	259
saloutos	0:083111ae2a11	260	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
saloutos	0:083111ae2a11	261	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
saloutos	0:083111ae2a11	262
saloutos	0:083111ae2a11	263	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
saloutos	0:083111ae2a11	264	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
saloutos	0:083111ae2a11	265
saloutos	0:083111ae2a11	266	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
saloutos	0:083111ae2a11	267	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
saloutos	0:083111ae2a11	268
saloutos	0:083111ae2a11	269	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
saloutos	0:083111ae2a11	270	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
saloutos	0:083111ae2a11	271
saloutos	0:083111ae2a11	272	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
saloutos	0:083111ae2a11	273	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
saloutos	0:083111ae2a11	274
saloutos	0:083111ae2a11	275	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
saloutos	0:083111ae2a11	276	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
saloutos	0:083111ae2a11	277
saloutos	0:083111ae2a11	278	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
saloutos	0:083111ae2a11	279	to disable the clock before changing frequency.
saloutos	0:083111ae2a11	280	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
saloutos	0:083111ae2a11	281
saloutos	0:083111ae2a11	282	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
saloutos	0:083111ae2a11	283	commands during the CAS latency and stores data in the Read FIFO.
saloutos	0:083111ae2a11	284	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
saloutos	0:083111ae2a11	285
saloutos	0:083111ae2a11	286	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
saloutos	0:083111ae2a11	287	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
saloutos	0:083111ae2a11	288	}FMC_SDRAM_InitTypeDef;
saloutos	0:083111ae2a11	289
saloutos	0:083111ae2a11	290	/**
saloutos	0:083111ae2a11	291	* @brief FMC SDRAM Timing parameters structure definition
saloutos	0:083111ae2a11	292	*/
saloutos	0:083111ae2a11	293	typedef struct
saloutos	0:083111ae2a11	294	{
saloutos	0:083111ae2a11	295	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
saloutos	0:083111ae2a11	296	an active or Refresh command in number of memory clock cycles.
saloutos	0:083111ae2a11	297	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
saloutos	0:083111ae2a11	298
saloutos	0:083111ae2a11	299	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
saloutos	0:083111ae2a11	300	issuing the Activate command in number of memory clock cycles.
saloutos	0:083111ae2a11	301	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
saloutos	0:083111ae2a11	302
saloutos	0:083111ae2a11	303	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
saloutos	0:083111ae2a11	304	cycles.
saloutos	0:083111ae2a11	305	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
saloutos	0:083111ae2a11	306
saloutos	0:083111ae2a11	307	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
saloutos	0:083111ae2a11	308	and the delay between two consecutive Refresh commands in number of
saloutos	0:083111ae2a11	309	memory clock cycles.
saloutos	0:083111ae2a11	310	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
saloutos	0:083111ae2a11	311
saloutos	0:083111ae2a11	312	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
saloutos	0:083111ae2a11	313	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
saloutos	0:083111ae2a11	314
saloutos	0:083111ae2a11	315	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
saloutos	0:083111ae2a11	316	in number of memory clock cycles.
saloutos	0:083111ae2a11	317	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
saloutos	0:083111ae2a11	318
saloutos	0:083111ae2a11	319	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
saloutos	0:083111ae2a11	320	command in number of memory clock cycles.
saloutos	0:083111ae2a11	321	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
saloutos	0:083111ae2a11	322	}FMC_SDRAM_TimingTypeDef;
saloutos	0:083111ae2a11	323
saloutos	0:083111ae2a11	324	/**
saloutos	0:083111ae2a11	325	* @brief SDRAM command parameters structure definition
saloutos	0:083111ae2a11	326	*/
saloutos	0:083111ae2a11	327	typedef struct
saloutos	0:083111ae2a11	328	{
saloutos	0:083111ae2a11	329	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
saloutos	0:083111ae2a11	330	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
saloutos	0:083111ae2a11	331
saloutos	0:083111ae2a11	332	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
saloutos	0:083111ae2a11	333	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
saloutos	0:083111ae2a11	334
saloutos	0:083111ae2a11	335	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
saloutos	0:083111ae2a11	336	in auto refresh mode.
saloutos	0:083111ae2a11	337	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
saloutos	0:083111ae2a11	338	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
saloutos	0:083111ae2a11	339	}FMC_SDRAM_CommandTypeDef;
saloutos	0:083111ae2a11	340	/**
saloutos	0:083111ae2a11	341	* @}
saloutos	0:083111ae2a11	342	*/
saloutos	0:083111ae2a11	343
saloutos	0:083111ae2a11	344	/* Private constants ---------------------------------------------------------*/
saloutos	0:083111ae2a11	345	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
saloutos	0:083111ae2a11	346	* @{
saloutos	0:083111ae2a11	347	*/
saloutos	0:083111ae2a11	348
saloutos	0:083111ae2a11	349	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
saloutos	0:083111ae2a11	350	* @{
saloutos	0:083111ae2a11	351	*/
saloutos	0:083111ae2a11	352	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
saloutos	0:083111ae2a11	353	* @{
saloutos	0:083111ae2a11	354	*/
saloutos	0:083111ae2a11	355	#define FMC_NORSRAM_BANK1 0x00000000U
saloutos	0:083111ae2a11	356	#define FMC_NORSRAM_BANK2 0x00000002U
saloutos	0:083111ae2a11	357	#define FMC_NORSRAM_BANK3 0x00000004U
saloutos	0:083111ae2a11	358	#define FMC_NORSRAM_BANK4 0x00000006U
saloutos	0:083111ae2a11	359	/**
saloutos	0:083111ae2a11	360	* @}
saloutos	0:083111ae2a11	361	*/
saloutos	0:083111ae2a11	362
saloutos	0:083111ae2a11	363	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
saloutos	0:083111ae2a11	364	* @{
saloutos	0:083111ae2a11	365	*/
saloutos	0:083111ae2a11	366	#define FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
saloutos	0:083111ae2a11	367	#define FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
saloutos	0:083111ae2a11	368	/**
saloutos	0:083111ae2a11	369	* @}
saloutos	0:083111ae2a11	370	*/
saloutos	0:083111ae2a11	371
saloutos	0:083111ae2a11	372	/** @defgroup FMC_Memory_Type FMC Memory Type
saloutos	0:083111ae2a11	373	* @{
saloutos	0:083111ae2a11	374	*/
saloutos	0:083111ae2a11	375	#define FMC_MEMORY_TYPE_SRAM 0x00000000U
saloutos	0:083111ae2a11	376	#define FMC_MEMORY_TYPE_PSRAM 0x00000004U
saloutos	0:083111ae2a11	377	#define FMC_MEMORY_TYPE_NOR 0x00000008U
saloutos	0:083111ae2a11	378	/**
saloutos	0:083111ae2a11	379	* @}
saloutos	0:083111ae2a11	380	*/
saloutos	0:083111ae2a11	381
saloutos	0:083111ae2a11	382	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
saloutos	0:083111ae2a11	383	* @{
saloutos	0:083111ae2a11	384	*/
saloutos	0:083111ae2a11	385	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
saloutos	0:083111ae2a11	386	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
saloutos	0:083111ae2a11	387	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
saloutos	0:083111ae2a11	388	/**
saloutos	0:083111ae2a11	389	* @}
saloutos	0:083111ae2a11	390	*/
saloutos	0:083111ae2a11	391
saloutos	0:083111ae2a11	392	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
saloutos	0:083111ae2a11	393	* @{
saloutos	0:083111ae2a11	394	*/
saloutos	0:083111ae2a11	395	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
saloutos	0:083111ae2a11	396	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
saloutos	0:083111ae2a11	397	/**
saloutos	0:083111ae2a11	398	* @}
saloutos	0:083111ae2a11	399	*/
saloutos	0:083111ae2a11	400
saloutos	0:083111ae2a11	401	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
saloutos	0:083111ae2a11	402	* @{
saloutos	0:083111ae2a11	403	*/
saloutos	0:083111ae2a11	404	#define FMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
saloutos	0:083111ae2a11	405	#define FMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
saloutos	0:083111ae2a11	406	/**
saloutos	0:083111ae2a11	407	* @}
saloutos	0:083111ae2a11	408	*/
saloutos	0:083111ae2a11	409
saloutos	0:083111ae2a11	410	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
saloutos	0:083111ae2a11	411	* @{
saloutos	0:083111ae2a11	412	*/
saloutos	0:083111ae2a11	413	#define FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
saloutos	0:083111ae2a11	414	#define FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
saloutos	0:083111ae2a11	415	/**
saloutos	0:083111ae2a11	416	* @}
saloutos	0:083111ae2a11	417	*/
saloutos	0:083111ae2a11	418
saloutos	0:083111ae2a11	419	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
saloutos	0:083111ae2a11	420	* @{
saloutos	0:083111ae2a11	421	*/
saloutos	0:083111ae2a11	422	/** @note This mode is not available for the STM32F446/469/479xx devices
saloutos	0:083111ae2a11	423	*/
saloutos	0:083111ae2a11	424	#define FMC_WRAP_MODE_DISABLE 0x00000000U
saloutos	0:083111ae2a11	425	#define FMC_WRAP_MODE_ENABLE 0x00000400U
saloutos	0:083111ae2a11	426	/**
saloutos	0:083111ae2a11	427	* @}
saloutos	0:083111ae2a11	428	*/
saloutos	0:083111ae2a11	429
saloutos	0:083111ae2a11	430	/** @defgroup FMC_Wait_Timing FMC Wait Timing
saloutos	0:083111ae2a11	431	* @{
saloutos	0:083111ae2a11	432	*/
saloutos	0:083111ae2a11	433	#define FMC_WAIT_TIMING_BEFORE_WS 0x00000000U
saloutos	0:083111ae2a11	434	#define FMC_WAIT_TIMING_DURING_WS 0x00000800U
saloutos	0:083111ae2a11	435	/**
saloutos	0:083111ae2a11	436	* @}
saloutos	0:083111ae2a11	437	*/
saloutos	0:083111ae2a11	438
saloutos	0:083111ae2a11	439	/** @defgroup FMC_Write_Operation FMC Write Operation
saloutos	0:083111ae2a11	440	* @{
saloutos	0:083111ae2a11	441	*/
saloutos	0:083111ae2a11	442	#define FMC_WRITE_OPERATION_DISABLE 0x00000000U
saloutos	0:083111ae2a11	443	#define FMC_WRITE_OPERATION_ENABLE 0x00001000U
saloutos	0:083111ae2a11	444	/**
saloutos	0:083111ae2a11	445	* @}
saloutos	0:083111ae2a11	446	*/
saloutos	0:083111ae2a11	447
saloutos	0:083111ae2a11	448	/** @defgroup FMC_Wait_Signal FMC Wait Signal
saloutos	0:083111ae2a11	449	* @{
saloutos	0:083111ae2a11	450	*/
saloutos	0:083111ae2a11	451	#define FMC_WAIT_SIGNAL_DISABLE 0x00000000U
saloutos	0:083111ae2a11	452	#define FMC_WAIT_SIGNAL_ENABLE 0x00002000U
saloutos	0:083111ae2a11	453	/**
saloutos	0:083111ae2a11	454	* @}
saloutos	0:083111ae2a11	455	*/
saloutos	0:083111ae2a11	456
saloutos	0:083111ae2a11	457	/** @defgroup FMC_Extended_Mode FMC Extended Mode
saloutos	0:083111ae2a11	458	* @{
saloutos	0:083111ae2a11	459	*/
saloutos	0:083111ae2a11	460	#define FMC_EXTENDED_MODE_DISABLE 0x00000000U
saloutos	0:083111ae2a11	461	#define FMC_EXTENDED_MODE_ENABLE 0x00004000U
saloutos	0:083111ae2a11	462	/**
saloutos	0:083111ae2a11	463	* @}
saloutos	0:083111ae2a11	464	*/
saloutos	0:083111ae2a11	465
saloutos	0:083111ae2a11	466	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
saloutos	0:083111ae2a11	467	* @{
saloutos	0:083111ae2a11	468	*/
saloutos	0:083111ae2a11	469	#define FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
saloutos	0:083111ae2a11	470	#define FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
saloutos	0:083111ae2a11	471	/**
saloutos	0:083111ae2a11	472	* @}
saloutos	0:083111ae2a11	473	*/
saloutos	0:083111ae2a11	474
saloutos	0:083111ae2a11	475	/** @defgroup FMC_Page_Size FMC Page Size
saloutos	0:083111ae2a11	476	* @{
saloutos	0:083111ae2a11	477	*/
saloutos	0:083111ae2a11	478	#define FMC_PAGE_SIZE_NONE 0x00000000U
saloutos	0:083111ae2a11	479	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
saloutos	0:083111ae2a11	480	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
saloutos	0:083111ae2a11	481	#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 \| FMC_BCR1_CPSIZE_1))
saloutos	0:083111ae2a11	482	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
saloutos	0:083111ae2a11	483	/**
saloutos	0:083111ae2a11	484	* @}
saloutos	0:083111ae2a11	485	*/
saloutos	0:083111ae2a11	486
saloutos	0:083111ae2a11	487	/** @defgroup FMC_Write_FIFO FMC Write FIFO
saloutos	0:083111ae2a11	488	* @note These values are available only for the STM32F446/469/479xx devices.
saloutos	0:083111ae2a11	489	* @{
saloutos	0:083111ae2a11	490	*/
saloutos	0:083111ae2a11	491	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
saloutos	0:083111ae2a11	492	#define FMC_WRITE_FIFO_ENABLE 0x00000000U
saloutos	0:083111ae2a11	493	/**
saloutos	0:083111ae2a11	494	* @}
saloutos	0:083111ae2a11	495	*/
saloutos	0:083111ae2a11	496
saloutos	0:083111ae2a11	497	/** @defgroup FMC_Write_Burst FMC Write Burst
saloutos	0:083111ae2a11	498	* @{
saloutos	0:083111ae2a11	499	*/
saloutos	0:083111ae2a11	500	#define FMC_WRITE_BURST_DISABLE 0x00000000U
saloutos	0:083111ae2a11	501	#define FMC_WRITE_BURST_ENABLE 0x00080000U
saloutos	0:083111ae2a11	502	/**
saloutos	0:083111ae2a11	503	* @}
saloutos	0:083111ae2a11	504	*/
saloutos	0:083111ae2a11	505
saloutos	0:083111ae2a11	506	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
saloutos	0:083111ae2a11	507	* @{
saloutos	0:083111ae2a11	508	*/
saloutos	0:083111ae2a11	509	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
saloutos	0:083111ae2a11	510	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
saloutos	0:083111ae2a11	511	/**
saloutos	0:083111ae2a11	512	* @}
saloutos	0:083111ae2a11	513	*/
saloutos	0:083111ae2a11	514
saloutos	0:083111ae2a11	515	/** @defgroup FMC_Access_Mode FMC Access Mode
saloutos	0:083111ae2a11	516	* @{
saloutos	0:083111ae2a11	517	*/
saloutos	0:083111ae2a11	518	#define FMC_ACCESS_MODE_A 0x00000000U
saloutos	0:083111ae2a11	519	#define FMC_ACCESS_MODE_B 0x10000000U
saloutos	0:083111ae2a11	520	#define FMC_ACCESS_MODE_C 0x20000000U
saloutos	0:083111ae2a11	521	#define FMC_ACCESS_MODE_D 0x30000000U
saloutos	0:083111ae2a11	522	/**
saloutos	0:083111ae2a11	523	* @}
saloutos	0:083111ae2a11	524	*/
saloutos	0:083111ae2a11	525
saloutos	0:083111ae2a11	526	/**
saloutos	0:083111ae2a11	527	* @}
saloutos	0:083111ae2a11	528	*/
saloutos	0:083111ae2a11	529
saloutos	0:083111ae2a11	530	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
saloutos	0:083111ae2a11	531	* @{
saloutos	0:083111ae2a11	532	*/
saloutos	0:083111ae2a11	533	/** @defgroup FMC_NAND_Bank FMC NAND Bank
saloutos	0:083111ae2a11	534	* @{
saloutos	0:083111ae2a11	535	*/
saloutos	0:083111ae2a11	536	#define FMC_NAND_BANK2 0x00000010U
saloutos	0:083111ae2a11	537	#define FMC_NAND_BANK3 0x00000100U
saloutos	0:083111ae2a11	538	/**
saloutos	0:083111ae2a11	539	* @}
saloutos	0:083111ae2a11	540	*/
saloutos	0:083111ae2a11	541
saloutos	0:083111ae2a11	542	/** @defgroup FMC_Wait_feature FMC Wait feature
saloutos	0:083111ae2a11	543	* @{
saloutos	0:083111ae2a11	544	*/
saloutos	0:083111ae2a11	545	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
saloutos	0:083111ae2a11	546	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
saloutos	0:083111ae2a11	547	/**
saloutos	0:083111ae2a11	548	* @}
saloutos	0:083111ae2a11	549	*/
saloutos	0:083111ae2a11	550
saloutos	0:083111ae2a11	551	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
saloutos	0:083111ae2a11	552	* @{
saloutos	0:083111ae2a11	553	*/
saloutos	0:083111ae2a11	554	#define FMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
saloutos	0:083111ae2a11	555	#define FMC_PCR_MEMORY_TYPE_NAND 0x00000008U
saloutos	0:083111ae2a11	556	/**
saloutos	0:083111ae2a11	557	* @}
saloutos	0:083111ae2a11	558	*/
saloutos	0:083111ae2a11	559
saloutos	0:083111ae2a11	560	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
saloutos	0:083111ae2a11	561	* @{
saloutos	0:083111ae2a11	562	*/
saloutos	0:083111ae2a11	563	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
saloutos	0:083111ae2a11	564	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
saloutos	0:083111ae2a11	565	/**
saloutos	0:083111ae2a11	566	* @}
saloutos	0:083111ae2a11	567	*/
saloutos	0:083111ae2a11	568
saloutos	0:083111ae2a11	569	/** @defgroup FMC_ECC FMC ECC
saloutos	0:083111ae2a11	570	* @{
saloutos	0:083111ae2a11	571	*/
saloutos	0:083111ae2a11	572	#define FMC_NAND_ECC_DISABLE 0x00000000U
saloutos	0:083111ae2a11	573	#define FMC_NAND_ECC_ENABLE 0x00000040U
saloutos	0:083111ae2a11	574	/**
saloutos	0:083111ae2a11	575	* @}
saloutos	0:083111ae2a11	576	*/
saloutos	0:083111ae2a11	577
saloutos	0:083111ae2a11	578	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
saloutos	0:083111ae2a11	579	* @{
saloutos	0:083111ae2a11	580	*/
saloutos	0:083111ae2a11	581	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
saloutos	0:083111ae2a11	582	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
saloutos	0:083111ae2a11	583	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
saloutos	0:083111ae2a11	584	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
saloutos	0:083111ae2a11	585	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
saloutos	0:083111ae2a11	586	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
saloutos	0:083111ae2a11	587	/**
saloutos	0:083111ae2a11	588	* @}
saloutos	0:083111ae2a11	589	*/
saloutos	0:083111ae2a11	590
saloutos	0:083111ae2a11	591	/**
saloutos	0:083111ae2a11	592	* @}
saloutos	0:083111ae2a11	593	*/
saloutos	0:083111ae2a11	594
saloutos	0:083111ae2a11	595	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
saloutos	0:083111ae2a11	596	* @{
saloutos	0:083111ae2a11	597	*/
saloutos	0:083111ae2a11	598	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
saloutos	0:083111ae2a11	599	* @{
saloutos	0:083111ae2a11	600	*/
saloutos	0:083111ae2a11	601	#define FMC_SDRAM_BANK1 0x00000000U
saloutos	0:083111ae2a11	602	#define FMC_SDRAM_BANK2 0x00000001U
saloutos	0:083111ae2a11	603	/**
saloutos	0:083111ae2a11	604	* @}
saloutos	0:083111ae2a11	605	*/
saloutos	0:083111ae2a11	606
saloutos	0:083111ae2a11	607	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
saloutos	0:083111ae2a11	608	* @{
saloutos	0:083111ae2a11	609	*/
saloutos	0:083111ae2a11	610	#define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000U
saloutos	0:083111ae2a11	611	#define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001U
saloutos	0:083111ae2a11	612	#define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002U
saloutos	0:083111ae2a11	613	#define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003U
saloutos	0:083111ae2a11	614	/**
saloutos	0:083111ae2a11	615	* @}
saloutos	0:083111ae2a11	616	*/
saloutos	0:083111ae2a11	617
saloutos	0:083111ae2a11	618	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
saloutos	0:083111ae2a11	619	* @{
saloutos	0:083111ae2a11	620	*/
saloutos	0:083111ae2a11	621	#define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000U
saloutos	0:083111ae2a11	622	#define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004U
saloutos	0:083111ae2a11	623	#define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008U
saloutos	0:083111ae2a11	624	/**
saloutos	0:083111ae2a11	625	* @}
saloutos	0:083111ae2a11	626	*/
saloutos	0:083111ae2a11	627
saloutos	0:083111ae2a11	628	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
saloutos	0:083111ae2a11	629	* @{
saloutos	0:083111ae2a11	630	*/
saloutos	0:083111ae2a11	631	#define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000U
saloutos	0:083111ae2a11	632	#define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010U
saloutos	0:083111ae2a11	633	#define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020U
saloutos	0:083111ae2a11	634	/**
saloutos	0:083111ae2a11	635	* @}
saloutos	0:083111ae2a11	636	*/
saloutos	0:083111ae2a11	637
saloutos	0:083111ae2a11	638	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
saloutos	0:083111ae2a11	639	* @{
saloutos	0:083111ae2a11	640	*/
saloutos	0:083111ae2a11	641	#define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000U
saloutos	0:083111ae2a11	642	#define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040U
saloutos	0:083111ae2a11	643	/**
saloutos	0:083111ae2a11	644	* @}
saloutos	0:083111ae2a11	645	*/
saloutos	0:083111ae2a11	646
saloutos	0:083111ae2a11	647	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
saloutos	0:083111ae2a11	648	* @{
saloutos	0:083111ae2a11	649	*/
saloutos	0:083111ae2a11	650	#define FMC_SDRAM_CAS_LATENCY_1 0x00000080U
saloutos	0:083111ae2a11	651	#define FMC_SDRAM_CAS_LATENCY_2 0x00000100U
saloutos	0:083111ae2a11	652	#define FMC_SDRAM_CAS_LATENCY_3 0x00000180U
saloutos	0:083111ae2a11	653	/**
saloutos	0:083111ae2a11	654	* @}
saloutos	0:083111ae2a11	655	*/
saloutos	0:083111ae2a11	656
saloutos	0:083111ae2a11	657	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
saloutos	0:083111ae2a11	658	* @{
saloutos	0:083111ae2a11	659	*/
saloutos	0:083111ae2a11	660	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000U
saloutos	0:083111ae2a11	661	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200U
saloutos	0:083111ae2a11	662
saloutos	0:083111ae2a11	663	/**
saloutos	0:083111ae2a11	664	* @}
saloutos	0:083111ae2a11	665	*/
saloutos	0:083111ae2a11	666
saloutos	0:083111ae2a11	667	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
saloutos	0:083111ae2a11	668	* @{
saloutos	0:083111ae2a11	669	*/
saloutos	0:083111ae2a11	670	#define FMC_SDRAM_CLOCK_DISABLE 0x00000000U
saloutos	0:083111ae2a11	671	#define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800U
saloutos	0:083111ae2a11	672	#define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00U
saloutos	0:083111ae2a11	673	/**
saloutos	0:083111ae2a11	674	* @}
saloutos	0:083111ae2a11	675	*/
saloutos	0:083111ae2a11	676
saloutos	0:083111ae2a11	677	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
saloutos	0:083111ae2a11	678	* @{
saloutos	0:083111ae2a11	679	*/
saloutos	0:083111ae2a11	680	#define FMC_SDRAM_RBURST_DISABLE 0x00000000U
saloutos	0:083111ae2a11	681	#define FMC_SDRAM_RBURST_ENABLE 0x00001000U
saloutos	0:083111ae2a11	682	/**
saloutos	0:083111ae2a11	683	* @}
saloutos	0:083111ae2a11	684	*/
saloutos	0:083111ae2a11	685
saloutos	0:083111ae2a11	686	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
saloutos	0:083111ae2a11	687	* @{
saloutos	0:083111ae2a11	688	*/
saloutos	0:083111ae2a11	689	#define FMC_SDRAM_RPIPE_DELAY_0 0x00000000U
saloutos	0:083111ae2a11	690	#define FMC_SDRAM_RPIPE_DELAY_1 0x00002000U
saloutos	0:083111ae2a11	691	#define FMC_SDRAM_RPIPE_DELAY_2 0x00004000U
saloutos	0:083111ae2a11	692	/**
saloutos	0:083111ae2a11	693	* @}
saloutos	0:083111ae2a11	694	*/
saloutos	0:083111ae2a11	695
saloutos	0:083111ae2a11	696	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
saloutos	0:083111ae2a11	697	* @{
saloutos	0:083111ae2a11	698	*/
saloutos	0:083111ae2a11	699	#define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000U
saloutos	0:083111ae2a11	700	#define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001U
saloutos	0:083111ae2a11	701	#define FMC_SDRAM_CMD_PALL 0x00000002U
saloutos	0:083111ae2a11	702	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003U
saloutos	0:083111ae2a11	703	#define FMC_SDRAM_CMD_LOAD_MODE 0x00000004U
saloutos	0:083111ae2a11	704	#define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005U
saloutos	0:083111ae2a11	705	#define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006U
saloutos	0:083111ae2a11	706	/**
saloutos	0:083111ae2a11	707	* @}
saloutos	0:083111ae2a11	708	*/
saloutos	0:083111ae2a11	709
saloutos	0:083111ae2a11	710	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
saloutos	0:083111ae2a11	711	* @{
saloutos	0:083111ae2a11	712	*/
saloutos	0:083111ae2a11	713	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
saloutos	0:083111ae2a11	714	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
saloutos	0:083111ae2a11	715	#define FMC_SDRAM_CMD_TARGET_BANK1_2 0x00000018U
saloutos	0:083111ae2a11	716	/**
saloutos	0:083111ae2a11	717	* @}
saloutos	0:083111ae2a11	718	*/
saloutos	0:083111ae2a11	719
saloutos	0:083111ae2a11	720	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
saloutos	0:083111ae2a11	721	* @{
saloutos	0:083111ae2a11	722	*/
saloutos	0:083111ae2a11	723	#define FMC_SDRAM_NORMAL_MODE 0x00000000U
saloutos	0:083111ae2a11	724	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
saloutos	0:083111ae2a11	725	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
saloutos	0:083111ae2a11	726	/**
saloutos	0:083111ae2a11	727	* @}
saloutos	0:083111ae2a11	728	*/
saloutos	0:083111ae2a11	729
saloutos	0:083111ae2a11	730	/**
saloutos	0:083111ae2a11	731	* @}
saloutos	0:083111ae2a11	732	*/
saloutos	0:083111ae2a11	733
saloutos	0:083111ae2a11	734	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
saloutos	0:083111ae2a11	735	* @{
saloutos	0:083111ae2a11	736	*/
saloutos	0:083111ae2a11	737	#define FMC_IT_RISING_EDGE 0x00000008U
saloutos	0:083111ae2a11	738	#define FMC_IT_LEVEL 0x00000010U
saloutos	0:083111ae2a11	739	#define FMC_IT_FALLING_EDGE 0x00000020U
saloutos	0:083111ae2a11	740	#define FMC_IT_REFRESH_ERROR 0x00004000U
saloutos	0:083111ae2a11	741	/**
saloutos	0:083111ae2a11	742	* @}
saloutos	0:083111ae2a11	743	*/
saloutos	0:083111ae2a11	744
saloutos	0:083111ae2a11	745	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
saloutos	0:083111ae2a11	746	* @{
saloutos	0:083111ae2a11	747	*/
saloutos	0:083111ae2a11	748	#define FMC_FLAG_RISING_EDGE 0x00000001U
saloutos	0:083111ae2a11	749	#define FMC_FLAG_LEVEL 0x00000002U
saloutos	0:083111ae2a11	750	#define FMC_FLAG_FALLING_EDGE 0x00000004U
saloutos	0:083111ae2a11	751	#define FMC_FLAG_FEMPT 0x00000040U
saloutos	0:083111ae2a11	752	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
saloutos	0:083111ae2a11	753	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
saloutos	0:083111ae2a11	754	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
saloutos	0:083111ae2a11	755	/**
saloutos	0:083111ae2a11	756	* @}
saloutos	0:083111ae2a11	757	*/
saloutos	0:083111ae2a11	758
saloutos	0:083111ae2a11	759	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
saloutos	0:083111ae2a11	760	* @{
saloutos	0:083111ae2a11	761	*/
saloutos	0:083111ae2a11	762	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
saloutos	0:083111ae2a11	763	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
saloutos	0:083111ae2a11	764	#else
saloutos	0:083111ae2a11	765	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
saloutos	0:083111ae2a11	766	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
saloutos	0:083111ae2a11	767	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
saloutos	0:083111ae2a11	768	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
saloutos	0:083111ae2a11	769	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
saloutos	0:083111ae2a11	770	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
saloutos	0:083111ae2a11	771
saloutos	0:083111ae2a11	772
saloutos	0:083111ae2a11	773	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
saloutos	0:083111ae2a11	774	#define FMC_NAND_DEVICE FMC_Bank3
saloutos	0:083111ae2a11	775	#else
saloutos	0:083111ae2a11	776	#define FMC_NAND_DEVICE FMC_Bank2_3
saloutos	0:083111ae2a11	777	#define FMC_PCCARD_DEVICE FMC_Bank4
saloutos	0:083111ae2a11	778	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
saloutos	0:083111ae2a11	779	#define FMC_NORSRAM_DEVICE FMC_Bank1
saloutos	0:083111ae2a11	780	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
saloutos	0:083111ae2a11	781	#define FMC_SDRAM_DEVICE FMC_Bank5_6
saloutos	0:083111ae2a11	782	/**
saloutos	0:083111ae2a11	783	* @}
saloutos	0:083111ae2a11	784	*/
saloutos	0:083111ae2a11	785
saloutos	0:083111ae2a11	786	/**
saloutos	0:083111ae2a11	787	* @}
saloutos	0:083111ae2a11	788	*/
saloutos	0:083111ae2a11	789
saloutos	0:083111ae2a11	790	/* Private macro -------------------------------------------------------------*/
saloutos	0:083111ae2a11	791	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
saloutos	0:083111ae2a11	792	* @{
saloutos	0:083111ae2a11	793	*/
saloutos	0:083111ae2a11	794
saloutos	0:083111ae2a11	795	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
saloutos	0:083111ae2a11	796	* @brief macros to handle NOR device enable/disable and read/write operations
saloutos	0:083111ae2a11	797	* @{
saloutos	0:083111ae2a11	798	*/
saloutos	0:083111ae2a11	799	/**
saloutos	0:083111ae2a11	800	* @brief Enable the NORSRAM device access.
saloutos	0:083111ae2a11	801	* @param __INSTANCE__: FMC_NORSRAM Instance
saloutos	0:083111ae2a11	802	* @param __BANK__: FMC_NORSRAM Bank
saloutos	0:083111ae2a11	803	* @retval None
saloutos	0:083111ae2a11	804	*/
saloutos	0:083111ae2a11	805	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
saloutos	0:083111ae2a11	806
saloutos	0:083111ae2a11	807	/**
saloutos	0:083111ae2a11	808	* @brief Disable the NORSRAM device access.
saloutos	0:083111ae2a11	809	* @param __INSTANCE__: FMC_NORSRAM Instance
saloutos	0:083111ae2a11	810	* @param __BANK__: FMC_NORSRAM Bank
saloutos	0:083111ae2a11	811	* @retval None
saloutos	0:083111ae2a11	812	*/
saloutos	0:083111ae2a11	813	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
saloutos	0:083111ae2a11	814	/**
saloutos	0:083111ae2a11	815	* @}
saloutos	0:083111ae2a11	816	*/
saloutos	0:083111ae2a11	817
saloutos	0:083111ae2a11	818	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
saloutos	0:083111ae2a11	819	* @brief macros to handle NAND device enable/disable
saloutos	0:083111ae2a11	820	* @{
saloutos	0:083111ae2a11	821	*/
saloutos	0:083111ae2a11	822	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
saloutos	0:083111ae2a11	823	/**
saloutos	0:083111ae2a11	824	* @brief Enable the NAND device access.
saloutos	0:083111ae2a11	825	* @param __INSTANCE__: FMC_NAND Instance
saloutos	0:083111ae2a11	826	* @param __BANK__: FMC_NAND Bank
saloutos	0:083111ae2a11	827	* @retval None
saloutos	0:083111ae2a11	828	*/
saloutos	0:083111ae2a11	829	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
saloutos	0:083111ae2a11	830
saloutos	0:083111ae2a11	831	/**
saloutos	0:083111ae2a11	832	* @brief Disable the NAND device access.
saloutos	0:083111ae2a11	833	* @param __INSTANCE__: FMC_NAND Instance
saloutos	0:083111ae2a11	834	* @param __BANK__: FMC_NAND Bank
saloutos	0:083111ae2a11	835	* @retval None
saloutos	0:083111ae2a11	836	*/
saloutos	0:083111ae2a11	837	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
saloutos	0:083111ae2a11	838	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
saloutos	0:083111ae2a11	839	/**
saloutos	0:083111ae2a11	840	* @brief Enable the NAND device access.
saloutos	0:083111ae2a11	841	* @param __INSTANCE__: FMC_NAND Instance
saloutos	0:083111ae2a11	842	* @param __BANK__: FMC_NAND Bank
saloutos	0:083111ae2a11	843	* @retval None
saloutos	0:083111ae2a11	844	*/
saloutos	0:083111ae2a11	845	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
saloutos	0:083111ae2a11	846	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
saloutos	0:083111ae2a11	847
saloutos	0:083111ae2a11	848	/**
saloutos	0:083111ae2a11	849	* @brief Disable the NAND device access.
saloutos	0:083111ae2a11	850	* @param __INSTANCE__: FMC_NAND Instance
saloutos	0:083111ae2a11	851	* @param __BANK__: FMC_NAND Bank
saloutos	0:083111ae2a11	852	* @retval None
saloutos	0:083111ae2a11	853	*/
saloutos	0:083111ae2a11	854	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
saloutos	0:083111ae2a11	855	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
saloutos	0:083111ae2a11	856
saloutos	0:083111ae2a11	857	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
saloutos	0:083111ae2a11	858	/**
saloutos	0:083111ae2a11	859	* @}
saloutos	0:083111ae2a11	860	*/
saloutos	0:083111ae2a11	861	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
saloutos	0:083111ae2a11	862	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
saloutos	0:083111ae2a11	863	* @brief macros to handle SRAM read/write operations
saloutos	0:083111ae2a11	864	* @{
saloutos	0:083111ae2a11	865	*/
saloutos	0:083111ae2a11	866	/**
saloutos	0:083111ae2a11	867	* @brief Enable the PCCARD device access.
saloutos	0:083111ae2a11	868	* @param __INSTANCE__: FMC_PCCARD Instance
saloutos	0:083111ae2a11	869	* @retval None
saloutos	0:083111ae2a11	870	*/
saloutos	0:083111ae2a11	871	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
saloutos	0:083111ae2a11	872
saloutos	0:083111ae2a11	873	/**
saloutos	0:083111ae2a11	874	* @brief Disable the PCCARD device access.
saloutos	0:083111ae2a11	875	* @param __INSTANCE__: FMC_PCCARD Instance
saloutos	0:083111ae2a11	876	* @retval None
saloutos	0:083111ae2a11	877	*/
saloutos	0:083111ae2a11	878	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
saloutos	0:083111ae2a11	879	/**
saloutos	0:083111ae2a11	880	* @}
saloutos	0:083111ae2a11	881	*/
saloutos	0:083111ae2a11	882	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
saloutos	0:083111ae2a11	883
saloutos	0:083111ae2a11	884	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
saloutos	0:083111ae2a11	885	* @brief macros to handle FMC flags and interrupts
saloutos	0:083111ae2a11	886	* @{
saloutos	0:083111ae2a11	887	*/
saloutos	0:083111ae2a11	888	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
saloutos	0:083111ae2a11	889	/**
saloutos	0:083111ae2a11	890	* @brief Enable the NAND device interrupt.
saloutos	0:083111ae2a11	891	* @param __INSTANCE__: FMC_NAND instance
saloutos	0:083111ae2a11	892	* @param __BANK__: FMC_NAND Bank
saloutos	0:083111ae2a11	893	* @param __INTERRUPT__: FMC_NAND interrupt
saloutos	0:083111ae2a11	894	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	895	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
saloutos	0:083111ae2a11	896	* @arg FMC_IT_LEVEL: Interrupt level.
saloutos	0:083111ae2a11	897	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
saloutos	0:083111ae2a11	898	* @retval None
saloutos	0:083111ae2a11	899	*/
saloutos	0:083111ae2a11	900	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
saloutos	0:083111ae2a11	901
saloutos	0:083111ae2a11	902	/**
saloutos	0:083111ae2a11	903	* @brief Disable the NAND device interrupt.
saloutos	0:083111ae2a11	904	* @param __INSTANCE__: FMC_NAND Instance
saloutos	0:083111ae2a11	905	* @param __BANK__: FMC_NAND Bank
saloutos	0:083111ae2a11	906	* @param __INTERRUPT__: FMC_NAND interrupt
saloutos	0:083111ae2a11	907	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	908	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
saloutos	0:083111ae2a11	909	* @arg FMC_IT_LEVEL: Interrupt level.
saloutos	0:083111ae2a11	910	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
saloutos	0:083111ae2a11	911	* @retval None
saloutos	0:083111ae2a11	912	*/
saloutos	0:083111ae2a11	913	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
saloutos	0:083111ae2a11	914
saloutos	0:083111ae2a11	915	/**
saloutos	0:083111ae2a11	916	* @brief Get flag status of the NAND device.
saloutos	0:083111ae2a11	917	* @param __INSTANCE__: FMC_NAND Instance
saloutos	0:083111ae2a11	918	* @param __BANK__: FMC_NAND Bank
saloutos	0:083111ae2a11	919	* @param __FLAG__: FMC_NAND flag
saloutos	0:083111ae2a11	920	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	921	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
saloutos	0:083111ae2a11	922	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
saloutos	0:083111ae2a11	923	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
saloutos	0:083111ae2a11	924	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
saloutos	0:083111ae2a11	925	* @retval The state of FLAG (SET or RESET).
saloutos	0:083111ae2a11	926	*/
saloutos	0:083111ae2a11	927	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
saloutos	0:083111ae2a11	928	/**
saloutos	0:083111ae2a11	929	* @brief Clear flag status of the NAND device.
saloutos	0:083111ae2a11	930	* @param __INSTANCE__: FMC_NAND Instance
saloutos	0:083111ae2a11	931	* @param __BANK__: FMC_NAND Bank
saloutos	0:083111ae2a11	932	* @param __FLAG__: FMC_NAND flag
saloutos	0:083111ae2a11	933	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	934	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
saloutos	0:083111ae2a11	935	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
saloutos	0:083111ae2a11	936	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
saloutos	0:083111ae2a11	937	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
saloutos	0:083111ae2a11	938	* @retval None
saloutos	0:083111ae2a11	939	*/
saloutos	0:083111ae2a11	940	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
saloutos	0:083111ae2a11	941	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
saloutos	0:083111ae2a11	942	/**
saloutos	0:083111ae2a11	943	* @brief Enable the NAND device interrupt.
saloutos	0:083111ae2a11	944	* @param __INSTANCE__: FMC_NAND instance
saloutos	0:083111ae2a11	945	* @param __BANK__: FMC_NAND Bank
saloutos	0:083111ae2a11	946	* @param __INTERRUPT__: FMC_NAND interrupt
saloutos	0:083111ae2a11	947	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	948	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
saloutos	0:083111ae2a11	949	* @arg FMC_IT_LEVEL: Interrupt level.
saloutos	0:083111ae2a11	950	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
saloutos	0:083111ae2a11	951	* @retval None
saloutos	0:083111ae2a11	952	*/
saloutos	0:083111ae2a11	953	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
saloutos	0:083111ae2a11	954	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
saloutos	0:083111ae2a11	955
saloutos	0:083111ae2a11	956	/**
saloutos	0:083111ae2a11	957	* @brief Disable the NAND device interrupt.
saloutos	0:083111ae2a11	958	* @param __INSTANCE__: FMC_NAND Instance
saloutos	0:083111ae2a11	959	* @param __BANK__: FMC_NAND Bank
saloutos	0:083111ae2a11	960	* @param __INTERRUPT__: FMC_NAND interrupt
saloutos	0:083111ae2a11	961	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	962	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
saloutos	0:083111ae2a11	963	* @arg FMC_IT_LEVEL: Interrupt level.
saloutos	0:083111ae2a11	964	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
saloutos	0:083111ae2a11	965	* @retval None
saloutos	0:083111ae2a11	966	*/
saloutos	0:083111ae2a11	967	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
saloutos	0:083111ae2a11	968	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
saloutos	0:083111ae2a11	969
saloutos	0:083111ae2a11	970	/**
saloutos	0:083111ae2a11	971	* @brief Get flag status of the NAND device.
saloutos	0:083111ae2a11	972	* @param __INSTANCE__: FMC_NAND Instance
saloutos	0:083111ae2a11	973	* @param __BANK__: FMC_NAND Bank
saloutos	0:083111ae2a11	974	* @param __FLAG__: FMC_NAND flag
saloutos	0:083111ae2a11	975	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	976	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
saloutos	0:083111ae2a11	977	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
saloutos	0:083111ae2a11	978	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
saloutos	0:083111ae2a11	979	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
saloutos	0:083111ae2a11	980	* @retval The state of FLAG (SET or RESET).
saloutos	0:083111ae2a11	981	*/
saloutos	0:083111ae2a11	982	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
saloutos	0:083111ae2a11	983	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
saloutos	0:083111ae2a11	984	/**
saloutos	0:083111ae2a11	985	* @brief Clear flag status of the NAND device.
saloutos	0:083111ae2a11	986	* @param __INSTANCE__: FMC_NAND Instance
saloutos	0:083111ae2a11	987	* @param __BANK__: FMC_NAND Bank
saloutos	0:083111ae2a11	988	* @param __FLAG__: FMC_NAND flag
saloutos	0:083111ae2a11	989	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	990	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
saloutos	0:083111ae2a11	991	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
saloutos	0:083111ae2a11	992	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
saloutos	0:083111ae2a11	993	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
saloutos	0:083111ae2a11	994	* @retval None
saloutos	0:083111ae2a11	995	*/
saloutos	0:083111ae2a11	996	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
saloutos	0:083111ae2a11	997	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
saloutos	0:083111ae2a11	998	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
saloutos	0:083111ae2a11	999
saloutos	0:083111ae2a11	1000	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
saloutos	0:083111ae2a11	1001	/**
saloutos	0:083111ae2a11	1002	* @brief Enable the PCCARD device interrupt.
saloutos	0:083111ae2a11	1003	* @param __INSTANCE__: FMC_PCCARD instance
saloutos	0:083111ae2a11	1004	* @param __INTERRUPT__: FMC_PCCARD interrupt
saloutos	0:083111ae2a11	1005	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	1006	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
saloutos	0:083111ae2a11	1007	* @arg FMC_IT_LEVEL: Interrupt level.
saloutos	0:083111ae2a11	1008	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
saloutos	0:083111ae2a11	1009	* @retval None
saloutos	0:083111ae2a11	1010	*/
saloutos	0:083111ae2a11	1011	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
saloutos	0:083111ae2a11	1012
saloutos	0:083111ae2a11	1013	/**
saloutos	0:083111ae2a11	1014	* @brief Disable the PCCARD device interrupt.
saloutos	0:083111ae2a11	1015	* @param __INSTANCE__: FMC_PCCARD instance
saloutos	0:083111ae2a11	1016	* @param __INTERRUPT__: FMC_PCCARD interrupt
saloutos	0:083111ae2a11	1017	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	1018	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
saloutos	0:083111ae2a11	1019	* @arg FMC_IT_LEVEL: Interrupt level.
saloutos	0:083111ae2a11	1020	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
saloutos	0:083111ae2a11	1021	* @retval None
saloutos	0:083111ae2a11	1022	*/
saloutos	0:083111ae2a11	1023	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
saloutos	0:083111ae2a11	1024
saloutos	0:083111ae2a11	1025	/**
saloutos	0:083111ae2a11	1026	* @brief Get flag status of the PCCARD device.
saloutos	0:083111ae2a11	1027	* @param __INSTANCE__: FMC_PCCARD instance
saloutos	0:083111ae2a11	1028	* @param __FLAG__: FMC_PCCARD flag
saloutos	0:083111ae2a11	1029	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	1030	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
saloutos	0:083111ae2a11	1031	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
saloutos	0:083111ae2a11	1032	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
saloutos	0:083111ae2a11	1033	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
saloutos	0:083111ae2a11	1034	* @retval The state of FLAG (SET or RESET).
saloutos	0:083111ae2a11	1035	*/
saloutos	0:083111ae2a11	1036	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
saloutos	0:083111ae2a11	1037
saloutos	0:083111ae2a11	1038	/**
saloutos	0:083111ae2a11	1039	* @brief Clear flag status of the PCCARD device.
saloutos	0:083111ae2a11	1040	* @param __INSTANCE__: FMC_PCCARD instance
saloutos	0:083111ae2a11	1041	* @param __FLAG__: FMC_PCCARD flag
saloutos	0:083111ae2a11	1042	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	1043	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
saloutos	0:083111ae2a11	1044	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
saloutos	0:083111ae2a11	1045	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
saloutos	0:083111ae2a11	1046	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
saloutos	0:083111ae2a11	1047	* @retval None
saloutos	0:083111ae2a11	1048	*/
saloutos	0:083111ae2a11	1049	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
saloutos	0:083111ae2a11	1050	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
saloutos	0:083111ae2a11	1051
saloutos	0:083111ae2a11	1052	/**
saloutos	0:083111ae2a11	1053	* @brief Enable the SDRAM device interrupt.
saloutos	0:083111ae2a11	1054	* @param __INSTANCE__: FMC_SDRAM instance
saloutos	0:083111ae2a11	1055	* @param __INTERRUPT__: FMC_SDRAM interrupt
saloutos	0:083111ae2a11	1056	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	1057	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
saloutos	0:083111ae2a11	1058	* @retval None
saloutos	0:083111ae2a11	1059	*/
saloutos	0:083111ae2a11	1060	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
saloutos	0:083111ae2a11	1061
saloutos	0:083111ae2a11	1062	/**
saloutos	0:083111ae2a11	1063	* @brief Disable the SDRAM device interrupt.
saloutos	0:083111ae2a11	1064	* @param __INSTANCE__: FMC_SDRAM instance
saloutos	0:083111ae2a11	1065	* @param __INTERRUPT__: FMC_SDRAM interrupt
saloutos	0:083111ae2a11	1066	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	1067	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
saloutos	0:083111ae2a11	1068	* @retval None
saloutos	0:083111ae2a11	1069	*/
saloutos	0:083111ae2a11	1070	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
saloutos	0:083111ae2a11	1071
saloutos	0:083111ae2a11	1072	/**
saloutos	0:083111ae2a11	1073	* @brief Get flag status of the SDRAM device.
saloutos	0:083111ae2a11	1074	* @param __INSTANCE__: FMC_SDRAM instance
saloutos	0:083111ae2a11	1075	* @param __FLAG__: FMC_SDRAM flag
saloutos	0:083111ae2a11	1076	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	1077	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
saloutos	0:083111ae2a11	1078	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
saloutos	0:083111ae2a11	1079	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
saloutos	0:083111ae2a11	1080	* @retval The state of FLAG (SET or RESET).
saloutos	0:083111ae2a11	1081	*/
saloutos	0:083111ae2a11	1082	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
saloutos	0:083111ae2a11	1083
saloutos	0:083111ae2a11	1084	/**
saloutos	0:083111ae2a11	1085	* @brief Clear flag status of the SDRAM device.
saloutos	0:083111ae2a11	1086	* @param __INSTANCE__: FMC_SDRAM instance
saloutos	0:083111ae2a11	1087	* @param __FLAG__: FMC_SDRAM flag
saloutos	0:083111ae2a11	1088	* This parameter can be any combination of the following values:
saloutos	0:083111ae2a11	1089	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
saloutos	0:083111ae2a11	1090	* @retval None
saloutos	0:083111ae2a11	1091	*/
saloutos	0:083111ae2a11	1092	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
saloutos	0:083111ae2a11	1093	/**
saloutos	0:083111ae2a11	1094	* @}
saloutos	0:083111ae2a11	1095	*/
saloutos	0:083111ae2a11	1096
saloutos	0:083111ae2a11	1097	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
saloutos	0:083111ae2a11	1098	* @{
saloutos	0:083111ae2a11	1099	*/
saloutos	0:083111ae2a11	1100	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
saloutos	0:083111ae2a11	1101	((BANK) == FMC_NORSRAM_BANK2) \|\| \
saloutos	0:083111ae2a11	1102	((BANK) == FMC_NORSRAM_BANK3) \|\| \
saloutos	0:083111ae2a11	1103	((BANK) == FMC_NORSRAM_BANK4))
saloutos	0:083111ae2a11	1104
saloutos	0:083111ae2a11	1105	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
saloutos	0:083111ae2a11	1106	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
saloutos	0:083111ae2a11	1107
saloutos	0:083111ae2a11	1108	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
saloutos	0:083111ae2a11	1109	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
saloutos	0:083111ae2a11	1110	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
saloutos	0:083111ae2a11	1111
saloutos	0:083111ae2a11	1112	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
saloutos	0:083111ae2a11	1113	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
saloutos	0:083111ae2a11	1114	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
saloutos	0:083111ae2a11	1115
saloutos	0:083111ae2a11	1116	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
saloutos	0:083111ae2a11	1117	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
saloutos	0:083111ae2a11	1118	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
saloutos	0:083111ae2a11	1119	((__MODE__) == FMC_ACCESS_MODE_D))
saloutos	0:083111ae2a11	1120
saloutos	0:083111ae2a11	1121	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
saloutos	0:083111ae2a11	1122	((BANK) == FMC_NAND_BANK3))
saloutos	0:083111ae2a11	1123
saloutos	0:083111ae2a11	1124	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
saloutos	0:083111ae2a11	1125	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
saloutos	0:083111ae2a11	1126
saloutos	0:083111ae2a11	1127	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
saloutos	0:083111ae2a11	1128	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
saloutos	0:083111ae2a11	1129
saloutos	0:083111ae2a11	1130	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
saloutos	0:083111ae2a11	1131	((STATE) == FMC_NAND_ECC_ENABLE))
saloutos	0:083111ae2a11	1132
saloutos	0:083111ae2a11	1133	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
saloutos	0:083111ae2a11	1134	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
saloutos	0:083111ae2a11	1135	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
saloutos	0:083111ae2a11	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
saloutos	0:083111ae2a11	1137	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
saloutos	0:083111ae2a11	1138	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
saloutos	0:083111ae2a11	1139
saloutos	0:083111ae2a11	1140	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
saloutos	0:083111ae2a11	1141
saloutos	0:083111ae2a11	1142	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
saloutos	0:083111ae2a11	1143
saloutos	0:083111ae2a11	1144	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
saloutos	0:083111ae2a11	1145
saloutos	0:083111ae2a11	1146	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
saloutos	0:083111ae2a11	1147
saloutos	0:083111ae2a11	1148	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
saloutos	0:083111ae2a11	1149
saloutos	0:083111ae2a11	1150	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
saloutos	0:083111ae2a11	1151
saloutos	0:083111ae2a11	1152	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
saloutos	0:083111ae2a11	1153
saloutos	0:083111ae2a11	1154	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
saloutos	0:083111ae2a11	1155
saloutos	0:083111ae2a11	1156	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
saloutos	0:083111ae2a11	1157
saloutos	0:083111ae2a11	1158	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
saloutos	0:083111ae2a11	1159
saloutos	0:083111ae2a11	1160	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
saloutos	0:083111ae2a11	1161	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
saloutos	0:083111ae2a11	1162
saloutos	0:083111ae2a11	1163	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
saloutos	0:083111ae2a11	1164	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
saloutos	0:083111ae2a11	1165
saloutos	0:083111ae2a11	1166	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
saloutos	0:083111ae2a11	1167	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
saloutos	0:083111ae2a11	1168	((__MODE__) == FMC_WRAP_MODE_ENABLE))
saloutos	0:083111ae2a11	1169	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
saloutos	0:083111ae2a11	1170
saloutos	0:083111ae2a11	1171	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
saloutos	0:083111ae2a11	1172	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
saloutos	0:083111ae2a11	1173
saloutos	0:083111ae2a11	1174	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
saloutos	0:083111ae2a11	1175	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
saloutos	0:083111ae2a11	1176
saloutos	0:083111ae2a11	1177	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
saloutos	0:083111ae2a11	1178	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
saloutos	0:083111ae2a11	1179
saloutos	0:083111ae2a11	1180	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
saloutos	0:083111ae2a11	1181	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
saloutos	0:083111ae2a11	1182
saloutos	0:083111ae2a11	1183	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
saloutos	0:083111ae2a11	1184	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
saloutos	0:083111ae2a11	1185
saloutos	0:083111ae2a11	1186	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
saloutos	0:083111ae2a11	1187	((__BURST__) == FMC_WRITE_BURST_ENABLE))
saloutos	0:083111ae2a11	1188
saloutos	0:083111ae2a11	1189	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
saloutos	0:083111ae2a11	1190	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
saloutos	0:083111ae2a11	1191
saloutos	0:083111ae2a11	1192	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
saloutos	0:083111ae2a11	1193
saloutos	0:083111ae2a11	1194	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
saloutos	0:083111ae2a11	1195
saloutos	0:083111ae2a11	1196	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
saloutos	0:083111ae2a11	1197
saloutos	0:083111ae2a11	1198	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
saloutos	0:083111ae2a11	1199
saloutos	0:083111ae2a11	1200	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
saloutos	0:083111ae2a11	1201
saloutos	0:083111ae2a11	1202	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
saloutos	0:083111ae2a11	1203
saloutos	0:083111ae2a11	1204	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
saloutos	0:083111ae2a11	1205	((BANK) == FMC_SDRAM_BANK2))
saloutos	0:083111ae2a11	1206
saloutos	0:083111ae2a11	1207	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
saloutos	0:083111ae2a11	1208	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
saloutos	0:083111ae2a11	1209	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
saloutos	0:083111ae2a11	1210	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
saloutos	0:083111ae2a11	1211
saloutos	0:083111ae2a11	1212	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
saloutos	0:083111ae2a11	1213	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
saloutos	0:083111ae2a11	1214	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
saloutos	0:083111ae2a11	1215
saloutos	0:083111ae2a11	1216	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
saloutos	0:083111ae2a11	1217	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
saloutos	0:083111ae2a11	1218	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
saloutos	0:083111ae2a11	1219
saloutos	0:083111ae2a11	1220	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
saloutos	0:083111ae2a11	1221	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
saloutos	0:083111ae2a11	1222
saloutos	0:083111ae2a11	1223
saloutos	0:083111ae2a11	1224	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
saloutos	0:083111ae2a11	1225	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
saloutos	0:083111ae2a11	1226	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
saloutos	0:083111ae2a11	1227
saloutos	0:083111ae2a11	1228	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
saloutos	0:083111ae2a11	1229	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
saloutos	0:083111ae2a11	1230	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
saloutos	0:083111ae2a11	1231
saloutos	0:083111ae2a11	1232	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
saloutos	0:083111ae2a11	1233	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
saloutos	0:083111ae2a11	1234
saloutos	0:083111ae2a11	1235
saloutos	0:083111ae2a11	1236	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
saloutos	0:083111ae2a11	1237	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
saloutos	0:083111ae2a11	1238	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
saloutos	0:083111ae2a11	1239
saloutos	0:083111ae2a11	1240	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
saloutos	0:083111ae2a11	1241
saloutos	0:083111ae2a11	1242	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
saloutos	0:083111ae2a11	1243
saloutos	0:083111ae2a11	1244	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
saloutos	0:083111ae2a11	1245
saloutos	0:083111ae2a11	1246	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
saloutos	0:083111ae2a11	1247
saloutos	0:083111ae2a11	1248	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
saloutos	0:083111ae2a11	1249
saloutos	0:083111ae2a11	1250	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
saloutos	0:083111ae2a11	1251
saloutos	0:083111ae2a11	1252	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
saloutos	0:083111ae2a11	1253
saloutos	0:083111ae2a11	1254	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
saloutos	0:083111ae2a11	1255	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
saloutos	0:083111ae2a11	1256	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
saloutos	0:083111ae2a11	1257	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
saloutos	0:083111ae2a11	1258	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
saloutos	0:083111ae2a11	1259	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
saloutos	0:083111ae2a11	1260	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
saloutos	0:083111ae2a11	1261
saloutos	0:083111ae2a11	1262	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
saloutos	0:083111ae2a11	1263	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
saloutos	0:083111ae2a11	1264	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
saloutos	0:083111ae2a11	1265
saloutos	0:083111ae2a11	1266	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
saloutos	0:083111ae2a11	1267
saloutos	0:083111ae2a11	1268	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
saloutos	0:083111ae2a11	1269
saloutos	0:083111ae2a11	1270	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
saloutos	0:083111ae2a11	1271
saloutos	0:083111ae2a11	1272	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
saloutos	0:083111ae2a11	1273
saloutos	0:083111ae2a11	1274	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
saloutos	0:083111ae2a11	1275	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
saloutos	0:083111ae2a11	1276
saloutos	0:083111ae2a11	1277	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
saloutos	0:083111ae2a11	1278	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
saloutos	0:083111ae2a11	1279	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
saloutos	0:083111ae2a11	1280	((SIZE) == FMC_PAGE_SIZE_512) \|\| \
saloutos	0:083111ae2a11	1281	((SIZE) == FMC_PAGE_SIZE_1024))
saloutos	0:083111ae2a11	1282
saloutos	0:083111ae2a11	1283	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
saloutos	0:083111ae2a11	1284	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
saloutos	0:083111ae2a11	1285	((FIFO) == FMC_WRITE_FIFO_ENABLE))
saloutos	0:083111ae2a11	1286	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
saloutos	0:083111ae2a11	1287
saloutos	0:083111ae2a11	1288	/**
saloutos	0:083111ae2a11	1289	* @}
saloutos	0:083111ae2a11	1290	*/
saloutos	0:083111ae2a11	1291
saloutos	0:083111ae2a11	1292	/**
saloutos	0:083111ae2a11	1293	* @}
saloutos	0:083111ae2a11	1294	*/
saloutos	0:083111ae2a11	1295
saloutos	0:083111ae2a11	1296	/* Private functions ---------------------------------------------------------*/
saloutos	0:083111ae2a11	1297	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
saloutos	0:083111ae2a11	1298	* @{
saloutos	0:083111ae2a11	1299	*/
saloutos	0:083111ae2a11	1300
saloutos	0:083111ae2a11	1301	/** @defgroup FMC_LL_NORSRAM NOR SRAM
saloutos	0:083111ae2a11	1302	* @{
saloutos	0:083111ae2a11	1303	*/
saloutos	0:083111ae2a11	1304	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
saloutos	0:083111ae2a11	1305	* @{
saloutos	0:083111ae2a11	1306	*/
saloutos	0:083111ae2a11	1307	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
saloutos	0:083111ae2a11	1308	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
saloutos	0:083111ae2a11	1309	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
saloutos	0:083111ae2a11	1310	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
saloutos	0:083111ae2a11	1311	/**
saloutos	0:083111ae2a11	1312	* @}
saloutos	0:083111ae2a11	1313	*/
saloutos	0:083111ae2a11	1314
saloutos	0:083111ae2a11	1315	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
saloutos	0:083111ae2a11	1316	* @{
saloutos	0:083111ae2a11	1317	*/
saloutos	0:083111ae2a11	1318	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
saloutos	0:083111ae2a11	1319	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
saloutos	0:083111ae2a11	1320	/**
saloutos	0:083111ae2a11	1321	* @}
saloutos	0:083111ae2a11	1322	*/
saloutos	0:083111ae2a11	1323	/**
saloutos	0:083111ae2a11	1324	* @}
saloutos	0:083111ae2a11	1325	*/
saloutos	0:083111ae2a11	1326
saloutos	0:083111ae2a11	1327	/** @defgroup FMC_LL_NAND NAND
saloutos	0:083111ae2a11	1328	* @{
saloutos	0:083111ae2a11	1329	*/
saloutos	0:083111ae2a11	1330	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
saloutos	0:083111ae2a11	1331	* @{
saloutos	0:083111ae2a11	1332	*/
saloutos	0:083111ae2a11	1333	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
saloutos	0:083111ae2a11	1334	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
saloutos	0:083111ae2a11	1335	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
saloutos	0:083111ae2a11	1336	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
saloutos	0:083111ae2a11	1337	/**
saloutos	0:083111ae2a11	1338	* @}
saloutos	0:083111ae2a11	1339	*/
saloutos	0:083111ae2a11	1340
saloutos	0:083111ae2a11	1341	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
saloutos	0:083111ae2a11	1342	* @{
saloutos	0:083111ae2a11	1343	*/
saloutos	0:083111ae2a11	1344	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
saloutos	0:083111ae2a11	1345	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
saloutos	0:083111ae2a11	1346	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
saloutos	0:083111ae2a11	1347
saloutos	0:083111ae2a11	1348	/**
saloutos	0:083111ae2a11	1349	* @}
saloutos	0:083111ae2a11	1350	*/
saloutos	0:083111ae2a11	1351	/**
saloutos	0:083111ae2a11	1352	* @}
saloutos	0:083111ae2a11	1353	*/
saloutos	0:083111ae2a11	1354	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
saloutos	0:083111ae2a11	1355	/** @defgroup FMC_LL_PCCARD PCCARD
saloutos	0:083111ae2a11	1356	* @{
saloutos	0:083111ae2a11	1357	*/
saloutos	0:083111ae2a11	1358	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
saloutos	0:083111ae2a11	1359	* @{
saloutos	0:083111ae2a11	1360	*/
saloutos	0:083111ae2a11	1361	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
saloutos	0:083111ae2a11	1362	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
saloutos	0:083111ae2a11	1363	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
saloutos	0:083111ae2a11	1364	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
saloutos	0:083111ae2a11	1365	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
saloutos	0:083111ae2a11	1366	/**
saloutos	0:083111ae2a11	1367	* @}
saloutos	0:083111ae2a11	1368	*/
saloutos	0:083111ae2a11	1369	/**
saloutos	0:083111ae2a11	1370	* @}
saloutos	0:083111ae2a11	1371	*/
saloutos	0:083111ae2a11	1372	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
saloutos	0:083111ae2a11	1373
saloutos	0:083111ae2a11	1374	/** @defgroup FMC_LL_SDRAM SDRAM
saloutos	0:083111ae2a11	1375	* @{
saloutos	0:083111ae2a11	1376	*/
saloutos	0:083111ae2a11	1377	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
saloutos	0:083111ae2a11	1378	* @{
saloutos	0:083111ae2a11	1379	*/
saloutos	0:083111ae2a11	1380	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
saloutos	0:083111ae2a11	1381	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
saloutos	0:083111ae2a11	1382	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
saloutos	0:083111ae2a11	1383	/**
saloutos	0:083111ae2a11	1384	* @}
saloutos	0:083111ae2a11	1385	*/
saloutos	0:083111ae2a11	1386
saloutos	0:083111ae2a11	1387	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
saloutos	0:083111ae2a11	1388	* @{
saloutos	0:083111ae2a11	1389	*/
saloutos	0:083111ae2a11	1390	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
saloutos	0:083111ae2a11	1391	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
saloutos	0:083111ae2a11	1392	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
saloutos	0:083111ae2a11	1393	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
saloutos	0:083111ae2a11	1394	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
saloutos	0:083111ae2a11	1395	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
saloutos	0:083111ae2a11	1396	/**
saloutos	0:083111ae2a11	1397	* @}
saloutos	0:083111ae2a11	1398	*/
saloutos	0:083111ae2a11	1399	/**
saloutos	0:083111ae2a11	1400	* @}
saloutos	0:083111ae2a11	1401	*/
saloutos	0:083111ae2a11	1402
saloutos	0:083111ae2a11	1403	/**
saloutos	0:083111ae2a11	1404	* @}
saloutos	0:083111ae2a11	1405	*/
saloutos	0:083111ae2a11	1406
saloutos	0:083111ae2a11	1407	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
saloutos	0:083111ae2a11	1408	/**
saloutos	0:083111ae2a11	1409	* @}
saloutos	0:083111ae2a11	1410	*/
saloutos	0:083111ae2a11	1411
saloutos	0:083111ae2a11	1412	/**
saloutos	0:083111ae2a11	1413	* @}
saloutos	0:083111ae2a11	1414	*/
saloutos	0:083111ae2a11	1415	#ifdef __cplusplus
saloutos	0:083111ae2a11	1416	}
saloutos	0:083111ae2a11	1417	#endif
saloutos	0:083111ae2a11	1418
saloutos	0:083111ae2a11	1419	#endif /* __STM32F4xx_LL_FMC_H */
saloutos	0:083111ae2a11	1420
saloutos	0:083111ae2a11	1421	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	09 Mar 2021
Imports:	13
Forks:	0
Commits:	4
Dependents:	4
Dependencies:	0
Followers:	1

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