mbed-dev - Biomimetics MBED Library w/ Added Support for CAN3

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Biomimetics MBED Library w/ Added Support for CAN3

Dependents: CAN_TEST SPIne_Plus_DYNO_SENSORS SPIne_Plus_v2 SPIne_Plus_Dyno_v2

cmsis/core_cm33.h@0:083111ae2a11, 2020-11-26 (annotated)

Committer:: saloutos
Date:: Thu Nov 26 04:08:56 2020 +0000
Revision:: 0:083111ae2a11

first commit of leaned mbed dev lib

Who changed what in which revision?

User	Revision	Line number	New contents of line
saloutos	0:083111ae2a11	1	/************************************************************************//
saloutos	0:083111ae2a11	2	* @file core_cm33.h
saloutos	0:083111ae2a11	3	* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
saloutos	0:083111ae2a11	4	* @version V5.0.2
saloutos	0:083111ae2a11	5	* @date 13. February 2017
saloutos	0:083111ae2a11	6	******************************************************************************/
saloutos	0:083111ae2a11	7	/*
saloutos	0:083111ae2a11	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
saloutos	0:083111ae2a11	9	*
saloutos	0:083111ae2a11	10	* SPDX-License-Identifier: Apache-2.0
saloutos	0:083111ae2a11	11	*
saloutos	0:083111ae2a11	12	* Licensed under the Apache License, Version 2.0 (the License); you may
saloutos	0:083111ae2a11	13	* not use this file except in compliance with the License.
saloutos	0:083111ae2a11	14	* You may obtain a copy of the License at
saloutos	0:083111ae2a11	15	*
saloutos	0:083111ae2a11	16	* www.apache.org/licenses/LICENSE-2.0
saloutos	0:083111ae2a11	17	*
saloutos	0:083111ae2a11	18	* Unless required by applicable law or agreed to in writing, software
saloutos	0:083111ae2a11	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
saloutos	0:083111ae2a11	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
saloutos	0:083111ae2a11	21	* See the License for the specific language governing permissions and
saloutos	0:083111ae2a11	22	* limitations under the License.
saloutos	0:083111ae2a11	23	*/
saloutos	0:083111ae2a11	24
saloutos	0:083111ae2a11	25	#if defined ( __ICCARM__ )
saloutos	0:083111ae2a11	26	#pragma system_include /* treat file as system include file for MISRA check */
saloutos	0:083111ae2a11	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
saloutos	0:083111ae2a11	28	#pragma clang system_header /* treat file as system include file */
saloutos	0:083111ae2a11	29	#endif
saloutos	0:083111ae2a11	30
saloutos	0:083111ae2a11	31	#ifndef __CORE_CM33_H_GENERIC
saloutos	0:083111ae2a11	32	#define __CORE_CM33_H_GENERIC
saloutos	0:083111ae2a11	33
saloutos	0:083111ae2a11	34	#include <stdint.h>
saloutos	0:083111ae2a11	35
saloutos	0:083111ae2a11	36	#ifdef __cplusplus
saloutos	0:083111ae2a11	37	extern "C" {
saloutos	0:083111ae2a11	38	#endif
saloutos	0:083111ae2a11	39
saloutos	0:083111ae2a11	40	/**
saloutos	0:083111ae2a11	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
saloutos	0:083111ae2a11	42	CMSIS violates the following MISRA-C:2004 rules:
saloutos	0:083111ae2a11	43
saloutos	0:083111ae2a11	44	\li Required Rule 8.5, object/function definition in header file.<br>
saloutos	0:083111ae2a11	45	Function definitions in header files are used to allow 'inlining'.
saloutos	0:083111ae2a11	46
saloutos	0:083111ae2a11	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
saloutos	0:083111ae2a11	48	Unions are used for effective representation of core registers.
saloutos	0:083111ae2a11	49
saloutos	0:083111ae2a11	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
saloutos	0:083111ae2a11	51	Function-like macros are used to allow more efficient code.
saloutos	0:083111ae2a11	52	*/
saloutos	0:083111ae2a11	53
saloutos	0:083111ae2a11	54
saloutos	0:083111ae2a11	55	/*******************************************************************************
saloutos	0:083111ae2a11	56	* CMSIS definitions
saloutos	0:083111ae2a11	57	******************************************************************************/
saloutos	0:083111ae2a11	58	/**
saloutos	0:083111ae2a11	59	\ingroup Cortex_M33
saloutos	0:083111ae2a11	60	@{
saloutos	0:083111ae2a11	61	*/
saloutos	0:083111ae2a11	62
saloutos	0:083111ae2a11	63	/* CMSIS CM33 definitions */
saloutos	0:083111ae2a11	64	#define __CM33_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
saloutos	0:083111ae2a11	65	#define __CM33_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
saloutos	0:083111ae2a11	66	#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) \| \
saloutos	0:083111ae2a11	67	__CM33_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
saloutos	0:083111ae2a11	68
saloutos	0:083111ae2a11	69	#define __CORTEX_M (33U) /!< Cortex-M Core /
saloutos	0:083111ae2a11	70
saloutos	0:083111ae2a11	71	/** __FPU_USED indicates whether an FPU is used or not.
saloutos	0:083111ae2a11	72	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
saloutos	0:083111ae2a11	73	*/
saloutos	0:083111ae2a11	74	#if defined ( __CC_ARM )
saloutos	0:083111ae2a11	75	#if defined __TARGET_FPU_VFP
saloutos	0:083111ae2a11	76	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos	0:083111ae2a11	77	#define __FPU_USED 1U
saloutos	0:083111ae2a11	78	#else
saloutos	0:083111ae2a11	79	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	80	#define __FPU_USED 0U
saloutos	0:083111ae2a11	81	#endif
saloutos	0:083111ae2a11	82	#else
saloutos	0:083111ae2a11	83	#define __FPU_USED 0U
saloutos	0:083111ae2a11	84	#endif
saloutos	0:083111ae2a11	85
saloutos	0:083111ae2a11	86	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
saloutos	0:083111ae2a11	87	#if defined __ARM_PCS_VFP
saloutos	0:083111ae2a11	88	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos	0:083111ae2a11	89	#define __FPU_USED 1U
saloutos	0:083111ae2a11	90	#else
saloutos	0:083111ae2a11	91	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	92	#define __FPU_USED 0U
saloutos	0:083111ae2a11	93	#endif
saloutos	0:083111ae2a11	94	#else
saloutos	0:083111ae2a11	95	#define __FPU_USED 0U
saloutos	0:083111ae2a11	96	#endif
saloutos	0:083111ae2a11	97
saloutos	0:083111ae2a11	98	#elif defined ( __GNUC__ )
saloutos	0:083111ae2a11	99	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
saloutos	0:083111ae2a11	100	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos	0:083111ae2a11	101	#define __FPU_USED 1U
saloutos	0:083111ae2a11	102	#else
saloutos	0:083111ae2a11	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	104	#define __FPU_USED 0U
saloutos	0:083111ae2a11	105	#endif
saloutos	0:083111ae2a11	106	#else
saloutos	0:083111ae2a11	107	#define __FPU_USED 0U
saloutos	0:083111ae2a11	108	#endif
saloutos	0:083111ae2a11	109
saloutos	0:083111ae2a11	110	#elif defined ( __ICCARM__ )
saloutos	0:083111ae2a11	111	#if defined __ARMVFP__
saloutos	0:083111ae2a11	112	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos	0:083111ae2a11	113	#define __FPU_USED 1U
saloutos	0:083111ae2a11	114	#else
saloutos	0:083111ae2a11	115	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	116	#define __FPU_USED 0U
saloutos	0:083111ae2a11	117	#endif
saloutos	0:083111ae2a11	118	#else
saloutos	0:083111ae2a11	119	#define __FPU_USED 0U
saloutos	0:083111ae2a11	120	#endif
saloutos	0:083111ae2a11	121
saloutos	0:083111ae2a11	122	#elif defined ( __TI_ARM__ )
saloutos	0:083111ae2a11	123	#if defined __TI_VFP_SUPPORT__
saloutos	0:083111ae2a11	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos	0:083111ae2a11	125	#define __FPU_USED 1U
saloutos	0:083111ae2a11	126	#else
saloutos	0:083111ae2a11	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	128	#define __FPU_USED 0U
saloutos	0:083111ae2a11	129	#endif
saloutos	0:083111ae2a11	130	#else
saloutos	0:083111ae2a11	131	#define __FPU_USED 0U
saloutos	0:083111ae2a11	132	#endif
saloutos	0:083111ae2a11	133
saloutos	0:083111ae2a11	134	#elif defined ( __TASKING__ )
saloutos	0:083111ae2a11	135	#if defined __FPU_VFP__
saloutos	0:083111ae2a11	136	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos	0:083111ae2a11	137	#define __FPU_USED 1U
saloutos	0:083111ae2a11	138	#else
saloutos	0:083111ae2a11	139	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	140	#define __FPU_USED 0U
saloutos	0:083111ae2a11	141	#endif
saloutos	0:083111ae2a11	142	#else
saloutos	0:083111ae2a11	143	#define __FPU_USED 0U
saloutos	0:083111ae2a11	144	#endif
saloutos	0:083111ae2a11	145
saloutos	0:083111ae2a11	146	#elif defined ( __CSMC__ )
saloutos	0:083111ae2a11	147	#if ( __CSMC__ & 0x400U)
saloutos	0:083111ae2a11	148	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos	0:083111ae2a11	149	#define __FPU_USED 1U
saloutos	0:083111ae2a11	150	#else
saloutos	0:083111ae2a11	151	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	152	#define __FPU_USED 0U
saloutos	0:083111ae2a11	153	#endif
saloutos	0:083111ae2a11	154	#else
saloutos	0:083111ae2a11	155	#define __FPU_USED 0U
saloutos	0:083111ae2a11	156	#endif
saloutos	0:083111ae2a11	157
saloutos	0:083111ae2a11	158	#endif
saloutos	0:083111ae2a11	159
saloutos	0:083111ae2a11	160	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
saloutos	0:083111ae2a11	161
saloutos	0:083111ae2a11	162
saloutos	0:083111ae2a11	163	#ifdef __cplusplus
saloutos	0:083111ae2a11	164	}
saloutos	0:083111ae2a11	165	#endif
saloutos	0:083111ae2a11	166
saloutos	0:083111ae2a11	167	#endif /* __CORE_CM33_H_GENERIC */
saloutos	0:083111ae2a11	168
saloutos	0:083111ae2a11	169	#ifndef __CMSIS_GENERIC
saloutos	0:083111ae2a11	170
saloutos	0:083111ae2a11	171	#ifndef __CORE_CM33_H_DEPENDANT
saloutos	0:083111ae2a11	172	#define __CORE_CM33_H_DEPENDANT
saloutos	0:083111ae2a11	173
saloutos	0:083111ae2a11	174	#ifdef __cplusplus
saloutos	0:083111ae2a11	175	extern "C" {
saloutos	0:083111ae2a11	176	#endif
saloutos	0:083111ae2a11	177
saloutos	0:083111ae2a11	178	/* check device defines and use defaults */
saloutos	0:083111ae2a11	179	#if defined __CHECK_DEVICE_DEFINES
saloutos	0:083111ae2a11	180	#ifndef __CM33_REV
saloutos	0:083111ae2a11	181	#define __CM33_REV 0x0000U
saloutos	0:083111ae2a11	182	#warning "__CM33_REV not defined in device header file; using default!"
saloutos	0:083111ae2a11	183	#endif
saloutos	0:083111ae2a11	184
saloutos	0:083111ae2a11	185	#ifndef __FPU_PRESENT
saloutos	0:083111ae2a11	186	#define __FPU_PRESENT 0U
saloutos	0:083111ae2a11	187	#warning "__FPU_PRESENT not defined in device header file; using default!"
saloutos	0:083111ae2a11	188	#endif
saloutos	0:083111ae2a11	189
saloutos	0:083111ae2a11	190	#ifndef __MPU_PRESENT
saloutos	0:083111ae2a11	191	#define __MPU_PRESENT 0U
saloutos	0:083111ae2a11	192	#warning "__MPU_PRESENT not defined in device header file; using default!"
saloutos	0:083111ae2a11	193	#endif
saloutos	0:083111ae2a11	194
saloutos	0:083111ae2a11	195	#ifndef __SAUREGION_PRESENT
saloutos	0:083111ae2a11	196	#define __SAUREGION_PRESENT 0U
saloutos	0:083111ae2a11	197	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
saloutos	0:083111ae2a11	198	#endif
saloutos	0:083111ae2a11	199
saloutos	0:083111ae2a11	200	#ifndef __DSP_PRESENT
saloutos	0:083111ae2a11	201	#define __DSP_PRESENT 0U
saloutos	0:083111ae2a11	202	#warning "__DSP_PRESENT not defined in device header file; using default!"
saloutos	0:083111ae2a11	203	#endif
saloutos	0:083111ae2a11	204
saloutos	0:083111ae2a11	205	#ifndef __NVIC_PRIO_BITS
saloutos	0:083111ae2a11	206	#define __NVIC_PRIO_BITS 3U
saloutos	0:083111ae2a11	207	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
saloutos	0:083111ae2a11	208	#endif
saloutos	0:083111ae2a11	209
saloutos	0:083111ae2a11	210	#ifndef __Vendor_SysTickConfig
saloutos	0:083111ae2a11	211	#define __Vendor_SysTickConfig 0U
saloutos	0:083111ae2a11	212	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
saloutos	0:083111ae2a11	213	#endif
saloutos	0:083111ae2a11	214	#endif
saloutos	0:083111ae2a11	215
saloutos	0:083111ae2a11	216	/* IO definitions (access restrictions to peripheral registers) */
saloutos	0:083111ae2a11	217	/**
saloutos	0:083111ae2a11	218	\defgroup CMSIS_glob_defs CMSIS Global Defines
saloutos	0:083111ae2a11	219
saloutos	0:083111ae2a11	220	<strong>IO Type Qualifiers</strong> are used
saloutos	0:083111ae2a11	221	\li to specify the access to peripheral variables.
saloutos	0:083111ae2a11	222	\li for automatic generation of peripheral register debug information.
saloutos	0:083111ae2a11	223	*/
saloutos	0:083111ae2a11	224	#ifdef __cplusplus
saloutos	0:083111ae2a11	225	#define __I volatile /!< Defines 'read only' permissions /
saloutos	0:083111ae2a11	226	#else
saloutos	0:083111ae2a11	227	#define __I volatile const /!< Defines 'read only' permissions /
saloutos	0:083111ae2a11	228	#endif
saloutos	0:083111ae2a11	229	#define __O volatile /!< Defines 'write only' permissions /
saloutos	0:083111ae2a11	230	#define __IO volatile /!< Defines 'read / write' permissions /
saloutos	0:083111ae2a11	231
saloutos	0:083111ae2a11	232	/* following defines should be used for structure members */
saloutos	0:083111ae2a11	233	#define __IM volatile const /! Defines 'read only' structure member permissions /
saloutos	0:083111ae2a11	234	#define __OM volatile /! Defines 'write only' structure member permissions /
saloutos	0:083111ae2a11	235	#define __IOM volatile /! Defines 'read / write' structure member permissions /
saloutos	0:083111ae2a11	236
saloutos	0:083111ae2a11	237	/@} end of group Cortex_M33 /
saloutos	0:083111ae2a11	238
saloutos	0:083111ae2a11	239
saloutos	0:083111ae2a11	240
saloutos	0:083111ae2a11	241	/*******************************************************************************
saloutos	0:083111ae2a11	242	* Register Abstraction
saloutos	0:083111ae2a11	243	Core Register contain:
saloutos	0:083111ae2a11	244	- Core Register
saloutos	0:083111ae2a11	245	- Core NVIC Register
saloutos	0:083111ae2a11	246	- Core SCB Register
saloutos	0:083111ae2a11	247	- Core SysTick Register
saloutos	0:083111ae2a11	248	- Core Debug Register
saloutos	0:083111ae2a11	249	- Core MPU Register
saloutos	0:083111ae2a11	250	- Core SAU Register
saloutos	0:083111ae2a11	251	- Core FPU Register
saloutos	0:083111ae2a11	252	******************************************************************************/
saloutos	0:083111ae2a11	253	/**
saloutos	0:083111ae2a11	254	\defgroup CMSIS_core_register Defines and Type Definitions
saloutos	0:083111ae2a11	255	\brief Type definitions and defines for Cortex-M processor based devices.
saloutos	0:083111ae2a11	256	*/
saloutos	0:083111ae2a11	257
saloutos	0:083111ae2a11	258	/**
saloutos	0:083111ae2a11	259	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	260	\defgroup CMSIS_CORE Status and Control Registers
saloutos	0:083111ae2a11	261	\brief Core Register type definitions.
saloutos	0:083111ae2a11	262	@{
saloutos	0:083111ae2a11	263	*/
saloutos	0:083111ae2a11	264
saloutos	0:083111ae2a11	265	/**
saloutos	0:083111ae2a11	266	\brief Union type to access the Application Program Status Register (APSR).
saloutos	0:083111ae2a11	267	*/
saloutos	0:083111ae2a11	268	typedef union
saloutos	0:083111ae2a11	269	{
saloutos	0:083111ae2a11	270	struct
saloutos	0:083111ae2a11	271	{
saloutos	0:083111ae2a11	272	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
saloutos	0:083111ae2a11	273	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
saloutos	0:083111ae2a11	274	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
saloutos	0:083111ae2a11	275	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
saloutos	0:083111ae2a11	276	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
saloutos	0:083111ae2a11	277	uint32_t C:1; /!< bit: 29 Carry condition code flag /
saloutos	0:083111ae2a11	278	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
saloutos	0:083111ae2a11	279	uint32_t N:1; /!< bit: 31 Negative condition code flag /
saloutos	0:083111ae2a11	280	} b; /!< Structure used for bit access /
saloutos	0:083111ae2a11	281	uint32_t w; /!< Type used for word access /
saloutos	0:083111ae2a11	282	} APSR_Type;
saloutos	0:083111ae2a11	283
saloutos	0:083111ae2a11	284	/* APSR Register Definitions */
saloutos	0:083111ae2a11	285	#define APSR_N_Pos 31U /!< APSR: N Position /
saloutos	0:083111ae2a11	286	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
saloutos	0:083111ae2a11	287
saloutos	0:083111ae2a11	288	#define APSR_Z_Pos 30U /!< APSR: Z Position /
saloutos	0:083111ae2a11	289	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
saloutos	0:083111ae2a11	290
saloutos	0:083111ae2a11	291	#define APSR_C_Pos 29U /!< APSR: C Position /
saloutos	0:083111ae2a11	292	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
saloutos	0:083111ae2a11	293
saloutos	0:083111ae2a11	294	#define APSR_V_Pos 28U /!< APSR: V Position /
saloutos	0:083111ae2a11	295	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
saloutos	0:083111ae2a11	296
saloutos	0:083111ae2a11	297	#define APSR_Q_Pos 27U /!< APSR: Q Position /
saloutos	0:083111ae2a11	298	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
saloutos	0:083111ae2a11	299
saloutos	0:083111ae2a11	300	#define APSR_GE_Pos 16U /!< APSR: GE Position /
saloutos	0:083111ae2a11	301	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
saloutos	0:083111ae2a11	302
saloutos	0:083111ae2a11	303
saloutos	0:083111ae2a11	304	/**
saloutos	0:083111ae2a11	305	\brief Union type to access the Interrupt Program Status Register (IPSR).
saloutos	0:083111ae2a11	306	*/
saloutos	0:083111ae2a11	307	typedef union
saloutos	0:083111ae2a11	308	{
saloutos	0:083111ae2a11	309	struct
saloutos	0:083111ae2a11	310	{
saloutos	0:083111ae2a11	311	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
saloutos	0:083111ae2a11	312	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
saloutos	0:083111ae2a11	313	} b; /!< Structure used for bit access /
saloutos	0:083111ae2a11	314	uint32_t w; /!< Type used for word access /
saloutos	0:083111ae2a11	315	} IPSR_Type;
saloutos	0:083111ae2a11	316
saloutos	0:083111ae2a11	317	/* IPSR Register Definitions */
saloutos	0:083111ae2a11	318	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
saloutos	0:083111ae2a11	319	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
saloutos	0:083111ae2a11	320
saloutos	0:083111ae2a11	321
saloutos	0:083111ae2a11	322	/**
saloutos	0:083111ae2a11	323	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
saloutos	0:083111ae2a11	324	*/
saloutos	0:083111ae2a11	325	typedef union
saloutos	0:083111ae2a11	326	{
saloutos	0:083111ae2a11	327	struct
saloutos	0:083111ae2a11	328	{
saloutos	0:083111ae2a11	329	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
saloutos	0:083111ae2a11	330	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
saloutos	0:083111ae2a11	331	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
saloutos	0:083111ae2a11	332	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
saloutos	0:083111ae2a11	333	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
saloutos	0:083111ae2a11	334	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
saloutos	0:083111ae2a11	335	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
saloutos	0:083111ae2a11	336	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
saloutos	0:083111ae2a11	337	uint32_t C:1; /!< bit: 29 Carry condition code flag /
saloutos	0:083111ae2a11	338	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
saloutos	0:083111ae2a11	339	uint32_t N:1; /!< bit: 31 Negative condition code flag /
saloutos	0:083111ae2a11	340	} b; /!< Structure used for bit access /
saloutos	0:083111ae2a11	341	uint32_t w; /!< Type used for word access /
saloutos	0:083111ae2a11	342	} xPSR_Type;
saloutos	0:083111ae2a11	343
saloutos	0:083111ae2a11	344	/* xPSR Register Definitions */
saloutos	0:083111ae2a11	345	#define xPSR_N_Pos 31U /!< xPSR: N Position /
saloutos	0:083111ae2a11	346	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
saloutos	0:083111ae2a11	347
saloutos	0:083111ae2a11	348	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
saloutos	0:083111ae2a11	349	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
saloutos	0:083111ae2a11	350
saloutos	0:083111ae2a11	351	#define xPSR_C_Pos 29U /!< xPSR: C Position /
saloutos	0:083111ae2a11	352	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
saloutos	0:083111ae2a11	353
saloutos	0:083111ae2a11	354	#define xPSR_V_Pos 28U /!< xPSR: V Position /
saloutos	0:083111ae2a11	355	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
saloutos	0:083111ae2a11	356
saloutos	0:083111ae2a11	357	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
saloutos	0:083111ae2a11	358	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
saloutos	0:083111ae2a11	359
saloutos	0:083111ae2a11	360	#define xPSR_IT_Pos 25U /!< xPSR: IT Position /
saloutos	0:083111ae2a11	361	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
saloutos	0:083111ae2a11	362
saloutos	0:083111ae2a11	363	#define xPSR_T_Pos 24U /!< xPSR: T Position /
saloutos	0:083111ae2a11	364	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
saloutos	0:083111ae2a11	365
saloutos	0:083111ae2a11	366	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
saloutos	0:083111ae2a11	367	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
saloutos	0:083111ae2a11	368
saloutos	0:083111ae2a11	369	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
saloutos	0:083111ae2a11	370	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
saloutos	0:083111ae2a11	371
saloutos	0:083111ae2a11	372
saloutos	0:083111ae2a11	373	/**
saloutos	0:083111ae2a11	374	\brief Union type to access the Control Registers (CONTROL).
saloutos	0:083111ae2a11	375	*/
saloutos	0:083111ae2a11	376	typedef union
saloutos	0:083111ae2a11	377	{
saloutos	0:083111ae2a11	378	struct
saloutos	0:083111ae2a11	379	{
saloutos	0:083111ae2a11	380	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
saloutos	0:083111ae2a11	381	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
saloutos	0:083111ae2a11	382	uint32_t FPCA:1; /!< bit: 2 Floating-point context active /
saloutos	0:083111ae2a11	383	uint32_t SFPA:1; /!< bit: 3 Secure floating-point active /
saloutos	0:083111ae2a11	384	uint32_t _reserved1:28; /!< bit: 4..31 Reserved /
saloutos	0:083111ae2a11	385	} b; /!< Structure used for bit access /
saloutos	0:083111ae2a11	386	uint32_t w; /!< Type used for word access /
saloutos	0:083111ae2a11	387	} CONTROL_Type;
saloutos	0:083111ae2a11	388
saloutos	0:083111ae2a11	389	/* CONTROL Register Definitions */
saloutos	0:083111ae2a11	390	#define CONTROL_SFPA_Pos 3U /!< CONTROL: SFPA Position /
saloutos	0:083111ae2a11	391	#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /!< CONTROL: SFPA Mask /
saloutos	0:083111ae2a11	392
saloutos	0:083111ae2a11	393	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
saloutos	0:083111ae2a11	394	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
saloutos	0:083111ae2a11	395
saloutos	0:083111ae2a11	396	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
saloutos	0:083111ae2a11	397	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
saloutos	0:083111ae2a11	398
saloutos	0:083111ae2a11	399	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
saloutos	0:083111ae2a11	400	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
saloutos	0:083111ae2a11	401
saloutos	0:083111ae2a11	402	/@} end of group CMSIS_CORE /
saloutos	0:083111ae2a11	403
saloutos	0:083111ae2a11	404
saloutos	0:083111ae2a11	405	/**
saloutos	0:083111ae2a11	406	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	407	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
saloutos	0:083111ae2a11	408	\brief Type definitions for the NVIC Registers
saloutos	0:083111ae2a11	409	@{
saloutos	0:083111ae2a11	410	*/
saloutos	0:083111ae2a11	411
saloutos	0:083111ae2a11	412	/**
saloutos	0:083111ae2a11	413	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
saloutos	0:083111ae2a11	414	*/
saloutos	0:083111ae2a11	415	typedef struct
saloutos	0:083111ae2a11	416	{
saloutos	0:083111ae2a11	417	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
saloutos	0:083111ae2a11	418	uint32_t RESERVED0[16U];
saloutos	0:083111ae2a11	419	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
saloutos	0:083111ae2a11	420	uint32_t RSERVED1[16U];
saloutos	0:083111ae2a11	421	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
saloutos	0:083111ae2a11	422	uint32_t RESERVED2[16U];
saloutos	0:083111ae2a11	423	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
saloutos	0:083111ae2a11	424	uint32_t RESERVED3[16U];
saloutos	0:083111ae2a11	425	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
saloutos	0:083111ae2a11	426	uint32_t RESERVED4[16U];
saloutos	0:083111ae2a11	427	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
saloutos	0:083111ae2a11	428	uint32_t RESERVED5[16U];
saloutos	0:083111ae2a11	429	__IOM uint8_t IPR[496U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
saloutos	0:083111ae2a11	430	uint32_t RESERVED6[580U];
saloutos	0:083111ae2a11	431	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
saloutos	0:083111ae2a11	432	} NVIC_Type;
saloutos	0:083111ae2a11	433
saloutos	0:083111ae2a11	434	/* Software Triggered Interrupt Register Definitions */
saloutos	0:083111ae2a11	435	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
saloutos	0:083111ae2a11	436	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
saloutos	0:083111ae2a11	437
saloutos	0:083111ae2a11	438	/@} end of group CMSIS_NVIC /
saloutos	0:083111ae2a11	439
saloutos	0:083111ae2a11	440
saloutos	0:083111ae2a11	441	/**
saloutos	0:083111ae2a11	442	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	443	\defgroup CMSIS_SCB System Control Block (SCB)
saloutos	0:083111ae2a11	444	\brief Type definitions for the System Control Block Registers
saloutos	0:083111ae2a11	445	@{
saloutos	0:083111ae2a11	446	*/
saloutos	0:083111ae2a11	447
saloutos	0:083111ae2a11	448	/**
saloutos	0:083111ae2a11	449	\brief Structure type to access the System Control Block (SCB).
saloutos	0:083111ae2a11	450	*/
saloutos	0:083111ae2a11	451	typedef struct
saloutos	0:083111ae2a11	452	{
saloutos	0:083111ae2a11	453	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
saloutos	0:083111ae2a11	454	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
saloutos	0:083111ae2a11	455	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
saloutos	0:083111ae2a11	456	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
saloutos	0:083111ae2a11	457	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
saloutos	0:083111ae2a11	458	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
saloutos	0:083111ae2a11	459	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
saloutos	0:083111ae2a11	460	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
saloutos	0:083111ae2a11	461	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
saloutos	0:083111ae2a11	462	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
saloutos	0:083111ae2a11	463	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
saloutos	0:083111ae2a11	464	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
saloutos	0:083111ae2a11	465	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
saloutos	0:083111ae2a11	466	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
saloutos	0:083111ae2a11	467	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
saloutos	0:083111ae2a11	468	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
saloutos	0:083111ae2a11	469	__IM uint32_t ID_ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
saloutos	0:083111ae2a11	470	__IM uint32_t ID_MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
saloutos	0:083111ae2a11	471	__IM uint32_t ID_ISAR[6U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
saloutos	0:083111ae2a11	472	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
saloutos	0:083111ae2a11	473	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
saloutos	0:083111ae2a11	474	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
saloutos	0:083111ae2a11	475	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
saloutos	0:083111ae2a11	476	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
saloutos	0:083111ae2a11	477	__IOM uint32_t NSACR; /!< Offset: 0x08C (R/W) Non-Secure Access Control Register /
saloutos	0:083111ae2a11	478	uint32_t RESERVED3[92U];
saloutos	0:083111ae2a11	479	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
saloutos	0:083111ae2a11	480	uint32_t RESERVED4[15U];
saloutos	0:083111ae2a11	481	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
saloutos	0:083111ae2a11	482	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
saloutos	0:083111ae2a11	483	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
saloutos	0:083111ae2a11	484	uint32_t RESERVED5[1U];
saloutos	0:083111ae2a11	485	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
saloutos	0:083111ae2a11	486	uint32_t RESERVED6[1U];
saloutos	0:083111ae2a11	487	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
saloutos	0:083111ae2a11	488	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
saloutos	0:083111ae2a11	489	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
saloutos	0:083111ae2a11	490	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
saloutos	0:083111ae2a11	491	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
saloutos	0:083111ae2a11	492	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
saloutos	0:083111ae2a11	493	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
saloutos	0:083111ae2a11	494	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
saloutos	0:083111ae2a11	495	uint32_t RESERVED7[6U];
saloutos	0:083111ae2a11	496	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
saloutos	0:083111ae2a11	497	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
saloutos	0:083111ae2a11	498	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
saloutos	0:083111ae2a11	499	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
saloutos	0:083111ae2a11	500	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
saloutos	0:083111ae2a11	501	uint32_t RESERVED8[1U];
saloutos	0:083111ae2a11	502	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
saloutos	0:083111ae2a11	503	} SCB_Type;
saloutos	0:083111ae2a11	504
saloutos	0:083111ae2a11	505	/* SCB CPUID Register Definitions */
saloutos	0:083111ae2a11	506	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
saloutos	0:083111ae2a11	507	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
saloutos	0:083111ae2a11	508
saloutos	0:083111ae2a11	509	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
saloutos	0:083111ae2a11	510	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
saloutos	0:083111ae2a11	511
saloutos	0:083111ae2a11	512	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
saloutos	0:083111ae2a11	513	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
saloutos	0:083111ae2a11	514
saloutos	0:083111ae2a11	515	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
saloutos	0:083111ae2a11	516	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
saloutos	0:083111ae2a11	517
saloutos	0:083111ae2a11	518	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
saloutos	0:083111ae2a11	519	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
saloutos	0:083111ae2a11	520
saloutos	0:083111ae2a11	521	/* SCB Interrupt Control State Register Definitions */
saloutos	0:083111ae2a11	522	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
saloutos	0:083111ae2a11	523	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
saloutos	0:083111ae2a11	524
saloutos	0:083111ae2a11	525	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
saloutos	0:083111ae2a11	526	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
saloutos	0:083111ae2a11	527
saloutos	0:083111ae2a11	528	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
saloutos	0:083111ae2a11	529	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
saloutos	0:083111ae2a11	530
saloutos	0:083111ae2a11	531	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
saloutos	0:083111ae2a11	532	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
saloutos	0:083111ae2a11	533
saloutos	0:083111ae2a11	534	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
saloutos	0:083111ae2a11	535	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
saloutos	0:083111ae2a11	536
saloutos	0:083111ae2a11	537	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
saloutos	0:083111ae2a11	538	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
saloutos	0:083111ae2a11	539
saloutos	0:083111ae2a11	540	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
saloutos	0:083111ae2a11	541	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
saloutos	0:083111ae2a11	542
saloutos	0:083111ae2a11	543	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
saloutos	0:083111ae2a11	544	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
saloutos	0:083111ae2a11	545
saloutos	0:083111ae2a11	546	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
saloutos	0:083111ae2a11	547	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
saloutos	0:083111ae2a11	548
saloutos	0:083111ae2a11	549	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
saloutos	0:083111ae2a11	550	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
saloutos	0:083111ae2a11	551
saloutos	0:083111ae2a11	552	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
saloutos	0:083111ae2a11	553	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
saloutos	0:083111ae2a11	554
saloutos	0:083111ae2a11	555	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
saloutos	0:083111ae2a11	556	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
saloutos	0:083111ae2a11	557
saloutos	0:083111ae2a11	558	/* SCB Vector Table Offset Register Definitions */
saloutos	0:083111ae2a11	559	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
saloutos	0:083111ae2a11	560	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
saloutos	0:083111ae2a11	561
saloutos	0:083111ae2a11	562	/* SCB Application Interrupt and Reset Control Register Definitions */
saloutos	0:083111ae2a11	563	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
saloutos	0:083111ae2a11	564	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
saloutos	0:083111ae2a11	565
saloutos	0:083111ae2a11	566	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
saloutos	0:083111ae2a11	567	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
saloutos	0:083111ae2a11	568
saloutos	0:083111ae2a11	569	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
saloutos	0:083111ae2a11	570	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
saloutos	0:083111ae2a11	571
saloutos	0:083111ae2a11	572	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
saloutos	0:083111ae2a11	573	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
saloutos	0:083111ae2a11	574
saloutos	0:083111ae2a11	575	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
saloutos	0:083111ae2a11	576	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
saloutos	0:083111ae2a11	577
saloutos	0:083111ae2a11	578	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
saloutos	0:083111ae2a11	579	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
saloutos	0:083111ae2a11	580
saloutos	0:083111ae2a11	581	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
saloutos	0:083111ae2a11	582	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
saloutos	0:083111ae2a11	583
saloutos	0:083111ae2a11	584	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
saloutos	0:083111ae2a11	585	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
saloutos	0:083111ae2a11	586
saloutos	0:083111ae2a11	587	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
saloutos	0:083111ae2a11	588	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
saloutos	0:083111ae2a11	589
saloutos	0:083111ae2a11	590	/* SCB System Control Register Definitions */
saloutos	0:083111ae2a11	591	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
saloutos	0:083111ae2a11	592	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
saloutos	0:083111ae2a11	593
saloutos	0:083111ae2a11	594	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
saloutos	0:083111ae2a11	595	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
saloutos	0:083111ae2a11	596
saloutos	0:083111ae2a11	597	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
saloutos	0:083111ae2a11	598	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
saloutos	0:083111ae2a11	599
saloutos	0:083111ae2a11	600	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
saloutos	0:083111ae2a11	601	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
saloutos	0:083111ae2a11	602
saloutos	0:083111ae2a11	603	/* SCB Configuration Control Register Definitions */
saloutos	0:083111ae2a11	604	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
saloutos	0:083111ae2a11	605	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
saloutos	0:083111ae2a11	606
saloutos	0:083111ae2a11	607	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
saloutos	0:083111ae2a11	608	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
saloutos	0:083111ae2a11	609
saloutos	0:083111ae2a11	610	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
saloutos	0:083111ae2a11	611	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
saloutos	0:083111ae2a11	612
saloutos	0:083111ae2a11	613	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
saloutos	0:083111ae2a11	614	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
saloutos	0:083111ae2a11	615
saloutos	0:083111ae2a11	616	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
saloutos	0:083111ae2a11	617	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
saloutos	0:083111ae2a11	618
saloutos	0:083111ae2a11	619	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
saloutos	0:083111ae2a11	620	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
saloutos	0:083111ae2a11	621
saloutos	0:083111ae2a11	622	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
saloutos	0:083111ae2a11	623	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
saloutos	0:083111ae2a11	624
saloutos	0:083111ae2a11	625	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
saloutos	0:083111ae2a11	626	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
saloutos	0:083111ae2a11	627
saloutos	0:083111ae2a11	628	/* SCB System Handler Control and State Register Definitions */
saloutos	0:083111ae2a11	629	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
saloutos	0:083111ae2a11	630	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
saloutos	0:083111ae2a11	631
saloutos	0:083111ae2a11	632	#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /!< SCB SHCSR: SECUREFAULTPENDED Position /
saloutos	0:083111ae2a11	633	#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /!< SCB SHCSR: SECUREFAULTPENDED Mask /
saloutos	0:083111ae2a11	634
saloutos	0:083111ae2a11	635	#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /!< SCB SHCSR: SECUREFAULTENA Position /
saloutos	0:083111ae2a11	636	#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /!< SCB SHCSR: SECUREFAULTENA Mask /
saloutos	0:083111ae2a11	637
saloutos	0:083111ae2a11	638	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
saloutos	0:083111ae2a11	639	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
saloutos	0:083111ae2a11	640
saloutos	0:083111ae2a11	641	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
saloutos	0:083111ae2a11	642	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
saloutos	0:083111ae2a11	643
saloutos	0:083111ae2a11	644	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
saloutos	0:083111ae2a11	645	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
saloutos	0:083111ae2a11	646
saloutos	0:083111ae2a11	647	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
saloutos	0:083111ae2a11	648	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
saloutos	0:083111ae2a11	649
saloutos	0:083111ae2a11	650	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
saloutos	0:083111ae2a11	651	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
saloutos	0:083111ae2a11	652
saloutos	0:083111ae2a11	653	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
saloutos	0:083111ae2a11	654	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
saloutos	0:083111ae2a11	655
saloutos	0:083111ae2a11	656	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
saloutos	0:083111ae2a11	657	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
saloutos	0:083111ae2a11	658
saloutos	0:083111ae2a11	659	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
saloutos	0:083111ae2a11	660	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
saloutos	0:083111ae2a11	661
saloutos	0:083111ae2a11	662	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
saloutos	0:083111ae2a11	663	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
saloutos	0:083111ae2a11	664
saloutos	0:083111ae2a11	665	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
saloutos	0:083111ae2a11	666	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
saloutos	0:083111ae2a11	667
saloutos	0:083111ae2a11	668	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
saloutos	0:083111ae2a11	669	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
saloutos	0:083111ae2a11	670
saloutos	0:083111ae2a11	671	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
saloutos	0:083111ae2a11	672	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
saloutos	0:083111ae2a11	673
saloutos	0:083111ae2a11	674	#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /!< SCB SHCSR: SECUREFAULTACT Position /
saloutos	0:083111ae2a11	675	#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /!< SCB SHCSR: SECUREFAULTACT Mask /
saloutos	0:083111ae2a11	676
saloutos	0:083111ae2a11	677	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
saloutos	0:083111ae2a11	678	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
saloutos	0:083111ae2a11	679
saloutos	0:083111ae2a11	680	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
saloutos	0:083111ae2a11	681	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
saloutos	0:083111ae2a11	682
saloutos	0:083111ae2a11	683	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
saloutos	0:083111ae2a11	684	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
saloutos	0:083111ae2a11	685
saloutos	0:083111ae2a11	686	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
saloutos	0:083111ae2a11	687	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
saloutos	0:083111ae2a11	688
saloutos	0:083111ae2a11	689	/* SCB Configurable Fault Status Register Definitions */
saloutos	0:083111ae2a11	690	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
saloutos	0:083111ae2a11	691	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
saloutos	0:083111ae2a11	692
saloutos	0:083111ae2a11	693	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
saloutos	0:083111ae2a11	694	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
saloutos	0:083111ae2a11	695
saloutos	0:083111ae2a11	696	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
saloutos	0:083111ae2a11	697	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
saloutos	0:083111ae2a11	698
saloutos	0:083111ae2a11	699	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
saloutos	0:083111ae2a11	700	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
saloutos	0:083111ae2a11	701	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
saloutos	0:083111ae2a11	702
saloutos	0:083111ae2a11	703	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
saloutos	0:083111ae2a11	704	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
saloutos	0:083111ae2a11	705
saloutos	0:083111ae2a11	706	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
saloutos	0:083111ae2a11	707	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
saloutos	0:083111ae2a11	708
saloutos	0:083111ae2a11	709	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
saloutos	0:083111ae2a11	710	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
saloutos	0:083111ae2a11	711
saloutos	0:083111ae2a11	712	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
saloutos	0:083111ae2a11	713	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
saloutos	0:083111ae2a11	714
saloutos	0:083111ae2a11	715	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
saloutos	0:083111ae2a11	716	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
saloutos	0:083111ae2a11	717
saloutos	0:083111ae2a11	718	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
saloutos	0:083111ae2a11	719	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
saloutos	0:083111ae2a11	720	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
saloutos	0:083111ae2a11	721
saloutos	0:083111ae2a11	722	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
saloutos	0:083111ae2a11	723	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
saloutos	0:083111ae2a11	724
saloutos	0:083111ae2a11	725	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
saloutos	0:083111ae2a11	726	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
saloutos	0:083111ae2a11	727
saloutos	0:083111ae2a11	728	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
saloutos	0:083111ae2a11	729	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
saloutos	0:083111ae2a11	730
saloutos	0:083111ae2a11	731	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
saloutos	0:083111ae2a11	732	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
saloutos	0:083111ae2a11	733
saloutos	0:083111ae2a11	734	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
saloutos	0:083111ae2a11	735	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
saloutos	0:083111ae2a11	736
saloutos	0:083111ae2a11	737	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
saloutos	0:083111ae2a11	738	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
saloutos	0:083111ae2a11	739
saloutos	0:083111ae2a11	740	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
saloutos	0:083111ae2a11	741	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
saloutos	0:083111ae2a11	742	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
saloutos	0:083111ae2a11	743
saloutos	0:083111ae2a11	744	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
saloutos	0:083111ae2a11	745	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
saloutos	0:083111ae2a11	746
saloutos	0:083111ae2a11	747	#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /!< SCB CFSR (UFSR): STKOF Position /
saloutos	0:083111ae2a11	748	#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /!< SCB CFSR (UFSR): STKOF Mask /
saloutos	0:083111ae2a11	749
saloutos	0:083111ae2a11	750	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
saloutos	0:083111ae2a11	751	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
saloutos	0:083111ae2a11	752
saloutos	0:083111ae2a11	753	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
saloutos	0:083111ae2a11	754	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
saloutos	0:083111ae2a11	755
saloutos	0:083111ae2a11	756	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
saloutos	0:083111ae2a11	757	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
saloutos	0:083111ae2a11	758
saloutos	0:083111ae2a11	759	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
saloutos	0:083111ae2a11	760	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
saloutos	0:083111ae2a11	761
saloutos	0:083111ae2a11	762	/* SCB Hard Fault Status Register Definitions */
saloutos	0:083111ae2a11	763	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
saloutos	0:083111ae2a11	764	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
saloutos	0:083111ae2a11	765
saloutos	0:083111ae2a11	766	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
saloutos	0:083111ae2a11	767	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
saloutos	0:083111ae2a11	768
saloutos	0:083111ae2a11	769	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
saloutos	0:083111ae2a11	770	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
saloutos	0:083111ae2a11	771
saloutos	0:083111ae2a11	772	/* SCB Debug Fault Status Register Definitions */
saloutos	0:083111ae2a11	773	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
saloutos	0:083111ae2a11	774	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
saloutos	0:083111ae2a11	775
saloutos	0:083111ae2a11	776	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
saloutos	0:083111ae2a11	777	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
saloutos	0:083111ae2a11	778
saloutos	0:083111ae2a11	779	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
saloutos	0:083111ae2a11	780	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
saloutos	0:083111ae2a11	781
saloutos	0:083111ae2a11	782	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
saloutos	0:083111ae2a11	783	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
saloutos	0:083111ae2a11	784
saloutos	0:083111ae2a11	785	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
saloutos	0:083111ae2a11	786	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
saloutos	0:083111ae2a11	787
saloutos	0:083111ae2a11	788	/* SCB Non-Secure Access Control Register Definitions */
saloutos	0:083111ae2a11	789	#define SCB_NSACR_CP11_Pos 11U /!< SCB NSACR: CP11 Position /
saloutos	0:083111ae2a11	790	#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /!< SCB NSACR: CP11 Mask /
saloutos	0:083111ae2a11	791
saloutos	0:083111ae2a11	792	#define SCB_NSACR_CP10_Pos 10U /!< SCB NSACR: CP10 Position /
saloutos	0:083111ae2a11	793	#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /!< SCB NSACR: CP10 Mask /
saloutos	0:083111ae2a11	794
saloutos	0:083111ae2a11	795	#define SCB_NSACR_CPn_Pos 0U /!< SCB NSACR: CPn Position /
saloutos	0:083111ae2a11	796	#define SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/) /!< SCB NSACR: CPn Mask /
saloutos	0:083111ae2a11	797
saloutos	0:083111ae2a11	798	/* SCB Cache Level ID Register Definitions */
saloutos	0:083111ae2a11	799	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
saloutos	0:083111ae2a11	800	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
saloutos	0:083111ae2a11	801
saloutos	0:083111ae2a11	802	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
saloutos	0:083111ae2a11	803	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
saloutos	0:083111ae2a11	804
saloutos	0:083111ae2a11	805	/* SCB Cache Type Register Definitions */
saloutos	0:083111ae2a11	806	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
saloutos	0:083111ae2a11	807	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
saloutos	0:083111ae2a11	808
saloutos	0:083111ae2a11	809	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
saloutos	0:083111ae2a11	810	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
saloutos	0:083111ae2a11	811
saloutos	0:083111ae2a11	812	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
saloutos	0:083111ae2a11	813	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
saloutos	0:083111ae2a11	814
saloutos	0:083111ae2a11	815	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
saloutos	0:083111ae2a11	816	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
saloutos	0:083111ae2a11	817
saloutos	0:083111ae2a11	818	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
saloutos	0:083111ae2a11	819	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
saloutos	0:083111ae2a11	820
saloutos	0:083111ae2a11	821	/* SCB Cache Size ID Register Definitions */
saloutos	0:083111ae2a11	822	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
saloutos	0:083111ae2a11	823	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
saloutos	0:083111ae2a11	824
saloutos	0:083111ae2a11	825	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
saloutos	0:083111ae2a11	826	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
saloutos	0:083111ae2a11	827
saloutos	0:083111ae2a11	828	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
saloutos	0:083111ae2a11	829	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
saloutos	0:083111ae2a11	830
saloutos	0:083111ae2a11	831	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
saloutos	0:083111ae2a11	832	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
saloutos	0:083111ae2a11	833
saloutos	0:083111ae2a11	834	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
saloutos	0:083111ae2a11	835	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
saloutos	0:083111ae2a11	836
saloutos	0:083111ae2a11	837	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
saloutos	0:083111ae2a11	838	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
saloutos	0:083111ae2a11	839
saloutos	0:083111ae2a11	840	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
saloutos	0:083111ae2a11	841	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
saloutos	0:083111ae2a11	842
saloutos	0:083111ae2a11	843	/* SCB Cache Size Selection Register Definitions */
saloutos	0:083111ae2a11	844	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
saloutos	0:083111ae2a11	845	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
saloutos	0:083111ae2a11	846
saloutos	0:083111ae2a11	847	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
saloutos	0:083111ae2a11	848	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
saloutos	0:083111ae2a11	849
saloutos	0:083111ae2a11	850	/* SCB Software Triggered Interrupt Register Definitions */
saloutos	0:083111ae2a11	851	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
saloutos	0:083111ae2a11	852	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
saloutos	0:083111ae2a11	853
saloutos	0:083111ae2a11	854	/* SCB D-Cache Invalidate by Set-way Register Definitions */
saloutos	0:083111ae2a11	855	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
saloutos	0:083111ae2a11	856	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
saloutos	0:083111ae2a11	857
saloutos	0:083111ae2a11	858	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
saloutos	0:083111ae2a11	859	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
saloutos	0:083111ae2a11	860
saloutos	0:083111ae2a11	861	/* SCB D-Cache Clean by Set-way Register Definitions */
saloutos	0:083111ae2a11	862	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
saloutos	0:083111ae2a11	863	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
saloutos	0:083111ae2a11	864
saloutos	0:083111ae2a11	865	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
saloutos	0:083111ae2a11	866	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
saloutos	0:083111ae2a11	867
saloutos	0:083111ae2a11	868	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
saloutos	0:083111ae2a11	869	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
saloutos	0:083111ae2a11	870	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
saloutos	0:083111ae2a11	871
saloutos	0:083111ae2a11	872	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
saloutos	0:083111ae2a11	873	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
saloutos	0:083111ae2a11	874
saloutos	0:083111ae2a11	875	/* Instruction Tightly-Coupled Memory Control Register Definitions */
saloutos	0:083111ae2a11	876	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
saloutos	0:083111ae2a11	877	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
saloutos	0:083111ae2a11	878
saloutos	0:083111ae2a11	879	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
saloutos	0:083111ae2a11	880	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
saloutos	0:083111ae2a11	881
saloutos	0:083111ae2a11	882	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
saloutos	0:083111ae2a11	883	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
saloutos	0:083111ae2a11	884
saloutos	0:083111ae2a11	885	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
saloutos	0:083111ae2a11	886	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
saloutos	0:083111ae2a11	887
saloutos	0:083111ae2a11	888	/* Data Tightly-Coupled Memory Control Register Definitions */
saloutos	0:083111ae2a11	889	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
saloutos	0:083111ae2a11	890	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
saloutos	0:083111ae2a11	891
saloutos	0:083111ae2a11	892	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
saloutos	0:083111ae2a11	893	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
saloutos	0:083111ae2a11	894
saloutos	0:083111ae2a11	895	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
saloutos	0:083111ae2a11	896	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
saloutos	0:083111ae2a11	897
saloutos	0:083111ae2a11	898	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
saloutos	0:083111ae2a11	899	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
saloutos	0:083111ae2a11	900
saloutos	0:083111ae2a11	901	/* AHBP Control Register Definitions */
saloutos	0:083111ae2a11	902	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
saloutos	0:083111ae2a11	903	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
saloutos	0:083111ae2a11	904
saloutos	0:083111ae2a11	905	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
saloutos	0:083111ae2a11	906	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
saloutos	0:083111ae2a11	907
saloutos	0:083111ae2a11	908	/* L1 Cache Control Register Definitions */
saloutos	0:083111ae2a11	909	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
saloutos	0:083111ae2a11	910	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
saloutos	0:083111ae2a11	911
saloutos	0:083111ae2a11	912	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
saloutos	0:083111ae2a11	913	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
saloutos	0:083111ae2a11	914
saloutos	0:083111ae2a11	915	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
saloutos	0:083111ae2a11	916	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
saloutos	0:083111ae2a11	917
saloutos	0:083111ae2a11	918	/* AHBS Control Register Definitions */
saloutos	0:083111ae2a11	919	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
saloutos	0:083111ae2a11	920	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
saloutos	0:083111ae2a11	921
saloutos	0:083111ae2a11	922	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
saloutos	0:083111ae2a11	923	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
saloutos	0:083111ae2a11	924
saloutos	0:083111ae2a11	925	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
saloutos	0:083111ae2a11	926	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
saloutos	0:083111ae2a11	927
saloutos	0:083111ae2a11	928	/* Auxiliary Bus Fault Status Register Definitions */
saloutos	0:083111ae2a11	929	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
saloutos	0:083111ae2a11	930	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
saloutos	0:083111ae2a11	931
saloutos	0:083111ae2a11	932	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
saloutos	0:083111ae2a11	933	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
saloutos	0:083111ae2a11	934
saloutos	0:083111ae2a11	935	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
saloutos	0:083111ae2a11	936	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
saloutos	0:083111ae2a11	937
saloutos	0:083111ae2a11	938	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
saloutos	0:083111ae2a11	939	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
saloutos	0:083111ae2a11	940
saloutos	0:083111ae2a11	941	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
saloutos	0:083111ae2a11	942	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
saloutos	0:083111ae2a11	943
saloutos	0:083111ae2a11	944	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
saloutos	0:083111ae2a11	945	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
saloutos	0:083111ae2a11	946
saloutos	0:083111ae2a11	947	/@} end of group CMSIS_SCB /
saloutos	0:083111ae2a11	948
saloutos	0:083111ae2a11	949
saloutos	0:083111ae2a11	950	/**
saloutos	0:083111ae2a11	951	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	952	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
saloutos	0:083111ae2a11	953	\brief Type definitions for the System Control and ID Register not in the SCB
saloutos	0:083111ae2a11	954	@{
saloutos	0:083111ae2a11	955	*/
saloutos	0:083111ae2a11	956
saloutos	0:083111ae2a11	957	/**
saloutos	0:083111ae2a11	958	\brief Structure type to access the System Control and ID Register not in the SCB.
saloutos	0:083111ae2a11	959	*/
saloutos	0:083111ae2a11	960	typedef struct
saloutos	0:083111ae2a11	961	{
saloutos	0:083111ae2a11	962	uint32_t RESERVED0[1U];
saloutos	0:083111ae2a11	963	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
saloutos	0:083111ae2a11	964	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
saloutos	0:083111ae2a11	965	__IOM uint32_t CPPWR; /!< Offset: 0x00C (R/W) Coprocessor Power Control Register /
saloutos	0:083111ae2a11	966	} SCnSCB_Type;
saloutos	0:083111ae2a11	967
saloutos	0:083111ae2a11	968	/* Interrupt Controller Type Register Definitions */
saloutos	0:083111ae2a11	969	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
saloutos	0:083111ae2a11	970	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
saloutos	0:083111ae2a11	971
saloutos	0:083111ae2a11	972	/@} end of group CMSIS_SCnotSCB /
saloutos	0:083111ae2a11	973
saloutos	0:083111ae2a11	974
saloutos	0:083111ae2a11	975	/**
saloutos	0:083111ae2a11	976	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	977	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
saloutos	0:083111ae2a11	978	\brief Type definitions for the System Timer Registers.
saloutos	0:083111ae2a11	979	@{
saloutos	0:083111ae2a11	980	*/
saloutos	0:083111ae2a11	981
saloutos	0:083111ae2a11	982	/**
saloutos	0:083111ae2a11	983	\brief Structure type to access the System Timer (SysTick).
saloutos	0:083111ae2a11	984	*/
saloutos	0:083111ae2a11	985	typedef struct
saloutos	0:083111ae2a11	986	{
saloutos	0:083111ae2a11	987	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
saloutos	0:083111ae2a11	988	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
saloutos	0:083111ae2a11	989	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
saloutos	0:083111ae2a11	990	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
saloutos	0:083111ae2a11	991	} SysTick_Type;
saloutos	0:083111ae2a11	992
saloutos	0:083111ae2a11	993	/* SysTick Control / Status Register Definitions */
saloutos	0:083111ae2a11	994	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
saloutos	0:083111ae2a11	995	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
saloutos	0:083111ae2a11	996
saloutos	0:083111ae2a11	997	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
saloutos	0:083111ae2a11	998	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
saloutos	0:083111ae2a11	999
saloutos	0:083111ae2a11	1000	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
saloutos	0:083111ae2a11	1001	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
saloutos	0:083111ae2a11	1002
saloutos	0:083111ae2a11	1003	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
saloutos	0:083111ae2a11	1004	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
saloutos	0:083111ae2a11	1005
saloutos	0:083111ae2a11	1006	/* SysTick Reload Register Definitions */
saloutos	0:083111ae2a11	1007	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
saloutos	0:083111ae2a11	1008	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
saloutos	0:083111ae2a11	1009
saloutos	0:083111ae2a11	1010	/* SysTick Current Register Definitions */
saloutos	0:083111ae2a11	1011	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
saloutos	0:083111ae2a11	1012	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
saloutos	0:083111ae2a11	1013
saloutos	0:083111ae2a11	1014	/* SysTick Calibration Register Definitions */
saloutos	0:083111ae2a11	1015	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
saloutos	0:083111ae2a11	1016	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
saloutos	0:083111ae2a11	1017
saloutos	0:083111ae2a11	1018	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
saloutos	0:083111ae2a11	1019	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
saloutos	0:083111ae2a11	1020
saloutos	0:083111ae2a11	1021	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
saloutos	0:083111ae2a11	1022	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
saloutos	0:083111ae2a11	1023
saloutos	0:083111ae2a11	1024	/@} end of group CMSIS_SysTick /
saloutos	0:083111ae2a11	1025
saloutos	0:083111ae2a11	1026
saloutos	0:083111ae2a11	1027	/**
saloutos	0:083111ae2a11	1028	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	1029	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
saloutos	0:083111ae2a11	1030	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
saloutos	0:083111ae2a11	1031	@{
saloutos	0:083111ae2a11	1032	*/
saloutos	0:083111ae2a11	1033
saloutos	0:083111ae2a11	1034	/**
saloutos	0:083111ae2a11	1035	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
saloutos	0:083111ae2a11	1036	*/
saloutos	0:083111ae2a11	1037	typedef struct
saloutos	0:083111ae2a11	1038	{
saloutos	0:083111ae2a11	1039	__OM union
saloutos	0:083111ae2a11	1040	{
saloutos	0:083111ae2a11	1041	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
saloutos	0:083111ae2a11	1042	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
saloutos	0:083111ae2a11	1043	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
saloutos	0:083111ae2a11	1044	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
saloutos	0:083111ae2a11	1045	uint32_t RESERVED0[864U];
saloutos	0:083111ae2a11	1046	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
saloutos	0:083111ae2a11	1047	uint32_t RESERVED1[15U];
saloutos	0:083111ae2a11	1048	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
saloutos	0:083111ae2a11	1049	uint32_t RESERVED2[15U];
saloutos	0:083111ae2a11	1050	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
saloutos	0:083111ae2a11	1051	uint32_t RESERVED3[29U];
saloutos	0:083111ae2a11	1052	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
saloutos	0:083111ae2a11	1053	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
saloutos	0:083111ae2a11	1054	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
saloutos	0:083111ae2a11	1055	uint32_t RESERVED4[43U];
saloutos	0:083111ae2a11	1056	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
saloutos	0:083111ae2a11	1057	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
saloutos	0:083111ae2a11	1058	uint32_t RESERVED5[1U];
saloutos	0:083111ae2a11	1059	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register /
saloutos	0:083111ae2a11	1060	uint32_t RESERVED6[4U];
saloutos	0:083111ae2a11	1061	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
saloutos	0:083111ae2a11	1062	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
saloutos	0:083111ae2a11	1063	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
saloutos	0:083111ae2a11	1064	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
saloutos	0:083111ae2a11	1065	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
saloutos	0:083111ae2a11	1066	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
saloutos	0:083111ae2a11	1067	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
saloutos	0:083111ae2a11	1068	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
saloutos	0:083111ae2a11	1069	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
saloutos	0:083111ae2a11	1070	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
saloutos	0:083111ae2a11	1071	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
saloutos	0:083111ae2a11	1072	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
saloutos	0:083111ae2a11	1073	} ITM_Type;
saloutos	0:083111ae2a11	1074
saloutos	0:083111ae2a11	1075	/* ITM Stimulus Port Register Definitions */
saloutos	0:083111ae2a11	1076	#define ITM_STIM_DISABLED_Pos 1U /!< ITM STIM: DISABLED Position /
saloutos	0:083111ae2a11	1077	#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /!< ITM STIM: DISABLED Mask /
saloutos	0:083111ae2a11	1078
saloutos	0:083111ae2a11	1079	#define ITM_STIM_FIFOREADY_Pos 0U /!< ITM STIM: FIFOREADY Position /
saloutos	0:083111ae2a11	1080	#define ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/) /!< ITM STIM: FIFOREADY Mask /
saloutos	0:083111ae2a11	1081
saloutos	0:083111ae2a11	1082	/* ITM Trace Privilege Register Definitions */
saloutos	0:083111ae2a11	1083	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
saloutos	0:083111ae2a11	1084	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
saloutos	0:083111ae2a11	1085
saloutos	0:083111ae2a11	1086	/* ITM Trace Control Register Definitions */
saloutos	0:083111ae2a11	1087	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
saloutos	0:083111ae2a11	1088	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
saloutos	0:083111ae2a11	1089
saloutos	0:083111ae2a11	1090	#define ITM_TCR_TRACEBUSID_Pos 16U /!< ITM TCR: ATBID Position /
saloutos	0:083111ae2a11	1091	#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /!< ITM TCR: ATBID Mask /
saloutos	0:083111ae2a11	1092
saloutos	0:083111ae2a11	1093	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
saloutos	0:083111ae2a11	1094	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
saloutos	0:083111ae2a11	1095
saloutos	0:083111ae2a11	1096	#define ITM_TCR_TSPRESCALE_Pos 8U /!< ITM TCR: TSPRESCALE Position /
saloutos	0:083111ae2a11	1097	#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /!< ITM TCR: TSPRESCALE Mask /
saloutos	0:083111ae2a11	1098
saloutos	0:083111ae2a11	1099	#define ITM_TCR_STALLENA_Pos 5U /!< ITM TCR: STALLENA Position /
saloutos	0:083111ae2a11	1100	#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /!< ITM TCR: STALLENA Mask /
saloutos	0:083111ae2a11	1101
saloutos	0:083111ae2a11	1102	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
saloutos	0:083111ae2a11	1103	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
saloutos	0:083111ae2a11	1104
saloutos	0:083111ae2a11	1105	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
saloutos	0:083111ae2a11	1106	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
saloutos	0:083111ae2a11	1107
saloutos	0:083111ae2a11	1108	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
saloutos	0:083111ae2a11	1109	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
saloutos	0:083111ae2a11	1110
saloutos	0:083111ae2a11	1111	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
saloutos	0:083111ae2a11	1112	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
saloutos	0:083111ae2a11	1113
saloutos	0:083111ae2a11	1114	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
saloutos	0:083111ae2a11	1115	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
saloutos	0:083111ae2a11	1116
saloutos	0:083111ae2a11	1117	/* ITM Integration Write Register Definitions */
saloutos	0:083111ae2a11	1118	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
saloutos	0:083111ae2a11	1119	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
saloutos	0:083111ae2a11	1120
saloutos	0:083111ae2a11	1121	/* ITM Integration Read Register Definitions */
saloutos	0:083111ae2a11	1122	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
saloutos	0:083111ae2a11	1123	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
saloutos	0:083111ae2a11	1124
saloutos	0:083111ae2a11	1125	/* ITM Integration Mode Control Register Definitions */
saloutos	0:083111ae2a11	1126	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
saloutos	0:083111ae2a11	1127	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
saloutos	0:083111ae2a11	1128
saloutos	0:083111ae2a11	1129	/* ITM Lock Status Register Definitions */
saloutos	0:083111ae2a11	1130	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
saloutos	0:083111ae2a11	1131	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
saloutos	0:083111ae2a11	1132
saloutos	0:083111ae2a11	1133	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
saloutos	0:083111ae2a11	1134	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
saloutos	0:083111ae2a11	1135
saloutos	0:083111ae2a11	1136	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
saloutos	0:083111ae2a11	1137	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
saloutos	0:083111ae2a11	1138
saloutos	0:083111ae2a11	1139	/@}/ /* end of group CMSIS_ITM */
saloutos	0:083111ae2a11	1140
saloutos	0:083111ae2a11	1141
saloutos	0:083111ae2a11	1142	/**
saloutos	0:083111ae2a11	1143	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	1144	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
saloutos	0:083111ae2a11	1145	\brief Type definitions for the Data Watchpoint and Trace (DWT)
saloutos	0:083111ae2a11	1146	@{
saloutos	0:083111ae2a11	1147	*/
saloutos	0:083111ae2a11	1148
saloutos	0:083111ae2a11	1149	/**
saloutos	0:083111ae2a11	1150	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
saloutos	0:083111ae2a11	1151	*/
saloutos	0:083111ae2a11	1152	typedef struct
saloutos	0:083111ae2a11	1153	{
saloutos	0:083111ae2a11	1154	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
saloutos	0:083111ae2a11	1155	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
saloutos	0:083111ae2a11	1156	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
saloutos	0:083111ae2a11	1157	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
saloutos	0:083111ae2a11	1158	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
saloutos	0:083111ae2a11	1159	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
saloutos	0:083111ae2a11	1160	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
saloutos	0:083111ae2a11	1161	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
saloutos	0:083111ae2a11	1162	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
saloutos	0:083111ae2a11	1163	uint32_t RESERVED1[1U];
saloutos	0:083111ae2a11	1164	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
saloutos	0:083111ae2a11	1165	uint32_t RESERVED2[1U];
saloutos	0:083111ae2a11	1166	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
saloutos	0:083111ae2a11	1167	uint32_t RESERVED3[1U];
saloutos	0:083111ae2a11	1168	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
saloutos	0:083111ae2a11	1169	uint32_t RESERVED4[1U];
saloutos	0:083111ae2a11	1170	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
saloutos	0:083111ae2a11	1171	uint32_t RESERVED5[1U];
saloutos	0:083111ae2a11	1172	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
saloutos	0:083111ae2a11	1173	uint32_t RESERVED6[1U];
saloutos	0:083111ae2a11	1174	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
saloutos	0:083111ae2a11	1175	uint32_t RESERVED7[1U];
saloutos	0:083111ae2a11	1176	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
saloutos	0:083111ae2a11	1177	uint32_t RESERVED8[1U];
saloutos	0:083111ae2a11	1178	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
saloutos	0:083111ae2a11	1179	uint32_t RESERVED9[1U];
saloutos	0:083111ae2a11	1180	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
saloutos	0:083111ae2a11	1181	uint32_t RESERVED10[1U];
saloutos	0:083111ae2a11	1182	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
saloutos	0:083111ae2a11	1183	uint32_t RESERVED11[1U];
saloutos	0:083111ae2a11	1184	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
saloutos	0:083111ae2a11	1185	uint32_t RESERVED12[1U];
saloutos	0:083111ae2a11	1186	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
saloutos	0:083111ae2a11	1187	uint32_t RESERVED13[1U];
saloutos	0:083111ae2a11	1188	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
saloutos	0:083111ae2a11	1189	uint32_t RESERVED14[1U];
saloutos	0:083111ae2a11	1190	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
saloutos	0:083111ae2a11	1191	uint32_t RESERVED15[1U];
saloutos	0:083111ae2a11	1192	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
saloutos	0:083111ae2a11	1193	uint32_t RESERVED16[1U];
saloutos	0:083111ae2a11	1194	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
saloutos	0:083111ae2a11	1195	uint32_t RESERVED17[1U];
saloutos	0:083111ae2a11	1196	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
saloutos	0:083111ae2a11	1197	uint32_t RESERVED18[1U];
saloutos	0:083111ae2a11	1198	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
saloutos	0:083111ae2a11	1199	uint32_t RESERVED19[1U];
saloutos	0:083111ae2a11	1200	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
saloutos	0:083111ae2a11	1201	uint32_t RESERVED20[1U];
saloutos	0:083111ae2a11	1202	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
saloutos	0:083111ae2a11	1203	uint32_t RESERVED21[1U];
saloutos	0:083111ae2a11	1204	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
saloutos	0:083111ae2a11	1205	uint32_t RESERVED22[1U];
saloutos	0:083111ae2a11	1206	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
saloutos	0:083111ae2a11	1207	uint32_t RESERVED23[1U];
saloutos	0:083111ae2a11	1208	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
saloutos	0:083111ae2a11	1209	uint32_t RESERVED24[1U];
saloutos	0:083111ae2a11	1210	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
saloutos	0:083111ae2a11	1211	uint32_t RESERVED25[1U];
saloutos	0:083111ae2a11	1212	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
saloutos	0:083111ae2a11	1213	uint32_t RESERVED26[1U];
saloutos	0:083111ae2a11	1214	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
saloutos	0:083111ae2a11	1215	uint32_t RESERVED27[1U];
saloutos	0:083111ae2a11	1216	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
saloutos	0:083111ae2a11	1217	uint32_t RESERVED28[1U];
saloutos	0:083111ae2a11	1218	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
saloutos	0:083111ae2a11	1219	uint32_t RESERVED29[1U];
saloutos	0:083111ae2a11	1220	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
saloutos	0:083111ae2a11	1221	uint32_t RESERVED30[1U];
saloutos	0:083111ae2a11	1222	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
saloutos	0:083111ae2a11	1223	uint32_t RESERVED31[1U];
saloutos	0:083111ae2a11	1224	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
saloutos	0:083111ae2a11	1225	uint32_t RESERVED32[934U];
saloutos	0:083111ae2a11	1226	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
saloutos	0:083111ae2a11	1227	uint32_t RESERVED33[1U];
saloutos	0:083111ae2a11	1228	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) Device Architecture Register /
saloutos	0:083111ae2a11	1229	} DWT_Type;
saloutos	0:083111ae2a11	1230
saloutos	0:083111ae2a11	1231	/* DWT Control Register Definitions */
saloutos	0:083111ae2a11	1232	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
saloutos	0:083111ae2a11	1233	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
saloutos	0:083111ae2a11	1234
saloutos	0:083111ae2a11	1235	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
saloutos	0:083111ae2a11	1236	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
saloutos	0:083111ae2a11	1237
saloutos	0:083111ae2a11	1238	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
saloutos	0:083111ae2a11	1239	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
saloutos	0:083111ae2a11	1240
saloutos	0:083111ae2a11	1241	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
saloutos	0:083111ae2a11	1242	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
saloutos	0:083111ae2a11	1243
saloutos	0:083111ae2a11	1244	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
saloutos	0:083111ae2a11	1245	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
saloutos	0:083111ae2a11	1246
saloutos	0:083111ae2a11	1247	#define DWT_CTRL_CYCDISS_Pos 23U /!< DWT CTRL: CYCDISS Position /
saloutos	0:083111ae2a11	1248	#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /!< DWT CTRL: CYCDISS Mask /
saloutos	0:083111ae2a11	1249
saloutos	0:083111ae2a11	1250	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
saloutos	0:083111ae2a11	1251	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
saloutos	0:083111ae2a11	1252
saloutos	0:083111ae2a11	1253	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
saloutos	0:083111ae2a11	1254	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
saloutos	0:083111ae2a11	1255
saloutos	0:083111ae2a11	1256	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
saloutos	0:083111ae2a11	1257	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
saloutos	0:083111ae2a11	1258
saloutos	0:083111ae2a11	1259	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
saloutos	0:083111ae2a11	1260	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
saloutos	0:083111ae2a11	1261
saloutos	0:083111ae2a11	1262	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
saloutos	0:083111ae2a11	1263	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
saloutos	0:083111ae2a11	1264
saloutos	0:083111ae2a11	1265	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
saloutos	0:083111ae2a11	1266	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
saloutos	0:083111ae2a11	1267
saloutos	0:083111ae2a11	1268	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
saloutos	0:083111ae2a11	1269	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
saloutos	0:083111ae2a11	1270
saloutos	0:083111ae2a11	1271	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
saloutos	0:083111ae2a11	1272	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
saloutos	0:083111ae2a11	1273
saloutos	0:083111ae2a11	1274	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
saloutos	0:083111ae2a11	1275	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
saloutos	0:083111ae2a11	1276
saloutos	0:083111ae2a11	1277	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
saloutos	0:083111ae2a11	1278	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
saloutos	0:083111ae2a11	1279
saloutos	0:083111ae2a11	1280	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
saloutos	0:083111ae2a11	1281	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
saloutos	0:083111ae2a11	1282
saloutos	0:083111ae2a11	1283	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
saloutos	0:083111ae2a11	1284	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
saloutos	0:083111ae2a11	1285
saloutos	0:083111ae2a11	1286	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
saloutos	0:083111ae2a11	1287	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
saloutos	0:083111ae2a11	1288
saloutos	0:083111ae2a11	1289	/* DWT CPI Count Register Definitions */
saloutos	0:083111ae2a11	1290	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
saloutos	0:083111ae2a11	1291	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
saloutos	0:083111ae2a11	1292
saloutos	0:083111ae2a11	1293	/* DWT Exception Overhead Count Register Definitions */
saloutos	0:083111ae2a11	1294	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
saloutos	0:083111ae2a11	1295	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
saloutos	0:083111ae2a11	1296
saloutos	0:083111ae2a11	1297	/* DWT Sleep Count Register Definitions */
saloutos	0:083111ae2a11	1298	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
saloutos	0:083111ae2a11	1299	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
saloutos	0:083111ae2a11	1300
saloutos	0:083111ae2a11	1301	/* DWT LSU Count Register Definitions */
saloutos	0:083111ae2a11	1302	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
saloutos	0:083111ae2a11	1303	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
saloutos	0:083111ae2a11	1304
saloutos	0:083111ae2a11	1305	/* DWT Folded-instruction Count Register Definitions */
saloutos	0:083111ae2a11	1306	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
saloutos	0:083111ae2a11	1307	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
saloutos	0:083111ae2a11	1308
saloutos	0:083111ae2a11	1309	/* DWT Comparator Function Register Definitions */
saloutos	0:083111ae2a11	1310	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
saloutos	0:083111ae2a11	1311	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
saloutos	0:083111ae2a11	1312
saloutos	0:083111ae2a11	1313	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
saloutos	0:083111ae2a11	1314	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
saloutos	0:083111ae2a11	1315
saloutos	0:083111ae2a11	1316	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
saloutos	0:083111ae2a11	1317	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
saloutos	0:083111ae2a11	1318
saloutos	0:083111ae2a11	1319	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
saloutos	0:083111ae2a11	1320	#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
saloutos	0:083111ae2a11	1321
saloutos	0:083111ae2a11	1322	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
saloutos	0:083111ae2a11	1323	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
saloutos	0:083111ae2a11	1324
saloutos	0:083111ae2a11	1325	/@}/ /* end of group CMSIS_DWT */
saloutos	0:083111ae2a11	1326
saloutos	0:083111ae2a11	1327
saloutos	0:083111ae2a11	1328	/**
saloutos	0:083111ae2a11	1329	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	1330	\defgroup CMSIS_TPI Trace Port Interface (TPI)
saloutos	0:083111ae2a11	1331	\brief Type definitions for the Trace Port Interface (TPI)
saloutos	0:083111ae2a11	1332	@{
saloutos	0:083111ae2a11	1333	*/
saloutos	0:083111ae2a11	1334
saloutos	0:083111ae2a11	1335	/**
saloutos	0:083111ae2a11	1336	\brief Structure type to access the Trace Port Interface Register (TPI).
saloutos	0:083111ae2a11	1337	*/
saloutos	0:083111ae2a11	1338	typedef struct
saloutos	0:083111ae2a11	1339	{
saloutos	0:083111ae2a11	1340	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
saloutos	0:083111ae2a11	1341	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
saloutos	0:083111ae2a11	1342	uint32_t RESERVED0[2U];
saloutos	0:083111ae2a11	1343	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
saloutos	0:083111ae2a11	1344	uint32_t RESERVED1[55U];
saloutos	0:083111ae2a11	1345	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
saloutos	0:083111ae2a11	1346	uint32_t RESERVED2[131U];
saloutos	0:083111ae2a11	1347	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
saloutos	0:083111ae2a11	1348	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
saloutos	0:083111ae2a11	1349	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
saloutos	0:083111ae2a11	1350	uint32_t RESERVED3[759U];
saloutos	0:083111ae2a11	1351	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
saloutos	0:083111ae2a11	1352	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
saloutos	0:083111ae2a11	1353	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
saloutos	0:083111ae2a11	1354	uint32_t RESERVED4[1U];
saloutos	0:083111ae2a11	1355	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
saloutos	0:083111ae2a11	1356	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
saloutos	0:083111ae2a11	1357	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
saloutos	0:083111ae2a11	1358	uint32_t RESERVED5[39U];
saloutos	0:083111ae2a11	1359	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
saloutos	0:083111ae2a11	1360	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
saloutos	0:083111ae2a11	1361	uint32_t RESERVED7[8U];
saloutos	0:083111ae2a11	1362	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
saloutos	0:083111ae2a11	1363	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
saloutos	0:083111ae2a11	1364	} TPI_Type;
saloutos	0:083111ae2a11	1365
saloutos	0:083111ae2a11	1366	/* TPI Asynchronous Clock Prescaler Register Definitions */
saloutos	0:083111ae2a11	1367	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
saloutos	0:083111ae2a11	1368	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
saloutos	0:083111ae2a11	1369
saloutos	0:083111ae2a11	1370	/* TPI Selected Pin Protocol Register Definitions */
saloutos	0:083111ae2a11	1371	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
saloutos	0:083111ae2a11	1372	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
saloutos	0:083111ae2a11	1373
saloutos	0:083111ae2a11	1374	/* TPI Formatter and Flush Status Register Definitions */
saloutos	0:083111ae2a11	1375	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
saloutos	0:083111ae2a11	1376	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
saloutos	0:083111ae2a11	1377
saloutos	0:083111ae2a11	1378	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
saloutos	0:083111ae2a11	1379	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
saloutos	0:083111ae2a11	1380
saloutos	0:083111ae2a11	1381	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
saloutos	0:083111ae2a11	1382	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
saloutos	0:083111ae2a11	1383
saloutos	0:083111ae2a11	1384	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
saloutos	0:083111ae2a11	1385	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
saloutos	0:083111ae2a11	1386
saloutos	0:083111ae2a11	1387	/* TPI Formatter and Flush Control Register Definitions */
saloutos	0:083111ae2a11	1388	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
saloutos	0:083111ae2a11	1389	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
saloutos	0:083111ae2a11	1390
saloutos	0:083111ae2a11	1391	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
saloutos	0:083111ae2a11	1392	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
saloutos	0:083111ae2a11	1393
saloutos	0:083111ae2a11	1394	/* TPI TRIGGER Register Definitions */
saloutos	0:083111ae2a11	1395	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
saloutos	0:083111ae2a11	1396	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
saloutos	0:083111ae2a11	1397
saloutos	0:083111ae2a11	1398	/* TPI Integration ETM Data Register Definitions (FIFO0) */
saloutos	0:083111ae2a11	1399	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
saloutos	0:083111ae2a11	1400	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
saloutos	0:083111ae2a11	1401
saloutos	0:083111ae2a11	1402	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
saloutos	0:083111ae2a11	1403	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
saloutos	0:083111ae2a11	1404
saloutos	0:083111ae2a11	1405	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
saloutos	0:083111ae2a11	1406	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
saloutos	0:083111ae2a11	1407
saloutos	0:083111ae2a11	1408	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
saloutos	0:083111ae2a11	1409	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
saloutos	0:083111ae2a11	1410
saloutos	0:083111ae2a11	1411	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
saloutos	0:083111ae2a11	1412	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
saloutos	0:083111ae2a11	1413
saloutos	0:083111ae2a11	1414	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
saloutos	0:083111ae2a11	1415	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
saloutos	0:083111ae2a11	1416
saloutos	0:083111ae2a11	1417	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
saloutos	0:083111ae2a11	1418	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
saloutos	0:083111ae2a11	1419
saloutos	0:083111ae2a11	1420	/* TPI ITATBCTR2 Register Definitions */
saloutos	0:083111ae2a11	1421	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
saloutos	0:083111ae2a11	1422	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
saloutos	0:083111ae2a11	1423
saloutos	0:083111ae2a11	1424	/* TPI Integration ITM Data Register Definitions (FIFO1) */
saloutos	0:083111ae2a11	1425	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
saloutos	0:083111ae2a11	1426	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
saloutos	0:083111ae2a11	1427
saloutos	0:083111ae2a11	1428	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
saloutos	0:083111ae2a11	1429	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
saloutos	0:083111ae2a11	1430
saloutos	0:083111ae2a11	1431	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
saloutos	0:083111ae2a11	1432	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
saloutos	0:083111ae2a11	1433
saloutos	0:083111ae2a11	1434	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
saloutos	0:083111ae2a11	1435	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
saloutos	0:083111ae2a11	1436
saloutos	0:083111ae2a11	1437	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
saloutos	0:083111ae2a11	1438	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
saloutos	0:083111ae2a11	1439
saloutos	0:083111ae2a11	1440	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
saloutos	0:083111ae2a11	1441	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
saloutos	0:083111ae2a11	1442
saloutos	0:083111ae2a11	1443	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
saloutos	0:083111ae2a11	1444	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
saloutos	0:083111ae2a11	1445
saloutos	0:083111ae2a11	1446	/* TPI ITATBCTR0 Register Definitions */
saloutos	0:083111ae2a11	1447	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
saloutos	0:083111ae2a11	1448	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
saloutos	0:083111ae2a11	1449
saloutos	0:083111ae2a11	1450	/* TPI Integration Mode Control Register Definitions */
saloutos	0:083111ae2a11	1451	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
saloutos	0:083111ae2a11	1452	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
saloutos	0:083111ae2a11	1453
saloutos	0:083111ae2a11	1454	/* TPI DEVID Register Definitions */
saloutos	0:083111ae2a11	1455	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
saloutos	0:083111ae2a11	1456	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
saloutos	0:083111ae2a11	1457
saloutos	0:083111ae2a11	1458	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
saloutos	0:083111ae2a11	1459	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
saloutos	0:083111ae2a11	1460
saloutos	0:083111ae2a11	1461	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
saloutos	0:083111ae2a11	1462	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
saloutos	0:083111ae2a11	1463
saloutos	0:083111ae2a11	1464	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
saloutos	0:083111ae2a11	1465	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
saloutos	0:083111ae2a11	1466
saloutos	0:083111ae2a11	1467	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
saloutos	0:083111ae2a11	1468	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
saloutos	0:083111ae2a11	1469
saloutos	0:083111ae2a11	1470	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
saloutos	0:083111ae2a11	1471	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
saloutos	0:083111ae2a11	1472
saloutos	0:083111ae2a11	1473	/* TPI DEVTYPE Register Definitions */
saloutos	0:083111ae2a11	1474	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
saloutos	0:083111ae2a11	1475	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
saloutos	0:083111ae2a11	1476
saloutos	0:083111ae2a11	1477	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
saloutos	0:083111ae2a11	1478	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
saloutos	0:083111ae2a11	1479
saloutos	0:083111ae2a11	1480	/@}/ /* end of group CMSIS_TPI */
saloutos	0:083111ae2a11	1481
saloutos	0:083111ae2a11	1482
saloutos	0:083111ae2a11	1483	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
saloutos	0:083111ae2a11	1484	/**
saloutos	0:083111ae2a11	1485	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	1486	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
saloutos	0:083111ae2a11	1487	\brief Type definitions for the Memory Protection Unit (MPU)
saloutos	0:083111ae2a11	1488	@{
saloutos	0:083111ae2a11	1489	*/
saloutos	0:083111ae2a11	1490
saloutos	0:083111ae2a11	1491	/**
saloutos	0:083111ae2a11	1492	\brief Structure type to access the Memory Protection Unit (MPU).
saloutos	0:083111ae2a11	1493	*/
saloutos	0:083111ae2a11	1494	typedef struct
saloutos	0:083111ae2a11	1495	{
saloutos	0:083111ae2a11	1496	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
saloutos	0:083111ae2a11	1497	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
saloutos	0:083111ae2a11	1498	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
saloutos	0:083111ae2a11	1499	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
saloutos	0:083111ae2a11	1500	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
saloutos	0:083111ae2a11	1501	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 /
saloutos	0:083111ae2a11	1502	__IOM uint32_t RLAR_A1; /!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 /
saloutos	0:083111ae2a11	1503	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 /
saloutos	0:083111ae2a11	1504	__IOM uint32_t RLAR_A2; /!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 /
saloutos	0:083111ae2a11	1505	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 /
saloutos	0:083111ae2a11	1506	__IOM uint32_t RLAR_A3; /!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 /
saloutos	0:083111ae2a11	1507	uint32_t RESERVED0[1];
saloutos	0:083111ae2a11	1508	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
saloutos	0:083111ae2a11	1509	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
saloutos	0:083111ae2a11	1510	} MPU_Type;
saloutos	0:083111ae2a11	1511
saloutos	0:083111ae2a11	1512	/* MPU Type Register Definitions */
saloutos	0:083111ae2a11	1513	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
saloutos	0:083111ae2a11	1514	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
saloutos	0:083111ae2a11	1515
saloutos	0:083111ae2a11	1516	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
saloutos	0:083111ae2a11	1517	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
saloutos	0:083111ae2a11	1518
saloutos	0:083111ae2a11	1519	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
saloutos	0:083111ae2a11	1520	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
saloutos	0:083111ae2a11	1521
saloutos	0:083111ae2a11	1522	/* MPU Control Register Definitions */
saloutos	0:083111ae2a11	1523	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
saloutos	0:083111ae2a11	1524	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
saloutos	0:083111ae2a11	1525
saloutos	0:083111ae2a11	1526	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
saloutos	0:083111ae2a11	1527	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
saloutos	0:083111ae2a11	1528
saloutos	0:083111ae2a11	1529	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
saloutos	0:083111ae2a11	1530	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
saloutos	0:083111ae2a11	1531
saloutos	0:083111ae2a11	1532	/* MPU Region Number Register Definitions */
saloutos	0:083111ae2a11	1533	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
saloutos	0:083111ae2a11	1534	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
saloutos	0:083111ae2a11	1535
saloutos	0:083111ae2a11	1536	/* MPU Region Base Address Register Definitions */
saloutos	0:083111ae2a11	1537	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
saloutos	0:083111ae2a11	1538	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
saloutos	0:083111ae2a11	1539
saloutos	0:083111ae2a11	1540	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
saloutos	0:083111ae2a11	1541	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
saloutos	0:083111ae2a11	1542
saloutos	0:083111ae2a11	1543	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
saloutos	0:083111ae2a11	1544	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
saloutos	0:083111ae2a11	1545
saloutos	0:083111ae2a11	1546	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
saloutos	0:083111ae2a11	1547	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
saloutos	0:083111ae2a11	1548
saloutos	0:083111ae2a11	1549	/* MPU Region Limit Address Register Definitions */
saloutos	0:083111ae2a11	1550	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
saloutos	0:083111ae2a11	1551	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
saloutos	0:083111ae2a11	1552
saloutos	0:083111ae2a11	1553	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
saloutos	0:083111ae2a11	1554	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
saloutos	0:083111ae2a11	1555
saloutos	0:083111ae2a11	1556	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: Region enable bit Position /
saloutos	0:083111ae2a11	1557	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: Region enable bit Disable Mask /
saloutos	0:083111ae2a11	1558
saloutos	0:083111ae2a11	1559	/* MPU Memory Attribute Indirection Register 0 Definitions */
saloutos	0:083111ae2a11	1560	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
saloutos	0:083111ae2a11	1561	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
saloutos	0:083111ae2a11	1562
saloutos	0:083111ae2a11	1563	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
saloutos	0:083111ae2a11	1564	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
saloutos	0:083111ae2a11	1565
saloutos	0:083111ae2a11	1566	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
saloutos	0:083111ae2a11	1567	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
saloutos	0:083111ae2a11	1568
saloutos	0:083111ae2a11	1569	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
saloutos	0:083111ae2a11	1570	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
saloutos	0:083111ae2a11	1571
saloutos	0:083111ae2a11	1572	/* MPU Memory Attribute Indirection Register 1 Definitions */
saloutos	0:083111ae2a11	1573	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
saloutos	0:083111ae2a11	1574	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
saloutos	0:083111ae2a11	1575
saloutos	0:083111ae2a11	1576	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
saloutos	0:083111ae2a11	1577	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
saloutos	0:083111ae2a11	1578
saloutos	0:083111ae2a11	1579	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
saloutos	0:083111ae2a11	1580	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
saloutos	0:083111ae2a11	1581
saloutos	0:083111ae2a11	1582	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
saloutos	0:083111ae2a11	1583	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
saloutos	0:083111ae2a11	1584
saloutos	0:083111ae2a11	1585	/@} end of group CMSIS_MPU /
saloutos	0:083111ae2a11	1586	#endif
saloutos	0:083111ae2a11	1587
saloutos	0:083111ae2a11	1588
saloutos	0:083111ae2a11	1589	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	1590	/**
saloutos	0:083111ae2a11	1591	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	1592	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
saloutos	0:083111ae2a11	1593	\brief Type definitions for the Security Attribution Unit (SAU)
saloutos	0:083111ae2a11	1594	@{
saloutos	0:083111ae2a11	1595	*/
saloutos	0:083111ae2a11	1596
saloutos	0:083111ae2a11	1597	/**
saloutos	0:083111ae2a11	1598	\brief Structure type to access the Security Attribution Unit (SAU).
saloutos	0:083111ae2a11	1599	*/
saloutos	0:083111ae2a11	1600	typedef struct
saloutos	0:083111ae2a11	1601	{
saloutos	0:083111ae2a11	1602	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
saloutos	0:083111ae2a11	1603	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
saloutos	0:083111ae2a11	1604	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
saloutos	0:083111ae2a11	1605	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
saloutos	0:083111ae2a11	1606	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
saloutos	0:083111ae2a11	1607	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
saloutos	0:083111ae2a11	1608	#else
saloutos	0:083111ae2a11	1609	uint32_t RESERVED0[3];
saloutos	0:083111ae2a11	1610	#endif
saloutos	0:083111ae2a11	1611	__IOM uint32_t SFSR; /!< Offset: 0x014 (R/W) Secure Fault Status Register /
saloutos	0:083111ae2a11	1612	__IOM uint32_t SFAR; /!< Offset: 0x018 (R/W) Secure Fault Address Register /
saloutos	0:083111ae2a11	1613	} SAU_Type;
saloutos	0:083111ae2a11	1614
saloutos	0:083111ae2a11	1615	/* SAU Control Register Definitions */
saloutos	0:083111ae2a11	1616	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
saloutos	0:083111ae2a11	1617	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
saloutos	0:083111ae2a11	1618
saloutos	0:083111ae2a11	1619	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
saloutos	0:083111ae2a11	1620	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
saloutos	0:083111ae2a11	1621
saloutos	0:083111ae2a11	1622	/* SAU Type Register Definitions */
saloutos	0:083111ae2a11	1623	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
saloutos	0:083111ae2a11	1624	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
saloutos	0:083111ae2a11	1625
saloutos	0:083111ae2a11	1626	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
saloutos	0:083111ae2a11	1627	/* SAU Region Number Register Definitions */
saloutos	0:083111ae2a11	1628	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
saloutos	0:083111ae2a11	1629	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
saloutos	0:083111ae2a11	1630
saloutos	0:083111ae2a11	1631	/* SAU Region Base Address Register Definitions */
saloutos	0:083111ae2a11	1632	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
saloutos	0:083111ae2a11	1633	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
saloutos	0:083111ae2a11	1634
saloutos	0:083111ae2a11	1635	/* SAU Region Limit Address Register Definitions */
saloutos	0:083111ae2a11	1636	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
saloutos	0:083111ae2a11	1637	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
saloutos	0:083111ae2a11	1638
saloutos	0:083111ae2a11	1639	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
saloutos	0:083111ae2a11	1640	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
saloutos	0:083111ae2a11	1641
saloutos	0:083111ae2a11	1642	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
saloutos	0:083111ae2a11	1643	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
saloutos	0:083111ae2a11	1644
saloutos	0:083111ae2a11	1645	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
saloutos	0:083111ae2a11	1646
saloutos	0:083111ae2a11	1647	/* Secure Fault Status Register Definitions */
saloutos	0:083111ae2a11	1648	#define SAU_SFSR_LSERR_Pos 7U /!< SAU SFSR: LSERR Position /
saloutos	0:083111ae2a11	1649	#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /!< SAU SFSR: LSERR Mask /
saloutos	0:083111ae2a11	1650
saloutos	0:083111ae2a11	1651	#define SAU_SFSR_SFARVALID_Pos 6U /!< SAU SFSR: SFARVALID Position /
saloutos	0:083111ae2a11	1652	#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /!< SAU SFSR: SFARVALID Mask /
saloutos	0:083111ae2a11	1653
saloutos	0:083111ae2a11	1654	#define SAU_SFSR_LSPERR_Pos 5U /!< SAU SFSR: LSPERR Position /
saloutos	0:083111ae2a11	1655	#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /!< SAU SFSR: LSPERR Mask /
saloutos	0:083111ae2a11	1656
saloutos	0:083111ae2a11	1657	#define SAU_SFSR_INVTRAN_Pos 4U /!< SAU SFSR: INVTRAN Position /
saloutos	0:083111ae2a11	1658	#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /!< SAU SFSR: INVTRAN Mask /
saloutos	0:083111ae2a11	1659
saloutos	0:083111ae2a11	1660	#define SAU_SFSR_AUVIOL_Pos 3U /!< SAU SFSR: AUVIOL Position /
saloutos	0:083111ae2a11	1661	#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /!< SAU SFSR: AUVIOL Mask /
saloutos	0:083111ae2a11	1662
saloutos	0:083111ae2a11	1663	#define SAU_SFSR_INVER_Pos 2U /!< SAU SFSR: INVER Position /
saloutos	0:083111ae2a11	1664	#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /!< SAU SFSR: INVER Mask /
saloutos	0:083111ae2a11	1665
saloutos	0:083111ae2a11	1666	#define SAU_SFSR_INVIS_Pos 1U /!< SAU SFSR: INVIS Position /
saloutos	0:083111ae2a11	1667	#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /!< SAU SFSR: INVIS Mask /
saloutos	0:083111ae2a11	1668
saloutos	0:083111ae2a11	1669	#define SAU_SFSR_INVEP_Pos 0U /!< SAU SFSR: INVEP Position /
saloutos	0:083111ae2a11	1670	#define SAU_SFSR_INVEP_Msk (1UL /<< SAU_SFSR_INVEP_Pos/) /!< SAU SFSR: INVEP Mask /
saloutos	0:083111ae2a11	1671
saloutos	0:083111ae2a11	1672	/@} end of group CMSIS_SAU /
saloutos	0:083111ae2a11	1673	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
saloutos	0:083111ae2a11	1674
saloutos	0:083111ae2a11	1675
saloutos	0:083111ae2a11	1676	/**
saloutos	0:083111ae2a11	1677	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	1678	\defgroup CMSIS_FPU Floating Point Unit (FPU)
saloutos	0:083111ae2a11	1679	\brief Type definitions for the Floating Point Unit (FPU)
saloutos	0:083111ae2a11	1680	@{
saloutos	0:083111ae2a11	1681	*/
saloutos	0:083111ae2a11	1682
saloutos	0:083111ae2a11	1683	/**
saloutos	0:083111ae2a11	1684	\brief Structure type to access the Floating Point Unit (FPU).
saloutos	0:083111ae2a11	1685	*/
saloutos	0:083111ae2a11	1686	typedef struct
saloutos	0:083111ae2a11	1687	{
saloutos	0:083111ae2a11	1688	uint32_t RESERVED0[1U];
saloutos	0:083111ae2a11	1689	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
saloutos	0:083111ae2a11	1690	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
saloutos	0:083111ae2a11	1691	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
saloutos	0:083111ae2a11	1692	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
saloutos	0:083111ae2a11	1693	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
saloutos	0:083111ae2a11	1694	} FPU_Type;
saloutos	0:083111ae2a11	1695
saloutos	0:083111ae2a11	1696	/* Floating-Point Context Control Register Definitions */
saloutos	0:083111ae2a11	1697	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
saloutos	0:083111ae2a11	1698	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
saloutos	0:083111ae2a11	1699
saloutos	0:083111ae2a11	1700	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
saloutos	0:083111ae2a11	1701	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
saloutos	0:083111ae2a11	1702
saloutos	0:083111ae2a11	1703	#define FPU_FPCCR_LSPENS_Pos 29U /!< FPCCR: LSPENS Position /
saloutos	0:083111ae2a11	1704	#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /!< FPCCR: LSPENS bit Mask /
saloutos	0:083111ae2a11	1705
saloutos	0:083111ae2a11	1706	#define FPU_FPCCR_CLRONRET_Pos 28U /!< FPCCR: CLRONRET Position /
saloutos	0:083111ae2a11	1707	#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /!< FPCCR: CLRONRET bit Mask /
saloutos	0:083111ae2a11	1708
saloutos	0:083111ae2a11	1709	#define FPU_FPCCR_CLRONRETS_Pos 27U /!< FPCCR: CLRONRETS Position /
saloutos	0:083111ae2a11	1710	#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /!< FPCCR: CLRONRETS bit Mask /
saloutos	0:083111ae2a11	1711
saloutos	0:083111ae2a11	1712	#define FPU_FPCCR_TS_Pos 26U /!< FPCCR: TS Position /
saloutos	0:083111ae2a11	1713	#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /!< FPCCR: TS bit Mask /
saloutos	0:083111ae2a11	1714
saloutos	0:083111ae2a11	1715	#define FPU_FPCCR_UFRDY_Pos 10U /!< FPCCR: UFRDY Position /
saloutos	0:083111ae2a11	1716	#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /!< FPCCR: UFRDY bit Mask /
saloutos	0:083111ae2a11	1717
saloutos	0:083111ae2a11	1718	#define FPU_FPCCR_SPLIMVIOL_Pos 9U /!< FPCCR: SPLIMVIOL Position /
saloutos	0:083111ae2a11	1719	#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /!< FPCCR: SPLIMVIOL bit Mask /
saloutos	0:083111ae2a11	1720
saloutos	0:083111ae2a11	1721	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
saloutos	0:083111ae2a11	1722	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
saloutos	0:083111ae2a11	1723
saloutos	0:083111ae2a11	1724	#define FPU_FPCCR_SFRDY_Pos 7U /!< FPCCR: SFRDY Position /
saloutos	0:083111ae2a11	1725	#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /!< FPCCR: SFRDY bit Mask /
saloutos	0:083111ae2a11	1726
saloutos	0:083111ae2a11	1727	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
saloutos	0:083111ae2a11	1728	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
saloutos	0:083111ae2a11	1729
saloutos	0:083111ae2a11	1730	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
saloutos	0:083111ae2a11	1731	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
saloutos	0:083111ae2a11	1732
saloutos	0:083111ae2a11	1733	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
saloutos	0:083111ae2a11	1734	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
saloutos	0:083111ae2a11	1735
saloutos	0:083111ae2a11	1736	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
saloutos	0:083111ae2a11	1737	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
saloutos	0:083111ae2a11	1738
saloutos	0:083111ae2a11	1739	#define FPU_FPCCR_S_Pos 2U /!< FPCCR: Security status of the FP context bit Position /
saloutos	0:083111ae2a11	1740	#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /!< FPCCR: Security status of the FP context bit Mask /
saloutos	0:083111ae2a11	1741
saloutos	0:083111ae2a11	1742	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
saloutos	0:083111ae2a11	1743	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
saloutos	0:083111ae2a11	1744
saloutos	0:083111ae2a11	1745	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
saloutos	0:083111ae2a11	1746	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
saloutos	0:083111ae2a11	1747
saloutos	0:083111ae2a11	1748	/* Floating-Point Context Address Register Definitions */
saloutos	0:083111ae2a11	1749	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
saloutos	0:083111ae2a11	1750	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
saloutos	0:083111ae2a11	1751
saloutos	0:083111ae2a11	1752	/* Floating-Point Default Status Control Register Definitions */
saloutos	0:083111ae2a11	1753	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
saloutos	0:083111ae2a11	1754	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
saloutos	0:083111ae2a11	1755
saloutos	0:083111ae2a11	1756	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
saloutos	0:083111ae2a11	1757	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
saloutos	0:083111ae2a11	1758
saloutos	0:083111ae2a11	1759	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
saloutos	0:083111ae2a11	1760	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
saloutos	0:083111ae2a11	1761
saloutos	0:083111ae2a11	1762	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
saloutos	0:083111ae2a11	1763	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
saloutos	0:083111ae2a11	1764
saloutos	0:083111ae2a11	1765	/* Media and FP Feature Register 0 Definitions */
saloutos	0:083111ae2a11	1766	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
saloutos	0:083111ae2a11	1767	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
saloutos	0:083111ae2a11	1768
saloutos	0:083111ae2a11	1769	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
saloutos	0:083111ae2a11	1770	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
saloutos	0:083111ae2a11	1771
saloutos	0:083111ae2a11	1772	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
saloutos	0:083111ae2a11	1773	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
saloutos	0:083111ae2a11	1774
saloutos	0:083111ae2a11	1775	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
saloutos	0:083111ae2a11	1776	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
saloutos	0:083111ae2a11	1777
saloutos	0:083111ae2a11	1778	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
saloutos	0:083111ae2a11	1779	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
saloutos	0:083111ae2a11	1780
saloutos	0:083111ae2a11	1781	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
saloutos	0:083111ae2a11	1782	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
saloutos	0:083111ae2a11	1783
saloutos	0:083111ae2a11	1784	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
saloutos	0:083111ae2a11	1785	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
saloutos	0:083111ae2a11	1786
saloutos	0:083111ae2a11	1787	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
saloutos	0:083111ae2a11	1788	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
saloutos	0:083111ae2a11	1789
saloutos	0:083111ae2a11	1790	/* Media and FP Feature Register 1 Definitions */
saloutos	0:083111ae2a11	1791	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
saloutos	0:083111ae2a11	1792	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
saloutos	0:083111ae2a11	1793
saloutos	0:083111ae2a11	1794	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
saloutos	0:083111ae2a11	1795	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
saloutos	0:083111ae2a11	1796
saloutos	0:083111ae2a11	1797	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
saloutos	0:083111ae2a11	1798	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
saloutos	0:083111ae2a11	1799
saloutos	0:083111ae2a11	1800	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
saloutos	0:083111ae2a11	1801	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
saloutos	0:083111ae2a11	1802
saloutos	0:083111ae2a11	1803	/@} end of group CMSIS_FPU /
saloutos	0:083111ae2a11	1804
saloutos	0:083111ae2a11	1805
saloutos	0:083111ae2a11	1806	/**
saloutos	0:083111ae2a11	1807	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	1808	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
saloutos	0:083111ae2a11	1809	\brief Type definitions for the Core Debug Registers
saloutos	0:083111ae2a11	1810	@{
saloutos	0:083111ae2a11	1811	*/
saloutos	0:083111ae2a11	1812
saloutos	0:083111ae2a11	1813	/**
saloutos	0:083111ae2a11	1814	\brief Structure type to access the Core Debug Register (CoreDebug).
saloutos	0:083111ae2a11	1815	*/
saloutos	0:083111ae2a11	1816	typedef struct
saloutos	0:083111ae2a11	1817	{
saloutos	0:083111ae2a11	1818	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
saloutos	0:083111ae2a11	1819	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
saloutos	0:083111ae2a11	1820	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
saloutos	0:083111ae2a11	1821	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
saloutos	0:083111ae2a11	1822	uint32_t RESERVED4[1U];
saloutos	0:083111ae2a11	1823	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
saloutos	0:083111ae2a11	1824	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
saloutos	0:083111ae2a11	1825	} CoreDebug_Type;
saloutos	0:083111ae2a11	1826
saloutos	0:083111ae2a11	1827	/* Debug Halting Control and Status Register Definitions */
saloutos	0:083111ae2a11	1828	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
saloutos	0:083111ae2a11	1829	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
saloutos	0:083111ae2a11	1830
saloutos	0:083111ae2a11	1831	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
saloutos	0:083111ae2a11	1832	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
saloutos	0:083111ae2a11	1833
saloutos	0:083111ae2a11	1834	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
saloutos	0:083111ae2a11	1835	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
saloutos	0:083111ae2a11	1836
saloutos	0:083111ae2a11	1837	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
saloutos	0:083111ae2a11	1838	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
saloutos	0:083111ae2a11	1839
saloutos	0:083111ae2a11	1840	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
saloutos	0:083111ae2a11	1841	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
saloutos	0:083111ae2a11	1842
saloutos	0:083111ae2a11	1843	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
saloutos	0:083111ae2a11	1844	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
saloutos	0:083111ae2a11	1845
saloutos	0:083111ae2a11	1846	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
saloutos	0:083111ae2a11	1847	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
saloutos	0:083111ae2a11	1848
saloutos	0:083111ae2a11	1849	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
saloutos	0:083111ae2a11	1850	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
saloutos	0:083111ae2a11	1851
saloutos	0:083111ae2a11	1852	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
saloutos	0:083111ae2a11	1853	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
saloutos	0:083111ae2a11	1854
saloutos	0:083111ae2a11	1855	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
saloutos	0:083111ae2a11	1856	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
saloutos	0:083111ae2a11	1857
saloutos	0:083111ae2a11	1858	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
saloutos	0:083111ae2a11	1859	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
saloutos	0:083111ae2a11	1860
saloutos	0:083111ae2a11	1861	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
saloutos	0:083111ae2a11	1862	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
saloutos	0:083111ae2a11	1863
saloutos	0:083111ae2a11	1864	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
saloutos	0:083111ae2a11	1865	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
saloutos	0:083111ae2a11	1866
saloutos	0:083111ae2a11	1867	/* Debug Core Register Selector Register Definitions */
saloutos	0:083111ae2a11	1868	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
saloutos	0:083111ae2a11	1869	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
saloutos	0:083111ae2a11	1870
saloutos	0:083111ae2a11	1871	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
saloutos	0:083111ae2a11	1872	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
saloutos	0:083111ae2a11	1873
saloutos	0:083111ae2a11	1874	/* Debug Exception and Monitor Control Register Definitions */
saloutos	0:083111ae2a11	1875	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
saloutos	0:083111ae2a11	1876	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
saloutos	0:083111ae2a11	1877
saloutos	0:083111ae2a11	1878	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
saloutos	0:083111ae2a11	1879	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
saloutos	0:083111ae2a11	1880
saloutos	0:083111ae2a11	1881	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
saloutos	0:083111ae2a11	1882	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
saloutos	0:083111ae2a11	1883
saloutos	0:083111ae2a11	1884	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
saloutos	0:083111ae2a11	1885	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
saloutos	0:083111ae2a11	1886
saloutos	0:083111ae2a11	1887	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
saloutos	0:083111ae2a11	1888	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
saloutos	0:083111ae2a11	1889
saloutos	0:083111ae2a11	1890	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
saloutos	0:083111ae2a11	1891	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
saloutos	0:083111ae2a11	1892
saloutos	0:083111ae2a11	1893	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
saloutos	0:083111ae2a11	1894	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
saloutos	0:083111ae2a11	1895
saloutos	0:083111ae2a11	1896	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
saloutos	0:083111ae2a11	1897	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
saloutos	0:083111ae2a11	1898
saloutos	0:083111ae2a11	1899	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
saloutos	0:083111ae2a11	1900	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
saloutos	0:083111ae2a11	1901
saloutos	0:083111ae2a11	1902	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
saloutos	0:083111ae2a11	1903	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
saloutos	0:083111ae2a11	1904
saloutos	0:083111ae2a11	1905	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
saloutos	0:083111ae2a11	1906	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
saloutos	0:083111ae2a11	1907
saloutos	0:083111ae2a11	1908	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
saloutos	0:083111ae2a11	1909	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
saloutos	0:083111ae2a11	1910
saloutos	0:083111ae2a11	1911	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
saloutos	0:083111ae2a11	1912	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
saloutos	0:083111ae2a11	1913
saloutos	0:083111ae2a11	1914	/* Debug Authentication Control Register Definitions */
saloutos	0:083111ae2a11	1915	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
saloutos	0:083111ae2a11	1916	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
saloutos	0:083111ae2a11	1917
saloutos	0:083111ae2a11	1918	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
saloutos	0:083111ae2a11	1919	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
saloutos	0:083111ae2a11	1920
saloutos	0:083111ae2a11	1921	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
saloutos	0:083111ae2a11	1922	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
saloutos	0:083111ae2a11	1923
saloutos	0:083111ae2a11	1924	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
saloutos	0:083111ae2a11	1925	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
saloutos	0:083111ae2a11	1926
saloutos	0:083111ae2a11	1927	/* Debug Security Control and Status Register Definitions */
saloutos	0:083111ae2a11	1928	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
saloutos	0:083111ae2a11	1929	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
saloutos	0:083111ae2a11	1930
saloutos	0:083111ae2a11	1931	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
saloutos	0:083111ae2a11	1932	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
saloutos	0:083111ae2a11	1933
saloutos	0:083111ae2a11	1934	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
saloutos	0:083111ae2a11	1935	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
saloutos	0:083111ae2a11	1936
saloutos	0:083111ae2a11	1937	/@} end of group CMSIS_CoreDebug /
saloutos	0:083111ae2a11	1938
saloutos	0:083111ae2a11	1939
saloutos	0:083111ae2a11	1940	/**
saloutos	0:083111ae2a11	1941	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	1942	\defgroup CMSIS_core_bitfield Core register bit field macros
saloutos	0:083111ae2a11	1943	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
saloutos	0:083111ae2a11	1944	@{
saloutos	0:083111ae2a11	1945	*/
saloutos	0:083111ae2a11	1946
saloutos	0:083111ae2a11	1947	/**
saloutos	0:083111ae2a11	1948	\brief Mask and shift a bit field value for use in a register bit range.
saloutos	0:083111ae2a11	1949	\param[in] field Name of the register bit field.
saloutos	0:083111ae2a11	1950	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
saloutos	0:083111ae2a11	1951	\return Masked and shifted value.
saloutos	0:083111ae2a11	1952	*/
saloutos	0:083111ae2a11	1953	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
saloutos	0:083111ae2a11	1954
saloutos	0:083111ae2a11	1955	/**
saloutos	0:083111ae2a11	1956	\brief Mask and shift a register value to extract a bit filed value.
saloutos	0:083111ae2a11	1957	\param[in] field Name of the register bit field.
saloutos	0:083111ae2a11	1958	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
saloutos	0:083111ae2a11	1959	\return Masked and shifted bit field value.
saloutos	0:083111ae2a11	1960	*/
saloutos	0:083111ae2a11	1961	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
saloutos	0:083111ae2a11	1962
saloutos	0:083111ae2a11	1963	/@} end of group CMSIS_core_bitfield /
saloutos	0:083111ae2a11	1964
saloutos	0:083111ae2a11	1965
saloutos	0:083111ae2a11	1966	/**
saloutos	0:083111ae2a11	1967	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	1968	\defgroup CMSIS_core_base Core Definitions
saloutos	0:083111ae2a11	1969	\brief Definitions for base addresses, unions, and structures.
saloutos	0:083111ae2a11	1970	@{
saloutos	0:083111ae2a11	1971	*/
saloutos	0:083111ae2a11	1972
saloutos	0:083111ae2a11	1973	/* Memory mapping of Core Hardware */
saloutos	0:083111ae2a11	1974	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
saloutos	0:083111ae2a11	1975	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
saloutos	0:083111ae2a11	1976	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
saloutos	0:083111ae2a11	1977	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
saloutos	0:083111ae2a11	1978	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
saloutos	0:083111ae2a11	1979	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
saloutos	0:083111ae2a11	1980	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
saloutos	0:083111ae2a11	1981	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
saloutos	0:083111ae2a11	1982
saloutos	0:083111ae2a11	1983	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
saloutos	0:083111ae2a11	1984	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
saloutos	0:083111ae2a11	1985	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
saloutos	0:083111ae2a11	1986	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
saloutos	0:083111ae2a11	1987	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
saloutos	0:083111ae2a11	1988	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
saloutos	0:083111ae2a11	1989	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
saloutos	0:083111ae2a11	1990	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
saloutos	0:083111ae2a11	1991
saloutos	0:083111ae2a11	1992	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
saloutos	0:083111ae2a11	1993	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
saloutos	0:083111ae2a11	1994	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
saloutos	0:083111ae2a11	1995	#endif
saloutos	0:083111ae2a11	1996
saloutos	0:083111ae2a11	1997	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	1998	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
saloutos	0:083111ae2a11	1999	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
saloutos	0:083111ae2a11	2000	#endif
saloutos	0:083111ae2a11	2001
saloutos	0:083111ae2a11	2002	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
saloutos	0:083111ae2a11	2003	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
saloutos	0:083111ae2a11	2004
saloutos	0:083111ae2a11	2005	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	2006	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
saloutos	0:083111ae2a11	2007	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
saloutos	0:083111ae2a11	2008	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
saloutos	0:083111ae2a11	2009	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
saloutos	0:083111ae2a11	2010	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
saloutos	0:083111ae2a11	2011
saloutos	0:083111ae2a11	2012	#define SCnSCB_NS ((SCnSCB_Type ) SCS_BASE_NS ) /!< System control Register not in SCB(non-secure address space) */
saloutos	0:083111ae2a11	2013	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
saloutos	0:083111ae2a11	2014	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
saloutos	0:083111ae2a11	2015	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
saloutos	0:083111ae2a11	2016	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
saloutos	0:083111ae2a11	2017
saloutos	0:083111ae2a11	2018	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
saloutos	0:083111ae2a11	2019	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
saloutos	0:083111ae2a11	2020	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
saloutos	0:083111ae2a11	2021	#endif
saloutos	0:083111ae2a11	2022
saloutos	0:083111ae2a11	2023	#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /!< Floating Point Unit (non-secure address space) /
saloutos	0:083111ae2a11	2024	#define FPU_NS ((FPU_Type ) FPU_BASE_NS ) /!< Floating Point Unit (non-secure address space) */
saloutos	0:083111ae2a11	2025
saloutos	0:083111ae2a11	2026	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
saloutos	0:083111ae2a11	2027	/@} /
saloutos	0:083111ae2a11	2028
saloutos	0:083111ae2a11	2029
saloutos	0:083111ae2a11	2030
saloutos	0:083111ae2a11	2031	/*******************************************************************************
saloutos	0:083111ae2a11	2032	* Hardware Abstraction Layer
saloutos	0:083111ae2a11	2033	Core Function Interface contains:
saloutos	0:083111ae2a11	2034	- Core NVIC Functions
saloutos	0:083111ae2a11	2035	- Core SysTick Functions
saloutos	0:083111ae2a11	2036	- Core Debug Functions
saloutos	0:083111ae2a11	2037	- Core Register Access Functions
saloutos	0:083111ae2a11	2038	******************************************************************************/
saloutos	0:083111ae2a11	2039	/**
saloutos	0:083111ae2a11	2040	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
saloutos	0:083111ae2a11	2041	*/
saloutos	0:083111ae2a11	2042
saloutos	0:083111ae2a11	2043
saloutos	0:083111ae2a11	2044
saloutos	0:083111ae2a11	2045	/* ########################## NVIC functions #################################### */
saloutos	0:083111ae2a11	2046	/**
saloutos	0:083111ae2a11	2047	\ingroup CMSIS_Core_FunctionInterface
saloutos	0:083111ae2a11	2048	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
saloutos	0:083111ae2a11	2049	\brief Functions that manage interrupts and exceptions via the NVIC.
saloutos	0:083111ae2a11	2050	@{
saloutos	0:083111ae2a11	2051	*/
saloutos	0:083111ae2a11	2052
saloutos	0:083111ae2a11	2053	#ifdef CMSIS_NVIC_VIRTUAL
saloutos	0:083111ae2a11	2054	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
saloutos	0:083111ae2a11	2055	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
saloutos	0:083111ae2a11	2056	#endif
saloutos	0:083111ae2a11	2057	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
saloutos	0:083111ae2a11	2058	#else
saloutos	0:083111ae2a11	2059	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
saloutos	0:083111ae2a11	2060	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
saloutos	0:083111ae2a11	2061	#define NVIC_EnableIRQ __NVIC_EnableIRQ
saloutos	0:083111ae2a11	2062	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
saloutos	0:083111ae2a11	2063	#define NVIC_DisableIRQ __NVIC_DisableIRQ
saloutos	0:083111ae2a11	2064	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
saloutos	0:083111ae2a11	2065	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
saloutos	0:083111ae2a11	2066	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
saloutos	0:083111ae2a11	2067	#define NVIC_GetActive __NVIC_GetActive
saloutos	0:083111ae2a11	2068	#define NVIC_SetPriority __NVIC_SetPriority
saloutos	0:083111ae2a11	2069	#define NVIC_GetPriority __NVIC_GetPriority
saloutos	0:083111ae2a11	2070	#define NVIC_SystemReset __NVIC_SystemReset
saloutos	0:083111ae2a11	2071	#endif /* CMSIS_NVIC_VIRTUAL */
saloutos	0:083111ae2a11	2072
saloutos	0:083111ae2a11	2073	#ifdef CMSIS_VECTAB_VIRTUAL
saloutos	0:083111ae2a11	2074	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
saloutos	0:083111ae2a11	2075	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
saloutos	0:083111ae2a11	2076	#endif
saloutos	0:083111ae2a11	2077	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
saloutos	0:083111ae2a11	2078	#else
saloutos	0:083111ae2a11	2079	#define NVIC_SetVector __NVIC_SetVector
saloutos	0:083111ae2a11	2080	#define NVIC_GetVector __NVIC_GetVector
saloutos	0:083111ae2a11	2081	#endif /* (CMSIS_VECTAB_VIRTUAL) */
saloutos	0:083111ae2a11	2082
saloutos	0:083111ae2a11	2083	#define NVIC_USER_IRQ_OFFSET 16
saloutos	0:083111ae2a11	2084
saloutos	0:083111ae2a11	2085
saloutos	0:083111ae2a11	2086
saloutos	0:083111ae2a11	2087	/**
saloutos	0:083111ae2a11	2088	\brief Set Priority Grouping
saloutos	0:083111ae2a11	2089	\details Sets the priority grouping field using the required unlock sequence.
saloutos	0:083111ae2a11	2090	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
saloutos	0:083111ae2a11	2091	Only values from 0..7 are used.
saloutos	0:083111ae2a11	2092	In case of a conflict between priority grouping and available
saloutos	0:083111ae2a11	2093	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
saloutos	0:083111ae2a11	2094	\param [in] PriorityGroup Priority grouping field.
saloutos	0:083111ae2a11	2095	*/
saloutos	0:083111ae2a11	2096	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
saloutos	0:083111ae2a11	2097	{
saloutos	0:083111ae2a11	2098	uint32_t reg_value;
saloutos	0:083111ae2a11	2099	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
saloutos	0:083111ae2a11	2100
saloutos	0:083111ae2a11	2101	reg_value = SCB->AIRCR; /* read old register configuration */
saloutos	0:083111ae2a11	2102	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
saloutos	0:083111ae2a11	2103	reg_value = (reg_value \|
saloutos	0:083111ae2a11	2104	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
saloutos	0:083111ae2a11	2105	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
saloutos	0:083111ae2a11	2106	SCB->AIRCR = reg_value;
saloutos	0:083111ae2a11	2107	}
saloutos	0:083111ae2a11	2108
saloutos	0:083111ae2a11	2109
saloutos	0:083111ae2a11	2110	/**
saloutos	0:083111ae2a11	2111	\brief Get Priority Grouping
saloutos	0:083111ae2a11	2112	\details Reads the priority grouping field from the NVIC Interrupt Controller.
saloutos	0:083111ae2a11	2113	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
saloutos	0:083111ae2a11	2114	*/
saloutos	0:083111ae2a11	2115	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
saloutos	0:083111ae2a11	2116	{
saloutos	0:083111ae2a11	2117	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
saloutos	0:083111ae2a11	2118	}
saloutos	0:083111ae2a11	2119
saloutos	0:083111ae2a11	2120
saloutos	0:083111ae2a11	2121	/**
saloutos	0:083111ae2a11	2122	\brief Enable Interrupt
saloutos	0:083111ae2a11	2123	\details Enables a device specific interrupt in the NVIC interrupt controller.
saloutos	0:083111ae2a11	2124	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2125	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2126	*/
saloutos	0:083111ae2a11	2127	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2128	{
saloutos	0:083111ae2a11	2129	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2130	{
saloutos	0:083111ae2a11	2131	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	2132	}
saloutos	0:083111ae2a11	2133	}
saloutos	0:083111ae2a11	2134
saloutos	0:083111ae2a11	2135
saloutos	0:083111ae2a11	2136	/**
saloutos	0:083111ae2a11	2137	\brief Get Interrupt Enable status
saloutos	0:083111ae2a11	2138	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
saloutos	0:083111ae2a11	2139	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2140	\return 0 Interrupt is not enabled.
saloutos	0:083111ae2a11	2141	\return 1 Interrupt is enabled.
saloutos	0:083111ae2a11	2142	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2143	*/
saloutos	0:083111ae2a11	2144	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2145	{
saloutos	0:083111ae2a11	2146	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2147	{
saloutos	0:083111ae2a11	2148	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	2149	}
saloutos	0:083111ae2a11	2150	else
saloutos	0:083111ae2a11	2151	{
saloutos	0:083111ae2a11	2152	return(0U);
saloutos	0:083111ae2a11	2153	}
saloutos	0:083111ae2a11	2154	}
saloutos	0:083111ae2a11	2155
saloutos	0:083111ae2a11	2156
saloutos	0:083111ae2a11	2157	/**
saloutos	0:083111ae2a11	2158	\brief Disable Interrupt
saloutos	0:083111ae2a11	2159	\details Disables a device specific interrupt in the NVIC interrupt controller.
saloutos	0:083111ae2a11	2160	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2161	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2162	*/
saloutos	0:083111ae2a11	2163	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2164	{
saloutos	0:083111ae2a11	2165	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2166	{
saloutos	0:083111ae2a11	2167	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	2168	__DSB();
saloutos	0:083111ae2a11	2169	__ISB();
saloutos	0:083111ae2a11	2170	}
saloutos	0:083111ae2a11	2171	}
saloutos	0:083111ae2a11	2172
saloutos	0:083111ae2a11	2173
saloutos	0:083111ae2a11	2174	/**
saloutos	0:083111ae2a11	2175	\brief Get Pending Interrupt
saloutos	0:083111ae2a11	2176	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
saloutos	0:083111ae2a11	2177	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2178	\return 0 Interrupt status is not pending.
saloutos	0:083111ae2a11	2179	\return 1 Interrupt status is pending.
saloutos	0:083111ae2a11	2180	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2181	*/
saloutos	0:083111ae2a11	2182	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2183	{
saloutos	0:083111ae2a11	2184	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2185	{
saloutos	0:083111ae2a11	2186	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	2187	}
saloutos	0:083111ae2a11	2188	else
saloutos	0:083111ae2a11	2189	{
saloutos	0:083111ae2a11	2190	return(0U);
saloutos	0:083111ae2a11	2191	}
saloutos	0:083111ae2a11	2192	}
saloutos	0:083111ae2a11	2193
saloutos	0:083111ae2a11	2194
saloutos	0:083111ae2a11	2195	/**
saloutos	0:083111ae2a11	2196	\brief Set Pending Interrupt
saloutos	0:083111ae2a11	2197	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
saloutos	0:083111ae2a11	2198	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2199	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2200	*/
saloutos	0:083111ae2a11	2201	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2202	{
saloutos	0:083111ae2a11	2203	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2204	{
saloutos	0:083111ae2a11	2205	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	2206	}
saloutos	0:083111ae2a11	2207	}
saloutos	0:083111ae2a11	2208
saloutos	0:083111ae2a11	2209
saloutos	0:083111ae2a11	2210	/**
saloutos	0:083111ae2a11	2211	\brief Clear Pending Interrupt
saloutos	0:083111ae2a11	2212	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
saloutos	0:083111ae2a11	2213	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2214	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2215	*/
saloutos	0:083111ae2a11	2216	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2217	{
saloutos	0:083111ae2a11	2218	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2219	{
saloutos	0:083111ae2a11	2220	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	2221	}
saloutos	0:083111ae2a11	2222	}
saloutos	0:083111ae2a11	2223
saloutos	0:083111ae2a11	2224
saloutos	0:083111ae2a11	2225	/**
saloutos	0:083111ae2a11	2226	\brief Get Active Interrupt
saloutos	0:083111ae2a11	2227	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
saloutos	0:083111ae2a11	2228	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2229	\return 0 Interrupt status is not active.
saloutos	0:083111ae2a11	2230	\return 1 Interrupt status is active.
saloutos	0:083111ae2a11	2231	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2232	*/
saloutos	0:083111ae2a11	2233	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2234	{
saloutos	0:083111ae2a11	2235	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2236	{
saloutos	0:083111ae2a11	2237	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	2238	}
saloutos	0:083111ae2a11	2239	else
saloutos	0:083111ae2a11	2240	{
saloutos	0:083111ae2a11	2241	return(0U);
saloutos	0:083111ae2a11	2242	}
saloutos	0:083111ae2a11	2243	}
saloutos	0:083111ae2a11	2244
saloutos	0:083111ae2a11	2245
saloutos	0:083111ae2a11	2246	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	2247	/**
saloutos	0:083111ae2a11	2248	\brief Get Interrupt Target State
saloutos	0:083111ae2a11	2249	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
saloutos	0:083111ae2a11	2250	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2251	\return 0 if interrupt is assigned to Secure
saloutos	0:083111ae2a11	2252	\return 1 if interrupt is assigned to Non Secure
saloutos	0:083111ae2a11	2253	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2254	*/
saloutos	0:083111ae2a11	2255	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2256	{
saloutos	0:083111ae2a11	2257	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2258	{
saloutos	0:083111ae2a11	2259	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	2260	}
saloutos	0:083111ae2a11	2261	else
saloutos	0:083111ae2a11	2262	{
saloutos	0:083111ae2a11	2263	return(0U);
saloutos	0:083111ae2a11	2264	}
saloutos	0:083111ae2a11	2265	}
saloutos	0:083111ae2a11	2266
saloutos	0:083111ae2a11	2267
saloutos	0:083111ae2a11	2268	/**
saloutos	0:083111ae2a11	2269	\brief Set Interrupt Target State
saloutos	0:083111ae2a11	2270	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
saloutos	0:083111ae2a11	2271	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2272	\return 0 if interrupt is assigned to Secure
saloutos	0:083111ae2a11	2273	1 if interrupt is assigned to Non Secure
saloutos	0:083111ae2a11	2274	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2275	*/
saloutos	0:083111ae2a11	2276	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2277	{
saloutos	0:083111ae2a11	2278	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2279	{
saloutos	0:083111ae2a11	2280	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
saloutos	0:083111ae2a11	2281	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	2282	}
saloutos	0:083111ae2a11	2283	else
saloutos	0:083111ae2a11	2284	{
saloutos	0:083111ae2a11	2285	return(0U);
saloutos	0:083111ae2a11	2286	}
saloutos	0:083111ae2a11	2287	}
saloutos	0:083111ae2a11	2288
saloutos	0:083111ae2a11	2289
saloutos	0:083111ae2a11	2290	/**
saloutos	0:083111ae2a11	2291	\brief Clear Interrupt Target State
saloutos	0:083111ae2a11	2292	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
saloutos	0:083111ae2a11	2293	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2294	\return 0 if interrupt is assigned to Secure
saloutos	0:083111ae2a11	2295	1 if interrupt is assigned to Non Secure
saloutos	0:083111ae2a11	2296	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2297	*/
saloutos	0:083111ae2a11	2298	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2299	{
saloutos	0:083111ae2a11	2300	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2301	{
saloutos	0:083111ae2a11	2302	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
saloutos	0:083111ae2a11	2303	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	2304	}
saloutos	0:083111ae2a11	2305	else
saloutos	0:083111ae2a11	2306	{
saloutos	0:083111ae2a11	2307	return(0U);
saloutos	0:083111ae2a11	2308	}
saloutos	0:083111ae2a11	2309	}
saloutos	0:083111ae2a11	2310	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
saloutos	0:083111ae2a11	2311
saloutos	0:083111ae2a11	2312
saloutos	0:083111ae2a11	2313	/**
saloutos	0:083111ae2a11	2314	\brief Set Interrupt Priority
saloutos	0:083111ae2a11	2315	\details Sets the priority of a device specific interrupt or a processor exception.
saloutos	0:083111ae2a11	2316	The interrupt number can be positive to specify a device specific interrupt,
saloutos	0:083111ae2a11	2317	or negative to specify a processor exception.
saloutos	0:083111ae2a11	2318	\param [in] IRQn Interrupt number.
saloutos	0:083111ae2a11	2319	\param [in] priority Priority to set.
saloutos	0:083111ae2a11	2320	\note The priority cannot be set for every processor exception.
saloutos	0:083111ae2a11	2321	*/
saloutos	0:083111ae2a11	2322	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
saloutos	0:083111ae2a11	2323	{
saloutos	0:083111ae2a11	2324	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2325	{
saloutos	0:083111ae2a11	2326	NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
saloutos	0:083111ae2a11	2327	}
saloutos	0:083111ae2a11	2328	else
saloutos	0:083111ae2a11	2329	{
saloutos	0:083111ae2a11	2330	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
saloutos	0:083111ae2a11	2331	}
saloutos	0:083111ae2a11	2332	}
saloutos	0:083111ae2a11	2333
saloutos	0:083111ae2a11	2334
saloutos	0:083111ae2a11	2335	/**
saloutos	0:083111ae2a11	2336	\brief Get Interrupt Priority
saloutos	0:083111ae2a11	2337	\details Reads the priority of a device specific interrupt or a processor exception.
saloutos	0:083111ae2a11	2338	The interrupt number can be positive to specify a device specific interrupt,
saloutos	0:083111ae2a11	2339	or negative to specify a processor exception.
saloutos	0:083111ae2a11	2340	\param [in] IRQn Interrupt number.
saloutos	0:083111ae2a11	2341	\return Interrupt Priority.
saloutos	0:083111ae2a11	2342	Value is aligned automatically to the implemented priority bits of the microcontroller.
saloutos	0:083111ae2a11	2343	*/
saloutos	0:083111ae2a11	2344	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2345	{
saloutos	0:083111ae2a11	2346
saloutos	0:083111ae2a11	2347	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2348	{
saloutos	0:083111ae2a11	2349	return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
saloutos	0:083111ae2a11	2350	}
saloutos	0:083111ae2a11	2351	else
saloutos	0:083111ae2a11	2352	{
saloutos	0:083111ae2a11	2353	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
saloutos	0:083111ae2a11	2354	}
saloutos	0:083111ae2a11	2355	}
saloutos	0:083111ae2a11	2356
saloutos	0:083111ae2a11	2357
saloutos	0:083111ae2a11	2358	/**
saloutos	0:083111ae2a11	2359	\brief Encode Priority
saloutos	0:083111ae2a11	2360	\details Encodes the priority for an interrupt with the given priority group,
saloutos	0:083111ae2a11	2361	preemptive priority value, and subpriority value.
saloutos	0:083111ae2a11	2362	In case of a conflict between priority grouping and available
saloutos	0:083111ae2a11	2363	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
saloutos	0:083111ae2a11	2364	\param [in] PriorityGroup Used priority group.
saloutos	0:083111ae2a11	2365	\param [in] PreemptPriority Preemptive priority value (starting from 0).
saloutos	0:083111ae2a11	2366	\param [in] SubPriority Subpriority value (starting from 0).
saloutos	0:083111ae2a11	2367	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
saloutos	0:083111ae2a11	2368	*/
saloutos	0:083111ae2a11	2369	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
saloutos	0:083111ae2a11	2370	{
saloutos	0:083111ae2a11	2371	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
saloutos	0:083111ae2a11	2372	uint32_t PreemptPriorityBits;
saloutos	0:083111ae2a11	2373	uint32_t SubPriorityBits;
saloutos	0:083111ae2a11	2374
saloutos	0:083111ae2a11	2375	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
saloutos	0:083111ae2a11	2376	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
saloutos	0:083111ae2a11	2377
saloutos	0:083111ae2a11	2378	return (
saloutos	0:083111ae2a11	2379	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
saloutos	0:083111ae2a11	2380	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
saloutos	0:083111ae2a11	2381	);
saloutos	0:083111ae2a11	2382	}
saloutos	0:083111ae2a11	2383
saloutos	0:083111ae2a11	2384
saloutos	0:083111ae2a11	2385	/**
saloutos	0:083111ae2a11	2386	\brief Decode Priority
saloutos	0:083111ae2a11	2387	\details Decodes an interrupt priority value with a given priority group to
saloutos	0:083111ae2a11	2388	preemptive priority value and subpriority value.
saloutos	0:083111ae2a11	2389	In case of a conflict between priority grouping and available
saloutos	0:083111ae2a11	2390	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
saloutos	0:083111ae2a11	2391	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
saloutos	0:083111ae2a11	2392	\param [in] PriorityGroup Used priority group.
saloutos	0:083111ae2a11	2393	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
saloutos	0:083111ae2a11	2394	\param [out] pSubPriority Subpriority value (starting from 0).
saloutos	0:083111ae2a11	2395	*/
saloutos	0:083111ae2a11	2396	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
saloutos	0:083111ae2a11	2397	{
saloutos	0:083111ae2a11	2398	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
saloutos	0:083111ae2a11	2399	uint32_t PreemptPriorityBits;
saloutos	0:083111ae2a11	2400	uint32_t SubPriorityBits;
saloutos	0:083111ae2a11	2401
saloutos	0:083111ae2a11	2402	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
saloutos	0:083111ae2a11	2403	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
saloutos	0:083111ae2a11	2404
saloutos	0:083111ae2a11	2405	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
saloutos	0:083111ae2a11	2406	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
saloutos	0:083111ae2a11	2407	}
saloutos	0:083111ae2a11	2408
saloutos	0:083111ae2a11	2409
saloutos	0:083111ae2a11	2410	/**
saloutos	0:083111ae2a11	2411	\brief Set Interrupt Vector
saloutos	0:083111ae2a11	2412	\details Sets an interrupt vector in SRAM based interrupt vector table.
saloutos	0:083111ae2a11	2413	The interrupt number can be positive to specify a device specific interrupt,
saloutos	0:083111ae2a11	2414	or negative to specify a processor exception.
saloutos	0:083111ae2a11	2415	VTOR must been relocated to SRAM before.
saloutos	0:083111ae2a11	2416	\param [in] IRQn Interrupt number
saloutos	0:083111ae2a11	2417	\param [in] vector Address of interrupt handler function
saloutos	0:083111ae2a11	2418	*/
saloutos	0:083111ae2a11	2419	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
saloutos	0:083111ae2a11	2420	{
saloutos	0:083111ae2a11	2421	uint32_t vectors = (uint32_t )SCB->VTOR;
saloutos	0:083111ae2a11	2422	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
saloutos	0:083111ae2a11	2423	}
saloutos	0:083111ae2a11	2424
saloutos	0:083111ae2a11	2425
saloutos	0:083111ae2a11	2426	/**
saloutos	0:083111ae2a11	2427	\brief Get Interrupt Vector
saloutos	0:083111ae2a11	2428	\details Reads an interrupt vector from interrupt vector table.
saloutos	0:083111ae2a11	2429	The interrupt number can be positive to specify a device specific interrupt,
saloutos	0:083111ae2a11	2430	or negative to specify a processor exception.
saloutos	0:083111ae2a11	2431	\param [in] IRQn Interrupt number.
saloutos	0:083111ae2a11	2432	\return Address of interrupt handler function
saloutos	0:083111ae2a11	2433	*/
saloutos	0:083111ae2a11	2434	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2435	{
saloutos	0:083111ae2a11	2436	uint32_t vectors = (uint32_t )SCB->VTOR;
saloutos	0:083111ae2a11	2437	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
saloutos	0:083111ae2a11	2438	}
saloutos	0:083111ae2a11	2439
saloutos	0:083111ae2a11	2440
saloutos	0:083111ae2a11	2441	/**
saloutos	0:083111ae2a11	2442	\brief System Reset
saloutos	0:083111ae2a11	2443	\details Initiates a system reset request to reset the MCU.
saloutos	0:083111ae2a11	2444	*/
saloutos	0:083111ae2a11	2445	__STATIC_INLINE void __NVIC_SystemReset(void)
saloutos	0:083111ae2a11	2446	{
saloutos	0:083111ae2a11	2447	__DSB(); /* Ensure all outstanding memory accesses included
saloutos	0:083111ae2a11	2448	buffered write are completed before reset */
saloutos	0:083111ae2a11	2449	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
saloutos	0:083111ae2a11	2450	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
saloutos	0:083111ae2a11	2451	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
saloutos	0:083111ae2a11	2452	__DSB(); /* Ensure completion of memory access */
saloutos	0:083111ae2a11	2453
saloutos	0:083111ae2a11	2454	for(;;) /* wait until reset */
saloutos	0:083111ae2a11	2455	{
saloutos	0:083111ae2a11	2456	__NOP();
saloutos	0:083111ae2a11	2457	}
saloutos	0:083111ae2a11	2458	}
saloutos	0:083111ae2a11	2459
saloutos	0:083111ae2a11	2460	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	2461	/**
saloutos	0:083111ae2a11	2462	\brief Set Priority Grouping (non-secure)
saloutos	0:083111ae2a11	2463	\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
saloutos	0:083111ae2a11	2464	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
saloutos	0:083111ae2a11	2465	Only values from 0..7 are used.
saloutos	0:083111ae2a11	2466	In case of a conflict between priority grouping and available
saloutos	0:083111ae2a11	2467	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
saloutos	0:083111ae2a11	2468	\param [in] PriorityGroup Priority grouping field.
saloutos	0:083111ae2a11	2469	*/
saloutos	0:083111ae2a11	2470	__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
saloutos	0:083111ae2a11	2471	{
saloutos	0:083111ae2a11	2472	uint32_t reg_value;
saloutos	0:083111ae2a11	2473	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
saloutos	0:083111ae2a11	2474
saloutos	0:083111ae2a11	2475	reg_value = SCB_NS->AIRCR; /* read old register configuration */
saloutos	0:083111ae2a11	2476	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
saloutos	0:083111ae2a11	2477	reg_value = (reg_value \|
saloutos	0:083111ae2a11	2478	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
saloutos	0:083111ae2a11	2479	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
saloutos	0:083111ae2a11	2480	SCB_NS->AIRCR = reg_value;
saloutos	0:083111ae2a11	2481	}
saloutos	0:083111ae2a11	2482
saloutos	0:083111ae2a11	2483
saloutos	0:083111ae2a11	2484	/**
saloutos	0:083111ae2a11	2485	\brief Get Priority Grouping (non-secure)
saloutos	0:083111ae2a11	2486	\details Reads the priority grouping field from the non-secure NVIC when in secure state.
saloutos	0:083111ae2a11	2487	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
saloutos	0:083111ae2a11	2488	*/
saloutos	0:083111ae2a11	2489	__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
saloutos	0:083111ae2a11	2490	{
saloutos	0:083111ae2a11	2491	return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
saloutos	0:083111ae2a11	2492	}
saloutos	0:083111ae2a11	2493
saloutos	0:083111ae2a11	2494
saloutos	0:083111ae2a11	2495	/**
saloutos	0:083111ae2a11	2496	\brief Enable Interrupt (non-secure)
saloutos	0:083111ae2a11	2497	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
saloutos	0:083111ae2a11	2498	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2499	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2500	*/
saloutos	0:083111ae2a11	2501	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2502	{
saloutos	0:083111ae2a11	2503	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2504	{
saloutos	0:083111ae2a11	2505	NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	2506	}
saloutos	0:083111ae2a11	2507	}
saloutos	0:083111ae2a11	2508
saloutos	0:083111ae2a11	2509
saloutos	0:083111ae2a11	2510	/**
saloutos	0:083111ae2a11	2511	\brief Get Interrupt Enable status (non-secure)
saloutos	0:083111ae2a11	2512	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
saloutos	0:083111ae2a11	2513	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2514	\return 0 Interrupt is not enabled.
saloutos	0:083111ae2a11	2515	\return 1 Interrupt is enabled.
saloutos	0:083111ae2a11	2516	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2517	*/
saloutos	0:083111ae2a11	2518	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2519	{
saloutos	0:083111ae2a11	2520	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2521	{
saloutos	0:083111ae2a11	2522	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	2523	}
saloutos	0:083111ae2a11	2524	else
saloutos	0:083111ae2a11	2525	{
saloutos	0:083111ae2a11	2526	return(0U);
saloutos	0:083111ae2a11	2527	}
saloutos	0:083111ae2a11	2528	}
saloutos	0:083111ae2a11	2529
saloutos	0:083111ae2a11	2530
saloutos	0:083111ae2a11	2531	/**
saloutos	0:083111ae2a11	2532	\brief Disable Interrupt (non-secure)
saloutos	0:083111ae2a11	2533	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
saloutos	0:083111ae2a11	2534	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2535	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2536	*/
saloutos	0:083111ae2a11	2537	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2538	{
saloutos	0:083111ae2a11	2539	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2540	{
saloutos	0:083111ae2a11	2541	NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	2542	}
saloutos	0:083111ae2a11	2543	}
saloutos	0:083111ae2a11	2544
saloutos	0:083111ae2a11	2545
saloutos	0:083111ae2a11	2546	/**
saloutos	0:083111ae2a11	2547	\brief Get Pending Interrupt (non-secure)
saloutos	0:083111ae2a11	2548	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
saloutos	0:083111ae2a11	2549	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2550	\return 0 Interrupt status is not pending.
saloutos	0:083111ae2a11	2551	\return 1 Interrupt status is pending.
saloutos	0:083111ae2a11	2552	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2553	*/
saloutos	0:083111ae2a11	2554	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2555	{
saloutos	0:083111ae2a11	2556	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2557	{
saloutos	0:083111ae2a11	2558	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	2559	}
saloutos	0:083111ae2a11	2560	}
saloutos	0:083111ae2a11	2561
saloutos	0:083111ae2a11	2562
saloutos	0:083111ae2a11	2563	/**
saloutos	0:083111ae2a11	2564	\brief Set Pending Interrupt (non-secure)
saloutos	0:083111ae2a11	2565	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
saloutos	0:083111ae2a11	2566	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2567	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2568	*/
saloutos	0:083111ae2a11	2569	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2570	{
saloutos	0:083111ae2a11	2571	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2572	{
saloutos	0:083111ae2a11	2573	NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	2574	}
saloutos	0:083111ae2a11	2575	}
saloutos	0:083111ae2a11	2576
saloutos	0:083111ae2a11	2577
saloutos	0:083111ae2a11	2578	/**
saloutos	0:083111ae2a11	2579	\brief Clear Pending Interrupt (non-secure)
saloutos	0:083111ae2a11	2580	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
saloutos	0:083111ae2a11	2581	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2582	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2583	*/
saloutos	0:083111ae2a11	2584	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2585	{
saloutos	0:083111ae2a11	2586	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2587	{
saloutos	0:083111ae2a11	2588	NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	2589	}
saloutos	0:083111ae2a11	2590	}
saloutos	0:083111ae2a11	2591
saloutos	0:083111ae2a11	2592
saloutos	0:083111ae2a11	2593	/**
saloutos	0:083111ae2a11	2594	\brief Get Active Interrupt (non-secure)
saloutos	0:083111ae2a11	2595	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
saloutos	0:083111ae2a11	2596	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	2597	\return 0 Interrupt status is not active.
saloutos	0:083111ae2a11	2598	\return 1 Interrupt status is active.
saloutos	0:083111ae2a11	2599	\note IRQn must not be negative.
saloutos	0:083111ae2a11	2600	*/
saloutos	0:083111ae2a11	2601	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2602	{
saloutos	0:083111ae2a11	2603	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2604	{
saloutos	0:083111ae2a11	2605	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	2606	}
saloutos	0:083111ae2a11	2607	else
saloutos	0:083111ae2a11	2608	{
saloutos	0:083111ae2a11	2609	return(0U);
saloutos	0:083111ae2a11	2610	}
saloutos	0:083111ae2a11	2611	}
saloutos	0:083111ae2a11	2612
saloutos	0:083111ae2a11	2613
saloutos	0:083111ae2a11	2614	/**
saloutos	0:083111ae2a11	2615	\brief Set Interrupt Priority (non-secure)
saloutos	0:083111ae2a11	2616	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
saloutos	0:083111ae2a11	2617	The interrupt number can be positive to specify a device specific interrupt,
saloutos	0:083111ae2a11	2618	or negative to specify a processor exception.
saloutos	0:083111ae2a11	2619	\param [in] IRQn Interrupt number.
saloutos	0:083111ae2a11	2620	\param [in] priority Priority to set.
saloutos	0:083111ae2a11	2621	\note The priority cannot be set for every non-secure processor exception.
saloutos	0:083111ae2a11	2622	*/
saloutos	0:083111ae2a11	2623	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
saloutos	0:083111ae2a11	2624	{
saloutos	0:083111ae2a11	2625	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2626	{
saloutos	0:083111ae2a11	2627	NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
saloutos	0:083111ae2a11	2628	}
saloutos	0:083111ae2a11	2629	else
saloutos	0:083111ae2a11	2630	{
saloutos	0:083111ae2a11	2631	SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
saloutos	0:083111ae2a11	2632	}
saloutos	0:083111ae2a11	2633	}
saloutos	0:083111ae2a11	2634
saloutos	0:083111ae2a11	2635
saloutos	0:083111ae2a11	2636	/**
saloutos	0:083111ae2a11	2637	\brief Get Interrupt Priority (non-secure)
saloutos	0:083111ae2a11	2638	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
saloutos	0:083111ae2a11	2639	The interrupt number can be positive to specify a device specific interrupt,
saloutos	0:083111ae2a11	2640	or negative to specify a processor exception.
saloutos	0:083111ae2a11	2641	\param [in] IRQn Interrupt number.
saloutos	0:083111ae2a11	2642	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
saloutos	0:083111ae2a11	2643	*/
saloutos	0:083111ae2a11	2644	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	2645	{
saloutos	0:083111ae2a11	2646
saloutos	0:083111ae2a11	2647	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	2648	{
saloutos	0:083111ae2a11	2649	return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
saloutos	0:083111ae2a11	2650	}
saloutos	0:083111ae2a11	2651	else
saloutos	0:083111ae2a11	2652	{
saloutos	0:083111ae2a11	2653	return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
saloutos	0:083111ae2a11	2654	}
saloutos	0:083111ae2a11	2655	}
saloutos	0:083111ae2a11	2656	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
saloutos	0:083111ae2a11	2657
saloutos	0:083111ae2a11	2658	/@} end of CMSIS_Core_NVICFunctions /
saloutos	0:083111ae2a11	2659
saloutos	0:083111ae2a11	2660
saloutos	0:083111ae2a11	2661	/* ########################## FPU functions #################################### */
saloutos	0:083111ae2a11	2662	/**
saloutos	0:083111ae2a11	2663	\ingroup CMSIS_Core_FunctionInterface
saloutos	0:083111ae2a11	2664	\defgroup CMSIS_Core_FpuFunctions FPU Functions
saloutos	0:083111ae2a11	2665	\brief Function that provides FPU type.
saloutos	0:083111ae2a11	2666	@{
saloutos	0:083111ae2a11	2667	*/
saloutos	0:083111ae2a11	2668
saloutos	0:083111ae2a11	2669	/**
saloutos	0:083111ae2a11	2670	\brief get FPU type
saloutos	0:083111ae2a11	2671	\details returns the FPU type
saloutos	0:083111ae2a11	2672	\returns
saloutos	0:083111ae2a11	2673	- \b 0: No FPU
saloutos	0:083111ae2a11	2674	- \b 1: Single precision FPU
saloutos	0:083111ae2a11	2675	- \b 2: Double + Single precision FPU
saloutos	0:083111ae2a11	2676	*/
saloutos	0:083111ae2a11	2677	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
saloutos	0:083111ae2a11	2678	{
saloutos	0:083111ae2a11	2679	uint32_t mvfr0;
saloutos	0:083111ae2a11	2680
saloutos	0:083111ae2a11	2681	mvfr0 = FPU->MVFR0;
saloutos	0:083111ae2a11	2682	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
saloutos	0:083111ae2a11	2683	{
saloutos	0:083111ae2a11	2684	return 2U; /* Double + Single precision FPU */
saloutos	0:083111ae2a11	2685	}
saloutos	0:083111ae2a11	2686	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
saloutos	0:083111ae2a11	2687	{
saloutos	0:083111ae2a11	2688	return 1U; /* Single precision FPU */
saloutos	0:083111ae2a11	2689	}
saloutos	0:083111ae2a11	2690	else
saloutos	0:083111ae2a11	2691	{
saloutos	0:083111ae2a11	2692	return 0U; /* No FPU */
saloutos	0:083111ae2a11	2693	}
saloutos	0:083111ae2a11	2694	}
saloutos	0:083111ae2a11	2695
saloutos	0:083111ae2a11	2696
saloutos	0:083111ae2a11	2697	/@} end of CMSIS_Core_FpuFunctions /
saloutos	0:083111ae2a11	2698
saloutos	0:083111ae2a11	2699
saloutos	0:083111ae2a11	2700
saloutos	0:083111ae2a11	2701	/* ########################## SAU functions #################################### */
saloutos	0:083111ae2a11	2702	/**
saloutos	0:083111ae2a11	2703	\ingroup CMSIS_Core_FunctionInterface
saloutos	0:083111ae2a11	2704	\defgroup CMSIS_Core_SAUFunctions SAU Functions
saloutos	0:083111ae2a11	2705	\brief Functions that configure the SAU.
saloutos	0:083111ae2a11	2706	@{
saloutos	0:083111ae2a11	2707	*/
saloutos	0:083111ae2a11	2708
saloutos	0:083111ae2a11	2709	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	2710
saloutos	0:083111ae2a11	2711	/**
saloutos	0:083111ae2a11	2712	\brief Enable SAU
saloutos	0:083111ae2a11	2713	\details Enables the Security Attribution Unit (SAU).
saloutos	0:083111ae2a11	2714	*/
saloutos	0:083111ae2a11	2715	__STATIC_INLINE void TZ_SAU_Enable(void)
saloutos	0:083111ae2a11	2716	{
saloutos	0:083111ae2a11	2717	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
saloutos	0:083111ae2a11	2718	}
saloutos	0:083111ae2a11	2719
saloutos	0:083111ae2a11	2720
saloutos	0:083111ae2a11	2721
saloutos	0:083111ae2a11	2722	/**
saloutos	0:083111ae2a11	2723	\brief Disable SAU
saloutos	0:083111ae2a11	2724	\details Disables the Security Attribution Unit (SAU).
saloutos	0:083111ae2a11	2725	*/
saloutos	0:083111ae2a11	2726	__STATIC_INLINE void TZ_SAU_Disable(void)
saloutos	0:083111ae2a11	2727	{
saloutos	0:083111ae2a11	2728	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
saloutos	0:083111ae2a11	2729	}
saloutos	0:083111ae2a11	2730
saloutos	0:083111ae2a11	2731	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
saloutos	0:083111ae2a11	2732
saloutos	0:083111ae2a11	2733	/@} end of CMSIS_Core_SAUFunctions /
saloutos	0:083111ae2a11	2734
saloutos	0:083111ae2a11	2735
saloutos	0:083111ae2a11	2736
saloutos	0:083111ae2a11	2737
saloutos	0:083111ae2a11	2738	/* ################################## SysTick function ############################################ */
saloutos	0:083111ae2a11	2739	/**
saloutos	0:083111ae2a11	2740	\ingroup CMSIS_Core_FunctionInterface
saloutos	0:083111ae2a11	2741	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
saloutos	0:083111ae2a11	2742	\brief Functions that configure the System.
saloutos	0:083111ae2a11	2743	@{
saloutos	0:083111ae2a11	2744	*/
saloutos	0:083111ae2a11	2745
saloutos	0:083111ae2a11	2746	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
saloutos	0:083111ae2a11	2747
saloutos	0:083111ae2a11	2748	/**
saloutos	0:083111ae2a11	2749	\brief System Tick Configuration
saloutos	0:083111ae2a11	2750	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
saloutos	0:083111ae2a11	2751	Counter is in free running mode to generate periodic interrupts.
saloutos	0:083111ae2a11	2752	\param [in] ticks Number of ticks between two interrupts.
saloutos	0:083111ae2a11	2753	\return 0 Function succeeded.
saloutos	0:083111ae2a11	2754	\return 1 Function failed.
saloutos	0:083111ae2a11	2755	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
saloutos	0:083111ae2a11	2756	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
saloutos	0:083111ae2a11	2757	must contain a vendor-specific implementation of this function.
saloutos	0:083111ae2a11	2758	*/
saloutos	0:083111ae2a11	2759	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
saloutos	0:083111ae2a11	2760	{
saloutos	0:083111ae2a11	2761	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
saloutos	0:083111ae2a11	2762	{
saloutos	0:083111ae2a11	2763	return (1UL); /* Reload value impossible */
saloutos	0:083111ae2a11	2764	}
saloutos	0:083111ae2a11	2765
saloutos	0:083111ae2a11	2766	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
saloutos	0:083111ae2a11	2767	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
saloutos	0:083111ae2a11	2768	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
saloutos	0:083111ae2a11	2769	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
saloutos	0:083111ae2a11	2770	SysTick_CTRL_TICKINT_Msk \|
saloutos	0:083111ae2a11	2771	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
saloutos	0:083111ae2a11	2772	return (0UL); /* Function successful */
saloutos	0:083111ae2a11	2773	}
saloutos	0:083111ae2a11	2774
saloutos	0:083111ae2a11	2775	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	2776	/**
saloutos	0:083111ae2a11	2777	\brief System Tick Configuration (non-secure)
saloutos	0:083111ae2a11	2778	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
saloutos	0:083111ae2a11	2779	Counter is in free running mode to generate periodic interrupts.
saloutos	0:083111ae2a11	2780	\param [in] ticks Number of ticks between two interrupts.
saloutos	0:083111ae2a11	2781	\return 0 Function succeeded.
saloutos	0:083111ae2a11	2782	\return 1 Function failed.
saloutos	0:083111ae2a11	2783	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
saloutos	0:083111ae2a11	2784	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
saloutos	0:083111ae2a11	2785	must contain a vendor-specific implementation of this function.
saloutos	0:083111ae2a11	2786
saloutos	0:083111ae2a11	2787	*/
saloutos	0:083111ae2a11	2788	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
saloutos	0:083111ae2a11	2789	{
saloutos	0:083111ae2a11	2790	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
saloutos	0:083111ae2a11	2791	{
saloutos	0:083111ae2a11	2792	return (1UL); /* Reload value impossible */
saloutos	0:083111ae2a11	2793	}
saloutos	0:083111ae2a11	2794
saloutos	0:083111ae2a11	2795	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
saloutos	0:083111ae2a11	2796	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
saloutos	0:083111ae2a11	2797	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
saloutos	0:083111ae2a11	2798	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
saloutos	0:083111ae2a11	2799	SysTick_CTRL_TICKINT_Msk \|
saloutos	0:083111ae2a11	2800	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
saloutos	0:083111ae2a11	2801	return (0UL); /* Function successful */
saloutos	0:083111ae2a11	2802	}
saloutos	0:083111ae2a11	2803	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
saloutos	0:083111ae2a11	2804
saloutos	0:083111ae2a11	2805	#endif
saloutos	0:083111ae2a11	2806
saloutos	0:083111ae2a11	2807	/@} end of CMSIS_Core_SysTickFunctions /
saloutos	0:083111ae2a11	2808
saloutos	0:083111ae2a11	2809
saloutos	0:083111ae2a11	2810
saloutos	0:083111ae2a11	2811	/* ##################################### Debug In/Output function ########################################### */
saloutos	0:083111ae2a11	2812	/**
saloutos	0:083111ae2a11	2813	\ingroup CMSIS_Core_FunctionInterface
saloutos	0:083111ae2a11	2814	\defgroup CMSIS_core_DebugFunctions ITM Functions
saloutos	0:083111ae2a11	2815	\brief Functions that access the ITM debug interface.
saloutos	0:083111ae2a11	2816	@{
saloutos	0:083111ae2a11	2817	*/
saloutos	0:083111ae2a11	2818
saloutos	0:083111ae2a11	2819	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
saloutos	0:083111ae2a11	2820	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
saloutos	0:083111ae2a11	2821
saloutos	0:083111ae2a11	2822
saloutos	0:083111ae2a11	2823	/**
saloutos	0:083111ae2a11	2824	\brief ITM Send Character
saloutos	0:083111ae2a11	2825	\details Transmits a character via the ITM channel 0, and
saloutos	0:083111ae2a11	2826	\li Just returns when no debugger is connected that has booked the output.
saloutos	0:083111ae2a11	2827	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
saloutos	0:083111ae2a11	2828	\param [in] ch Character to transmit.
saloutos	0:083111ae2a11	2829	\returns Character to transmit.
saloutos	0:083111ae2a11	2830	*/
saloutos	0:083111ae2a11	2831	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
saloutos	0:083111ae2a11	2832	{
saloutos	0:083111ae2a11	2833	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
saloutos	0:083111ae2a11	2834	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
saloutos	0:083111ae2a11	2835	{
saloutos	0:083111ae2a11	2836	while (ITM->PORT[0U].u32 == 0UL)
saloutos	0:083111ae2a11	2837	{
saloutos	0:083111ae2a11	2838	__NOP();
saloutos	0:083111ae2a11	2839	}
saloutos	0:083111ae2a11	2840	ITM->PORT[0U].u8 = (uint8_t)ch;
saloutos	0:083111ae2a11	2841	}
saloutos	0:083111ae2a11	2842	return (ch);
saloutos	0:083111ae2a11	2843	}
saloutos	0:083111ae2a11	2844
saloutos	0:083111ae2a11	2845
saloutos	0:083111ae2a11	2846	/**
saloutos	0:083111ae2a11	2847	\brief ITM Receive Character
saloutos	0:083111ae2a11	2848	\details Inputs a character via the external variable \ref ITM_RxBuffer.
saloutos	0:083111ae2a11	2849	\return Received character.
saloutos	0:083111ae2a11	2850	\return -1 No character pending.
saloutos	0:083111ae2a11	2851	*/
saloutos	0:083111ae2a11	2852	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
saloutos	0:083111ae2a11	2853	{
saloutos	0:083111ae2a11	2854	int32_t ch = -1; /* no character available */
saloutos	0:083111ae2a11	2855
saloutos	0:083111ae2a11	2856	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
saloutos	0:083111ae2a11	2857	{
saloutos	0:083111ae2a11	2858	ch = ITM_RxBuffer;
saloutos	0:083111ae2a11	2859	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
saloutos	0:083111ae2a11	2860	}
saloutos	0:083111ae2a11	2861
saloutos	0:083111ae2a11	2862	return (ch);
saloutos	0:083111ae2a11	2863	}
saloutos	0:083111ae2a11	2864
saloutos	0:083111ae2a11	2865
saloutos	0:083111ae2a11	2866	/**
saloutos	0:083111ae2a11	2867	\brief ITM Check Character
saloutos	0:083111ae2a11	2868	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
saloutos	0:083111ae2a11	2869	\return 0 No character available.
saloutos	0:083111ae2a11	2870	\return 1 Character available.
saloutos	0:083111ae2a11	2871	*/
saloutos	0:083111ae2a11	2872	__STATIC_INLINE int32_t ITM_CheckChar (void)
saloutos	0:083111ae2a11	2873	{
saloutos	0:083111ae2a11	2874
saloutos	0:083111ae2a11	2875	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
saloutos	0:083111ae2a11	2876	{
saloutos	0:083111ae2a11	2877	return (0); /* no character available */
saloutos	0:083111ae2a11	2878	}
saloutos	0:083111ae2a11	2879	else
saloutos	0:083111ae2a11	2880	{
saloutos	0:083111ae2a11	2881	return (1); /* character available */
saloutos	0:083111ae2a11	2882	}
saloutos	0:083111ae2a11	2883	}
saloutos	0:083111ae2a11	2884
saloutos	0:083111ae2a11	2885	/@} end of CMSIS_core_DebugFunctions /
saloutos	0:083111ae2a11	2886
saloutos	0:083111ae2a11	2887
saloutos	0:083111ae2a11	2888
saloutos	0:083111ae2a11	2889
saloutos	0:083111ae2a11	2890	#ifdef __cplusplus
saloutos	0:083111ae2a11	2891	}
saloutos	0:083111ae2a11	2892	#endif
saloutos	0:083111ae2a11	2893
saloutos	0:083111ae2a11	2894	#endif /* __CORE_CM33_H_DEPENDANT */
saloutos	0:083111ae2a11	2895
saloutos	0:083111ae2a11	2896	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	09 Mar 2021
Imports:	13
Forks:	0
Commits:	4
Dependents:	4
Dependencies:	0
Followers:	1

cmsis/core_cm33.h@0:083111ae2a11, 2020-11-26 (annotated)

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