Aditya Mehrotra / mbed-dev

Biomimetics MBED Library w/ Added Support for CAN3

Dependents:   CAN_TEST SPIne_Plus_DYNO_SENSORS SPIne_Plus_v2 SPIne_Plus_Dyno_v2

cmsis/core_cm3.h@0:083111ae2a11, 2020-11-26 (annotated)

Committer:
saloutos
Date:
Thu Nov 26 04:08:56 2020 +0000
Revision:
0:083111ae2a11
first commit of leaned mbed dev lib

Who changed what in which revision?

UserRevisionLine numberNew contents of line
saloutos 0:083111ae2a11 1 /**************************************************************************//**
saloutos 0:083111ae2a11 2 * @file core_cm3.h
saloutos 0:083111ae2a11 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
saloutos 0:083111ae2a11 4 * @version V5.0.2
saloutos 0:083111ae2a11 5 * @date 13. February 2017
saloutos 0:083111ae2a11 6 ******************************************************************************/
saloutos 0:083111ae2a11 7 /*
saloutos 0:083111ae2a11 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
saloutos 0:083111ae2a11 9 *
saloutos 0:083111ae2a11 10 * SPDX-License-Identifier: Apache-2.0
saloutos 0:083111ae2a11 11 *
saloutos 0:083111ae2a11 12 * Licensed under the Apache License, Version 2.0 (the License); you may
saloutos 0:083111ae2a11 13 * not use this file except in compliance with the License.
saloutos 0:083111ae2a11 14 * You may obtain a copy of the License at
saloutos 0:083111ae2a11 15 *
saloutos 0:083111ae2a11 16 * www.apache.org/licenses/LICENSE-2.0
saloutos 0:083111ae2a11 17 *
saloutos 0:083111ae2a11 18 * Unless required by applicable law or agreed to in writing, software
saloutos 0:083111ae2a11 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
saloutos 0:083111ae2a11 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
saloutos 0:083111ae2a11 21 * See the License for the specific language governing permissions and
saloutos 0:083111ae2a11 22 * limitations under the License.
saloutos 0:083111ae2a11 23 */
saloutos 0:083111ae2a11 24
saloutos 0:083111ae2a11 25 #if defined ( __ICCARM__ )
saloutos 0:083111ae2a11 26 #pragma system_include /* treat file as system include file for MISRA check */
saloutos 0:083111ae2a11 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
saloutos 0:083111ae2a11 28 #pragma clang system_header /* treat file as system include file */
saloutos 0:083111ae2a11 29 #endif
saloutos 0:083111ae2a11 30
saloutos 0:083111ae2a11 31 #ifndef __CORE_CM3_H_GENERIC
saloutos 0:083111ae2a11 32 #define __CORE_CM3_H_GENERIC
saloutos 0:083111ae2a11 33
saloutos 0:083111ae2a11 34 #include <stdint.h>
saloutos 0:083111ae2a11 35
saloutos 0:083111ae2a11 36 #ifdef __cplusplus
saloutos 0:083111ae2a11 37 extern "C" {
saloutos 0:083111ae2a11 38 #endif
saloutos 0:083111ae2a11 39
saloutos 0:083111ae2a11 40 /**
saloutos 0:083111ae2a11 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
saloutos 0:083111ae2a11 42 CMSIS violates the following MISRA-C:2004 rules:
saloutos 0:083111ae2a11 43
saloutos 0:083111ae2a11 44 \li Required Rule 8.5, object/function definition in header file.<br>
saloutos 0:083111ae2a11 45 Function definitions in header files are used to allow 'inlining'.
saloutos 0:083111ae2a11 46
saloutos 0:083111ae2a11 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
saloutos 0:083111ae2a11 48 Unions are used for effective representation of core registers.
saloutos 0:083111ae2a11 49
saloutos 0:083111ae2a11 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
saloutos 0:083111ae2a11 51 Function-like macros are used to allow more efficient code.
saloutos 0:083111ae2a11 52 */
saloutos 0:083111ae2a11 53
saloutos 0:083111ae2a11 54
saloutos 0:083111ae2a11 55 /*******************************************************************************
saloutos 0:083111ae2a11 56 * CMSIS definitions
saloutos 0:083111ae2a11 57 ******************************************************************************/
saloutos 0:083111ae2a11 58 /**
saloutos 0:083111ae2a11 59 \ingroup Cortex_M3
saloutos 0:083111ae2a11 60 @{
saloutos 0:083111ae2a11 61 */
saloutos 0:083111ae2a11 62
saloutos 0:083111ae2a11 63 /* CMSIS CM3 definitions */
saloutos 0:083111ae2a11 64 #define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
saloutos 0:083111ae2a11 65 #define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
saloutos 0:083111ae2a11 66 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
saloutos 0:083111ae2a11 67 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
saloutos 0:083111ae2a11 68
saloutos 0:083111ae2a11 69 #define __CORTEX_M (3U) /*!< Cortex-M Core */
saloutos 0:083111ae2a11 70
saloutos 0:083111ae2a11 71 /** __FPU_USED indicates whether an FPU is used or not.
saloutos 0:083111ae2a11 72 This core does not support an FPU at all
saloutos 0:083111ae2a11 73 */
saloutos 0:083111ae2a11 74 #define __FPU_USED 0U
saloutos 0:083111ae2a11 75
saloutos 0:083111ae2a11 76 #if defined ( __CC_ARM )
saloutos 0:083111ae2a11 77 #if defined __TARGET_FPU_VFP
saloutos 0:083111ae2a11 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 79 #endif
saloutos 0:083111ae2a11 80
saloutos 0:083111ae2a11 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
saloutos 0:083111ae2a11 82 #if defined __ARM_PCS_VFP
saloutos 0:083111ae2a11 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 84 #endif
saloutos 0:083111ae2a11 85
saloutos 0:083111ae2a11 86 #elif defined ( __GNUC__ )
saloutos 0:083111ae2a11 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
saloutos 0:083111ae2a11 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 89 #endif
saloutos 0:083111ae2a11 90
saloutos 0:083111ae2a11 91 #elif defined ( __ICCARM__ )
saloutos 0:083111ae2a11 92 #if defined __ARMVFP__
saloutos 0:083111ae2a11 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 94 #endif
saloutos 0:083111ae2a11 95
saloutos 0:083111ae2a11 96 #elif defined ( __TI_ARM__ )
saloutos 0:083111ae2a11 97 #if defined __TI_VFP_SUPPORT__
saloutos 0:083111ae2a11 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 99 #endif
saloutos 0:083111ae2a11 100
saloutos 0:083111ae2a11 101 #elif defined ( __TASKING__ )
saloutos 0:083111ae2a11 102 #if defined __FPU_VFP__
saloutos 0:083111ae2a11 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 104 #endif
saloutos 0:083111ae2a11 105
saloutos 0:083111ae2a11 106 #elif defined ( __CSMC__ )
saloutos 0:083111ae2a11 107 #if ( __CSMC__ & 0x400U)
saloutos 0:083111ae2a11 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 109 #endif
saloutos 0:083111ae2a11 110
saloutos 0:083111ae2a11 111 #endif
saloutos 0:083111ae2a11 112
saloutos 0:083111ae2a11 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
saloutos 0:083111ae2a11 114
saloutos 0:083111ae2a11 115
saloutos 0:083111ae2a11 116 #ifdef __cplusplus
saloutos 0:083111ae2a11 117 }
saloutos 0:083111ae2a11 118 #endif
saloutos 0:083111ae2a11 119
saloutos 0:083111ae2a11 120 #endif /* __CORE_CM3_H_GENERIC */
saloutos 0:083111ae2a11 121
saloutos 0:083111ae2a11 122 #ifndef __CMSIS_GENERIC
saloutos 0:083111ae2a11 123
saloutos 0:083111ae2a11 124 #ifndef __CORE_CM3_H_DEPENDANT
saloutos 0:083111ae2a11 125 #define __CORE_CM3_H_DEPENDANT
saloutos 0:083111ae2a11 126
saloutos 0:083111ae2a11 127 #ifdef __cplusplus
saloutos 0:083111ae2a11 128 extern "C" {
saloutos 0:083111ae2a11 129 #endif
saloutos 0:083111ae2a11 130
saloutos 0:083111ae2a11 131 /* check device defines and use defaults */
saloutos 0:083111ae2a11 132 #if defined __CHECK_DEVICE_DEFINES
saloutos 0:083111ae2a11 133 #ifndef __CM3_REV
saloutos 0:083111ae2a11 134 #define __CM3_REV 0x0200U
saloutos 0:083111ae2a11 135 #warning "__CM3_REV not defined in device header file; using default!"
saloutos 0:083111ae2a11 136 #endif
saloutos 0:083111ae2a11 137
saloutos 0:083111ae2a11 138 #ifndef __MPU_PRESENT
saloutos 0:083111ae2a11 139 #define __MPU_PRESENT 0U
saloutos 0:083111ae2a11 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
saloutos 0:083111ae2a11 141 #endif
saloutos 0:083111ae2a11 142
saloutos 0:083111ae2a11 143 #ifndef __NVIC_PRIO_BITS
saloutos 0:083111ae2a11 144 #define __NVIC_PRIO_BITS 3U
saloutos 0:083111ae2a11 145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
saloutos 0:083111ae2a11 146 #endif
saloutos 0:083111ae2a11 147
saloutos 0:083111ae2a11 148 #ifndef __Vendor_SysTickConfig
saloutos 0:083111ae2a11 149 #define __Vendor_SysTickConfig 0U
saloutos 0:083111ae2a11 150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
saloutos 0:083111ae2a11 151 #endif
saloutos 0:083111ae2a11 152 #endif
saloutos 0:083111ae2a11 153
saloutos 0:083111ae2a11 154 /* IO definitions (access restrictions to peripheral registers) */
saloutos 0:083111ae2a11 155 /**
saloutos 0:083111ae2a11 156 \defgroup CMSIS_glob_defs CMSIS Global Defines
saloutos 0:083111ae2a11 157
saloutos 0:083111ae2a11 158 <strong>IO Type Qualifiers</strong> are used
saloutos 0:083111ae2a11 159 \li to specify the access to peripheral variables.
saloutos 0:083111ae2a11 160 \li for automatic generation of peripheral register debug information.
saloutos 0:083111ae2a11 161 */
saloutos 0:083111ae2a11 162 #ifdef __cplusplus
saloutos 0:083111ae2a11 163 #define __I volatile /*!< Defines 'read only' permissions */
saloutos 0:083111ae2a11 164 #else
saloutos 0:083111ae2a11 165 #define __I volatile const /*!< Defines 'read only' permissions */
saloutos 0:083111ae2a11 166 #endif
saloutos 0:083111ae2a11 167 #define __O volatile /*!< Defines 'write only' permissions */
saloutos 0:083111ae2a11 168 #define __IO volatile /*!< Defines 'read / write' permissions */
saloutos 0:083111ae2a11 169
saloutos 0:083111ae2a11 170 /* following defines should be used for structure members */
saloutos 0:083111ae2a11 171 #define __IM volatile const /*! Defines 'read only' structure member permissions */
saloutos 0:083111ae2a11 172 #define __OM volatile /*! Defines 'write only' structure member permissions */
saloutos 0:083111ae2a11 173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
saloutos 0:083111ae2a11 174
saloutos 0:083111ae2a11 175 /*@} end of group Cortex_M3 */
saloutos 0:083111ae2a11 176
saloutos 0:083111ae2a11 177
saloutos 0:083111ae2a11 178
saloutos 0:083111ae2a11 179 /*******************************************************************************
saloutos 0:083111ae2a11 180 * Register Abstraction
saloutos 0:083111ae2a11 181 Core Register contain:
saloutos 0:083111ae2a11 182 - Core Register
saloutos 0:083111ae2a11 183 - Core NVIC Register
saloutos 0:083111ae2a11 184 - Core SCB Register
saloutos 0:083111ae2a11 185 - Core SysTick Register
saloutos 0:083111ae2a11 186 - Core Debug Register
saloutos 0:083111ae2a11 187 - Core MPU Register
saloutos 0:083111ae2a11 188 ******************************************************************************/
saloutos 0:083111ae2a11 189 /**
saloutos 0:083111ae2a11 190 \defgroup CMSIS_core_register Defines and Type Definitions
saloutos 0:083111ae2a11 191 \brief Type definitions and defines for Cortex-M processor based devices.
saloutos 0:083111ae2a11 192 */
saloutos 0:083111ae2a11 193
saloutos 0:083111ae2a11 194 /**
saloutos 0:083111ae2a11 195 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 196 \defgroup CMSIS_CORE Status and Control Registers
saloutos 0:083111ae2a11 197 \brief Core Register type definitions.
saloutos 0:083111ae2a11 198 @{
saloutos 0:083111ae2a11 199 */
saloutos 0:083111ae2a11 200
saloutos 0:083111ae2a11 201 /**
saloutos 0:083111ae2a11 202 \brief Union type to access the Application Program Status Register (APSR).
saloutos 0:083111ae2a11 203 */
saloutos 0:083111ae2a11 204 typedef union
saloutos 0:083111ae2a11 205 {
saloutos 0:083111ae2a11 206 struct
saloutos 0:083111ae2a11 207 {
saloutos 0:083111ae2a11 208 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
saloutos 0:083111ae2a11 209 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
saloutos 0:083111ae2a11 210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
saloutos 0:083111ae2a11 211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
saloutos 0:083111ae2a11 212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
saloutos 0:083111ae2a11 213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
saloutos 0:083111ae2a11 214 } b; /*!< Structure used for bit access */
saloutos 0:083111ae2a11 215 uint32_t w; /*!< Type used for word access */
saloutos 0:083111ae2a11 216 } APSR_Type;
saloutos 0:083111ae2a11 217
saloutos 0:083111ae2a11 218 /* APSR Register Definitions */
saloutos 0:083111ae2a11 219 #define APSR_N_Pos 31U /*!< APSR: N Position */
saloutos 0:083111ae2a11 220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
saloutos 0:083111ae2a11 221
saloutos 0:083111ae2a11 222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
saloutos 0:083111ae2a11 223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
saloutos 0:083111ae2a11 224
saloutos 0:083111ae2a11 225 #define APSR_C_Pos 29U /*!< APSR: C Position */
saloutos 0:083111ae2a11 226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
saloutos 0:083111ae2a11 227
saloutos 0:083111ae2a11 228 #define APSR_V_Pos 28U /*!< APSR: V Position */
saloutos 0:083111ae2a11 229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
saloutos 0:083111ae2a11 230
saloutos 0:083111ae2a11 231 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
saloutos 0:083111ae2a11 232 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
saloutos 0:083111ae2a11 233
saloutos 0:083111ae2a11 234
saloutos 0:083111ae2a11 235 /**
saloutos 0:083111ae2a11 236 \brief Union type to access the Interrupt Program Status Register (IPSR).
saloutos 0:083111ae2a11 237 */
saloutos 0:083111ae2a11 238 typedef union
saloutos 0:083111ae2a11 239 {
saloutos 0:083111ae2a11 240 struct
saloutos 0:083111ae2a11 241 {
saloutos 0:083111ae2a11 242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
saloutos 0:083111ae2a11 243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
saloutos 0:083111ae2a11 244 } b; /*!< Structure used for bit access */
saloutos 0:083111ae2a11 245 uint32_t w; /*!< Type used for word access */
saloutos 0:083111ae2a11 246 } IPSR_Type;
saloutos 0:083111ae2a11 247
saloutos 0:083111ae2a11 248 /* IPSR Register Definitions */
saloutos 0:083111ae2a11 249 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
saloutos 0:083111ae2a11 250 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
saloutos 0:083111ae2a11 251
saloutos 0:083111ae2a11 252
saloutos 0:083111ae2a11 253 /**
saloutos 0:083111ae2a11 254 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
saloutos 0:083111ae2a11 255 */
saloutos 0:083111ae2a11 256 typedef union
saloutos 0:083111ae2a11 257 {
saloutos 0:083111ae2a11 258 struct
saloutos 0:083111ae2a11 259 {
saloutos 0:083111ae2a11 260 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
saloutos 0:083111ae2a11 261 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
saloutos 0:083111ae2a11 262 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
saloutos 0:083111ae2a11 263 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
saloutos 0:083111ae2a11 264 uint32_t T:1; /*!< bit: 24 Thumb bit */
saloutos 0:083111ae2a11 265 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
saloutos 0:083111ae2a11 266 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
saloutos 0:083111ae2a11 267 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
saloutos 0:083111ae2a11 268 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
saloutos 0:083111ae2a11 269 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
saloutos 0:083111ae2a11 270 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
saloutos 0:083111ae2a11 271 } b; /*!< Structure used for bit access */
saloutos 0:083111ae2a11 272 uint32_t w; /*!< Type used for word access */
saloutos 0:083111ae2a11 273 } xPSR_Type;
saloutos 0:083111ae2a11 274
saloutos 0:083111ae2a11 275 /* xPSR Register Definitions */
saloutos 0:083111ae2a11 276 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
saloutos 0:083111ae2a11 277 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
saloutos 0:083111ae2a11 278
saloutos 0:083111ae2a11 279 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
saloutos 0:083111ae2a11 280 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
saloutos 0:083111ae2a11 281
saloutos 0:083111ae2a11 282 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
saloutos 0:083111ae2a11 283 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
saloutos 0:083111ae2a11 284
saloutos 0:083111ae2a11 285 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
saloutos 0:083111ae2a11 286 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
saloutos 0:083111ae2a11 287
saloutos 0:083111ae2a11 288 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
saloutos 0:083111ae2a11 289 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
saloutos 0:083111ae2a11 290
saloutos 0:083111ae2a11 291 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
saloutos 0:083111ae2a11 292 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
saloutos 0:083111ae2a11 293
saloutos 0:083111ae2a11 294 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
saloutos 0:083111ae2a11 295 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
saloutos 0:083111ae2a11 296
saloutos 0:083111ae2a11 297 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
saloutos 0:083111ae2a11 298 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
saloutos 0:083111ae2a11 299
saloutos 0:083111ae2a11 300 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
saloutos 0:083111ae2a11 301 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
saloutos 0:083111ae2a11 302
saloutos 0:083111ae2a11 303
saloutos 0:083111ae2a11 304 /**
saloutos 0:083111ae2a11 305 \brief Union type to access the Control Registers (CONTROL).
saloutos 0:083111ae2a11 306 */
saloutos 0:083111ae2a11 307 typedef union
saloutos 0:083111ae2a11 308 {
saloutos 0:083111ae2a11 309 struct
saloutos 0:083111ae2a11 310 {
saloutos 0:083111ae2a11 311 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
saloutos 0:083111ae2a11 312 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
saloutos 0:083111ae2a11 313 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
saloutos 0:083111ae2a11 314 } b; /*!< Structure used for bit access */
saloutos 0:083111ae2a11 315 uint32_t w; /*!< Type used for word access */
saloutos 0:083111ae2a11 316 } CONTROL_Type;
saloutos 0:083111ae2a11 317
saloutos 0:083111ae2a11 318 /* CONTROL Register Definitions */
saloutos 0:083111ae2a11 319 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
saloutos 0:083111ae2a11 320 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
saloutos 0:083111ae2a11 321
saloutos 0:083111ae2a11 322 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
saloutos 0:083111ae2a11 323 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
saloutos 0:083111ae2a11 324
saloutos 0:083111ae2a11 325 /*@} end of group CMSIS_CORE */
saloutos 0:083111ae2a11 326
saloutos 0:083111ae2a11 327
saloutos 0:083111ae2a11 328 /**
saloutos 0:083111ae2a11 329 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 330 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
saloutos 0:083111ae2a11 331 \brief Type definitions for the NVIC Registers
saloutos 0:083111ae2a11 332 @{
saloutos 0:083111ae2a11 333 */
saloutos 0:083111ae2a11 334
saloutos 0:083111ae2a11 335 /**
saloutos 0:083111ae2a11 336 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
saloutos 0:083111ae2a11 337 */
saloutos 0:083111ae2a11 338 typedef struct
saloutos 0:083111ae2a11 339 {
saloutos 0:083111ae2a11 340 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
saloutos 0:083111ae2a11 341 uint32_t RESERVED0[24U];
saloutos 0:083111ae2a11 342 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
saloutos 0:083111ae2a11 343 uint32_t RSERVED1[24U];
saloutos 0:083111ae2a11 344 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
saloutos 0:083111ae2a11 345 uint32_t RESERVED2[24U];
saloutos 0:083111ae2a11 346 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
saloutos 0:083111ae2a11 347 uint32_t RESERVED3[24U];
saloutos 0:083111ae2a11 348 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
saloutos 0:083111ae2a11 349 uint32_t RESERVED4[56U];
saloutos 0:083111ae2a11 350 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
saloutos 0:083111ae2a11 351 uint32_t RESERVED5[644U];
saloutos 0:083111ae2a11 352 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
saloutos 0:083111ae2a11 353 } NVIC_Type;
saloutos 0:083111ae2a11 354
saloutos 0:083111ae2a11 355 /* Software Triggered Interrupt Register Definitions */
saloutos 0:083111ae2a11 356 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
saloutos 0:083111ae2a11 357 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
saloutos 0:083111ae2a11 358
saloutos 0:083111ae2a11 359 /*@} end of group CMSIS_NVIC */
saloutos 0:083111ae2a11 360
saloutos 0:083111ae2a11 361
saloutos 0:083111ae2a11 362 /**
saloutos 0:083111ae2a11 363 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 364 \defgroup CMSIS_SCB System Control Block (SCB)
saloutos 0:083111ae2a11 365 \brief Type definitions for the System Control Block Registers
saloutos 0:083111ae2a11 366 @{
saloutos 0:083111ae2a11 367 */
saloutos 0:083111ae2a11 368
saloutos 0:083111ae2a11 369 /**
saloutos 0:083111ae2a11 370 \brief Structure type to access the System Control Block (SCB).
saloutos 0:083111ae2a11 371 */
saloutos 0:083111ae2a11 372 typedef struct
saloutos 0:083111ae2a11 373 {
saloutos 0:083111ae2a11 374 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
saloutos 0:083111ae2a11 375 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
saloutos 0:083111ae2a11 376 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
saloutos 0:083111ae2a11 377 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
saloutos 0:083111ae2a11 378 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
saloutos 0:083111ae2a11 379 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
saloutos 0:083111ae2a11 380 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
saloutos 0:083111ae2a11 381 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
saloutos 0:083111ae2a11 382 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
saloutos 0:083111ae2a11 383 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
saloutos 0:083111ae2a11 384 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
saloutos 0:083111ae2a11 385 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
saloutos 0:083111ae2a11 386 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
saloutos 0:083111ae2a11 387 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
saloutos 0:083111ae2a11 388 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
saloutos 0:083111ae2a11 389 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
saloutos 0:083111ae2a11 390 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
saloutos 0:083111ae2a11 391 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
saloutos 0:083111ae2a11 392 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
saloutos 0:083111ae2a11 393 uint32_t RESERVED0[5U];
saloutos 0:083111ae2a11 394 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
saloutos 0:083111ae2a11 395 } SCB_Type;
saloutos 0:083111ae2a11 396
saloutos 0:083111ae2a11 397 /* SCB CPUID Register Definitions */
saloutos 0:083111ae2a11 398 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
saloutos 0:083111ae2a11 399 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
saloutos 0:083111ae2a11 400
saloutos 0:083111ae2a11 401 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
saloutos 0:083111ae2a11 402 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
saloutos 0:083111ae2a11 403
saloutos 0:083111ae2a11 404 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
saloutos 0:083111ae2a11 405 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
saloutos 0:083111ae2a11 406
saloutos 0:083111ae2a11 407 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
saloutos 0:083111ae2a11 408 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
saloutos 0:083111ae2a11 409
saloutos 0:083111ae2a11 410 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
saloutos 0:083111ae2a11 411 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
saloutos 0:083111ae2a11 412
saloutos 0:083111ae2a11 413 /* SCB Interrupt Control State Register Definitions */
saloutos 0:083111ae2a11 414 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
saloutos 0:083111ae2a11 415 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
saloutos 0:083111ae2a11 416
saloutos 0:083111ae2a11 417 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
saloutos 0:083111ae2a11 418 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
saloutos 0:083111ae2a11 419
saloutos 0:083111ae2a11 420 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
saloutos 0:083111ae2a11 421 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
saloutos 0:083111ae2a11 422
saloutos 0:083111ae2a11 423 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
saloutos 0:083111ae2a11 424 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
saloutos 0:083111ae2a11 425
saloutos 0:083111ae2a11 426 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
saloutos 0:083111ae2a11 427 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
saloutos 0:083111ae2a11 428
saloutos 0:083111ae2a11 429 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
saloutos 0:083111ae2a11 430 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
saloutos 0:083111ae2a11 431
saloutos 0:083111ae2a11 432 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
saloutos 0:083111ae2a11 433 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
saloutos 0:083111ae2a11 434
saloutos 0:083111ae2a11 435 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
saloutos 0:083111ae2a11 436 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
saloutos 0:083111ae2a11 437
saloutos 0:083111ae2a11 438 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
saloutos 0:083111ae2a11 439 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
saloutos 0:083111ae2a11 440
saloutos 0:083111ae2a11 441 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
saloutos 0:083111ae2a11 442 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
saloutos 0:083111ae2a11 443
saloutos 0:083111ae2a11 444 /* SCB Vector Table Offset Register Definitions */
saloutos 0:083111ae2a11 445 #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
saloutos 0:083111ae2a11 446 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
saloutos 0:083111ae2a11 447 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
saloutos 0:083111ae2a11 448
saloutos 0:083111ae2a11 449 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
saloutos 0:083111ae2a11 450 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
saloutos 0:083111ae2a11 451 #else
saloutos 0:083111ae2a11 452 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
saloutos 0:083111ae2a11 453 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
saloutos 0:083111ae2a11 454 #endif
saloutos 0:083111ae2a11 455
saloutos 0:083111ae2a11 456 /* SCB Application Interrupt and Reset Control Register Definitions */
saloutos 0:083111ae2a11 457 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
saloutos 0:083111ae2a11 458 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
saloutos 0:083111ae2a11 459
saloutos 0:083111ae2a11 460 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
saloutos 0:083111ae2a11 461 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
saloutos 0:083111ae2a11 462
saloutos 0:083111ae2a11 463 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
saloutos 0:083111ae2a11 464 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
saloutos 0:083111ae2a11 465
saloutos 0:083111ae2a11 466 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
saloutos 0:083111ae2a11 467 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
saloutos 0:083111ae2a11 468
saloutos 0:083111ae2a11 469 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
saloutos 0:083111ae2a11 470 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
saloutos 0:083111ae2a11 471
saloutos 0:083111ae2a11 472 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
saloutos 0:083111ae2a11 473 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
saloutos 0:083111ae2a11 474
saloutos 0:083111ae2a11 475 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
saloutos 0:083111ae2a11 476 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
saloutos 0:083111ae2a11 477
saloutos 0:083111ae2a11 478 /* SCB System Control Register Definitions */
saloutos 0:083111ae2a11 479 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
saloutos 0:083111ae2a11 480 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
saloutos 0:083111ae2a11 481
saloutos 0:083111ae2a11 482 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
saloutos 0:083111ae2a11 483 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
saloutos 0:083111ae2a11 484
saloutos 0:083111ae2a11 485 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
saloutos 0:083111ae2a11 486 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
saloutos 0:083111ae2a11 487
saloutos 0:083111ae2a11 488 /* SCB Configuration Control Register Definitions */
saloutos 0:083111ae2a11 489 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
saloutos 0:083111ae2a11 490 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
saloutos 0:083111ae2a11 491
saloutos 0:083111ae2a11 492 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
saloutos 0:083111ae2a11 493 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
saloutos 0:083111ae2a11 494
saloutos 0:083111ae2a11 495 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
saloutos 0:083111ae2a11 496 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
saloutos 0:083111ae2a11 497
saloutos 0:083111ae2a11 498 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
saloutos 0:083111ae2a11 499 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
saloutos 0:083111ae2a11 500
saloutos 0:083111ae2a11 501 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
saloutos 0:083111ae2a11 502 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
saloutos 0:083111ae2a11 503
saloutos 0:083111ae2a11 504 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
saloutos 0:083111ae2a11 505 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
saloutos 0:083111ae2a11 506
saloutos 0:083111ae2a11 507 /* SCB System Handler Control and State Register Definitions */
saloutos 0:083111ae2a11 508 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
saloutos 0:083111ae2a11 509 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
saloutos 0:083111ae2a11 510
saloutos 0:083111ae2a11 511 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
saloutos 0:083111ae2a11 512 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
saloutos 0:083111ae2a11 513
saloutos 0:083111ae2a11 514 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
saloutos 0:083111ae2a11 515 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
saloutos 0:083111ae2a11 516
saloutos 0:083111ae2a11 517 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
saloutos 0:083111ae2a11 518 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
saloutos 0:083111ae2a11 519
saloutos 0:083111ae2a11 520 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
saloutos 0:083111ae2a11 521 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
saloutos 0:083111ae2a11 522
saloutos 0:083111ae2a11 523 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
saloutos 0:083111ae2a11 524 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
saloutos 0:083111ae2a11 525
saloutos 0:083111ae2a11 526 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
saloutos 0:083111ae2a11 527 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
saloutos 0:083111ae2a11 528
saloutos 0:083111ae2a11 529 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
saloutos 0:083111ae2a11 530 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
saloutos 0:083111ae2a11 531
saloutos 0:083111ae2a11 532 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
saloutos 0:083111ae2a11 533 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
saloutos 0:083111ae2a11 534
saloutos 0:083111ae2a11 535 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
saloutos 0:083111ae2a11 536 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
saloutos 0:083111ae2a11 537
saloutos 0:083111ae2a11 538 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
saloutos 0:083111ae2a11 539 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
saloutos 0:083111ae2a11 540
saloutos 0:083111ae2a11 541 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
saloutos 0:083111ae2a11 542 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
saloutos 0:083111ae2a11 543
saloutos 0:083111ae2a11 544 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
saloutos 0:083111ae2a11 545 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
saloutos 0:083111ae2a11 546
saloutos 0:083111ae2a11 547 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
saloutos 0:083111ae2a11 548 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
saloutos 0:083111ae2a11 549
saloutos 0:083111ae2a11 550 /* SCB Configurable Fault Status Register Definitions */
saloutos 0:083111ae2a11 551 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
saloutos 0:083111ae2a11 552 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
saloutos 0:083111ae2a11 553
saloutos 0:083111ae2a11 554 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
saloutos 0:083111ae2a11 555 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
saloutos 0:083111ae2a11 556
saloutos 0:083111ae2a11 557 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
saloutos 0:083111ae2a11 558 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
saloutos 0:083111ae2a11 559
saloutos 0:083111ae2a11 560 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
saloutos 0:083111ae2a11 561 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
saloutos 0:083111ae2a11 562 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
saloutos 0:083111ae2a11 563
saloutos 0:083111ae2a11 564 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
saloutos 0:083111ae2a11 565 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
saloutos 0:083111ae2a11 566
saloutos 0:083111ae2a11 567 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
saloutos 0:083111ae2a11 568 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
saloutos 0:083111ae2a11 569
saloutos 0:083111ae2a11 570 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
saloutos 0:083111ae2a11 571 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
saloutos 0:083111ae2a11 572
saloutos 0:083111ae2a11 573 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
saloutos 0:083111ae2a11 574 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
saloutos 0:083111ae2a11 575
saloutos 0:083111ae2a11 576 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
saloutos 0:083111ae2a11 577 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
saloutos 0:083111ae2a11 578 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
saloutos 0:083111ae2a11 579
saloutos 0:083111ae2a11 580 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
saloutos 0:083111ae2a11 581 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
saloutos 0:083111ae2a11 582
saloutos 0:083111ae2a11 583 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
saloutos 0:083111ae2a11 584 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
saloutos 0:083111ae2a11 585
saloutos 0:083111ae2a11 586 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
saloutos 0:083111ae2a11 587 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
saloutos 0:083111ae2a11 588
saloutos 0:083111ae2a11 589 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
saloutos 0:083111ae2a11 590 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
saloutos 0:083111ae2a11 591
saloutos 0:083111ae2a11 592 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
saloutos 0:083111ae2a11 593 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
saloutos 0:083111ae2a11 594
saloutos 0:083111ae2a11 595 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
saloutos 0:083111ae2a11 596 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
saloutos 0:083111ae2a11 597 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
saloutos 0:083111ae2a11 598
saloutos 0:083111ae2a11 599 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
saloutos 0:083111ae2a11 600 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
saloutos 0:083111ae2a11 601
saloutos 0:083111ae2a11 602 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
saloutos 0:083111ae2a11 603 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
saloutos 0:083111ae2a11 604
saloutos 0:083111ae2a11 605 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
saloutos 0:083111ae2a11 606 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
saloutos 0:083111ae2a11 607
saloutos 0:083111ae2a11 608 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
saloutos 0:083111ae2a11 609 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
saloutos 0:083111ae2a11 610
saloutos 0:083111ae2a11 611 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
saloutos 0:083111ae2a11 612 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
saloutos 0:083111ae2a11 613
saloutos 0:083111ae2a11 614 /* SCB Hard Fault Status Register Definitions */
saloutos 0:083111ae2a11 615 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
saloutos 0:083111ae2a11 616 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
saloutos 0:083111ae2a11 617
saloutos 0:083111ae2a11 618 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
saloutos 0:083111ae2a11 619 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
saloutos 0:083111ae2a11 620
saloutos 0:083111ae2a11 621 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
saloutos 0:083111ae2a11 622 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
saloutos 0:083111ae2a11 623
saloutos 0:083111ae2a11 624 /* SCB Debug Fault Status Register Definitions */
saloutos 0:083111ae2a11 625 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
saloutos 0:083111ae2a11 626 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
saloutos 0:083111ae2a11 627
saloutos 0:083111ae2a11 628 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
saloutos 0:083111ae2a11 629 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
saloutos 0:083111ae2a11 630
saloutos 0:083111ae2a11 631 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
saloutos 0:083111ae2a11 632 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
saloutos 0:083111ae2a11 633
saloutos 0:083111ae2a11 634 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
saloutos 0:083111ae2a11 635 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
saloutos 0:083111ae2a11 636
saloutos 0:083111ae2a11 637 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
saloutos 0:083111ae2a11 638 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
saloutos 0:083111ae2a11 639
saloutos 0:083111ae2a11 640 /*@} end of group CMSIS_SCB */
saloutos 0:083111ae2a11 641
saloutos 0:083111ae2a11 642
saloutos 0:083111ae2a11 643 /**
saloutos 0:083111ae2a11 644 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 645 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
saloutos 0:083111ae2a11 646 \brief Type definitions for the System Control and ID Register not in the SCB
saloutos 0:083111ae2a11 647 @{
saloutos 0:083111ae2a11 648 */
saloutos 0:083111ae2a11 649
saloutos 0:083111ae2a11 650 /**
saloutos 0:083111ae2a11 651 \brief Structure type to access the System Control and ID Register not in the SCB.
saloutos 0:083111ae2a11 652 */
saloutos 0:083111ae2a11 653 typedef struct
saloutos 0:083111ae2a11 654 {
saloutos 0:083111ae2a11 655 uint32_t RESERVED0[1U];
saloutos 0:083111ae2a11 656 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
saloutos 0:083111ae2a11 657 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
saloutos 0:083111ae2a11 658 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
saloutos 0:083111ae2a11 659 #else
saloutos 0:083111ae2a11 660 uint32_t RESERVED1[1U];
saloutos 0:083111ae2a11 661 #endif
saloutos 0:083111ae2a11 662 } SCnSCB_Type;
saloutos 0:083111ae2a11 663
saloutos 0:083111ae2a11 664 /* Interrupt Controller Type Register Definitions */
saloutos 0:083111ae2a11 665 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
saloutos 0:083111ae2a11 666 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
saloutos 0:083111ae2a11 667
saloutos 0:083111ae2a11 668 /* Auxiliary Control Register Definitions */
saloutos 0:083111ae2a11 669
saloutos 0:083111ae2a11 670 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
saloutos 0:083111ae2a11 671 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
saloutos 0:083111ae2a11 672
saloutos 0:083111ae2a11 673 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
saloutos 0:083111ae2a11 674 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
saloutos 0:083111ae2a11 675
saloutos 0:083111ae2a11 676 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
saloutos 0:083111ae2a11 677 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
saloutos 0:083111ae2a11 678
saloutos 0:083111ae2a11 679 /*@} end of group CMSIS_SCnotSCB */
saloutos 0:083111ae2a11 680
saloutos 0:083111ae2a11 681
saloutos 0:083111ae2a11 682 /**
saloutos 0:083111ae2a11 683 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 684 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
saloutos 0:083111ae2a11 685 \brief Type definitions for the System Timer Registers.
saloutos 0:083111ae2a11 686 @{
saloutos 0:083111ae2a11 687 */
saloutos 0:083111ae2a11 688
saloutos 0:083111ae2a11 689 /**
saloutos 0:083111ae2a11 690 \brief Structure type to access the System Timer (SysTick).
saloutos 0:083111ae2a11 691 */
saloutos 0:083111ae2a11 692 typedef struct
saloutos 0:083111ae2a11 693 {
saloutos 0:083111ae2a11 694 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
saloutos 0:083111ae2a11 695 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
saloutos 0:083111ae2a11 696 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
saloutos 0:083111ae2a11 697 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
saloutos 0:083111ae2a11 698 } SysTick_Type;
saloutos 0:083111ae2a11 699
saloutos 0:083111ae2a11 700 /* SysTick Control / Status Register Definitions */
saloutos 0:083111ae2a11 701 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
saloutos 0:083111ae2a11 702 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
saloutos 0:083111ae2a11 703
saloutos 0:083111ae2a11 704 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
saloutos 0:083111ae2a11 705 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
saloutos 0:083111ae2a11 706
saloutos 0:083111ae2a11 707 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
saloutos 0:083111ae2a11 708 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
saloutos 0:083111ae2a11 709
saloutos 0:083111ae2a11 710 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
saloutos 0:083111ae2a11 711 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
saloutos 0:083111ae2a11 712
saloutos 0:083111ae2a11 713 /* SysTick Reload Register Definitions */
saloutos 0:083111ae2a11 714 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
saloutos 0:083111ae2a11 715 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
saloutos 0:083111ae2a11 716
saloutos 0:083111ae2a11 717 /* SysTick Current Register Definitions */
saloutos 0:083111ae2a11 718 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
saloutos 0:083111ae2a11 719 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
saloutos 0:083111ae2a11 720
saloutos 0:083111ae2a11 721 /* SysTick Calibration Register Definitions */
saloutos 0:083111ae2a11 722 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
saloutos 0:083111ae2a11 723 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
saloutos 0:083111ae2a11 724
saloutos 0:083111ae2a11 725 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
saloutos 0:083111ae2a11 726 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
saloutos 0:083111ae2a11 727
saloutos 0:083111ae2a11 728 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
saloutos 0:083111ae2a11 729 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
saloutos 0:083111ae2a11 730
saloutos 0:083111ae2a11 731 /*@} end of group CMSIS_SysTick */
saloutos 0:083111ae2a11 732
saloutos 0:083111ae2a11 733
saloutos 0:083111ae2a11 734 /**
saloutos 0:083111ae2a11 735 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 736 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
saloutos 0:083111ae2a11 737 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
saloutos 0:083111ae2a11 738 @{
saloutos 0:083111ae2a11 739 */
saloutos 0:083111ae2a11 740
saloutos 0:083111ae2a11 741 /**
saloutos 0:083111ae2a11 742 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
saloutos 0:083111ae2a11 743 */
saloutos 0:083111ae2a11 744 typedef struct
saloutos 0:083111ae2a11 745 {
saloutos 0:083111ae2a11 746 __OM union
saloutos 0:083111ae2a11 747 {
saloutos 0:083111ae2a11 748 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
saloutos 0:083111ae2a11 749 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
saloutos 0:083111ae2a11 750 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
saloutos 0:083111ae2a11 751 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
saloutos 0:083111ae2a11 752 uint32_t RESERVED0[864U];
saloutos 0:083111ae2a11 753 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
saloutos 0:083111ae2a11 754 uint32_t RESERVED1[15U];
saloutos 0:083111ae2a11 755 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
saloutos 0:083111ae2a11 756 uint32_t RESERVED2[15U];
saloutos 0:083111ae2a11 757 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
saloutos 0:083111ae2a11 758 uint32_t RESERVED3[29U];
saloutos 0:083111ae2a11 759 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
saloutos 0:083111ae2a11 760 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
saloutos 0:083111ae2a11 761 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
saloutos 0:083111ae2a11 762 uint32_t RESERVED4[43U];
saloutos 0:083111ae2a11 763 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
saloutos 0:083111ae2a11 764 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
saloutos 0:083111ae2a11 765 uint32_t RESERVED5[6U];
saloutos 0:083111ae2a11 766 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
saloutos 0:083111ae2a11 767 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
saloutos 0:083111ae2a11 768 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
saloutos 0:083111ae2a11 769 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
saloutos 0:083111ae2a11 770 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
saloutos 0:083111ae2a11 771 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
saloutos 0:083111ae2a11 772 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
saloutos 0:083111ae2a11 773 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
saloutos 0:083111ae2a11 774 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
saloutos 0:083111ae2a11 775 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
saloutos 0:083111ae2a11 776 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
saloutos 0:083111ae2a11 777 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
saloutos 0:083111ae2a11 778 } ITM_Type;
saloutos 0:083111ae2a11 779
saloutos 0:083111ae2a11 780 /* ITM Trace Privilege Register Definitions */
saloutos 0:083111ae2a11 781 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
saloutos 0:083111ae2a11 782 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
saloutos 0:083111ae2a11 783
saloutos 0:083111ae2a11 784 /* ITM Trace Control Register Definitions */
saloutos 0:083111ae2a11 785 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
saloutos 0:083111ae2a11 786 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
saloutos 0:083111ae2a11 787
saloutos 0:083111ae2a11 788 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
saloutos 0:083111ae2a11 789 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
saloutos 0:083111ae2a11 790
saloutos 0:083111ae2a11 791 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
saloutos 0:083111ae2a11 792 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
saloutos 0:083111ae2a11 793
saloutos 0:083111ae2a11 794 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
saloutos 0:083111ae2a11 795 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
saloutos 0:083111ae2a11 796
saloutos 0:083111ae2a11 797 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
saloutos 0:083111ae2a11 798 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
saloutos 0:083111ae2a11 799
saloutos 0:083111ae2a11 800 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
saloutos 0:083111ae2a11 801 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
saloutos 0:083111ae2a11 802
saloutos 0:083111ae2a11 803 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
saloutos 0:083111ae2a11 804 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
saloutos 0:083111ae2a11 805
saloutos 0:083111ae2a11 806 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
saloutos 0:083111ae2a11 807 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
saloutos 0:083111ae2a11 808
saloutos 0:083111ae2a11 809 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
saloutos 0:083111ae2a11 810 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
saloutos 0:083111ae2a11 811
saloutos 0:083111ae2a11 812 /* ITM Integration Write Register Definitions */
saloutos 0:083111ae2a11 813 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
saloutos 0:083111ae2a11 814 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
saloutos 0:083111ae2a11 815
saloutos 0:083111ae2a11 816 /* ITM Integration Read Register Definitions */
saloutos 0:083111ae2a11 817 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
saloutos 0:083111ae2a11 818 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
saloutos 0:083111ae2a11 819
saloutos 0:083111ae2a11 820 /* ITM Integration Mode Control Register Definitions */
saloutos 0:083111ae2a11 821 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
saloutos 0:083111ae2a11 822 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
saloutos 0:083111ae2a11 823
saloutos 0:083111ae2a11 824 /* ITM Lock Status Register Definitions */
saloutos 0:083111ae2a11 825 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
saloutos 0:083111ae2a11 826 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
saloutos 0:083111ae2a11 827
saloutos 0:083111ae2a11 828 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
saloutos 0:083111ae2a11 829 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
saloutos 0:083111ae2a11 830
saloutos 0:083111ae2a11 831 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
saloutos 0:083111ae2a11 832 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
saloutos 0:083111ae2a11 833
saloutos 0:083111ae2a11 834 /*@}*/ /* end of group CMSIS_ITM */
saloutos 0:083111ae2a11 835
saloutos 0:083111ae2a11 836
saloutos 0:083111ae2a11 837 /**
saloutos 0:083111ae2a11 838 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 839 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
saloutos 0:083111ae2a11 840 \brief Type definitions for the Data Watchpoint and Trace (DWT)
saloutos 0:083111ae2a11 841 @{
saloutos 0:083111ae2a11 842 */
saloutos 0:083111ae2a11 843
saloutos 0:083111ae2a11 844 /**
saloutos 0:083111ae2a11 845 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
saloutos 0:083111ae2a11 846 */
saloutos 0:083111ae2a11 847 typedef struct
saloutos 0:083111ae2a11 848 {
saloutos 0:083111ae2a11 849 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
saloutos 0:083111ae2a11 850 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
saloutos 0:083111ae2a11 851 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
saloutos 0:083111ae2a11 852 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
saloutos 0:083111ae2a11 853 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
saloutos 0:083111ae2a11 854 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
saloutos 0:083111ae2a11 855 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
saloutos 0:083111ae2a11 856 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
saloutos 0:083111ae2a11 857 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
saloutos 0:083111ae2a11 858 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
saloutos 0:083111ae2a11 859 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
saloutos 0:083111ae2a11 860 uint32_t RESERVED0[1U];
saloutos 0:083111ae2a11 861 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
saloutos 0:083111ae2a11 862 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
saloutos 0:083111ae2a11 863 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
saloutos 0:083111ae2a11 864 uint32_t RESERVED1[1U];
saloutos 0:083111ae2a11 865 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
saloutos 0:083111ae2a11 866 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
saloutos 0:083111ae2a11 867 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
saloutos 0:083111ae2a11 868 uint32_t RESERVED2[1U];
saloutos 0:083111ae2a11 869 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
saloutos 0:083111ae2a11 870 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
saloutos 0:083111ae2a11 871 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
saloutos 0:083111ae2a11 872 } DWT_Type;
saloutos 0:083111ae2a11 873
saloutos 0:083111ae2a11 874 /* DWT Control Register Definitions */
saloutos 0:083111ae2a11 875 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
saloutos 0:083111ae2a11 876 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
saloutos 0:083111ae2a11 877
saloutos 0:083111ae2a11 878 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
saloutos 0:083111ae2a11 879 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
saloutos 0:083111ae2a11 880
saloutos 0:083111ae2a11 881 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
saloutos 0:083111ae2a11 882 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
saloutos 0:083111ae2a11 883
saloutos 0:083111ae2a11 884 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
saloutos 0:083111ae2a11 885 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
saloutos 0:083111ae2a11 886
saloutos 0:083111ae2a11 887 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
saloutos 0:083111ae2a11 888 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
saloutos 0:083111ae2a11 889
saloutos 0:083111ae2a11 890 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
saloutos 0:083111ae2a11 891 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
saloutos 0:083111ae2a11 892
saloutos 0:083111ae2a11 893 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
saloutos 0:083111ae2a11 894 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
saloutos 0:083111ae2a11 895
saloutos 0:083111ae2a11 896 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
saloutos 0:083111ae2a11 897 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
saloutos 0:083111ae2a11 898
saloutos 0:083111ae2a11 899 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
saloutos 0:083111ae2a11 900 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
saloutos 0:083111ae2a11 901
saloutos 0:083111ae2a11 902 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
saloutos 0:083111ae2a11 903 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
saloutos 0:083111ae2a11 904
saloutos 0:083111ae2a11 905 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
saloutos 0:083111ae2a11 906 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
saloutos 0:083111ae2a11 907
saloutos 0:083111ae2a11 908 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
saloutos 0:083111ae2a11 909 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
saloutos 0:083111ae2a11 910
saloutos 0:083111ae2a11 911 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
saloutos 0:083111ae2a11 912 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
saloutos 0:083111ae2a11 913
saloutos 0:083111ae2a11 914 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
saloutos 0:083111ae2a11 915 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
saloutos 0:083111ae2a11 916
saloutos 0:083111ae2a11 917 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
saloutos 0:083111ae2a11 918 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
saloutos 0:083111ae2a11 919
saloutos 0:083111ae2a11 920 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
saloutos 0:083111ae2a11 921 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
saloutos 0:083111ae2a11 922
saloutos 0:083111ae2a11 923 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
saloutos 0:083111ae2a11 924 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
saloutos 0:083111ae2a11 925
saloutos 0:083111ae2a11 926 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
saloutos 0:083111ae2a11 927 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
saloutos 0:083111ae2a11 928
saloutos 0:083111ae2a11 929 /* DWT CPI Count Register Definitions */
saloutos 0:083111ae2a11 930 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
saloutos 0:083111ae2a11 931 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
saloutos 0:083111ae2a11 932
saloutos 0:083111ae2a11 933 /* DWT Exception Overhead Count Register Definitions */
saloutos 0:083111ae2a11 934 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
saloutos 0:083111ae2a11 935 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
saloutos 0:083111ae2a11 936
saloutos 0:083111ae2a11 937 /* DWT Sleep Count Register Definitions */
saloutos 0:083111ae2a11 938 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
saloutos 0:083111ae2a11 939 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
saloutos 0:083111ae2a11 940
saloutos 0:083111ae2a11 941 /* DWT LSU Count Register Definitions */
saloutos 0:083111ae2a11 942 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
saloutos 0:083111ae2a11 943 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
saloutos 0:083111ae2a11 944
saloutos 0:083111ae2a11 945 /* DWT Folded-instruction Count Register Definitions */
saloutos 0:083111ae2a11 946 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
saloutos 0:083111ae2a11 947 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
saloutos 0:083111ae2a11 948
saloutos 0:083111ae2a11 949 /* DWT Comparator Mask Register Definitions */
saloutos 0:083111ae2a11 950 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
saloutos 0:083111ae2a11 951 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
saloutos 0:083111ae2a11 952
saloutos 0:083111ae2a11 953 /* DWT Comparator Function Register Definitions */
saloutos 0:083111ae2a11 954 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
saloutos 0:083111ae2a11 955 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
saloutos 0:083111ae2a11 956
saloutos 0:083111ae2a11 957 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
saloutos 0:083111ae2a11 958 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
saloutos 0:083111ae2a11 959
saloutos 0:083111ae2a11 960 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
saloutos 0:083111ae2a11 961 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
saloutos 0:083111ae2a11 962
saloutos 0:083111ae2a11 963 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
saloutos 0:083111ae2a11 964 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
saloutos 0:083111ae2a11 965
saloutos 0:083111ae2a11 966 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
saloutos 0:083111ae2a11 967 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
saloutos 0:083111ae2a11 968
saloutos 0:083111ae2a11 969 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
saloutos 0:083111ae2a11 970 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
saloutos 0:083111ae2a11 971
saloutos 0:083111ae2a11 972 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
saloutos 0:083111ae2a11 973 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
saloutos 0:083111ae2a11 974
saloutos 0:083111ae2a11 975 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
saloutos 0:083111ae2a11 976 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
saloutos 0:083111ae2a11 977
saloutos 0:083111ae2a11 978 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
saloutos 0:083111ae2a11 979 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
saloutos 0:083111ae2a11 980
saloutos 0:083111ae2a11 981 /*@}*/ /* end of group CMSIS_DWT */
saloutos 0:083111ae2a11 982
saloutos 0:083111ae2a11 983
saloutos 0:083111ae2a11 984 /**
saloutos 0:083111ae2a11 985 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 986 \defgroup CMSIS_TPI Trace Port Interface (TPI)
saloutos 0:083111ae2a11 987 \brief Type definitions for the Trace Port Interface (TPI)
saloutos 0:083111ae2a11 988 @{
saloutos 0:083111ae2a11 989 */
saloutos 0:083111ae2a11 990
saloutos 0:083111ae2a11 991 /**
saloutos 0:083111ae2a11 992 \brief Structure type to access the Trace Port Interface Register (TPI).
saloutos 0:083111ae2a11 993 */
saloutos 0:083111ae2a11 994 typedef struct
saloutos 0:083111ae2a11 995 {
saloutos 0:083111ae2a11 996 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
saloutos 0:083111ae2a11 997 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
saloutos 0:083111ae2a11 998 uint32_t RESERVED0[2U];
saloutos 0:083111ae2a11 999 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
saloutos 0:083111ae2a11 1000 uint32_t RESERVED1[55U];
saloutos 0:083111ae2a11 1001 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
saloutos 0:083111ae2a11 1002 uint32_t RESERVED2[131U];
saloutos 0:083111ae2a11 1003 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
saloutos 0:083111ae2a11 1004 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
saloutos 0:083111ae2a11 1005 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
saloutos 0:083111ae2a11 1006 uint32_t RESERVED3[759U];
saloutos 0:083111ae2a11 1007 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
saloutos 0:083111ae2a11 1008 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
saloutos 0:083111ae2a11 1009 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
saloutos 0:083111ae2a11 1010 uint32_t RESERVED4[1U];
saloutos 0:083111ae2a11 1011 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
saloutos 0:083111ae2a11 1012 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
saloutos 0:083111ae2a11 1013 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
saloutos 0:083111ae2a11 1014 uint32_t RESERVED5[39U];
saloutos 0:083111ae2a11 1015 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
saloutos 0:083111ae2a11 1016 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
saloutos 0:083111ae2a11 1017 uint32_t RESERVED7[8U];
saloutos 0:083111ae2a11 1018 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
saloutos 0:083111ae2a11 1019 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
saloutos 0:083111ae2a11 1020 } TPI_Type;
saloutos 0:083111ae2a11 1021
saloutos 0:083111ae2a11 1022 /* TPI Asynchronous Clock Prescaler Register Definitions */
saloutos 0:083111ae2a11 1023 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
saloutos 0:083111ae2a11 1024 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
saloutos 0:083111ae2a11 1025
saloutos 0:083111ae2a11 1026 /* TPI Selected Pin Protocol Register Definitions */
saloutos 0:083111ae2a11 1027 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
saloutos 0:083111ae2a11 1028 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
saloutos 0:083111ae2a11 1029
saloutos 0:083111ae2a11 1030 /* TPI Formatter and Flush Status Register Definitions */
saloutos 0:083111ae2a11 1031 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
saloutos 0:083111ae2a11 1032 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
saloutos 0:083111ae2a11 1033
saloutos 0:083111ae2a11 1034 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
saloutos 0:083111ae2a11 1035 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
saloutos 0:083111ae2a11 1036
saloutos 0:083111ae2a11 1037 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
saloutos 0:083111ae2a11 1038 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
saloutos 0:083111ae2a11 1039
saloutos 0:083111ae2a11 1040 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
saloutos 0:083111ae2a11 1041 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
saloutos 0:083111ae2a11 1042
saloutos 0:083111ae2a11 1043 /* TPI Formatter and Flush Control Register Definitions */
saloutos 0:083111ae2a11 1044 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
saloutos 0:083111ae2a11 1045 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
saloutos 0:083111ae2a11 1046
saloutos 0:083111ae2a11 1047 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
saloutos 0:083111ae2a11 1048 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
saloutos 0:083111ae2a11 1049
saloutos 0:083111ae2a11 1050 /* TPI TRIGGER Register Definitions */
saloutos 0:083111ae2a11 1051 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
saloutos 0:083111ae2a11 1052 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
saloutos 0:083111ae2a11 1053
saloutos 0:083111ae2a11 1054 /* TPI Integration ETM Data Register Definitions (FIFO0) */
saloutos 0:083111ae2a11 1055 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
saloutos 0:083111ae2a11 1056 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
saloutos 0:083111ae2a11 1057
saloutos 0:083111ae2a11 1058 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
saloutos 0:083111ae2a11 1059 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
saloutos 0:083111ae2a11 1060
saloutos 0:083111ae2a11 1061 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
saloutos 0:083111ae2a11 1062 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
saloutos 0:083111ae2a11 1063
saloutos 0:083111ae2a11 1064 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
saloutos 0:083111ae2a11 1065 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
saloutos 0:083111ae2a11 1066
saloutos 0:083111ae2a11 1067 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
saloutos 0:083111ae2a11 1068 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
saloutos 0:083111ae2a11 1069
saloutos 0:083111ae2a11 1070 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
saloutos 0:083111ae2a11 1071 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
saloutos 0:083111ae2a11 1072
saloutos 0:083111ae2a11 1073 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
saloutos 0:083111ae2a11 1074 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
saloutos 0:083111ae2a11 1075
saloutos 0:083111ae2a11 1076 /* TPI ITATBCTR2 Register Definitions */
saloutos 0:083111ae2a11 1077 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
saloutos 0:083111ae2a11 1078 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
saloutos 0:083111ae2a11 1079
saloutos 0:083111ae2a11 1080 /* TPI Integration ITM Data Register Definitions (FIFO1) */
saloutos 0:083111ae2a11 1081 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
saloutos 0:083111ae2a11 1082 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
saloutos 0:083111ae2a11 1083
saloutos 0:083111ae2a11 1084 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
saloutos 0:083111ae2a11 1085 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
saloutos 0:083111ae2a11 1086
saloutos 0:083111ae2a11 1087 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
saloutos 0:083111ae2a11 1088 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
saloutos 0:083111ae2a11 1089
saloutos 0:083111ae2a11 1090 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
saloutos 0:083111ae2a11 1091 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
saloutos 0:083111ae2a11 1092
saloutos 0:083111ae2a11 1093 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
saloutos 0:083111ae2a11 1094 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
saloutos 0:083111ae2a11 1095
saloutos 0:083111ae2a11 1096 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
saloutos 0:083111ae2a11 1097 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
saloutos 0:083111ae2a11 1098
saloutos 0:083111ae2a11 1099 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
saloutos 0:083111ae2a11 1100 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
saloutos 0:083111ae2a11 1101
saloutos 0:083111ae2a11 1102 /* TPI ITATBCTR0 Register Definitions */
saloutos 0:083111ae2a11 1103 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
saloutos 0:083111ae2a11 1104 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
saloutos 0:083111ae2a11 1105
saloutos 0:083111ae2a11 1106 /* TPI Integration Mode Control Register Definitions */
saloutos 0:083111ae2a11 1107 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
saloutos 0:083111ae2a11 1108 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
saloutos 0:083111ae2a11 1109
saloutos 0:083111ae2a11 1110 /* TPI DEVID Register Definitions */
saloutos 0:083111ae2a11 1111 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
saloutos 0:083111ae2a11 1112 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
saloutos 0:083111ae2a11 1113
saloutos 0:083111ae2a11 1114 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
saloutos 0:083111ae2a11 1115 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
saloutos 0:083111ae2a11 1116
saloutos 0:083111ae2a11 1117 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
saloutos 0:083111ae2a11 1118 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
saloutos 0:083111ae2a11 1119
saloutos 0:083111ae2a11 1120 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
saloutos 0:083111ae2a11 1121 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
saloutos 0:083111ae2a11 1122
saloutos 0:083111ae2a11 1123 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
saloutos 0:083111ae2a11 1124 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
saloutos 0:083111ae2a11 1125
saloutos 0:083111ae2a11 1126 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
saloutos 0:083111ae2a11 1127 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
saloutos 0:083111ae2a11 1128
saloutos 0:083111ae2a11 1129 /* TPI DEVTYPE Register Definitions */
saloutos 0:083111ae2a11 1130 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
saloutos 0:083111ae2a11 1131 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
saloutos 0:083111ae2a11 1132
saloutos 0:083111ae2a11 1133 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
saloutos 0:083111ae2a11 1134 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
saloutos 0:083111ae2a11 1135
saloutos 0:083111ae2a11 1136 /*@}*/ /* end of group CMSIS_TPI */
saloutos 0:083111ae2a11 1137
saloutos 0:083111ae2a11 1138
saloutos 0:083111ae2a11 1139 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
saloutos 0:083111ae2a11 1140 /**
saloutos 0:083111ae2a11 1141 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 1142 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
saloutos 0:083111ae2a11 1143 \brief Type definitions for the Memory Protection Unit (MPU)
saloutos 0:083111ae2a11 1144 @{
saloutos 0:083111ae2a11 1145 */
saloutos 0:083111ae2a11 1146
saloutos 0:083111ae2a11 1147 /**
saloutos 0:083111ae2a11 1148 \brief Structure type to access the Memory Protection Unit (MPU).
saloutos 0:083111ae2a11 1149 */
saloutos 0:083111ae2a11 1150 typedef struct
saloutos 0:083111ae2a11 1151 {
saloutos 0:083111ae2a11 1152 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
saloutos 0:083111ae2a11 1153 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
saloutos 0:083111ae2a11 1154 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
saloutos 0:083111ae2a11 1155 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
saloutos 0:083111ae2a11 1156 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
saloutos 0:083111ae2a11 1157 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
saloutos 0:083111ae2a11 1158 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
saloutos 0:083111ae2a11 1159 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
saloutos 0:083111ae2a11 1160 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
saloutos 0:083111ae2a11 1161 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
saloutos 0:083111ae2a11 1162 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
saloutos 0:083111ae2a11 1163 } MPU_Type;
saloutos 0:083111ae2a11 1164
saloutos 0:083111ae2a11 1165 /* MPU Type Register Definitions */
saloutos 0:083111ae2a11 1166 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
saloutos 0:083111ae2a11 1167 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
saloutos 0:083111ae2a11 1168
saloutos 0:083111ae2a11 1169 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
saloutos 0:083111ae2a11 1170 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
saloutos 0:083111ae2a11 1171
saloutos 0:083111ae2a11 1172 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
saloutos 0:083111ae2a11 1173 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
saloutos 0:083111ae2a11 1174
saloutos 0:083111ae2a11 1175 /* MPU Control Register Definitions */
saloutos 0:083111ae2a11 1176 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
saloutos 0:083111ae2a11 1177 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
saloutos 0:083111ae2a11 1178
saloutos 0:083111ae2a11 1179 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
saloutos 0:083111ae2a11 1180 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
saloutos 0:083111ae2a11 1181
saloutos 0:083111ae2a11 1182 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
saloutos 0:083111ae2a11 1183 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
saloutos 0:083111ae2a11 1184
saloutos 0:083111ae2a11 1185 /* MPU Region Number Register Definitions */
saloutos 0:083111ae2a11 1186 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
saloutos 0:083111ae2a11 1187 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
saloutos 0:083111ae2a11 1188
saloutos 0:083111ae2a11 1189 /* MPU Region Base Address Register Definitions */
saloutos 0:083111ae2a11 1190 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
saloutos 0:083111ae2a11 1191 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
saloutos 0:083111ae2a11 1192
saloutos 0:083111ae2a11 1193 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
saloutos 0:083111ae2a11 1194 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
saloutos 0:083111ae2a11 1195
saloutos 0:083111ae2a11 1196 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
saloutos 0:083111ae2a11 1197 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
saloutos 0:083111ae2a11 1198
saloutos 0:083111ae2a11 1199 /* MPU Region Attribute and Size Register Definitions */
saloutos 0:083111ae2a11 1200 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
saloutos 0:083111ae2a11 1201 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
saloutos 0:083111ae2a11 1202
saloutos 0:083111ae2a11 1203 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
saloutos 0:083111ae2a11 1204 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
saloutos 0:083111ae2a11 1205
saloutos 0:083111ae2a11 1206 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
saloutos 0:083111ae2a11 1207 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
saloutos 0:083111ae2a11 1208
saloutos 0:083111ae2a11 1209 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
saloutos 0:083111ae2a11 1210 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
saloutos 0:083111ae2a11 1211
saloutos 0:083111ae2a11 1212 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
saloutos 0:083111ae2a11 1213 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
saloutos 0:083111ae2a11 1214
saloutos 0:083111ae2a11 1215 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
saloutos 0:083111ae2a11 1216 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
saloutos 0:083111ae2a11 1217
saloutos 0:083111ae2a11 1218 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
saloutos 0:083111ae2a11 1219 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
saloutos 0:083111ae2a11 1220
saloutos 0:083111ae2a11 1221 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
saloutos 0:083111ae2a11 1222 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
saloutos 0:083111ae2a11 1223
saloutos 0:083111ae2a11 1224 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
saloutos 0:083111ae2a11 1225 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
saloutos 0:083111ae2a11 1226
saloutos 0:083111ae2a11 1227 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
saloutos 0:083111ae2a11 1228 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
saloutos 0:083111ae2a11 1229
saloutos 0:083111ae2a11 1230 /*@} end of group CMSIS_MPU */
saloutos 0:083111ae2a11 1231 #endif
saloutos 0:083111ae2a11 1232
saloutos 0:083111ae2a11 1233
saloutos 0:083111ae2a11 1234 /**
saloutos 0:083111ae2a11 1235 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 1236 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
saloutos 0:083111ae2a11 1237 \brief Type definitions for the Core Debug Registers
saloutos 0:083111ae2a11 1238 @{
saloutos 0:083111ae2a11 1239 */
saloutos 0:083111ae2a11 1240
saloutos 0:083111ae2a11 1241 /**
saloutos 0:083111ae2a11 1242 \brief Structure type to access the Core Debug Register (CoreDebug).
saloutos 0:083111ae2a11 1243 */
saloutos 0:083111ae2a11 1244 typedef struct
saloutos 0:083111ae2a11 1245 {
saloutos 0:083111ae2a11 1246 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
saloutos 0:083111ae2a11 1247 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
saloutos 0:083111ae2a11 1248 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
saloutos 0:083111ae2a11 1249 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
saloutos 0:083111ae2a11 1250 } CoreDebug_Type;
saloutos 0:083111ae2a11 1251
saloutos 0:083111ae2a11 1252 /* Debug Halting Control and Status Register Definitions */
saloutos 0:083111ae2a11 1253 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
saloutos 0:083111ae2a11 1254 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
saloutos 0:083111ae2a11 1255
saloutos 0:083111ae2a11 1256 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
saloutos 0:083111ae2a11 1257 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
saloutos 0:083111ae2a11 1258
saloutos 0:083111ae2a11 1259 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
saloutos 0:083111ae2a11 1260 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
saloutos 0:083111ae2a11 1261
saloutos 0:083111ae2a11 1262 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
saloutos 0:083111ae2a11 1263 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
saloutos 0:083111ae2a11 1264
saloutos 0:083111ae2a11 1265 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
saloutos 0:083111ae2a11 1266 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
saloutos 0:083111ae2a11 1267
saloutos 0:083111ae2a11 1268 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
saloutos 0:083111ae2a11 1269 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
saloutos 0:083111ae2a11 1270
saloutos 0:083111ae2a11 1271 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
saloutos 0:083111ae2a11 1272 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
saloutos 0:083111ae2a11 1273
saloutos 0:083111ae2a11 1274 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
saloutos 0:083111ae2a11 1275 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
saloutos 0:083111ae2a11 1276
saloutos 0:083111ae2a11 1277 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
saloutos 0:083111ae2a11 1278 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
saloutos 0:083111ae2a11 1279
saloutos 0:083111ae2a11 1280 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
saloutos 0:083111ae2a11 1281 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
saloutos 0:083111ae2a11 1282
saloutos 0:083111ae2a11 1283 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
saloutos 0:083111ae2a11 1284 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
saloutos 0:083111ae2a11 1285
saloutos 0:083111ae2a11 1286 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
saloutos 0:083111ae2a11 1287 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
saloutos 0:083111ae2a11 1288
saloutos 0:083111ae2a11 1289 /* Debug Core Register Selector Register Definitions */
saloutos 0:083111ae2a11 1290 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
saloutos 0:083111ae2a11 1291 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
saloutos 0:083111ae2a11 1292
saloutos 0:083111ae2a11 1293 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
saloutos 0:083111ae2a11 1294 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
saloutos 0:083111ae2a11 1295
saloutos 0:083111ae2a11 1296 /* Debug Exception and Monitor Control Register Definitions */
saloutos 0:083111ae2a11 1297 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
saloutos 0:083111ae2a11 1298 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
saloutos 0:083111ae2a11 1299
saloutos 0:083111ae2a11 1300 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
saloutos 0:083111ae2a11 1301 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
saloutos 0:083111ae2a11 1302
saloutos 0:083111ae2a11 1303 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
saloutos 0:083111ae2a11 1304 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
saloutos 0:083111ae2a11 1305
saloutos 0:083111ae2a11 1306 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
saloutos 0:083111ae2a11 1307 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
saloutos 0:083111ae2a11 1308
saloutos 0:083111ae2a11 1309 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
saloutos 0:083111ae2a11 1310 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
saloutos 0:083111ae2a11 1311
saloutos 0:083111ae2a11 1312 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
saloutos 0:083111ae2a11 1313 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
saloutos 0:083111ae2a11 1314
saloutos 0:083111ae2a11 1315 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
saloutos 0:083111ae2a11 1316 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
saloutos 0:083111ae2a11 1317
saloutos 0:083111ae2a11 1318 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
saloutos 0:083111ae2a11 1319 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
saloutos 0:083111ae2a11 1320
saloutos 0:083111ae2a11 1321 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
saloutos 0:083111ae2a11 1322 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
saloutos 0:083111ae2a11 1323
saloutos 0:083111ae2a11 1324 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
saloutos 0:083111ae2a11 1325 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
saloutos 0:083111ae2a11 1326
saloutos 0:083111ae2a11 1327 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
saloutos 0:083111ae2a11 1328 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
saloutos 0:083111ae2a11 1329
saloutos 0:083111ae2a11 1330 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
saloutos 0:083111ae2a11 1331 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
saloutos 0:083111ae2a11 1332
saloutos 0:083111ae2a11 1333 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
saloutos 0:083111ae2a11 1334 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
saloutos 0:083111ae2a11 1335
saloutos 0:083111ae2a11 1336 /*@} end of group CMSIS_CoreDebug */
saloutos 0:083111ae2a11 1337
saloutos 0:083111ae2a11 1338
saloutos 0:083111ae2a11 1339 /**
saloutos 0:083111ae2a11 1340 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 1341 \defgroup CMSIS_core_bitfield Core register bit field macros
saloutos 0:083111ae2a11 1342 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
saloutos 0:083111ae2a11 1343 @{
saloutos 0:083111ae2a11 1344 */
saloutos 0:083111ae2a11 1345
saloutos 0:083111ae2a11 1346 /**
saloutos 0:083111ae2a11 1347 \brief Mask and shift a bit field value for use in a register bit range.
saloutos 0:083111ae2a11 1348 \param[in] field Name of the register bit field.
saloutos 0:083111ae2a11 1349 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
saloutos 0:083111ae2a11 1350 \return Masked and shifted value.
saloutos 0:083111ae2a11 1351 */
saloutos 0:083111ae2a11 1352 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
saloutos 0:083111ae2a11 1353
saloutos 0:083111ae2a11 1354 /**
saloutos 0:083111ae2a11 1355 \brief Mask and shift a register value to extract a bit filed value.
saloutos 0:083111ae2a11 1356 \param[in] field Name of the register bit field.
saloutos 0:083111ae2a11 1357 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
saloutos 0:083111ae2a11 1358 \return Masked and shifted bit field value.
saloutos 0:083111ae2a11 1359 */
saloutos 0:083111ae2a11 1360 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
saloutos 0:083111ae2a11 1361
saloutos 0:083111ae2a11 1362 /*@} end of group CMSIS_core_bitfield */
saloutos 0:083111ae2a11 1363
saloutos 0:083111ae2a11 1364
saloutos 0:083111ae2a11 1365 /**
saloutos 0:083111ae2a11 1366 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 1367 \defgroup CMSIS_core_base Core Definitions
saloutos 0:083111ae2a11 1368 \brief Definitions for base addresses, unions, and structures.
saloutos 0:083111ae2a11 1369 @{
saloutos 0:083111ae2a11 1370 */
saloutos 0:083111ae2a11 1371
saloutos 0:083111ae2a11 1372 /* Memory mapping of Core Hardware */
saloutos 0:083111ae2a11 1373 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
saloutos 0:083111ae2a11 1374 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
saloutos 0:083111ae2a11 1375 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
saloutos 0:083111ae2a11 1376 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
saloutos 0:083111ae2a11 1377 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
saloutos 0:083111ae2a11 1378 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
saloutos 0:083111ae2a11 1379 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
saloutos 0:083111ae2a11 1380 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
saloutos 0:083111ae2a11 1381
saloutos 0:083111ae2a11 1382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
saloutos 0:083111ae2a11 1383 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
saloutos 0:083111ae2a11 1384 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
saloutos 0:083111ae2a11 1385 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
saloutos 0:083111ae2a11 1386 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
saloutos 0:083111ae2a11 1387 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
saloutos 0:083111ae2a11 1388 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
saloutos 0:083111ae2a11 1389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
saloutos 0:083111ae2a11 1390
saloutos 0:083111ae2a11 1391 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
saloutos 0:083111ae2a11 1392 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
saloutos 0:083111ae2a11 1393 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
saloutos 0:083111ae2a11 1394 #endif
saloutos 0:083111ae2a11 1395
saloutos 0:083111ae2a11 1396 /*@} */
saloutos 0:083111ae2a11 1397
saloutos 0:083111ae2a11 1398
saloutos 0:083111ae2a11 1399
saloutos 0:083111ae2a11 1400 /*******************************************************************************
saloutos 0:083111ae2a11 1401 * Hardware Abstraction Layer
saloutos 0:083111ae2a11 1402 Core Function Interface contains:
saloutos 0:083111ae2a11 1403 - Core NVIC Functions
saloutos 0:083111ae2a11 1404 - Core SysTick Functions
saloutos 0:083111ae2a11 1405 - Core Debug Functions
saloutos 0:083111ae2a11 1406 - Core Register Access Functions
saloutos 0:083111ae2a11 1407 ******************************************************************************/
saloutos 0:083111ae2a11 1408 /**
saloutos 0:083111ae2a11 1409 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
saloutos 0:083111ae2a11 1410 */
saloutos 0:083111ae2a11 1411
saloutos 0:083111ae2a11 1412
saloutos 0:083111ae2a11 1413
saloutos 0:083111ae2a11 1414 /* ########################## NVIC functions #################################### */
saloutos 0:083111ae2a11 1415 /**
saloutos 0:083111ae2a11 1416 \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 1417 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
saloutos 0:083111ae2a11 1418 \brief Functions that manage interrupts and exceptions via the NVIC.
saloutos 0:083111ae2a11 1419 @{
saloutos 0:083111ae2a11 1420 */
saloutos 0:083111ae2a11 1421
saloutos 0:083111ae2a11 1422 #ifdef CMSIS_NVIC_VIRTUAL
saloutos 0:083111ae2a11 1423 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
saloutos 0:083111ae2a11 1424 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
saloutos 0:083111ae2a11 1425 #endif
saloutos 0:083111ae2a11 1426 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
saloutos 0:083111ae2a11 1427 #else
saloutos 0:083111ae2a11 1428 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
saloutos 0:083111ae2a11 1429 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
saloutos 0:083111ae2a11 1430 #define NVIC_EnableIRQ __NVIC_EnableIRQ
saloutos 0:083111ae2a11 1431 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
saloutos 0:083111ae2a11 1432 #define NVIC_DisableIRQ __NVIC_DisableIRQ
saloutos 0:083111ae2a11 1433 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
saloutos 0:083111ae2a11 1434 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
saloutos 0:083111ae2a11 1435 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
saloutos 0:083111ae2a11 1436 #define NVIC_GetActive __NVIC_GetActive
saloutos 0:083111ae2a11 1437 #define NVIC_SetPriority __NVIC_SetPriority
saloutos 0:083111ae2a11 1438 #define NVIC_GetPriority __NVIC_GetPriority
saloutos 0:083111ae2a11 1439 #define NVIC_SystemReset __NVIC_SystemReset
saloutos 0:083111ae2a11 1440 #endif /* CMSIS_NVIC_VIRTUAL */
saloutos 0:083111ae2a11 1441
saloutos 0:083111ae2a11 1442 #ifdef CMSIS_VECTAB_VIRTUAL
saloutos 0:083111ae2a11 1443 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
saloutos 0:083111ae2a11 1444 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
saloutos 0:083111ae2a11 1445 #endif
saloutos 0:083111ae2a11 1446 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
saloutos 0:083111ae2a11 1447 #else
saloutos 0:083111ae2a11 1448 #define NVIC_SetVector __NVIC_SetVector
saloutos 0:083111ae2a11 1449 #define NVIC_GetVector __NVIC_GetVector
saloutos 0:083111ae2a11 1450 #endif /* (CMSIS_VECTAB_VIRTUAL) */
saloutos 0:083111ae2a11 1451
saloutos 0:083111ae2a11 1452 #define NVIC_USER_IRQ_OFFSET 16
saloutos 0:083111ae2a11 1453
saloutos 0:083111ae2a11 1454
saloutos 0:083111ae2a11 1455
saloutos 0:083111ae2a11 1456 /**
saloutos 0:083111ae2a11 1457 \brief Set Priority Grouping
saloutos 0:083111ae2a11 1458 \details Sets the priority grouping field using the required unlock sequence.
saloutos 0:083111ae2a11 1459 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
saloutos 0:083111ae2a11 1460 Only values from 0..7 are used.
saloutos 0:083111ae2a11 1461 In case of a conflict between priority grouping and available
saloutos 0:083111ae2a11 1462 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
saloutos 0:083111ae2a11 1463 \param [in] PriorityGroup Priority grouping field.
saloutos 0:083111ae2a11 1464 */
saloutos 0:083111ae2a11 1465 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
saloutos 0:083111ae2a11 1466 {
saloutos 0:083111ae2a11 1467 uint32_t reg_value;
saloutos 0:083111ae2a11 1468 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
saloutos 0:083111ae2a11 1469
saloutos 0:083111ae2a11 1470 reg_value = SCB->AIRCR; /* read old register configuration */
saloutos 0:083111ae2a11 1471 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
saloutos 0:083111ae2a11 1472 reg_value = (reg_value |
saloutos 0:083111ae2a11 1473 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
saloutos 0:083111ae2a11 1474 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
saloutos 0:083111ae2a11 1475 SCB->AIRCR = reg_value;
saloutos 0:083111ae2a11 1476 }
saloutos 0:083111ae2a11 1477
saloutos 0:083111ae2a11 1478
saloutos 0:083111ae2a11 1479 /**
saloutos 0:083111ae2a11 1480 \brief Get Priority Grouping
saloutos 0:083111ae2a11 1481 \details Reads the priority grouping field from the NVIC Interrupt Controller.
saloutos 0:083111ae2a11 1482 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
saloutos 0:083111ae2a11 1483 */
saloutos 0:083111ae2a11 1484 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
saloutos 0:083111ae2a11 1485 {
saloutos 0:083111ae2a11 1486 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
saloutos 0:083111ae2a11 1487 }
saloutos 0:083111ae2a11 1488
saloutos 0:083111ae2a11 1489
saloutos 0:083111ae2a11 1490 /**
saloutos 0:083111ae2a11 1491 \brief Enable Interrupt
saloutos 0:083111ae2a11 1492 \details Enables a device specific interrupt in the NVIC interrupt controller.
saloutos 0:083111ae2a11 1493 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1494 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1495 */
saloutos 0:083111ae2a11 1496 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1497 {
saloutos 0:083111ae2a11 1498 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1499 {
saloutos 0:083111ae2a11 1500 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos 0:083111ae2a11 1501 }
saloutos 0:083111ae2a11 1502 }
saloutos 0:083111ae2a11 1503
saloutos 0:083111ae2a11 1504
saloutos 0:083111ae2a11 1505 /**
saloutos 0:083111ae2a11 1506 \brief Get Interrupt Enable status
saloutos 0:083111ae2a11 1507 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
saloutos 0:083111ae2a11 1508 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1509 \return 0 Interrupt is not enabled.
saloutos 0:083111ae2a11 1510 \return 1 Interrupt is enabled.
saloutos 0:083111ae2a11 1511 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1512 */
saloutos 0:083111ae2a11 1513 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1514 {
saloutos 0:083111ae2a11 1515 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1516 {
saloutos 0:083111ae2a11 1517 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos 0:083111ae2a11 1518 }
saloutos 0:083111ae2a11 1519 else
saloutos 0:083111ae2a11 1520 {
saloutos 0:083111ae2a11 1521 return(0U);
saloutos 0:083111ae2a11 1522 }
saloutos 0:083111ae2a11 1523 }
saloutos 0:083111ae2a11 1524
saloutos 0:083111ae2a11 1525
saloutos 0:083111ae2a11 1526 /**
saloutos 0:083111ae2a11 1527 \brief Disable Interrupt
saloutos 0:083111ae2a11 1528 \details Disables a device specific interrupt in the NVIC interrupt controller.
saloutos 0:083111ae2a11 1529 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1530 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1531 */
saloutos 0:083111ae2a11 1532 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1533 {
saloutos 0:083111ae2a11 1534 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1535 {
saloutos 0:083111ae2a11 1536 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos 0:083111ae2a11 1537 __DSB();
saloutos 0:083111ae2a11 1538 __ISB();
saloutos 0:083111ae2a11 1539 }
saloutos 0:083111ae2a11 1540 }
saloutos 0:083111ae2a11 1541
saloutos 0:083111ae2a11 1542
saloutos 0:083111ae2a11 1543 /**
saloutos 0:083111ae2a11 1544 \brief Get Pending Interrupt
saloutos 0:083111ae2a11 1545 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
saloutos 0:083111ae2a11 1546 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1547 \return 0 Interrupt status is not pending.
saloutos 0:083111ae2a11 1548 \return 1 Interrupt status is pending.
saloutos 0:083111ae2a11 1549 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1550 */
saloutos 0:083111ae2a11 1551 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1552 {
saloutos 0:083111ae2a11 1553 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1554 {
saloutos 0:083111ae2a11 1555 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos 0:083111ae2a11 1556 }
saloutos 0:083111ae2a11 1557 else
saloutos 0:083111ae2a11 1558 {
saloutos 0:083111ae2a11 1559 return(0U);
saloutos 0:083111ae2a11 1560 }
saloutos 0:083111ae2a11 1561 }
saloutos 0:083111ae2a11 1562
saloutos 0:083111ae2a11 1563
saloutos 0:083111ae2a11 1564 /**
saloutos 0:083111ae2a11 1565 \brief Set Pending Interrupt
saloutos 0:083111ae2a11 1566 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
saloutos 0:083111ae2a11 1567 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1568 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1569 */
saloutos 0:083111ae2a11 1570 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1571 {
saloutos 0:083111ae2a11 1572 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1573 {
saloutos 0:083111ae2a11 1574 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos 0:083111ae2a11 1575 }
saloutos 0:083111ae2a11 1576 }
saloutos 0:083111ae2a11 1577
saloutos 0:083111ae2a11 1578
saloutos 0:083111ae2a11 1579 /**
saloutos 0:083111ae2a11 1580 \brief Clear Pending Interrupt
saloutos 0:083111ae2a11 1581 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
saloutos 0:083111ae2a11 1582 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1583 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1584 */
saloutos 0:083111ae2a11 1585 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1586 {
saloutos 0:083111ae2a11 1587 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1588 {
saloutos 0:083111ae2a11 1589 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos 0:083111ae2a11 1590 }
saloutos 0:083111ae2a11 1591 }
saloutos 0:083111ae2a11 1592
saloutos 0:083111ae2a11 1593
saloutos 0:083111ae2a11 1594 /**
saloutos 0:083111ae2a11 1595 \brief Get Active Interrupt
saloutos 0:083111ae2a11 1596 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
saloutos 0:083111ae2a11 1597 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1598 \return 0 Interrupt status is not active.
saloutos 0:083111ae2a11 1599 \return 1 Interrupt status is active.
saloutos 0:083111ae2a11 1600 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1601 */
saloutos 0:083111ae2a11 1602 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1603 {
saloutos 0:083111ae2a11 1604 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1605 {
saloutos 0:083111ae2a11 1606 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos 0:083111ae2a11 1607 }
saloutos 0:083111ae2a11 1608 else
saloutos 0:083111ae2a11 1609 {
saloutos 0:083111ae2a11 1610 return(0U);
saloutos 0:083111ae2a11 1611 }
saloutos 0:083111ae2a11 1612 }
saloutos 0:083111ae2a11 1613
saloutos 0:083111ae2a11 1614
saloutos 0:083111ae2a11 1615 /**
saloutos 0:083111ae2a11 1616 \brief Set Interrupt Priority
saloutos 0:083111ae2a11 1617 \details Sets the priority of a device specific interrupt or a processor exception.
saloutos 0:083111ae2a11 1618 The interrupt number can be positive to specify a device specific interrupt,
saloutos 0:083111ae2a11 1619 or negative to specify a processor exception.
saloutos 0:083111ae2a11 1620 \param [in] IRQn Interrupt number.
saloutos 0:083111ae2a11 1621 \param [in] priority Priority to set.
saloutos 0:083111ae2a11 1622 \note The priority cannot be set for every processor exception.
saloutos 0:083111ae2a11 1623 */
saloutos 0:083111ae2a11 1624 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
saloutos 0:083111ae2a11 1625 {
saloutos 0:083111ae2a11 1626 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1627 {
saloutos 0:083111ae2a11 1628 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
saloutos 0:083111ae2a11 1629 }
saloutos 0:083111ae2a11 1630 else
saloutos 0:083111ae2a11 1631 {
saloutos 0:083111ae2a11 1632 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
saloutos 0:083111ae2a11 1633 }
saloutos 0:083111ae2a11 1634 }
saloutos 0:083111ae2a11 1635
saloutos 0:083111ae2a11 1636
saloutos 0:083111ae2a11 1637 /**
saloutos 0:083111ae2a11 1638 \brief Get Interrupt Priority
saloutos 0:083111ae2a11 1639 \details Reads the priority of a device specific interrupt or a processor exception.
saloutos 0:083111ae2a11 1640 The interrupt number can be positive to specify a device specific interrupt,
saloutos 0:083111ae2a11 1641 or negative to specify a processor exception.
saloutos 0:083111ae2a11 1642 \param [in] IRQn Interrupt number.
saloutos 0:083111ae2a11 1643 \return Interrupt Priority.
saloutos 0:083111ae2a11 1644 Value is aligned automatically to the implemented priority bits of the microcontroller.
saloutos 0:083111ae2a11 1645 */
saloutos 0:083111ae2a11 1646 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1647 {
saloutos 0:083111ae2a11 1648
saloutos 0:083111ae2a11 1649 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1650 {
saloutos 0:083111ae2a11 1651 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
saloutos 0:083111ae2a11 1652 }
saloutos 0:083111ae2a11 1653 else
saloutos 0:083111ae2a11 1654 {
saloutos 0:083111ae2a11 1655 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
saloutos 0:083111ae2a11 1656 }
saloutos 0:083111ae2a11 1657 }
saloutos 0:083111ae2a11 1658
saloutos 0:083111ae2a11 1659
saloutos 0:083111ae2a11 1660 /**
saloutos 0:083111ae2a11 1661 \brief Encode Priority
saloutos 0:083111ae2a11 1662 \details Encodes the priority for an interrupt with the given priority group,
saloutos 0:083111ae2a11 1663 preemptive priority value, and subpriority value.
saloutos 0:083111ae2a11 1664 In case of a conflict between priority grouping and available
saloutos 0:083111ae2a11 1665 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
saloutos 0:083111ae2a11 1666 \param [in] PriorityGroup Used priority group.
saloutos 0:083111ae2a11 1667 \param [in] PreemptPriority Preemptive priority value (starting from 0).
saloutos 0:083111ae2a11 1668 \param [in] SubPriority Subpriority value (starting from 0).
saloutos 0:083111ae2a11 1669 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
saloutos 0:083111ae2a11 1670 */
saloutos 0:083111ae2a11 1671 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
saloutos 0:083111ae2a11 1672 {
saloutos 0:083111ae2a11 1673 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
saloutos 0:083111ae2a11 1674 uint32_t PreemptPriorityBits;
saloutos 0:083111ae2a11 1675 uint32_t SubPriorityBits;
saloutos 0:083111ae2a11 1676
saloutos 0:083111ae2a11 1677 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
saloutos 0:083111ae2a11 1678 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
saloutos 0:083111ae2a11 1679
saloutos 0:083111ae2a11 1680 return (
saloutos 0:083111ae2a11 1681 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
saloutos 0:083111ae2a11 1682 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
saloutos 0:083111ae2a11 1683 );
saloutos 0:083111ae2a11 1684 }
saloutos 0:083111ae2a11 1685
saloutos 0:083111ae2a11 1686
saloutos 0:083111ae2a11 1687 /**
saloutos 0:083111ae2a11 1688 \brief Decode Priority
saloutos 0:083111ae2a11 1689 \details Decodes an interrupt priority value with a given priority group to
saloutos 0:083111ae2a11 1690 preemptive priority value and subpriority value.
saloutos 0:083111ae2a11 1691 In case of a conflict between priority grouping and available
saloutos 0:083111ae2a11 1692 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
saloutos 0:083111ae2a11 1693 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
saloutos 0:083111ae2a11 1694 \param [in] PriorityGroup Used priority group.
saloutos 0:083111ae2a11 1695 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
saloutos 0:083111ae2a11 1696 \param [out] pSubPriority Subpriority value (starting from 0).
saloutos 0:083111ae2a11 1697 */
saloutos 0:083111ae2a11 1698 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
saloutos 0:083111ae2a11 1699 {
saloutos 0:083111ae2a11 1700 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
saloutos 0:083111ae2a11 1701 uint32_t PreemptPriorityBits;
saloutos 0:083111ae2a11 1702 uint32_t SubPriorityBits;
saloutos 0:083111ae2a11 1703
saloutos 0:083111ae2a11 1704 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
saloutos 0:083111ae2a11 1705 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
saloutos 0:083111ae2a11 1706
saloutos 0:083111ae2a11 1707 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
saloutos 0:083111ae2a11 1708 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
saloutos 0:083111ae2a11 1709 }
saloutos 0:083111ae2a11 1710
saloutos 0:083111ae2a11 1711
saloutos 0:083111ae2a11 1712 /**
saloutos 0:083111ae2a11 1713 \brief Set Interrupt Vector
saloutos 0:083111ae2a11 1714 \details Sets an interrupt vector in SRAM based interrupt vector table.
saloutos 0:083111ae2a11 1715 The interrupt number can be positive to specify a device specific interrupt,
saloutos 0:083111ae2a11 1716 or negative to specify a processor exception.
saloutos 0:083111ae2a11 1717 VTOR must been relocated to SRAM before.
saloutos 0:083111ae2a11 1718 \param [in] IRQn Interrupt number
saloutos 0:083111ae2a11 1719 \param [in] vector Address of interrupt handler function
saloutos 0:083111ae2a11 1720 */
saloutos 0:083111ae2a11 1721 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
saloutos 0:083111ae2a11 1722 {
saloutos 0:083111ae2a11 1723 uint32_t *vectors = (uint32_t *)SCB->VTOR;
saloutos 0:083111ae2a11 1724 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
saloutos 0:083111ae2a11 1725 }
saloutos 0:083111ae2a11 1726
saloutos 0:083111ae2a11 1727
saloutos 0:083111ae2a11 1728 /**
saloutos 0:083111ae2a11 1729 \brief Get Interrupt Vector
saloutos 0:083111ae2a11 1730 \details Reads an interrupt vector from interrupt vector table.
saloutos 0:083111ae2a11 1731 The interrupt number can be positive to specify a device specific interrupt,
saloutos 0:083111ae2a11 1732 or negative to specify a processor exception.
saloutos 0:083111ae2a11 1733 \param [in] IRQn Interrupt number.
saloutos 0:083111ae2a11 1734 \return Address of interrupt handler function
saloutos 0:083111ae2a11 1735 */
saloutos 0:083111ae2a11 1736 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1737 {
saloutos 0:083111ae2a11 1738 uint32_t *vectors = (uint32_t *)SCB->VTOR;
saloutos 0:083111ae2a11 1739 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
saloutos 0:083111ae2a11 1740 }
saloutos 0:083111ae2a11 1741
saloutos 0:083111ae2a11 1742
saloutos 0:083111ae2a11 1743 /**
saloutos 0:083111ae2a11 1744 \brief System Reset
saloutos 0:083111ae2a11 1745 \details Initiates a system reset request to reset the MCU.
saloutos 0:083111ae2a11 1746 */
saloutos 0:083111ae2a11 1747 __STATIC_INLINE void __NVIC_SystemReset(void)
saloutos 0:083111ae2a11 1748 {
saloutos 0:083111ae2a11 1749 __DSB(); /* Ensure all outstanding memory accesses included
saloutos 0:083111ae2a11 1750 buffered write are completed before reset */
saloutos 0:083111ae2a11 1751 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
saloutos 0:083111ae2a11 1752 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
saloutos 0:083111ae2a11 1753 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
saloutos 0:083111ae2a11 1754 __DSB(); /* Ensure completion of memory access */
saloutos 0:083111ae2a11 1755
saloutos 0:083111ae2a11 1756 for(;;) /* wait until reset */
saloutos 0:083111ae2a11 1757 {
saloutos 0:083111ae2a11 1758 __NOP();
saloutos 0:083111ae2a11 1759 }
saloutos 0:083111ae2a11 1760 }
saloutos 0:083111ae2a11 1761
saloutos 0:083111ae2a11 1762 /*@} end of CMSIS_Core_NVICFunctions */
saloutos 0:083111ae2a11 1763
saloutos 0:083111ae2a11 1764
saloutos 0:083111ae2a11 1765 /* ########################## FPU functions #################################### */
saloutos 0:083111ae2a11 1766 /**
saloutos 0:083111ae2a11 1767 \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 1768 \defgroup CMSIS_Core_FpuFunctions FPU Functions
saloutos 0:083111ae2a11 1769 \brief Function that provides FPU type.
saloutos 0:083111ae2a11 1770 @{
saloutos 0:083111ae2a11 1771 */
saloutos 0:083111ae2a11 1772
saloutos 0:083111ae2a11 1773 /**
saloutos 0:083111ae2a11 1774 \brief get FPU type
saloutos 0:083111ae2a11 1775 \details returns the FPU type
saloutos 0:083111ae2a11 1776 \returns
saloutos 0:083111ae2a11 1777 - \b 0: No FPU
saloutos 0:083111ae2a11 1778 - \b 1: Single precision FPU
saloutos 0:083111ae2a11 1779 - \b 2: Double + Single precision FPU
saloutos 0:083111ae2a11 1780 */
saloutos 0:083111ae2a11 1781 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
saloutos 0:083111ae2a11 1782 {
saloutos 0:083111ae2a11 1783 return 0U; /* No FPU */
saloutos 0:083111ae2a11 1784 }
saloutos 0:083111ae2a11 1785
saloutos 0:083111ae2a11 1786
saloutos 0:083111ae2a11 1787 /*@} end of CMSIS_Core_FpuFunctions */
saloutos 0:083111ae2a11 1788
saloutos 0:083111ae2a11 1789
saloutos 0:083111ae2a11 1790
saloutos 0:083111ae2a11 1791 /* ################################## SysTick function ############################################ */
saloutos 0:083111ae2a11 1792 /**
saloutos 0:083111ae2a11 1793 \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 1794 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
saloutos 0:083111ae2a11 1795 \brief Functions that configure the System.
saloutos 0:083111ae2a11 1796 @{
saloutos 0:083111ae2a11 1797 */
saloutos 0:083111ae2a11 1798
saloutos 0:083111ae2a11 1799 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
saloutos 0:083111ae2a11 1800
saloutos 0:083111ae2a11 1801 /**
saloutos 0:083111ae2a11 1802 \brief System Tick Configuration
saloutos 0:083111ae2a11 1803 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
saloutos 0:083111ae2a11 1804 Counter is in free running mode to generate periodic interrupts.
saloutos 0:083111ae2a11 1805 \param [in] ticks Number of ticks between two interrupts.
saloutos 0:083111ae2a11 1806 \return 0 Function succeeded.
saloutos 0:083111ae2a11 1807 \return 1 Function failed.
saloutos 0:083111ae2a11 1808 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
saloutos 0:083111ae2a11 1809 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
saloutos 0:083111ae2a11 1810 must contain a vendor-specific implementation of this function.
saloutos 0:083111ae2a11 1811 */
saloutos 0:083111ae2a11 1812 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
saloutos 0:083111ae2a11 1813 {
saloutos 0:083111ae2a11 1814 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
saloutos 0:083111ae2a11 1815 {
saloutos 0:083111ae2a11 1816 return (1UL); /* Reload value impossible */
saloutos 0:083111ae2a11 1817 }
saloutos 0:083111ae2a11 1818
saloutos 0:083111ae2a11 1819 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
saloutos 0:083111ae2a11 1820 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
saloutos 0:083111ae2a11 1821 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
saloutos 0:083111ae2a11 1822 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
saloutos 0:083111ae2a11 1823 SysTick_CTRL_TICKINT_Msk |
saloutos 0:083111ae2a11 1824 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
saloutos 0:083111ae2a11 1825 return (0UL); /* Function successful */
saloutos 0:083111ae2a11 1826 }
saloutos 0:083111ae2a11 1827
saloutos 0:083111ae2a11 1828 #endif
saloutos 0:083111ae2a11 1829
saloutos 0:083111ae2a11 1830 /*@} end of CMSIS_Core_SysTickFunctions */
saloutos 0:083111ae2a11 1831
saloutos 0:083111ae2a11 1832
saloutos 0:083111ae2a11 1833
saloutos 0:083111ae2a11 1834 /* ##################################### Debug In/Output function ########################################### */
saloutos 0:083111ae2a11 1835 /**
saloutos 0:083111ae2a11 1836 \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 1837 \defgroup CMSIS_core_DebugFunctions ITM Functions
saloutos 0:083111ae2a11 1838 \brief Functions that access the ITM debug interface.
saloutos 0:083111ae2a11 1839 @{
saloutos 0:083111ae2a11 1840 */
saloutos 0:083111ae2a11 1841
saloutos 0:083111ae2a11 1842 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
saloutos 0:083111ae2a11 1843 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
saloutos 0:083111ae2a11 1844
saloutos 0:083111ae2a11 1845
saloutos 0:083111ae2a11 1846 /**
saloutos 0:083111ae2a11 1847 \brief ITM Send Character
saloutos 0:083111ae2a11 1848 \details Transmits a character via the ITM channel 0, and
saloutos 0:083111ae2a11 1849 \li Just returns when no debugger is connected that has booked the output.
saloutos 0:083111ae2a11 1850 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
saloutos 0:083111ae2a11 1851 \param [in] ch Character to transmit.
saloutos 0:083111ae2a11 1852 \returns Character to transmit.
saloutos 0:083111ae2a11 1853 */
saloutos 0:083111ae2a11 1854 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
saloutos 0:083111ae2a11 1855 {
saloutos 0:083111ae2a11 1856 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
saloutos 0:083111ae2a11 1857 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
saloutos 0:083111ae2a11 1858 {
saloutos 0:083111ae2a11 1859 while (ITM->PORT[0U].u32 == 0UL)
saloutos 0:083111ae2a11 1860 {
saloutos 0:083111ae2a11 1861 __NOP();
saloutos 0:083111ae2a11 1862 }
saloutos 0:083111ae2a11 1863 ITM->PORT[0U].u8 = (uint8_t)ch;
saloutos 0:083111ae2a11 1864 }
saloutos 0:083111ae2a11 1865 return (ch);
saloutos 0:083111ae2a11 1866 }
saloutos 0:083111ae2a11 1867
saloutos 0:083111ae2a11 1868
saloutos 0:083111ae2a11 1869 /**
saloutos 0:083111ae2a11 1870 \brief ITM Receive Character
saloutos 0:083111ae2a11 1871 \details Inputs a character via the external variable \ref ITM_RxBuffer.
saloutos 0:083111ae2a11 1872 \return Received character.
saloutos 0:083111ae2a11 1873 \return -1 No character pending.
saloutos 0:083111ae2a11 1874 */
saloutos 0:083111ae2a11 1875 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
saloutos 0:083111ae2a11 1876 {
saloutos 0:083111ae2a11 1877 int32_t ch = -1; /* no character available */
saloutos 0:083111ae2a11 1878
saloutos 0:083111ae2a11 1879 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
saloutos 0:083111ae2a11 1880 {
saloutos 0:083111ae2a11 1881 ch = ITM_RxBuffer;
saloutos 0:083111ae2a11 1882 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
saloutos 0:083111ae2a11 1883 }
saloutos 0:083111ae2a11 1884
saloutos 0:083111ae2a11 1885 return (ch);
saloutos 0:083111ae2a11 1886 }
saloutos 0:083111ae2a11 1887
saloutos 0:083111ae2a11 1888
saloutos 0:083111ae2a11 1889 /**
saloutos 0:083111ae2a11 1890 \brief ITM Check Character
saloutos 0:083111ae2a11 1891 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
saloutos 0:083111ae2a11 1892 \return 0 No character available.
saloutos 0:083111ae2a11 1893 \return 1 Character available.
saloutos 0:083111ae2a11 1894 */
saloutos 0:083111ae2a11 1895 __STATIC_INLINE int32_t ITM_CheckChar (void)
saloutos 0:083111ae2a11 1896 {
saloutos 0:083111ae2a11 1897
saloutos 0:083111ae2a11 1898 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
saloutos 0:083111ae2a11 1899 {
saloutos 0:083111ae2a11 1900 return (0); /* no character available */
saloutos 0:083111ae2a11 1901 }
saloutos 0:083111ae2a11 1902 else
saloutos 0:083111ae2a11 1903 {
saloutos 0:083111ae2a11 1904 return (1); /* character available */
saloutos 0:083111ae2a11 1905 }
saloutos 0:083111ae2a11 1906 }
saloutos 0:083111ae2a11 1907
saloutos 0:083111ae2a11 1908 /*@} end of CMSIS_core_DebugFunctions */
saloutos 0:083111ae2a11 1909
saloutos 0:083111ae2a11 1910
saloutos 0:083111ae2a11 1911
saloutos 0:083111ae2a11 1912
saloutos 0:083111ae2a11 1913 #ifdef __cplusplus
saloutos 0:083111ae2a11 1914 }
saloutos 0:083111ae2a11 1915 #endif
saloutos 0:083111ae2a11 1916
saloutos 0:083111ae2a11 1917 #endif /* __CORE_CM3_H_DEPENDANT */
saloutos 0:083111ae2a11 1918
saloutos 0:083111ae2a11 1919 #endif /* __CMSIS_GENERIC */