mbed-dev - Biomimetics MBED Library w/ Added Support for CAN3

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Biomimetics MBED Library w/ Added Support for CAN3

Dependents: CAN_TEST SPIne_Plus_DYNO_SENSORS SPIne_Plus_v2 SPIne_Plus_Dyno_v2

cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armclang.h@0:083111ae2a11, 2020-11-26 (annotated)

Committer:: saloutos
Date:: Thu Nov 26 04:08:56 2020 +0000
Revision:: 0:083111ae2a11

first commit of leaned mbed dev lib

Who changed what in which revision?

User	Revision	Line number	New contents of line
saloutos	0:083111ae2a11	1	/************************************************************************//
saloutos	0:083111ae2a11	2	* @file cmsis_armclang.h
saloutos	0:083111ae2a11	3	* @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
saloutos	0:083111ae2a11	4	* @version V5.0.3
saloutos	0:083111ae2a11	5	* @date 27. March 2017
saloutos	0:083111ae2a11	6	******************************************************************************/
saloutos	0:083111ae2a11	7	/*
saloutos	0:083111ae2a11	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
saloutos	0:083111ae2a11	9	*
saloutos	0:083111ae2a11	10	* SPDX-License-Identifier: Apache-2.0
saloutos	0:083111ae2a11	11	*
saloutos	0:083111ae2a11	12	* Licensed under the Apache License, Version 2.0 (the License); you may
saloutos	0:083111ae2a11	13	* not use this file except in compliance with the License.
saloutos	0:083111ae2a11	14	* You may obtain a copy of the License at
saloutos	0:083111ae2a11	15	*
saloutos	0:083111ae2a11	16	* www.apache.org/licenses/LICENSE-2.0
saloutos	0:083111ae2a11	17	*
saloutos	0:083111ae2a11	18	* Unless required by applicable law or agreed to in writing, software
saloutos	0:083111ae2a11	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
saloutos	0:083111ae2a11	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
saloutos	0:083111ae2a11	21	* See the License for the specific language governing permissions and
saloutos	0:083111ae2a11	22	* limitations under the License.
saloutos	0:083111ae2a11	23	*/
saloutos	0:083111ae2a11	24
saloutos	0:083111ae2a11	25	//lint -esym(9058, IRQn) disable MISRA 2012 Rule 2.4 for IRQn
saloutos	0:083111ae2a11	26
saloutos	0:083111ae2a11	27	#ifndef __CMSIS_ARMCLANG_H
saloutos	0:083111ae2a11	28	#define __CMSIS_ARMCLANG_H
saloutos	0:083111ae2a11	29
saloutos	0:083111ae2a11	30	#ifndef __ARM_COMPAT_H
saloutos	0:083111ae2a11	31	#include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
saloutos	0:083111ae2a11	32	#endif
saloutos	0:083111ae2a11	33
saloutos	0:083111ae2a11	34	/* CMSIS compiler specific defines */
saloutos	0:083111ae2a11	35	#ifndef __ASM
saloutos	0:083111ae2a11	36	#define __ASM __asm
saloutos	0:083111ae2a11	37	#endif
saloutos	0:083111ae2a11	38	#ifndef __INLINE
saloutos	0:083111ae2a11	39	#define __INLINE __inline
saloutos	0:083111ae2a11	40	#endif
saloutos	0:083111ae2a11	41	#ifndef __STATIC_INLINE
saloutos	0:083111ae2a11	42	#define __STATIC_INLINE static __inline
saloutos	0:083111ae2a11	43	#endif
saloutos	0:083111ae2a11	44	#ifndef __NO_RETURN
saloutos	0:083111ae2a11	45	#define __NO_RETURN __attribute__((noreturn))
saloutos	0:083111ae2a11	46	#endif
saloutos	0:083111ae2a11	47	#ifndef __USED
saloutos	0:083111ae2a11	48	#define __USED __attribute__((used))
saloutos	0:083111ae2a11	49	#endif
saloutos	0:083111ae2a11	50	#ifndef __WEAK
saloutos	0:083111ae2a11	51	#define __WEAK __attribute__((weak))
saloutos	0:083111ae2a11	52	#endif
saloutos	0:083111ae2a11	53	#ifndef __PACKED
saloutos	0:083111ae2a11	54	#define __PACKED __attribute__((packed, aligned(1)))
saloutos	0:083111ae2a11	55	#endif
saloutos	0:083111ae2a11	56	#ifndef __PACKED_STRUCT
saloutos	0:083111ae2a11	57	#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
saloutos	0:083111ae2a11	58	#endif
saloutos	0:083111ae2a11	59	#ifndef __UNALIGNED_UINT32 /* deprecated */
saloutos	0:083111ae2a11	60	#pragma clang diagnostic push
saloutos	0:083111ae2a11	61	#pragma clang diagnostic ignored "-Wpacked"
saloutos	0:083111ae2a11	62	//lint -esym(9058, T_UINT32) disable MISRA 2012 Rule 2.4 for T_UINT32
saloutos	0:083111ae2a11	63	struct __attribute__((packed)) T_UINT32 { uint32_t v; };
saloutos	0:083111ae2a11	64	#pragma clang diagnostic pop
saloutos	0:083111ae2a11	65	#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
saloutos	0:083111ae2a11	66	#endif
saloutos	0:083111ae2a11	67	#ifndef __UNALIGNED_UINT16_WRITE
saloutos	0:083111ae2a11	68	#pragma clang diagnostic push
saloutos	0:083111ae2a11	69	#pragma clang diagnostic ignored "-Wpacked"
saloutos	0:083111ae2a11	70	//lint -esym(9058, T_UINT16_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE
saloutos	0:083111ae2a11	71	__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
saloutos	0:083111ae2a11	72	#pragma clang diagnostic pop
saloutos	0:083111ae2a11	73	#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE )(void )(addr))->v) = (val))
saloutos	0:083111ae2a11	74	#endif
saloutos	0:083111ae2a11	75	#ifndef __UNALIGNED_UINT16_READ
saloutos	0:083111ae2a11	76	#pragma clang diagnostic push
saloutos	0:083111ae2a11	77	#pragma clang diagnostic ignored "-Wpacked"
saloutos	0:083111ae2a11	78	//lint -esym(9058, T_UINT16_READ) disable MISRA 2012 Rule 2.4 for T_UINT16_READ
saloutos	0:083111ae2a11	79	__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
saloutos	0:083111ae2a11	80	#pragma clang diagnostic pop
saloutos	0:083111ae2a11	81	#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ )(const void )(addr))->v)
saloutos	0:083111ae2a11	82	#endif
saloutos	0:083111ae2a11	83	#ifndef __UNALIGNED_UINT32_WRITE
saloutos	0:083111ae2a11	84	#pragma clang diagnostic push
saloutos	0:083111ae2a11	85	#pragma clang diagnostic ignored "-Wpacked"
saloutos	0:083111ae2a11	86	//lint -esym(9058, T_UINT32_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE
saloutos	0:083111ae2a11	87	__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
saloutos	0:083111ae2a11	88	#pragma clang diagnostic pop
saloutos	0:083111ae2a11	89	#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE )(void )(addr))->v) = (val))
saloutos	0:083111ae2a11	90	#endif
saloutos	0:083111ae2a11	91	#ifndef __UNALIGNED_UINT32_READ
saloutos	0:083111ae2a11	92	#pragma clang diagnostic push
saloutos	0:083111ae2a11	93	#pragma clang diagnostic ignored "-Wpacked"
saloutos	0:083111ae2a11	94	__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
saloutos	0:083111ae2a11	95	#pragma clang diagnostic pop
saloutos	0:083111ae2a11	96	#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ )(const void )(addr))->v)
saloutos	0:083111ae2a11	97	#endif
saloutos	0:083111ae2a11	98	#ifndef __ALIGNED
saloutos	0:083111ae2a11	99	#define __ALIGNED(x) __attribute__((aligned(x)))
saloutos	0:083111ae2a11	100	#endif
saloutos	0:083111ae2a11	101
saloutos	0:083111ae2a11	102
saloutos	0:083111ae2a11	103	/* ########################### Core Function Access ########################### */
saloutos	0:083111ae2a11	104	/** \ingroup CMSIS_Core_FunctionInterface
saloutos	0:083111ae2a11	105	\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
saloutos	0:083111ae2a11	106	@{
saloutos	0:083111ae2a11	107	*/
saloutos	0:083111ae2a11	108
saloutos	0:083111ae2a11	109	/**
saloutos	0:083111ae2a11	110	\brief Enable IRQ Interrupts
saloutos	0:083111ae2a11	111	\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
saloutos	0:083111ae2a11	112	Can only be executed in Privileged modes.
saloutos	0:083111ae2a11	113	*/
saloutos	0:083111ae2a11	114	/* intrinsic void __enable_irq(); see arm_compat.h */
saloutos	0:083111ae2a11	115
saloutos	0:083111ae2a11	116
saloutos	0:083111ae2a11	117	/**
saloutos	0:083111ae2a11	118	\brief Disable IRQ Interrupts
saloutos	0:083111ae2a11	119	\details Disables IRQ interrupts by setting the I-bit in the CPSR.
saloutos	0:083111ae2a11	120	Can only be executed in Privileged modes.
saloutos	0:083111ae2a11	121	*/
saloutos	0:083111ae2a11	122	/* intrinsic void __disable_irq(); see arm_compat.h */
saloutos	0:083111ae2a11	123
saloutos	0:083111ae2a11	124
saloutos	0:083111ae2a11	125	/**
saloutos	0:083111ae2a11	126	\brief Get Control Register
saloutos	0:083111ae2a11	127	\details Returns the content of the Control Register.
saloutos	0:083111ae2a11	128	\return Control Register value
saloutos	0:083111ae2a11	129	*/
saloutos	0:083111ae2a11	130	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
saloutos	0:083111ae2a11	131	{
saloutos	0:083111ae2a11	132	uint32_t result;
saloutos	0:083111ae2a11	133
saloutos	0:083111ae2a11	134	__ASM volatile ("MRS %0, control" : "=r" (result) );
saloutos	0:083111ae2a11	135	return(result);
saloutos	0:083111ae2a11	136	}
saloutos	0:083111ae2a11	137
saloutos	0:083111ae2a11	138
saloutos	0:083111ae2a11	139	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos	0:083111ae2a11	140	/**
saloutos	0:083111ae2a11	141	\brief Get Control Register (non-secure)
saloutos	0:083111ae2a11	142	\details Returns the content of the non-secure Control Register when in secure mode.
saloutos	0:083111ae2a11	143	\return non-secure Control Register value
saloutos	0:083111ae2a11	144	*/
saloutos	0:083111ae2a11	145	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
saloutos	0:083111ae2a11	146	{
saloutos	0:083111ae2a11	147	uint32_t result;
saloutos	0:083111ae2a11	148
saloutos	0:083111ae2a11	149	__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
saloutos	0:083111ae2a11	150	return(result);
saloutos	0:083111ae2a11	151	}
saloutos	0:083111ae2a11	152	#endif
saloutos	0:083111ae2a11	153
saloutos	0:083111ae2a11	154
saloutos	0:083111ae2a11	155	/**
saloutos	0:083111ae2a11	156	\brief Set Control Register
saloutos	0:083111ae2a11	157	\details Writes the given value to the Control Register.
saloutos	0:083111ae2a11	158	\param [in] control Control Register value to set
saloutos	0:083111ae2a11	159	*/
saloutos	0:083111ae2a11	160	__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
saloutos	0:083111ae2a11	161	{
saloutos	0:083111ae2a11	162	__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
saloutos	0:083111ae2a11	163	}
saloutos	0:083111ae2a11	164
saloutos	0:083111ae2a11	165
saloutos	0:083111ae2a11	166	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos	0:083111ae2a11	167	/**
saloutos	0:083111ae2a11	168	\brief Set Control Register (non-secure)
saloutos	0:083111ae2a11	169	\details Writes the given value to the non-secure Control Register when in secure state.
saloutos	0:083111ae2a11	170	\param [in] control Control Register value to set
saloutos	0:083111ae2a11	171	*/
saloutos	0:083111ae2a11	172	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
saloutos	0:083111ae2a11	173	{
saloutos	0:083111ae2a11	174	__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
saloutos	0:083111ae2a11	175	}
saloutos	0:083111ae2a11	176	#endif
saloutos	0:083111ae2a11	177
saloutos	0:083111ae2a11	178
saloutos	0:083111ae2a11	179	/**
saloutos	0:083111ae2a11	180	\brief Get IPSR Register
saloutos	0:083111ae2a11	181	\details Returns the content of the IPSR Register.
saloutos	0:083111ae2a11	182	\return IPSR Register value
saloutos	0:083111ae2a11	183	*/
saloutos	0:083111ae2a11	184	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
saloutos	0:083111ae2a11	185	{
saloutos	0:083111ae2a11	186	uint32_t result;
saloutos	0:083111ae2a11	187
saloutos	0:083111ae2a11	188	__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
saloutos	0:083111ae2a11	189	return(result);
saloutos	0:083111ae2a11	190	}
saloutos	0:083111ae2a11	191
saloutos	0:083111ae2a11	192
saloutos	0:083111ae2a11	193	/**
saloutos	0:083111ae2a11	194	\brief Get APSR Register
saloutos	0:083111ae2a11	195	\details Returns the content of the APSR Register.
saloutos	0:083111ae2a11	196	\return APSR Register value
saloutos	0:083111ae2a11	197	*/
saloutos	0:083111ae2a11	198	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
saloutos	0:083111ae2a11	199	{
saloutos	0:083111ae2a11	200	uint32_t result;
saloutos	0:083111ae2a11	201
saloutos	0:083111ae2a11	202	__ASM volatile ("MRS %0, apsr" : "=r" (result) );
saloutos	0:083111ae2a11	203	return(result);
saloutos	0:083111ae2a11	204	}
saloutos	0:083111ae2a11	205
saloutos	0:083111ae2a11	206
saloutos	0:083111ae2a11	207	/**
saloutos	0:083111ae2a11	208	\brief Get xPSR Register
saloutos	0:083111ae2a11	209	\details Returns the content of the xPSR Register.
saloutos	0:083111ae2a11	210	\return xPSR Register value
saloutos	0:083111ae2a11	211	*/
saloutos	0:083111ae2a11	212	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
saloutos	0:083111ae2a11	213	{
saloutos	0:083111ae2a11	214	uint32_t result;
saloutos	0:083111ae2a11	215
saloutos	0:083111ae2a11	216	__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
saloutos	0:083111ae2a11	217	return(result);
saloutos	0:083111ae2a11	218	}
saloutos	0:083111ae2a11	219
saloutos	0:083111ae2a11	220
saloutos	0:083111ae2a11	221	/**
saloutos	0:083111ae2a11	222	\brief Get Process Stack Pointer
saloutos	0:083111ae2a11	223	\details Returns the current value of the Process Stack Pointer (PSP).
saloutos	0:083111ae2a11	224	\return PSP Register value
saloutos	0:083111ae2a11	225	*/
saloutos	0:083111ae2a11	226	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
saloutos	0:083111ae2a11	227	{
saloutos	0:083111ae2a11	228	register uint32_t result;
saloutos	0:083111ae2a11	229
saloutos	0:083111ae2a11	230	__ASM volatile ("MRS %0, psp" : "=r" (result) );
saloutos	0:083111ae2a11	231	return(result);
saloutos	0:083111ae2a11	232	}
saloutos	0:083111ae2a11	233
saloutos	0:083111ae2a11	234
saloutos	0:083111ae2a11	235	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos	0:083111ae2a11	236	/**
saloutos	0:083111ae2a11	237	\brief Get Process Stack Pointer (non-secure)
saloutos	0:083111ae2a11	238	\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
saloutos	0:083111ae2a11	239	\return PSP Register value
saloutos	0:083111ae2a11	240	*/
saloutos	0:083111ae2a11	241	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
saloutos	0:083111ae2a11	242	{
saloutos	0:083111ae2a11	243	register uint32_t result;
saloutos	0:083111ae2a11	244
saloutos	0:083111ae2a11	245	__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
saloutos	0:083111ae2a11	246	return(result);
saloutos	0:083111ae2a11	247	}
saloutos	0:083111ae2a11	248	#endif
saloutos	0:083111ae2a11	249
saloutos	0:083111ae2a11	250
saloutos	0:083111ae2a11	251	/**
saloutos	0:083111ae2a11	252	\brief Set Process Stack Pointer
saloutos	0:083111ae2a11	253	\details Assigns the given value to the Process Stack Pointer (PSP).
saloutos	0:083111ae2a11	254	\param [in] topOfProcStack Process Stack Pointer value to set
saloutos	0:083111ae2a11	255	*/
saloutos	0:083111ae2a11	256	__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
saloutos	0:083111ae2a11	257	{
saloutos	0:083111ae2a11	258	__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
saloutos	0:083111ae2a11	259	}
saloutos	0:083111ae2a11	260
saloutos	0:083111ae2a11	261
saloutos	0:083111ae2a11	262	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos	0:083111ae2a11	263	/**
saloutos	0:083111ae2a11	264	\brief Set Process Stack Pointer (non-secure)
saloutos	0:083111ae2a11	265	\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
saloutos	0:083111ae2a11	266	\param [in] topOfProcStack Process Stack Pointer value to set
saloutos	0:083111ae2a11	267	*/
saloutos	0:083111ae2a11	268	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
saloutos	0:083111ae2a11	269	{
saloutos	0:083111ae2a11	270	__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
saloutos	0:083111ae2a11	271	}
saloutos	0:083111ae2a11	272	#endif
saloutos	0:083111ae2a11	273
saloutos	0:083111ae2a11	274
saloutos	0:083111ae2a11	275	/**
saloutos	0:083111ae2a11	276	\brief Get Main Stack Pointer
saloutos	0:083111ae2a11	277	\details Returns the current value of the Main Stack Pointer (MSP).
saloutos	0:083111ae2a11	278	\return MSP Register value
saloutos	0:083111ae2a11	279	*/
saloutos	0:083111ae2a11	280	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
saloutos	0:083111ae2a11	281	{
saloutos	0:083111ae2a11	282	register uint32_t result;
saloutos	0:083111ae2a11	283
saloutos	0:083111ae2a11	284	__ASM volatile ("MRS %0, msp" : "=r" (result) );
saloutos	0:083111ae2a11	285	return(result);
saloutos	0:083111ae2a11	286	}
saloutos	0:083111ae2a11	287
saloutos	0:083111ae2a11	288
saloutos	0:083111ae2a11	289	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos	0:083111ae2a11	290	/**
saloutos	0:083111ae2a11	291	\brief Get Main Stack Pointer (non-secure)
saloutos	0:083111ae2a11	292	\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
saloutos	0:083111ae2a11	293	\return MSP Register value
saloutos	0:083111ae2a11	294	*/
saloutos	0:083111ae2a11	295	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
saloutos	0:083111ae2a11	296	{
saloutos	0:083111ae2a11	297	register uint32_t result;
saloutos	0:083111ae2a11	298
saloutos	0:083111ae2a11	299	__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
saloutos	0:083111ae2a11	300	return(result);
saloutos	0:083111ae2a11	301	}
saloutos	0:083111ae2a11	302	#endif
saloutos	0:083111ae2a11	303
saloutos	0:083111ae2a11	304
saloutos	0:083111ae2a11	305	/**
saloutos	0:083111ae2a11	306	\brief Set Main Stack Pointer
saloutos	0:083111ae2a11	307	\details Assigns the given value to the Main Stack Pointer (MSP).
saloutos	0:083111ae2a11	308	\param [in] topOfMainStack Main Stack Pointer value to set
saloutos	0:083111ae2a11	309	*/
saloutos	0:083111ae2a11	310	__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
saloutos	0:083111ae2a11	311	{
saloutos	0:083111ae2a11	312	__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
saloutos	0:083111ae2a11	313	}
saloutos	0:083111ae2a11	314
saloutos	0:083111ae2a11	315
saloutos	0:083111ae2a11	316	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos	0:083111ae2a11	317	/**
saloutos	0:083111ae2a11	318	\brief Set Main Stack Pointer (non-secure)
saloutos	0:083111ae2a11	319	\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
saloutos	0:083111ae2a11	320	\param [in] topOfMainStack Main Stack Pointer value to set
saloutos	0:083111ae2a11	321	*/
saloutos	0:083111ae2a11	322	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
saloutos	0:083111ae2a11	323	{
saloutos	0:083111ae2a11	324	__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
saloutos	0:083111ae2a11	325	}
saloutos	0:083111ae2a11	326	#endif
saloutos	0:083111ae2a11	327
saloutos	0:083111ae2a11	328
saloutos	0:083111ae2a11	329	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos	0:083111ae2a11	330	/**
saloutos	0:083111ae2a11	331	\brief Get Stack Pointer (non-secure)
saloutos	0:083111ae2a11	332	\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
saloutos	0:083111ae2a11	333	\return SP Register value
saloutos	0:083111ae2a11	334	*/
saloutos	0:083111ae2a11	335	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
saloutos	0:083111ae2a11	336	{
saloutos	0:083111ae2a11	337	register uint32_t result;
saloutos	0:083111ae2a11	338
saloutos	0:083111ae2a11	339	__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
saloutos	0:083111ae2a11	340	return(result);
saloutos	0:083111ae2a11	341	}
saloutos	0:083111ae2a11	342
saloutos	0:083111ae2a11	343
saloutos	0:083111ae2a11	344	/**
saloutos	0:083111ae2a11	345	\brief Set Stack Pointer (non-secure)
saloutos	0:083111ae2a11	346	\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
saloutos	0:083111ae2a11	347	\param [in] topOfStack Stack Pointer value to set
saloutos	0:083111ae2a11	348	*/
saloutos	0:083111ae2a11	349	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
saloutos	0:083111ae2a11	350	{
saloutos	0:083111ae2a11	351	__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
saloutos	0:083111ae2a11	352	}
saloutos	0:083111ae2a11	353	#endif
saloutos	0:083111ae2a11	354
saloutos	0:083111ae2a11	355
saloutos	0:083111ae2a11	356	/**
saloutos	0:083111ae2a11	357	\brief Get Priority Mask
saloutos	0:083111ae2a11	358	\details Returns the current state of the priority mask bit from the Priority Mask Register.
saloutos	0:083111ae2a11	359	\return Priority Mask value
saloutos	0:083111ae2a11	360	*/
saloutos	0:083111ae2a11	361	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
saloutos	0:083111ae2a11	362	{
saloutos	0:083111ae2a11	363	uint32_t result;
saloutos	0:083111ae2a11	364
saloutos	0:083111ae2a11	365	__ASM volatile ("MRS %0, primask" : "=r" (result) );
saloutos	0:083111ae2a11	366	return(result);
saloutos	0:083111ae2a11	367	}
saloutos	0:083111ae2a11	368
saloutos	0:083111ae2a11	369
saloutos	0:083111ae2a11	370	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos	0:083111ae2a11	371	/**
saloutos	0:083111ae2a11	372	\brief Get Priority Mask (non-secure)
saloutos	0:083111ae2a11	373	\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
saloutos	0:083111ae2a11	374	\return Priority Mask value
saloutos	0:083111ae2a11	375	*/
saloutos	0:083111ae2a11	376	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
saloutos	0:083111ae2a11	377	{
saloutos	0:083111ae2a11	378	uint32_t result;
saloutos	0:083111ae2a11	379
saloutos	0:083111ae2a11	380	__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
saloutos	0:083111ae2a11	381	return(result);
saloutos	0:083111ae2a11	382	}
saloutos	0:083111ae2a11	383	#endif
saloutos	0:083111ae2a11	384
saloutos	0:083111ae2a11	385
saloutos	0:083111ae2a11	386	/**
saloutos	0:083111ae2a11	387	\brief Set Priority Mask
saloutos	0:083111ae2a11	388	\details Assigns the given value to the Priority Mask Register.
saloutos	0:083111ae2a11	389	\param [in] priMask Priority Mask
saloutos	0:083111ae2a11	390	*/
saloutos	0:083111ae2a11	391	__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
saloutos	0:083111ae2a11	392	{
saloutos	0:083111ae2a11	393	__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
saloutos	0:083111ae2a11	394	}
saloutos	0:083111ae2a11	395
saloutos	0:083111ae2a11	396
saloutos	0:083111ae2a11	397	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos	0:083111ae2a11	398	/**
saloutos	0:083111ae2a11	399	\brief Set Priority Mask (non-secure)
saloutos	0:083111ae2a11	400	\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
saloutos	0:083111ae2a11	401	\param [in] priMask Priority Mask
saloutos	0:083111ae2a11	402	*/
saloutos	0:083111ae2a11	403	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
saloutos	0:083111ae2a11	404	{
saloutos	0:083111ae2a11	405	__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
saloutos	0:083111ae2a11	406	}
saloutos	0:083111ae2a11	407	#endif
saloutos	0:083111ae2a11	408
saloutos	0:083111ae2a11	409
saloutos	0:083111ae2a11	410	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
saloutos	0:083111ae2a11	411	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
saloutos	0:083111ae2a11	412	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos	0:083111ae2a11	413	/**
saloutos	0:083111ae2a11	414	\brief Enable FIQ
saloutos	0:083111ae2a11	415	\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
saloutos	0:083111ae2a11	416	Can only be executed in Privileged modes.
saloutos	0:083111ae2a11	417	*/
saloutos	0:083111ae2a11	418	#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
saloutos	0:083111ae2a11	419
saloutos	0:083111ae2a11	420
saloutos	0:083111ae2a11	421	/**
saloutos	0:083111ae2a11	422	\brief Disable FIQ
saloutos	0:083111ae2a11	423	\details Disables FIQ interrupts by setting the F-bit in the CPSR.
saloutos	0:083111ae2a11	424	Can only be executed in Privileged modes.
saloutos	0:083111ae2a11	425	*/
saloutos	0:083111ae2a11	426	#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
saloutos	0:083111ae2a11	427
saloutos	0:083111ae2a11	428
saloutos	0:083111ae2a11	429	/**
saloutos	0:083111ae2a11	430	\brief Get Base Priority
saloutos	0:083111ae2a11	431	\details Returns the current value of the Base Priority register.
saloutos	0:083111ae2a11	432	\return Base Priority register value
saloutos	0:083111ae2a11	433	*/
saloutos	0:083111ae2a11	434	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
saloutos	0:083111ae2a11	435	{
saloutos	0:083111ae2a11	436	uint32_t result;
saloutos	0:083111ae2a11	437
saloutos	0:083111ae2a11	438	__ASM volatile ("MRS %0, basepri" : "=r" (result) );
saloutos	0:083111ae2a11	439	return(result);
saloutos	0:083111ae2a11	440	}
saloutos	0:083111ae2a11	441
saloutos	0:083111ae2a11	442
saloutos	0:083111ae2a11	443	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos	0:083111ae2a11	444	/**
saloutos	0:083111ae2a11	445	\brief Get Base Priority (non-secure)
saloutos	0:083111ae2a11	446	\details Returns the current value of the non-secure Base Priority register when in secure state.
saloutos	0:083111ae2a11	447	\return Base Priority register value
saloutos	0:083111ae2a11	448	*/
saloutos	0:083111ae2a11	449	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
saloutos	0:083111ae2a11	450	{
saloutos	0:083111ae2a11	451	uint32_t result;
saloutos	0:083111ae2a11	452
saloutos	0:083111ae2a11	453	__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
saloutos	0:083111ae2a11	454	return(result);
saloutos	0:083111ae2a11	455	}
saloutos	0:083111ae2a11	456	#endif
saloutos	0:083111ae2a11	457
saloutos	0:083111ae2a11	458
saloutos	0:083111ae2a11	459	/**
saloutos	0:083111ae2a11	460	\brief Set Base Priority
saloutos	0:083111ae2a11	461	\details Assigns the given value to the Base Priority register.
saloutos	0:083111ae2a11	462	\param [in] basePri Base Priority value to set
saloutos	0:083111ae2a11	463	*/
saloutos	0:083111ae2a11	464	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
saloutos	0:083111ae2a11	465	{
saloutos	0:083111ae2a11	466	__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
saloutos	0:083111ae2a11	467	}
saloutos	0:083111ae2a11	468
saloutos	0:083111ae2a11	469
saloutos	0:083111ae2a11	470	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos	0:083111ae2a11	471	/**
saloutos	0:083111ae2a11	472	\brief Set Base Priority (non-secure)
saloutos	0:083111ae2a11	473	\details Assigns the given value to the non-secure Base Priority register when in secure state.
saloutos	0:083111ae2a11	474	\param [in] basePri Base Priority value to set
saloutos	0:083111ae2a11	475	*/
saloutos	0:083111ae2a11	476	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
saloutos	0:083111ae2a11	477	{
saloutos	0:083111ae2a11	478	__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
saloutos	0:083111ae2a11	479	}
saloutos	0:083111ae2a11	480	#endif
saloutos	0:083111ae2a11	481
saloutos	0:083111ae2a11	482
saloutos	0:083111ae2a11	483	/**
saloutos	0:083111ae2a11	484	\brief Set Base Priority with condition
saloutos	0:083111ae2a11	485	\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
saloutos	0:083111ae2a11	486	or the new value increases the BASEPRI priority level.
saloutos	0:083111ae2a11	487	\param [in] basePri Base Priority value to set
saloutos	0:083111ae2a11	488	*/
saloutos	0:083111ae2a11	489	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
saloutos	0:083111ae2a11	490	{
saloutos	0:083111ae2a11	491	__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
saloutos	0:083111ae2a11	492	}
saloutos	0:083111ae2a11	493
saloutos	0:083111ae2a11	494
saloutos	0:083111ae2a11	495	/**
saloutos	0:083111ae2a11	496	\brief Get Fault Mask
saloutos	0:083111ae2a11	497	\details Returns the current value of the Fault Mask register.
saloutos	0:083111ae2a11	498	\return Fault Mask register value
saloutos	0:083111ae2a11	499	*/
saloutos	0:083111ae2a11	500	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
saloutos	0:083111ae2a11	501	{
saloutos	0:083111ae2a11	502	uint32_t result;
saloutos	0:083111ae2a11	503
saloutos	0:083111ae2a11	504	__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
saloutos	0:083111ae2a11	505	return(result);
saloutos	0:083111ae2a11	506	}
saloutos	0:083111ae2a11	507
saloutos	0:083111ae2a11	508
saloutos	0:083111ae2a11	509	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos	0:083111ae2a11	510	/**
saloutos	0:083111ae2a11	511	\brief Get Fault Mask (non-secure)
saloutos	0:083111ae2a11	512	\details Returns the current value of the non-secure Fault Mask register when in secure state.
saloutos	0:083111ae2a11	513	\return Fault Mask register value
saloutos	0:083111ae2a11	514	*/
saloutos	0:083111ae2a11	515	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
saloutos	0:083111ae2a11	516	{
saloutos	0:083111ae2a11	517	uint32_t result;
saloutos	0:083111ae2a11	518
saloutos	0:083111ae2a11	519	__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
saloutos	0:083111ae2a11	520	return(result);
saloutos	0:083111ae2a11	521	}
saloutos	0:083111ae2a11	522	#endif
saloutos	0:083111ae2a11	523
saloutos	0:083111ae2a11	524
saloutos	0:083111ae2a11	525	/**
saloutos	0:083111ae2a11	526	\brief Set Fault Mask
saloutos	0:083111ae2a11	527	\details Assigns the given value to the Fault Mask register.
saloutos	0:083111ae2a11	528	\param [in] faultMask Fault Mask value to set
saloutos	0:083111ae2a11	529	*/
saloutos	0:083111ae2a11	530	__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
saloutos	0:083111ae2a11	531	{
saloutos	0:083111ae2a11	532	__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
saloutos	0:083111ae2a11	533	}
saloutos	0:083111ae2a11	534
saloutos	0:083111ae2a11	535
saloutos	0:083111ae2a11	536	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
saloutos	0:083111ae2a11	537	/**
saloutos	0:083111ae2a11	538	\brief Set Fault Mask (non-secure)
saloutos	0:083111ae2a11	539	\details Assigns the given value to the non-secure Fault Mask register when in secure state.
saloutos	0:083111ae2a11	540	\param [in] faultMask Fault Mask value to set
saloutos	0:083111ae2a11	541	*/
saloutos	0:083111ae2a11	542	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
saloutos	0:083111ae2a11	543	{
saloutos	0:083111ae2a11	544	__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
saloutos	0:083111ae2a11	545	}
saloutos	0:083111ae2a11	546	#endif
saloutos	0:083111ae2a11	547
saloutos	0:083111ae2a11	548	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
saloutos	0:083111ae2a11	549	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
saloutos	0:083111ae2a11	550	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
saloutos	0:083111ae2a11	551
saloutos	0:083111ae2a11	552
saloutos	0:083111ae2a11	553	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
saloutos	0:083111ae2a11	554	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
saloutos	0:083111ae2a11	555
saloutos	0:083111ae2a11	556	/**
saloutos	0:083111ae2a11	557	\brief Get Process Stack Pointer Limit
saloutos	0:083111ae2a11	558	\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
saloutos	0:083111ae2a11	559	\return PSPLIM Register value
saloutos	0:083111ae2a11	560	*/
saloutos	0:083111ae2a11	561	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
saloutos	0:083111ae2a11	562	{
saloutos	0:083111ae2a11	563	register uint32_t result;
saloutos	0:083111ae2a11	564
saloutos	0:083111ae2a11	565	__ASM volatile ("MRS %0, psplim" : "=r" (result) );
saloutos	0:083111ae2a11	566	return(result);
saloutos	0:083111ae2a11	567	}
saloutos	0:083111ae2a11	568
saloutos	0:083111ae2a11	569
saloutos	0:083111ae2a11	570	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
saloutos	0:083111ae2a11	571	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos	0:083111ae2a11	572	/**
saloutos	0:083111ae2a11	573	\brief Get Process Stack Pointer Limit (non-secure)
saloutos	0:083111ae2a11	574	\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
saloutos	0:083111ae2a11	575	\return PSPLIM Register value
saloutos	0:083111ae2a11	576	*/
saloutos	0:083111ae2a11	577	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
saloutos	0:083111ae2a11	578	{
saloutos	0:083111ae2a11	579	register uint32_t result;
saloutos	0:083111ae2a11	580
saloutos	0:083111ae2a11	581	__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
saloutos	0:083111ae2a11	582	return(result);
saloutos	0:083111ae2a11	583	}
saloutos	0:083111ae2a11	584	#endif
saloutos	0:083111ae2a11	585
saloutos	0:083111ae2a11	586
saloutos	0:083111ae2a11	587	/**
saloutos	0:083111ae2a11	588	\brief Set Process Stack Pointer Limit
saloutos	0:083111ae2a11	589	\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
saloutos	0:083111ae2a11	590	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
saloutos	0:083111ae2a11	591	*/
saloutos	0:083111ae2a11	592	__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
saloutos	0:083111ae2a11	593	{
saloutos	0:083111ae2a11	594	__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
saloutos	0:083111ae2a11	595	}
saloutos	0:083111ae2a11	596
saloutos	0:083111ae2a11	597
saloutos	0:083111ae2a11	598	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
saloutos	0:083111ae2a11	599	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos	0:083111ae2a11	600	/**
saloutos	0:083111ae2a11	601	\brief Set Process Stack Pointer (non-secure)
saloutos	0:083111ae2a11	602	\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
saloutos	0:083111ae2a11	603	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
saloutos	0:083111ae2a11	604	*/
saloutos	0:083111ae2a11	605	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
saloutos	0:083111ae2a11	606	{
saloutos	0:083111ae2a11	607	__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
saloutos	0:083111ae2a11	608	}
saloutos	0:083111ae2a11	609	#endif
saloutos	0:083111ae2a11	610
saloutos	0:083111ae2a11	611
saloutos	0:083111ae2a11	612	/**
saloutos	0:083111ae2a11	613	\brief Get Main Stack Pointer Limit
saloutos	0:083111ae2a11	614	\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
saloutos	0:083111ae2a11	615	\return MSPLIM Register value
saloutos	0:083111ae2a11	616	*/
saloutos	0:083111ae2a11	617	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
saloutos	0:083111ae2a11	618	{
saloutos	0:083111ae2a11	619	register uint32_t result;
saloutos	0:083111ae2a11	620
saloutos	0:083111ae2a11	621	__ASM volatile ("MRS %0, msplim" : "=r" (result) );
saloutos	0:083111ae2a11	622
saloutos	0:083111ae2a11	623	return(result);
saloutos	0:083111ae2a11	624	}
saloutos	0:083111ae2a11	625
saloutos	0:083111ae2a11	626
saloutos	0:083111ae2a11	627	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
saloutos	0:083111ae2a11	628	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos	0:083111ae2a11	629	/**
saloutos	0:083111ae2a11	630	\brief Get Main Stack Pointer Limit (non-secure)
saloutos	0:083111ae2a11	631	\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
saloutos	0:083111ae2a11	632	\return MSPLIM Register value
saloutos	0:083111ae2a11	633	*/
saloutos	0:083111ae2a11	634	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
saloutos	0:083111ae2a11	635	{
saloutos	0:083111ae2a11	636	register uint32_t result;
saloutos	0:083111ae2a11	637
saloutos	0:083111ae2a11	638	__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
saloutos	0:083111ae2a11	639	return(result);
saloutos	0:083111ae2a11	640	}
saloutos	0:083111ae2a11	641	#endif
saloutos	0:083111ae2a11	642
saloutos	0:083111ae2a11	643
saloutos	0:083111ae2a11	644	/**
saloutos	0:083111ae2a11	645	\brief Set Main Stack Pointer Limit
saloutos	0:083111ae2a11	646	\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
saloutos	0:083111ae2a11	647	\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
saloutos	0:083111ae2a11	648	*/
saloutos	0:083111ae2a11	649	__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
saloutos	0:083111ae2a11	650	{
saloutos	0:083111ae2a11	651	__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
saloutos	0:083111ae2a11	652	}
saloutos	0:083111ae2a11	653
saloutos	0:083111ae2a11	654
saloutos	0:083111ae2a11	655	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
saloutos	0:083111ae2a11	656	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos	0:083111ae2a11	657	/**
saloutos	0:083111ae2a11	658	\brief Set Main Stack Pointer Limit (non-secure)
saloutos	0:083111ae2a11	659	\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
saloutos	0:083111ae2a11	660	\param [in] MainStackPtrLimit Main Stack Pointer value to set
saloutos	0:083111ae2a11	661	*/
saloutos	0:083111ae2a11	662	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
saloutos	0:083111ae2a11	663	{
saloutos	0:083111ae2a11	664	__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
saloutos	0:083111ae2a11	665	}
saloutos	0:083111ae2a11	666	#endif
saloutos	0:083111ae2a11	667
saloutos	0:083111ae2a11	668	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
saloutos	0:083111ae2a11	669	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
saloutos	0:083111ae2a11	670
saloutos	0:083111ae2a11	671
saloutos	0:083111ae2a11	672	#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
saloutos	0:083111ae2a11	673	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos	0:083111ae2a11	674
saloutos	0:083111ae2a11	675	/**
saloutos	0:083111ae2a11	676	\brief Get FPSCR
saloutos	0:083111ae2a11	677	\details Returns the current value of the Floating Point Status/Control register.
saloutos	0:083111ae2a11	678	\return Floating Point Status/Control register value
saloutos	0:083111ae2a11	679	*/
saloutos	0:083111ae2a11	680	/* #define __get_FPSCR __builtin_arm_get_fpscr */
saloutos	0:083111ae2a11	681	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
saloutos	0:083111ae2a11	682	{
saloutos	0:083111ae2a11	683	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
saloutos	0:083111ae2a11	684	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
saloutos	0:083111ae2a11	685	uint32_t result;
saloutos	0:083111ae2a11	686
saloutos	0:083111ae2a11	687	__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
saloutos	0:083111ae2a11	688	return(result);
saloutos	0:083111ae2a11	689	#else
saloutos	0:083111ae2a11	690	return(0U);
saloutos	0:083111ae2a11	691	#endif
saloutos	0:083111ae2a11	692	}
saloutos	0:083111ae2a11	693
saloutos	0:083111ae2a11	694
saloutos	0:083111ae2a11	695	/**
saloutos	0:083111ae2a11	696	\brief Set FPSCR
saloutos	0:083111ae2a11	697	\details Assigns the given value to the Floating Point Status/Control register.
saloutos	0:083111ae2a11	698	\param [in] fpscr Floating Point Status/Control value to set
saloutos	0:083111ae2a11	699	*/
saloutos	0:083111ae2a11	700	/* #define __set_FPSCR __builtin_arm_set_fpscr */
saloutos	0:083111ae2a11	701	__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
saloutos	0:083111ae2a11	702	{
saloutos	0:083111ae2a11	703	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
saloutos	0:083111ae2a11	704	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
saloutos	0:083111ae2a11	705	__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
saloutos	0:083111ae2a11	706	#else
saloutos	0:083111ae2a11	707	(void)fpscr;
saloutos	0:083111ae2a11	708	#endif
saloutos	0:083111ae2a11	709	}
saloutos	0:083111ae2a11	710
saloutos	0:083111ae2a11	711	#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
saloutos	0:083111ae2a11	712	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
saloutos	0:083111ae2a11	713
saloutos	0:083111ae2a11	714
saloutos	0:083111ae2a11	715
saloutos	0:083111ae2a11	716	/@} end of CMSIS_Core_RegAccFunctions /
saloutos	0:083111ae2a11	717
saloutos	0:083111ae2a11	718
saloutos	0:083111ae2a11	719	/* ########################## Core Instruction Access ######################### */
saloutos	0:083111ae2a11	720	/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
saloutos	0:083111ae2a11	721	Access to dedicated instructions
saloutos	0:083111ae2a11	722	@{
saloutos	0:083111ae2a11	723	*/
saloutos	0:083111ae2a11	724
saloutos	0:083111ae2a11	725	/* Define macros for porting to both thumb1 and thumb2.
saloutos	0:083111ae2a11	726	* For thumb1, use low register (r0-r7), specified by constraint "l"
saloutos	0:083111ae2a11	727	* Otherwise, use general registers, specified by constraint "r" */
saloutos	0:083111ae2a11	728	#if defined (__thumb__) && !defined (__thumb2__)
saloutos	0:083111ae2a11	729	#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
saloutos	0:083111ae2a11	730	#define __CMSIS_GCC_USE_REG(r) "l" (r)
saloutos	0:083111ae2a11	731	#else
saloutos	0:083111ae2a11	732	#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
saloutos	0:083111ae2a11	733	#define __CMSIS_GCC_USE_REG(r) "r" (r)
saloutos	0:083111ae2a11	734	#endif
saloutos	0:083111ae2a11	735
saloutos	0:083111ae2a11	736	/**
saloutos	0:083111ae2a11	737	\brief No Operation
saloutos	0:083111ae2a11	738	\details No Operation does nothing. This instruction can be used for code alignment purposes.
saloutos	0:083111ae2a11	739	*/
saloutos	0:083111ae2a11	740	#define __NOP __builtin_arm_nop
saloutos	0:083111ae2a11	741
saloutos	0:083111ae2a11	742	/**
saloutos	0:083111ae2a11	743	\brief Wait For Interrupt
saloutos	0:083111ae2a11	744	\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
saloutos	0:083111ae2a11	745	*/
saloutos	0:083111ae2a11	746	#define __WFI __builtin_arm_wfi
saloutos	0:083111ae2a11	747
saloutos	0:083111ae2a11	748
saloutos	0:083111ae2a11	749	/**
saloutos	0:083111ae2a11	750	\brief Wait For Event
saloutos	0:083111ae2a11	751	\details Wait For Event is a hint instruction that permits the processor to enter
saloutos	0:083111ae2a11	752	a low-power state until one of a number of events occurs.
saloutos	0:083111ae2a11	753	*/
saloutos	0:083111ae2a11	754	#define __WFE __builtin_arm_wfe
saloutos	0:083111ae2a11	755
saloutos	0:083111ae2a11	756
saloutos	0:083111ae2a11	757	/**
saloutos	0:083111ae2a11	758	\brief Send Event
saloutos	0:083111ae2a11	759	\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
saloutos	0:083111ae2a11	760	*/
saloutos	0:083111ae2a11	761	#define __SEV __builtin_arm_sev
saloutos	0:083111ae2a11	762
saloutos	0:083111ae2a11	763
saloutos	0:083111ae2a11	764	/**
saloutos	0:083111ae2a11	765	\brief Instruction Synchronization Barrier
saloutos	0:083111ae2a11	766	\details Instruction Synchronization Barrier flushes the pipeline in the processor,
saloutos	0:083111ae2a11	767	so that all instructions following the ISB are fetched from cache or memory,
saloutos	0:083111ae2a11	768	after the instruction has been completed.
saloutos	0:083111ae2a11	769	*/
saloutos	0:083111ae2a11	770	#define __ISB() __builtin_arm_isb(0xF);
saloutos	0:083111ae2a11	771
saloutos	0:083111ae2a11	772	/**
saloutos	0:083111ae2a11	773	\brief Data Synchronization Barrier
saloutos	0:083111ae2a11	774	\details Acts as a special kind of Data Memory Barrier.
saloutos	0:083111ae2a11	775	It completes when all explicit memory accesses before this instruction complete.
saloutos	0:083111ae2a11	776	*/
saloutos	0:083111ae2a11	777	#define __DSB() __builtin_arm_dsb(0xF);
saloutos	0:083111ae2a11	778
saloutos	0:083111ae2a11	779
saloutos	0:083111ae2a11	780	/**
saloutos	0:083111ae2a11	781	\brief Data Memory Barrier
saloutos	0:083111ae2a11	782	\details Ensures the apparent order of the explicit memory operations before
saloutos	0:083111ae2a11	783	and after the instruction, without ensuring their completion.
saloutos	0:083111ae2a11	784	*/
saloutos	0:083111ae2a11	785	#define __DMB() __builtin_arm_dmb(0xF);
saloutos	0:083111ae2a11	786
saloutos	0:083111ae2a11	787
saloutos	0:083111ae2a11	788	/**
saloutos	0:083111ae2a11	789	\brief Reverse byte order (32 bit)
saloutos	0:083111ae2a11	790	\details Reverses the byte order in integer value.
saloutos	0:083111ae2a11	791	\param [in] value Value to reverse
saloutos	0:083111ae2a11	792	\return Reversed value
saloutos	0:083111ae2a11	793	*/
saloutos	0:083111ae2a11	794	#define __REV __builtin_bswap32
saloutos	0:083111ae2a11	795
saloutos	0:083111ae2a11	796
saloutos	0:083111ae2a11	797	/**
saloutos	0:083111ae2a11	798	\brief Reverse byte order (16 bit)
saloutos	0:083111ae2a11	799	\details Reverses the byte order in two unsigned short values.
saloutos	0:083111ae2a11	800	\param [in] value Value to reverse
saloutos	0:083111ae2a11	801	\return Reversed value
saloutos	0:083111ae2a11	802	*/
saloutos	0:083111ae2a11	803	#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
saloutos	0:083111ae2a11	804	#if 0
saloutos	0:083111ae2a11	805	__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
saloutos	0:083111ae2a11	806	{
saloutos	0:083111ae2a11	807	uint32_t result;
saloutos	0:083111ae2a11	808
saloutos	0:083111ae2a11	809	__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
saloutos	0:083111ae2a11	810	return(result);
saloutos	0:083111ae2a11	811	}
saloutos	0:083111ae2a11	812	#endif
saloutos	0:083111ae2a11	813
saloutos	0:083111ae2a11	814
saloutos	0:083111ae2a11	815	/**
saloutos	0:083111ae2a11	816	\brief Reverse byte order in signed short value
saloutos	0:083111ae2a11	817	\details Reverses the byte order in a signed short value with sign extension to integer.
saloutos	0:083111ae2a11	818	\param [in] value Value to reverse
saloutos	0:083111ae2a11	819	\return Reversed value
saloutos	0:083111ae2a11	820	*/
saloutos	0:083111ae2a11	821	/* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
saloutos	0:083111ae2a11	822	__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
saloutos	0:083111ae2a11	823	{
saloutos	0:083111ae2a11	824	int32_t result;
saloutos	0:083111ae2a11	825
saloutos	0:083111ae2a11	826	__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
saloutos	0:083111ae2a11	827	return(result);
saloutos	0:083111ae2a11	828	}
saloutos	0:083111ae2a11	829
saloutos	0:083111ae2a11	830
saloutos	0:083111ae2a11	831	/**
saloutos	0:083111ae2a11	832	\brief Rotate Right in unsigned value (32 bit)
saloutos	0:083111ae2a11	833	\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
saloutos	0:083111ae2a11	834	\param [in] op1 Value to rotate
saloutos	0:083111ae2a11	835	\param [in] op2 Number of Bits to rotate
saloutos	0:083111ae2a11	836	\return Rotated value
saloutos	0:083111ae2a11	837	*/
saloutos	0:083111ae2a11	838	__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	839	{
saloutos	0:083111ae2a11	840	return (op1 >> op2) \| (op1 << (32U - op2));
saloutos	0:083111ae2a11	841	}
saloutos	0:083111ae2a11	842
saloutos	0:083111ae2a11	843
saloutos	0:083111ae2a11	844	/**
saloutos	0:083111ae2a11	845	\brief Breakpoint
saloutos	0:083111ae2a11	846	\details Causes the processor to enter Debug state.
saloutos	0:083111ae2a11	847	Debug tools can use this to investigate system state when the instruction at a particular address is reached.
saloutos	0:083111ae2a11	848	\param [in] value is ignored by the processor.
saloutos	0:083111ae2a11	849	If required, a debugger can use it to store additional information about the breakpoint.
saloutos	0:083111ae2a11	850	*/
saloutos	0:083111ae2a11	851	#define __BKPT(value) __ASM volatile ("bkpt "#value)
saloutos	0:083111ae2a11	852
saloutos	0:083111ae2a11	853
saloutos	0:083111ae2a11	854	/**
saloutos	0:083111ae2a11	855	\brief Reverse bit order of value
saloutos	0:083111ae2a11	856	\details Reverses the bit order of the given value.
saloutos	0:083111ae2a11	857	\param [in] value Value to reverse
saloutos	0:083111ae2a11	858	\return Reversed value
saloutos	0:083111ae2a11	859	*/
saloutos	0:083111ae2a11	860	/* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
saloutos	0:083111ae2a11	861	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
saloutos	0:083111ae2a11	862	{
saloutos	0:083111ae2a11	863	uint32_t result;
saloutos	0:083111ae2a11	864
saloutos	0:083111ae2a11	865	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
saloutos	0:083111ae2a11	866	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
saloutos	0:083111ae2a11	867	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos	0:083111ae2a11	868	__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
saloutos	0:083111ae2a11	869	#else
saloutos	0:083111ae2a11	870	int32_t s = (4 /sizeof(v)/ * 8) - 1; /* extra shift needed at end */
saloutos	0:083111ae2a11	871
saloutos	0:083111ae2a11	872	result = value; /* r will be reversed bits of v; first get LSB of v */
saloutos	0:083111ae2a11	873	for (value >>= 1U; value; value >>= 1U)
saloutos	0:083111ae2a11	874	{
saloutos	0:083111ae2a11	875	result <<= 1U;
saloutos	0:083111ae2a11	876	result \|= value & 1U;
saloutos	0:083111ae2a11	877	s--;
saloutos	0:083111ae2a11	878	}
saloutos	0:083111ae2a11	879	result <<= s; /* shift when v's highest bits are zero */
saloutos	0:083111ae2a11	880	#endif
saloutos	0:083111ae2a11	881	return(result);
saloutos	0:083111ae2a11	882	}
saloutos	0:083111ae2a11	883
saloutos	0:083111ae2a11	884
saloutos	0:083111ae2a11	885	/**
saloutos	0:083111ae2a11	886	\brief Count leading zeros
saloutos	0:083111ae2a11	887	\details Counts the number of leading zeros of a data value.
saloutos	0:083111ae2a11	888	\param [in] value Value to count the leading zeros
saloutos	0:083111ae2a11	889	\return number of leading zeros in value
saloutos	0:083111ae2a11	890	*/
saloutos	0:083111ae2a11	891	#define __CLZ __builtin_clz
saloutos	0:083111ae2a11	892
saloutos	0:083111ae2a11	893
saloutos	0:083111ae2a11	894	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
saloutos	0:083111ae2a11	895	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
saloutos	0:083111ae2a11	896	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
saloutos	0:083111ae2a11	897	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
saloutos	0:083111ae2a11	898	/**
saloutos	0:083111ae2a11	899	\brief LDR Exclusive (8 bit)
saloutos	0:083111ae2a11	900	\details Executes a exclusive LDR instruction for 8 bit value.
saloutos	0:083111ae2a11	901	\param [in] ptr Pointer to data
saloutos	0:083111ae2a11	902	\return value of type uint8_t at (*ptr)
saloutos	0:083111ae2a11	903	*/
saloutos	0:083111ae2a11	904	#define __LDREXB (uint8_t)__builtin_arm_ldrex
saloutos	0:083111ae2a11	905
saloutos	0:083111ae2a11	906
saloutos	0:083111ae2a11	907	/**
saloutos	0:083111ae2a11	908	\brief LDR Exclusive (16 bit)
saloutos	0:083111ae2a11	909	\details Executes a exclusive LDR instruction for 16 bit values.
saloutos	0:083111ae2a11	910	\param [in] ptr Pointer to data
saloutos	0:083111ae2a11	911	\return value of type uint16_t at (*ptr)
saloutos	0:083111ae2a11	912	*/
saloutos	0:083111ae2a11	913	#define __LDREXH (uint16_t)__builtin_arm_ldrex
saloutos	0:083111ae2a11	914
saloutos	0:083111ae2a11	915
saloutos	0:083111ae2a11	916	/**
saloutos	0:083111ae2a11	917	\brief LDR Exclusive (32 bit)
saloutos	0:083111ae2a11	918	\details Executes a exclusive LDR instruction for 32 bit values.
saloutos	0:083111ae2a11	919	\param [in] ptr Pointer to data
saloutos	0:083111ae2a11	920	\return value of type uint32_t at (*ptr)
saloutos	0:083111ae2a11	921	*/
saloutos	0:083111ae2a11	922	#define __LDREXW (uint32_t)__builtin_arm_ldrex
saloutos	0:083111ae2a11	923
saloutos	0:083111ae2a11	924
saloutos	0:083111ae2a11	925	/**
saloutos	0:083111ae2a11	926	\brief STR Exclusive (8 bit)
saloutos	0:083111ae2a11	927	\details Executes a exclusive STR instruction for 8 bit values.
saloutos	0:083111ae2a11	928	\param [in] value Value to store
saloutos	0:083111ae2a11	929	\param [in] ptr Pointer to location
saloutos	0:083111ae2a11	930	\return 0 Function succeeded
saloutos	0:083111ae2a11	931	\return 1 Function failed
saloutos	0:083111ae2a11	932	*/
saloutos	0:083111ae2a11	933	#define __STREXB (uint32_t)__builtin_arm_strex
saloutos	0:083111ae2a11	934
saloutos	0:083111ae2a11	935
saloutos	0:083111ae2a11	936	/**
saloutos	0:083111ae2a11	937	\brief STR Exclusive (16 bit)
saloutos	0:083111ae2a11	938	\details Executes a exclusive STR instruction for 16 bit values.
saloutos	0:083111ae2a11	939	\param [in] value Value to store
saloutos	0:083111ae2a11	940	\param [in] ptr Pointer to location
saloutos	0:083111ae2a11	941	\return 0 Function succeeded
saloutos	0:083111ae2a11	942	\return 1 Function failed
saloutos	0:083111ae2a11	943	*/
saloutos	0:083111ae2a11	944	#define __STREXH (uint32_t)__builtin_arm_strex
saloutos	0:083111ae2a11	945
saloutos	0:083111ae2a11	946
saloutos	0:083111ae2a11	947	/**
saloutos	0:083111ae2a11	948	\brief STR Exclusive (32 bit)
saloutos	0:083111ae2a11	949	\details Executes a exclusive STR instruction for 32 bit values.
saloutos	0:083111ae2a11	950	\param [in] value Value to store
saloutos	0:083111ae2a11	951	\param [in] ptr Pointer to location
saloutos	0:083111ae2a11	952	\return 0 Function succeeded
saloutos	0:083111ae2a11	953	\return 1 Function failed
saloutos	0:083111ae2a11	954	*/
saloutos	0:083111ae2a11	955	#define __STREXW (uint32_t)__builtin_arm_strex
saloutos	0:083111ae2a11	956
saloutos	0:083111ae2a11	957
saloutos	0:083111ae2a11	958	/**
saloutos	0:083111ae2a11	959	\brief Remove the exclusive lock
saloutos	0:083111ae2a11	960	\details Removes the exclusive lock which is created by LDREX.
saloutos	0:083111ae2a11	961	*/
saloutos	0:083111ae2a11	962	#define __CLREX __builtin_arm_clrex
saloutos	0:083111ae2a11	963
saloutos	0:083111ae2a11	964	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
saloutos	0:083111ae2a11	965	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
saloutos	0:083111ae2a11	966	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
saloutos	0:083111ae2a11	967	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
saloutos	0:083111ae2a11	968
saloutos	0:083111ae2a11	969
saloutos	0:083111ae2a11	970	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
saloutos	0:083111ae2a11	971	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
saloutos	0:083111ae2a11	972	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
saloutos	0:083111ae2a11	973	/**
saloutos	0:083111ae2a11	974	\brief Signed Saturate
saloutos	0:083111ae2a11	975	\details Saturates a signed value.
saloutos	0:083111ae2a11	976	\param [in] value Value to be saturated
saloutos	0:083111ae2a11	977	\param [in] sat Bit position to saturate to (1..32)
saloutos	0:083111ae2a11	978	\return Saturated value
saloutos	0:083111ae2a11	979	*/
saloutos	0:083111ae2a11	980	#define __SSAT __builtin_arm_ssat
saloutos	0:083111ae2a11	981
saloutos	0:083111ae2a11	982
saloutos	0:083111ae2a11	983	/**
saloutos	0:083111ae2a11	984	\brief Unsigned Saturate
saloutos	0:083111ae2a11	985	\details Saturates an unsigned value.
saloutos	0:083111ae2a11	986	\param [in] value Value to be saturated
saloutos	0:083111ae2a11	987	\param [in] sat Bit position to saturate to (0..31)
saloutos	0:083111ae2a11	988	\return Saturated value
saloutos	0:083111ae2a11	989	*/
saloutos	0:083111ae2a11	990	#define __USAT __builtin_arm_usat
saloutos	0:083111ae2a11	991
saloutos	0:083111ae2a11	992
saloutos	0:083111ae2a11	993	/**
saloutos	0:083111ae2a11	994	\brief Rotate Right with Extend (32 bit)
saloutos	0:083111ae2a11	995	\details Moves each bit of a bitstring right by one bit.
saloutos	0:083111ae2a11	996	The carry input is shifted in at the left end of the bitstring.
saloutos	0:083111ae2a11	997	\param [in] value Value to rotate
saloutos	0:083111ae2a11	998	\return Rotated value
saloutos	0:083111ae2a11	999	*/
saloutos	0:083111ae2a11	1000	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
saloutos	0:083111ae2a11	1001	{
saloutos	0:083111ae2a11	1002	uint32_t result;
saloutos	0:083111ae2a11	1003
saloutos	0:083111ae2a11	1004	__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
saloutos	0:083111ae2a11	1005	return(result);
saloutos	0:083111ae2a11	1006	}
saloutos	0:083111ae2a11	1007
saloutos	0:083111ae2a11	1008
saloutos	0:083111ae2a11	1009	/**
saloutos	0:083111ae2a11	1010	\brief LDRT Unprivileged (8 bit)
saloutos	0:083111ae2a11	1011	\details Executes a Unprivileged LDRT instruction for 8 bit value.
saloutos	0:083111ae2a11	1012	\param [in] ptr Pointer to data
saloutos	0:083111ae2a11	1013	\return value of type uint8_t at (*ptr)
saloutos	0:083111ae2a11	1014	*/
saloutos	0:083111ae2a11	1015	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
saloutos	0:083111ae2a11	1016	{
saloutos	0:083111ae2a11	1017	uint32_t result;
saloutos	0:083111ae2a11	1018
saloutos	0:083111ae2a11	1019	__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos	0:083111ae2a11	1020	return ((uint8_t) result); /* Add explicit type cast here */
saloutos	0:083111ae2a11	1021	}
saloutos	0:083111ae2a11	1022
saloutos	0:083111ae2a11	1023
saloutos	0:083111ae2a11	1024	/**
saloutos	0:083111ae2a11	1025	\brief LDRT Unprivileged (16 bit)
saloutos	0:083111ae2a11	1026	\details Executes a Unprivileged LDRT instruction for 16 bit values.
saloutos	0:083111ae2a11	1027	\param [in] ptr Pointer to data
saloutos	0:083111ae2a11	1028	\return value of type uint16_t at (*ptr)
saloutos	0:083111ae2a11	1029	*/
saloutos	0:083111ae2a11	1030	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
saloutos	0:083111ae2a11	1031	{
saloutos	0:083111ae2a11	1032	uint32_t result;
saloutos	0:083111ae2a11	1033
saloutos	0:083111ae2a11	1034	__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos	0:083111ae2a11	1035	return ((uint16_t) result); /* Add explicit type cast here */
saloutos	0:083111ae2a11	1036	}
saloutos	0:083111ae2a11	1037
saloutos	0:083111ae2a11	1038
saloutos	0:083111ae2a11	1039	/**
saloutos	0:083111ae2a11	1040	\brief LDRT Unprivileged (32 bit)
saloutos	0:083111ae2a11	1041	\details Executes a Unprivileged LDRT instruction for 32 bit values.
saloutos	0:083111ae2a11	1042	\param [in] ptr Pointer to data
saloutos	0:083111ae2a11	1043	\return value of type uint32_t at (*ptr)
saloutos	0:083111ae2a11	1044	*/
saloutos	0:083111ae2a11	1045	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
saloutos	0:083111ae2a11	1046	{
saloutos	0:083111ae2a11	1047	uint32_t result;
saloutos	0:083111ae2a11	1048
saloutos	0:083111ae2a11	1049	__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos	0:083111ae2a11	1050	return(result);
saloutos	0:083111ae2a11	1051	}
saloutos	0:083111ae2a11	1052
saloutos	0:083111ae2a11	1053
saloutos	0:083111ae2a11	1054	/**
saloutos	0:083111ae2a11	1055	\brief STRT Unprivileged (8 bit)
saloutos	0:083111ae2a11	1056	\details Executes a Unprivileged STRT instruction for 8 bit values.
saloutos	0:083111ae2a11	1057	\param [in] value Value to store
saloutos	0:083111ae2a11	1058	\param [in] ptr Pointer to location
saloutos	0:083111ae2a11	1059	*/
saloutos	0:083111ae2a11	1060	__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
saloutos	0:083111ae2a11	1061	{
saloutos	0:083111ae2a11	1062	__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
saloutos	0:083111ae2a11	1063	}
saloutos	0:083111ae2a11	1064
saloutos	0:083111ae2a11	1065
saloutos	0:083111ae2a11	1066	/**
saloutos	0:083111ae2a11	1067	\brief STRT Unprivileged (16 bit)
saloutos	0:083111ae2a11	1068	\details Executes a Unprivileged STRT instruction for 16 bit values.
saloutos	0:083111ae2a11	1069	\param [in] value Value to store
saloutos	0:083111ae2a11	1070	\param [in] ptr Pointer to location
saloutos	0:083111ae2a11	1071	*/
saloutos	0:083111ae2a11	1072	__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
saloutos	0:083111ae2a11	1073	{
saloutos	0:083111ae2a11	1074	__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
saloutos	0:083111ae2a11	1075	}
saloutos	0:083111ae2a11	1076
saloutos	0:083111ae2a11	1077
saloutos	0:083111ae2a11	1078	/**
saloutos	0:083111ae2a11	1079	\brief STRT Unprivileged (32 bit)
saloutos	0:083111ae2a11	1080	\details Executes a Unprivileged STRT instruction for 32 bit values.
saloutos	0:083111ae2a11	1081	\param [in] value Value to store
saloutos	0:083111ae2a11	1082	\param [in] ptr Pointer to location
saloutos	0:083111ae2a11	1083	*/
saloutos	0:083111ae2a11	1084	__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
saloutos	0:083111ae2a11	1085	{
saloutos	0:083111ae2a11	1086	__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
saloutos	0:083111ae2a11	1087	}
saloutos	0:083111ae2a11	1088
saloutos	0:083111ae2a11	1089	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
saloutos	0:083111ae2a11	1090	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
saloutos	0:083111ae2a11	1091	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
saloutos	0:083111ae2a11	1092
saloutos	0:083111ae2a11	1093
saloutos	0:083111ae2a11	1094	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
saloutos	0:083111ae2a11	1095	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
saloutos	0:083111ae2a11	1096	/**
saloutos	0:083111ae2a11	1097	\brief Load-Acquire (8 bit)
saloutos	0:083111ae2a11	1098	\details Executes a LDAB instruction for 8 bit value.
saloutos	0:083111ae2a11	1099	\param [in] ptr Pointer to data
saloutos	0:083111ae2a11	1100	\return value of type uint8_t at (*ptr)
saloutos	0:083111ae2a11	1101	*/
saloutos	0:083111ae2a11	1102	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
saloutos	0:083111ae2a11	1103	{
saloutos	0:083111ae2a11	1104	uint32_t result;
saloutos	0:083111ae2a11	1105
saloutos	0:083111ae2a11	1106	__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos	0:083111ae2a11	1107	return ((uint8_t) result);
saloutos	0:083111ae2a11	1108	}
saloutos	0:083111ae2a11	1109
saloutos	0:083111ae2a11	1110
saloutos	0:083111ae2a11	1111	/**
saloutos	0:083111ae2a11	1112	\brief Load-Acquire (16 bit)
saloutos	0:083111ae2a11	1113	\details Executes a LDAH instruction for 16 bit values.
saloutos	0:083111ae2a11	1114	\param [in] ptr Pointer to data
saloutos	0:083111ae2a11	1115	\return value of type uint16_t at (*ptr)
saloutos	0:083111ae2a11	1116	*/
saloutos	0:083111ae2a11	1117	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
saloutos	0:083111ae2a11	1118	{
saloutos	0:083111ae2a11	1119	uint32_t result;
saloutos	0:083111ae2a11	1120
saloutos	0:083111ae2a11	1121	__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos	0:083111ae2a11	1122	return ((uint16_t) result);
saloutos	0:083111ae2a11	1123	}
saloutos	0:083111ae2a11	1124
saloutos	0:083111ae2a11	1125
saloutos	0:083111ae2a11	1126	/**
saloutos	0:083111ae2a11	1127	\brief Load-Acquire (32 bit)
saloutos	0:083111ae2a11	1128	\details Executes a LDA instruction for 32 bit values.
saloutos	0:083111ae2a11	1129	\param [in] ptr Pointer to data
saloutos	0:083111ae2a11	1130	\return value of type uint32_t at (*ptr)
saloutos	0:083111ae2a11	1131	*/
saloutos	0:083111ae2a11	1132	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
saloutos	0:083111ae2a11	1133	{
saloutos	0:083111ae2a11	1134	uint32_t result;
saloutos	0:083111ae2a11	1135
saloutos	0:083111ae2a11	1136	__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
saloutos	0:083111ae2a11	1137	return(result);
saloutos	0:083111ae2a11	1138	}
saloutos	0:083111ae2a11	1139
saloutos	0:083111ae2a11	1140
saloutos	0:083111ae2a11	1141	/**
saloutos	0:083111ae2a11	1142	\brief Store-Release (8 bit)
saloutos	0:083111ae2a11	1143	\details Executes a STLB instruction for 8 bit values.
saloutos	0:083111ae2a11	1144	\param [in] value Value to store
saloutos	0:083111ae2a11	1145	\param [in] ptr Pointer to location
saloutos	0:083111ae2a11	1146	*/
saloutos	0:083111ae2a11	1147	__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
saloutos	0:083111ae2a11	1148	{
saloutos	0:083111ae2a11	1149	__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
saloutos	0:083111ae2a11	1150	}
saloutos	0:083111ae2a11	1151
saloutos	0:083111ae2a11	1152
saloutos	0:083111ae2a11	1153	/**
saloutos	0:083111ae2a11	1154	\brief Store-Release (16 bit)
saloutos	0:083111ae2a11	1155	\details Executes a STLH instruction for 16 bit values.
saloutos	0:083111ae2a11	1156	\param [in] value Value to store
saloutos	0:083111ae2a11	1157	\param [in] ptr Pointer to location
saloutos	0:083111ae2a11	1158	*/
saloutos	0:083111ae2a11	1159	__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
saloutos	0:083111ae2a11	1160	{
saloutos	0:083111ae2a11	1161	__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
saloutos	0:083111ae2a11	1162	}
saloutos	0:083111ae2a11	1163
saloutos	0:083111ae2a11	1164
saloutos	0:083111ae2a11	1165	/**
saloutos	0:083111ae2a11	1166	\brief Store-Release (32 bit)
saloutos	0:083111ae2a11	1167	\details Executes a STL instruction for 32 bit values.
saloutos	0:083111ae2a11	1168	\param [in] value Value to store
saloutos	0:083111ae2a11	1169	\param [in] ptr Pointer to location
saloutos	0:083111ae2a11	1170	*/
saloutos	0:083111ae2a11	1171	__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
saloutos	0:083111ae2a11	1172	{
saloutos	0:083111ae2a11	1173	__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
saloutos	0:083111ae2a11	1174	}
saloutos	0:083111ae2a11	1175
saloutos	0:083111ae2a11	1176
saloutos	0:083111ae2a11	1177	/**
saloutos	0:083111ae2a11	1178	\brief Load-Acquire Exclusive (8 bit)
saloutos	0:083111ae2a11	1179	\details Executes a LDAB exclusive instruction for 8 bit value.
saloutos	0:083111ae2a11	1180	\param [in] ptr Pointer to data
saloutos	0:083111ae2a11	1181	\return value of type uint8_t at (*ptr)
saloutos	0:083111ae2a11	1182	*/
saloutos	0:083111ae2a11	1183	#define __LDAEXB (uint8_t)__builtin_arm_ldaex
saloutos	0:083111ae2a11	1184
saloutos	0:083111ae2a11	1185
saloutos	0:083111ae2a11	1186	/**
saloutos	0:083111ae2a11	1187	\brief Load-Acquire Exclusive (16 bit)
saloutos	0:083111ae2a11	1188	\details Executes a LDAH exclusive instruction for 16 bit values.
saloutos	0:083111ae2a11	1189	\param [in] ptr Pointer to data
saloutos	0:083111ae2a11	1190	\return value of type uint16_t at (*ptr)
saloutos	0:083111ae2a11	1191	*/
saloutos	0:083111ae2a11	1192	#define __LDAEXH (uint16_t)__builtin_arm_ldaex
saloutos	0:083111ae2a11	1193
saloutos	0:083111ae2a11	1194
saloutos	0:083111ae2a11	1195	/**
saloutos	0:083111ae2a11	1196	\brief Load-Acquire Exclusive (32 bit)
saloutos	0:083111ae2a11	1197	\details Executes a LDA exclusive instruction for 32 bit values.
saloutos	0:083111ae2a11	1198	\param [in] ptr Pointer to data
saloutos	0:083111ae2a11	1199	\return value of type uint32_t at (*ptr)
saloutos	0:083111ae2a11	1200	*/
saloutos	0:083111ae2a11	1201	#define __LDAEX (uint32_t)__builtin_arm_ldaex
saloutos	0:083111ae2a11	1202
saloutos	0:083111ae2a11	1203
saloutos	0:083111ae2a11	1204	/**
saloutos	0:083111ae2a11	1205	\brief Store-Release Exclusive (8 bit)
saloutos	0:083111ae2a11	1206	\details Executes a STLB exclusive instruction for 8 bit values.
saloutos	0:083111ae2a11	1207	\param [in] value Value to store
saloutos	0:083111ae2a11	1208	\param [in] ptr Pointer to location
saloutos	0:083111ae2a11	1209	\return 0 Function succeeded
saloutos	0:083111ae2a11	1210	\return 1 Function failed
saloutos	0:083111ae2a11	1211	*/
saloutos	0:083111ae2a11	1212	#define __STLEXB (uint32_t)__builtin_arm_stlex
saloutos	0:083111ae2a11	1213
saloutos	0:083111ae2a11	1214
saloutos	0:083111ae2a11	1215	/**
saloutos	0:083111ae2a11	1216	\brief Store-Release Exclusive (16 bit)
saloutos	0:083111ae2a11	1217	\details Executes a STLH exclusive instruction for 16 bit values.
saloutos	0:083111ae2a11	1218	\param [in] value Value to store
saloutos	0:083111ae2a11	1219	\param [in] ptr Pointer to location
saloutos	0:083111ae2a11	1220	\return 0 Function succeeded
saloutos	0:083111ae2a11	1221	\return 1 Function failed
saloutos	0:083111ae2a11	1222	*/
saloutos	0:083111ae2a11	1223	#define __STLEXH (uint32_t)__builtin_arm_stlex
saloutos	0:083111ae2a11	1224
saloutos	0:083111ae2a11	1225
saloutos	0:083111ae2a11	1226	/**
saloutos	0:083111ae2a11	1227	\brief Store-Release Exclusive (32 bit)
saloutos	0:083111ae2a11	1228	\details Executes a STL exclusive instruction for 32 bit values.
saloutos	0:083111ae2a11	1229	\param [in] value Value to store
saloutos	0:083111ae2a11	1230	\param [in] ptr Pointer to location
saloutos	0:083111ae2a11	1231	\return 0 Function succeeded
saloutos	0:083111ae2a11	1232	\return 1 Function failed
saloutos	0:083111ae2a11	1233	*/
saloutos	0:083111ae2a11	1234	#define __STLEX (uint32_t)__builtin_arm_stlex
saloutos	0:083111ae2a11	1235
saloutos	0:083111ae2a11	1236	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
saloutos	0:083111ae2a11	1237	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
saloutos	0:083111ae2a11	1238
saloutos	0:083111ae2a11	1239	/@}/ /* end of group CMSIS_Core_InstructionInterface */
saloutos	0:083111ae2a11	1240
saloutos	0:083111ae2a11	1241
saloutos	0:083111ae2a11	1242	/* ################### Compiler specific Intrinsics ########################### */
saloutos	0:083111ae2a11	1243	/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
saloutos	0:083111ae2a11	1244	Access to dedicated SIMD instructions
saloutos	0:083111ae2a11	1245	@{
saloutos	0:083111ae2a11	1246	*/
saloutos	0:083111ae2a11	1247
saloutos	0:083111ae2a11	1248	#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
saloutos	0:083111ae2a11	1249
saloutos	0:083111ae2a11	1250	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1251	{
saloutos	0:083111ae2a11	1252	uint32_t result;
saloutos	0:083111ae2a11	1253
saloutos	0:083111ae2a11	1254	__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1255	return(result);
saloutos	0:083111ae2a11	1256	}
saloutos	0:083111ae2a11	1257
saloutos	0:083111ae2a11	1258	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1259	{
saloutos	0:083111ae2a11	1260	uint32_t result;
saloutos	0:083111ae2a11	1261
saloutos	0:083111ae2a11	1262	__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1263	return(result);
saloutos	0:083111ae2a11	1264	}
saloutos	0:083111ae2a11	1265
saloutos	0:083111ae2a11	1266	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1267	{
saloutos	0:083111ae2a11	1268	uint32_t result;
saloutos	0:083111ae2a11	1269
saloutos	0:083111ae2a11	1270	__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1271	return(result);
saloutos	0:083111ae2a11	1272	}
saloutos	0:083111ae2a11	1273
saloutos	0:083111ae2a11	1274	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1275	{
saloutos	0:083111ae2a11	1276	uint32_t result;
saloutos	0:083111ae2a11	1277
saloutos	0:083111ae2a11	1278	__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1279	return(result);
saloutos	0:083111ae2a11	1280	}
saloutos	0:083111ae2a11	1281
saloutos	0:083111ae2a11	1282	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1283	{
saloutos	0:083111ae2a11	1284	uint32_t result;
saloutos	0:083111ae2a11	1285
saloutos	0:083111ae2a11	1286	__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1287	return(result);
saloutos	0:083111ae2a11	1288	}
saloutos	0:083111ae2a11	1289
saloutos	0:083111ae2a11	1290	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1291	{
saloutos	0:083111ae2a11	1292	uint32_t result;
saloutos	0:083111ae2a11	1293
saloutos	0:083111ae2a11	1294	__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1295	return(result);
saloutos	0:083111ae2a11	1296	}
saloutos	0:083111ae2a11	1297
saloutos	0:083111ae2a11	1298
saloutos	0:083111ae2a11	1299	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1300	{
saloutos	0:083111ae2a11	1301	uint32_t result;
saloutos	0:083111ae2a11	1302
saloutos	0:083111ae2a11	1303	__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1304	return(result);
saloutos	0:083111ae2a11	1305	}
saloutos	0:083111ae2a11	1306
saloutos	0:083111ae2a11	1307	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1308	{
saloutos	0:083111ae2a11	1309	uint32_t result;
saloutos	0:083111ae2a11	1310
saloutos	0:083111ae2a11	1311	__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1312	return(result);
saloutos	0:083111ae2a11	1313	}
saloutos	0:083111ae2a11	1314
saloutos	0:083111ae2a11	1315	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1316	{
saloutos	0:083111ae2a11	1317	uint32_t result;
saloutos	0:083111ae2a11	1318
saloutos	0:083111ae2a11	1319	__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1320	return(result);
saloutos	0:083111ae2a11	1321	}
saloutos	0:083111ae2a11	1322
saloutos	0:083111ae2a11	1323	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1324	{
saloutos	0:083111ae2a11	1325	uint32_t result;
saloutos	0:083111ae2a11	1326
saloutos	0:083111ae2a11	1327	__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1328	return(result);
saloutos	0:083111ae2a11	1329	}
saloutos	0:083111ae2a11	1330
saloutos	0:083111ae2a11	1331	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1332	{
saloutos	0:083111ae2a11	1333	uint32_t result;
saloutos	0:083111ae2a11	1334
saloutos	0:083111ae2a11	1335	__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1336	return(result);
saloutos	0:083111ae2a11	1337	}
saloutos	0:083111ae2a11	1338
saloutos	0:083111ae2a11	1339	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1340	{
saloutos	0:083111ae2a11	1341	uint32_t result;
saloutos	0:083111ae2a11	1342
saloutos	0:083111ae2a11	1343	__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1344	return(result);
saloutos	0:083111ae2a11	1345	}
saloutos	0:083111ae2a11	1346
saloutos	0:083111ae2a11	1347
saloutos	0:083111ae2a11	1348	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1349	{
saloutos	0:083111ae2a11	1350	uint32_t result;
saloutos	0:083111ae2a11	1351
saloutos	0:083111ae2a11	1352	__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1353	return(result);
saloutos	0:083111ae2a11	1354	}
saloutos	0:083111ae2a11	1355
saloutos	0:083111ae2a11	1356	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1357	{
saloutos	0:083111ae2a11	1358	uint32_t result;
saloutos	0:083111ae2a11	1359
saloutos	0:083111ae2a11	1360	__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1361	return(result);
saloutos	0:083111ae2a11	1362	}
saloutos	0:083111ae2a11	1363
saloutos	0:083111ae2a11	1364	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1365	{
saloutos	0:083111ae2a11	1366	uint32_t result;
saloutos	0:083111ae2a11	1367
saloutos	0:083111ae2a11	1368	__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1369	return(result);
saloutos	0:083111ae2a11	1370	}
saloutos	0:083111ae2a11	1371
saloutos	0:083111ae2a11	1372	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1373	{
saloutos	0:083111ae2a11	1374	uint32_t result;
saloutos	0:083111ae2a11	1375
saloutos	0:083111ae2a11	1376	__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1377	return(result);
saloutos	0:083111ae2a11	1378	}
saloutos	0:083111ae2a11	1379
saloutos	0:083111ae2a11	1380	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1381	{
saloutos	0:083111ae2a11	1382	uint32_t result;
saloutos	0:083111ae2a11	1383
saloutos	0:083111ae2a11	1384	__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1385	return(result);
saloutos	0:083111ae2a11	1386	}
saloutos	0:083111ae2a11	1387
saloutos	0:083111ae2a11	1388	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1389	{
saloutos	0:083111ae2a11	1390	uint32_t result;
saloutos	0:083111ae2a11	1391
saloutos	0:083111ae2a11	1392	__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1393	return(result);
saloutos	0:083111ae2a11	1394	}
saloutos	0:083111ae2a11	1395
saloutos	0:083111ae2a11	1396	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1397	{
saloutos	0:083111ae2a11	1398	uint32_t result;
saloutos	0:083111ae2a11	1399
saloutos	0:083111ae2a11	1400	__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1401	return(result);
saloutos	0:083111ae2a11	1402	}
saloutos	0:083111ae2a11	1403
saloutos	0:083111ae2a11	1404	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1405	{
saloutos	0:083111ae2a11	1406	uint32_t result;
saloutos	0:083111ae2a11	1407
saloutos	0:083111ae2a11	1408	__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1409	return(result);
saloutos	0:083111ae2a11	1410	}
saloutos	0:083111ae2a11	1411
saloutos	0:083111ae2a11	1412	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1413	{
saloutos	0:083111ae2a11	1414	uint32_t result;
saloutos	0:083111ae2a11	1415
saloutos	0:083111ae2a11	1416	__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1417	return(result);
saloutos	0:083111ae2a11	1418	}
saloutos	0:083111ae2a11	1419
saloutos	0:083111ae2a11	1420	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1421	{
saloutos	0:083111ae2a11	1422	uint32_t result;
saloutos	0:083111ae2a11	1423
saloutos	0:083111ae2a11	1424	__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1425	return(result);
saloutos	0:083111ae2a11	1426	}
saloutos	0:083111ae2a11	1427
saloutos	0:083111ae2a11	1428	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1429	{
saloutos	0:083111ae2a11	1430	uint32_t result;
saloutos	0:083111ae2a11	1431
saloutos	0:083111ae2a11	1432	__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1433	return(result);
saloutos	0:083111ae2a11	1434	}
saloutos	0:083111ae2a11	1435
saloutos	0:083111ae2a11	1436	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1437	{
saloutos	0:083111ae2a11	1438	uint32_t result;
saloutos	0:083111ae2a11	1439
saloutos	0:083111ae2a11	1440	__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1441	return(result);
saloutos	0:083111ae2a11	1442	}
saloutos	0:083111ae2a11	1443
saloutos	0:083111ae2a11	1444	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1445	{
saloutos	0:083111ae2a11	1446	uint32_t result;
saloutos	0:083111ae2a11	1447
saloutos	0:083111ae2a11	1448	__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1449	return(result);
saloutos	0:083111ae2a11	1450	}
saloutos	0:083111ae2a11	1451
saloutos	0:083111ae2a11	1452	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1453	{
saloutos	0:083111ae2a11	1454	uint32_t result;
saloutos	0:083111ae2a11	1455
saloutos	0:083111ae2a11	1456	__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1457	return(result);
saloutos	0:083111ae2a11	1458	}
saloutos	0:083111ae2a11	1459
saloutos	0:083111ae2a11	1460	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1461	{
saloutos	0:083111ae2a11	1462	uint32_t result;
saloutos	0:083111ae2a11	1463
saloutos	0:083111ae2a11	1464	__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1465	return(result);
saloutos	0:083111ae2a11	1466	}
saloutos	0:083111ae2a11	1467
saloutos	0:083111ae2a11	1468	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1469	{
saloutos	0:083111ae2a11	1470	uint32_t result;
saloutos	0:083111ae2a11	1471
saloutos	0:083111ae2a11	1472	__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1473	return(result);
saloutos	0:083111ae2a11	1474	}
saloutos	0:083111ae2a11	1475
saloutos	0:083111ae2a11	1476	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1477	{
saloutos	0:083111ae2a11	1478	uint32_t result;
saloutos	0:083111ae2a11	1479
saloutos	0:083111ae2a11	1480	__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1481	return(result);
saloutos	0:083111ae2a11	1482	}
saloutos	0:083111ae2a11	1483
saloutos	0:083111ae2a11	1484	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1485	{
saloutos	0:083111ae2a11	1486	uint32_t result;
saloutos	0:083111ae2a11	1487
saloutos	0:083111ae2a11	1488	__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1489	return(result);
saloutos	0:083111ae2a11	1490	}
saloutos	0:083111ae2a11	1491
saloutos	0:083111ae2a11	1492	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1493	{
saloutos	0:083111ae2a11	1494	uint32_t result;
saloutos	0:083111ae2a11	1495
saloutos	0:083111ae2a11	1496	__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1497	return(result);
saloutos	0:083111ae2a11	1498	}
saloutos	0:083111ae2a11	1499
saloutos	0:083111ae2a11	1500	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1501	{
saloutos	0:083111ae2a11	1502	uint32_t result;
saloutos	0:083111ae2a11	1503
saloutos	0:083111ae2a11	1504	__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1505	return(result);
saloutos	0:083111ae2a11	1506	}
saloutos	0:083111ae2a11	1507
saloutos	0:083111ae2a11	1508	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1509	{
saloutos	0:083111ae2a11	1510	uint32_t result;
saloutos	0:083111ae2a11	1511
saloutos	0:083111ae2a11	1512	__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1513	return(result);
saloutos	0:083111ae2a11	1514	}
saloutos	0:083111ae2a11	1515
saloutos	0:083111ae2a11	1516	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1517	{
saloutos	0:083111ae2a11	1518	uint32_t result;
saloutos	0:083111ae2a11	1519
saloutos	0:083111ae2a11	1520	__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1521	return(result);
saloutos	0:083111ae2a11	1522	}
saloutos	0:083111ae2a11	1523
saloutos	0:083111ae2a11	1524	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1525	{
saloutos	0:083111ae2a11	1526	uint32_t result;
saloutos	0:083111ae2a11	1527
saloutos	0:083111ae2a11	1528	__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1529	return(result);
saloutos	0:083111ae2a11	1530	}
saloutos	0:083111ae2a11	1531
saloutos	0:083111ae2a11	1532	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1533	{
saloutos	0:083111ae2a11	1534	uint32_t result;
saloutos	0:083111ae2a11	1535
saloutos	0:083111ae2a11	1536	__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1537	return(result);
saloutos	0:083111ae2a11	1538	}
saloutos	0:083111ae2a11	1539
saloutos	0:083111ae2a11	1540	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1541	{
saloutos	0:083111ae2a11	1542	uint32_t result;
saloutos	0:083111ae2a11	1543
saloutos	0:083111ae2a11	1544	__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1545	return(result);
saloutos	0:083111ae2a11	1546	}
saloutos	0:083111ae2a11	1547
saloutos	0:083111ae2a11	1548	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
saloutos	0:083111ae2a11	1549	{
saloutos	0:083111ae2a11	1550	uint32_t result;
saloutos	0:083111ae2a11	1551
saloutos	0:083111ae2a11	1552	__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
saloutos	0:083111ae2a11	1553	return(result);
saloutos	0:083111ae2a11	1554	}
saloutos	0:083111ae2a11	1555
saloutos	0:083111ae2a11	1556	#define __SSAT16(ARG1,ARG2) \
saloutos	0:083111ae2a11	1557	({ \
saloutos	0:083111ae2a11	1558	int32_t __RES, __ARG1 = (ARG1); \
saloutos	0:083111ae2a11	1559	__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
saloutos	0:083111ae2a11	1560	__RES; \
saloutos	0:083111ae2a11	1561	})
saloutos	0:083111ae2a11	1562
saloutos	0:083111ae2a11	1563	#define __USAT16(ARG1,ARG2) \
saloutos	0:083111ae2a11	1564	({ \
saloutos	0:083111ae2a11	1565	uint32_t __RES, __ARG1 = (ARG1); \
saloutos	0:083111ae2a11	1566	__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
saloutos	0:083111ae2a11	1567	__RES; \
saloutos	0:083111ae2a11	1568	})
saloutos	0:083111ae2a11	1569
saloutos	0:083111ae2a11	1570	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
saloutos	0:083111ae2a11	1571	{
saloutos	0:083111ae2a11	1572	uint32_t result;
saloutos	0:083111ae2a11	1573
saloutos	0:083111ae2a11	1574	__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
saloutos	0:083111ae2a11	1575	return(result);
saloutos	0:083111ae2a11	1576	}
saloutos	0:083111ae2a11	1577
saloutos	0:083111ae2a11	1578	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1579	{
saloutos	0:083111ae2a11	1580	uint32_t result;
saloutos	0:083111ae2a11	1581
saloutos	0:083111ae2a11	1582	__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1583	return(result);
saloutos	0:083111ae2a11	1584	}
saloutos	0:083111ae2a11	1585
saloutos	0:083111ae2a11	1586	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
saloutos	0:083111ae2a11	1587	{
saloutos	0:083111ae2a11	1588	uint32_t result;
saloutos	0:083111ae2a11	1589
saloutos	0:083111ae2a11	1590	__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
saloutos	0:083111ae2a11	1591	return(result);
saloutos	0:083111ae2a11	1592	}
saloutos	0:083111ae2a11	1593
saloutos	0:083111ae2a11	1594	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1595	{
saloutos	0:083111ae2a11	1596	uint32_t result;
saloutos	0:083111ae2a11	1597
saloutos	0:083111ae2a11	1598	__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1599	return(result);
saloutos	0:083111ae2a11	1600	}
saloutos	0:083111ae2a11	1601
saloutos	0:083111ae2a11	1602	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1603	{
saloutos	0:083111ae2a11	1604	uint32_t result;
saloutos	0:083111ae2a11	1605
saloutos	0:083111ae2a11	1606	__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1607	return(result);
saloutos	0:083111ae2a11	1608	}
saloutos	0:083111ae2a11	1609
saloutos	0:083111ae2a11	1610	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1611	{
saloutos	0:083111ae2a11	1612	uint32_t result;
saloutos	0:083111ae2a11	1613
saloutos	0:083111ae2a11	1614	__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1615	return(result);
saloutos	0:083111ae2a11	1616	}
saloutos	0:083111ae2a11	1617
saloutos	0:083111ae2a11	1618	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
saloutos	0:083111ae2a11	1619	{
saloutos	0:083111ae2a11	1620	uint32_t result;
saloutos	0:083111ae2a11	1621
saloutos	0:083111ae2a11	1622	__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
saloutos	0:083111ae2a11	1623	return(result);
saloutos	0:083111ae2a11	1624	}
saloutos	0:083111ae2a11	1625
saloutos	0:083111ae2a11	1626	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
saloutos	0:083111ae2a11	1627	{
saloutos	0:083111ae2a11	1628	uint32_t result;
saloutos	0:083111ae2a11	1629
saloutos	0:083111ae2a11	1630	__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
saloutos	0:083111ae2a11	1631	return(result);
saloutos	0:083111ae2a11	1632	}
saloutos	0:083111ae2a11	1633
saloutos	0:083111ae2a11	1634	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
saloutos	0:083111ae2a11	1635	{
saloutos	0:083111ae2a11	1636	union llreg_u{
saloutos	0:083111ae2a11	1637	uint32_t w32[2];
saloutos	0:083111ae2a11	1638	uint64_t w64;
saloutos	0:083111ae2a11	1639	} llr;
saloutos	0:083111ae2a11	1640	llr.w64 = acc;
saloutos	0:083111ae2a11	1641
saloutos	0:083111ae2a11	1642	#ifndef __ARMEB__ /* Little endian */
saloutos	0:083111ae2a11	1643	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
saloutos	0:083111ae2a11	1644	#else /* Big endian */
saloutos	0:083111ae2a11	1645	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
saloutos	0:083111ae2a11	1646	#endif
saloutos	0:083111ae2a11	1647
saloutos	0:083111ae2a11	1648	return(llr.w64);
saloutos	0:083111ae2a11	1649	}
saloutos	0:083111ae2a11	1650
saloutos	0:083111ae2a11	1651	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
saloutos	0:083111ae2a11	1652	{
saloutos	0:083111ae2a11	1653	union llreg_u{
saloutos	0:083111ae2a11	1654	uint32_t w32[2];
saloutos	0:083111ae2a11	1655	uint64_t w64;
saloutos	0:083111ae2a11	1656	} llr;
saloutos	0:083111ae2a11	1657	llr.w64 = acc;
saloutos	0:083111ae2a11	1658
saloutos	0:083111ae2a11	1659	#ifndef __ARMEB__ /* Little endian */
saloutos	0:083111ae2a11	1660	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
saloutos	0:083111ae2a11	1661	#else /* Big endian */
saloutos	0:083111ae2a11	1662	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
saloutos	0:083111ae2a11	1663	#endif
saloutos	0:083111ae2a11	1664
saloutos	0:083111ae2a11	1665	return(llr.w64);
saloutos	0:083111ae2a11	1666	}
saloutos	0:083111ae2a11	1667
saloutos	0:083111ae2a11	1668	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1669	{
saloutos	0:083111ae2a11	1670	uint32_t result;
saloutos	0:083111ae2a11	1671
saloutos	0:083111ae2a11	1672	__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1673	return(result);
saloutos	0:083111ae2a11	1674	}
saloutos	0:083111ae2a11	1675
saloutos	0:083111ae2a11	1676	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1677	{
saloutos	0:083111ae2a11	1678	uint32_t result;
saloutos	0:083111ae2a11	1679
saloutos	0:083111ae2a11	1680	__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1681	return(result);
saloutos	0:083111ae2a11	1682	}
saloutos	0:083111ae2a11	1683
saloutos	0:083111ae2a11	1684	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
saloutos	0:083111ae2a11	1685	{
saloutos	0:083111ae2a11	1686	uint32_t result;
saloutos	0:083111ae2a11	1687
saloutos	0:083111ae2a11	1688	__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
saloutos	0:083111ae2a11	1689	return(result);
saloutos	0:083111ae2a11	1690	}
saloutos	0:083111ae2a11	1691
saloutos	0:083111ae2a11	1692	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
saloutos	0:083111ae2a11	1693	{
saloutos	0:083111ae2a11	1694	uint32_t result;
saloutos	0:083111ae2a11	1695
saloutos	0:083111ae2a11	1696	__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
saloutos	0:083111ae2a11	1697	return(result);
saloutos	0:083111ae2a11	1698	}
saloutos	0:083111ae2a11	1699
saloutos	0:083111ae2a11	1700	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
saloutos	0:083111ae2a11	1701	{
saloutos	0:083111ae2a11	1702	union llreg_u{
saloutos	0:083111ae2a11	1703	uint32_t w32[2];
saloutos	0:083111ae2a11	1704	uint64_t w64;
saloutos	0:083111ae2a11	1705	} llr;
saloutos	0:083111ae2a11	1706	llr.w64 = acc;
saloutos	0:083111ae2a11	1707
saloutos	0:083111ae2a11	1708	#ifndef __ARMEB__ /* Little endian */
saloutos	0:083111ae2a11	1709	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
saloutos	0:083111ae2a11	1710	#else /* Big endian */
saloutos	0:083111ae2a11	1711	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
saloutos	0:083111ae2a11	1712	#endif
saloutos	0:083111ae2a11	1713
saloutos	0:083111ae2a11	1714	return(llr.w64);
saloutos	0:083111ae2a11	1715	}
saloutos	0:083111ae2a11	1716
saloutos	0:083111ae2a11	1717	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
saloutos	0:083111ae2a11	1718	{
saloutos	0:083111ae2a11	1719	union llreg_u{
saloutos	0:083111ae2a11	1720	uint32_t w32[2];
saloutos	0:083111ae2a11	1721	uint64_t w64;
saloutos	0:083111ae2a11	1722	} llr;
saloutos	0:083111ae2a11	1723	llr.w64 = acc;
saloutos	0:083111ae2a11	1724
saloutos	0:083111ae2a11	1725	#ifndef __ARMEB__ /* Little endian */
saloutos	0:083111ae2a11	1726	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
saloutos	0:083111ae2a11	1727	#else /* Big endian */
saloutos	0:083111ae2a11	1728	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
saloutos	0:083111ae2a11	1729	#endif
saloutos	0:083111ae2a11	1730
saloutos	0:083111ae2a11	1731	return(llr.w64);
saloutos	0:083111ae2a11	1732	}
saloutos	0:083111ae2a11	1733
saloutos	0:083111ae2a11	1734	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
saloutos	0:083111ae2a11	1735	{
saloutos	0:083111ae2a11	1736	uint32_t result;
saloutos	0:083111ae2a11	1737
saloutos	0:083111ae2a11	1738	__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1739	return(result);
saloutos	0:083111ae2a11	1740	}
saloutos	0:083111ae2a11	1741
saloutos	0:083111ae2a11	1742	__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
saloutos	0:083111ae2a11	1743	{
saloutos	0:083111ae2a11	1744	int32_t result;
saloutos	0:083111ae2a11	1745
saloutos	0:083111ae2a11	1746	__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1747	return(result);
saloutos	0:083111ae2a11	1748	}
saloutos	0:083111ae2a11	1749
saloutos	0:083111ae2a11	1750	__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
saloutos	0:083111ae2a11	1751	{
saloutos	0:083111ae2a11	1752	int32_t result;
saloutos	0:083111ae2a11	1753
saloutos	0:083111ae2a11	1754	__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
saloutos	0:083111ae2a11	1755	return(result);
saloutos	0:083111ae2a11	1756	}
saloutos	0:083111ae2a11	1757
saloutos	0:083111ae2a11	1758	#if 0
saloutos	0:083111ae2a11	1759	#define __PKHBT(ARG1,ARG2,ARG3) \
saloutos	0:083111ae2a11	1760	({ \
saloutos	0:083111ae2a11	1761	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
saloutos	0:083111ae2a11	1762	__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
saloutos	0:083111ae2a11	1763	__RES; \
saloutos	0:083111ae2a11	1764	})
saloutos	0:083111ae2a11	1765
saloutos	0:083111ae2a11	1766	#define __PKHTB(ARG1,ARG2,ARG3) \
saloutos	0:083111ae2a11	1767	({ \
saloutos	0:083111ae2a11	1768	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
saloutos	0:083111ae2a11	1769	if (ARG3 == 0) \
saloutos	0:083111ae2a11	1770	__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
saloutos	0:083111ae2a11	1771	else \
saloutos	0:083111ae2a11	1772	__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
saloutos	0:083111ae2a11	1773	__RES; \
saloutos	0:083111ae2a11	1774	})
saloutos	0:083111ae2a11	1775	#endif
saloutos	0:083111ae2a11	1776
saloutos	0:083111ae2a11	1777	#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) \| \
saloutos	0:083111ae2a11	1778	((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
saloutos	0:083111ae2a11	1779
saloutos	0:083111ae2a11	1780	#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) \| \
saloutos	0:083111ae2a11	1781	((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
saloutos	0:083111ae2a11	1782
saloutos	0:083111ae2a11	1783	__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
saloutos	0:083111ae2a11	1784	{
saloutos	0:083111ae2a11	1785	int32_t result;
saloutos	0:083111ae2a11	1786
saloutos	0:083111ae2a11	1787	__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
saloutos	0:083111ae2a11	1788	return(result);
saloutos	0:083111ae2a11	1789	}
saloutos	0:083111ae2a11	1790
saloutos	0:083111ae2a11	1791	#endif /* (__ARM_FEATURE_DSP == 1) */
saloutos	0:083111ae2a11	1792	/@} end of group CMSIS_SIMD_intrinsics /
saloutos	0:083111ae2a11	1793
saloutos	0:083111ae2a11	1794
saloutos	0:083111ae2a11	1795	#endif /* __CMSIS_ARMCLANG_H */

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Type:	Library
Created:	09 Mar 2021
Imports:	13
Forks:	0
Commits:	4
Dependents:	4
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cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armclang.h@0:083111ae2a11, 2020-11-26 (annotated)

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