Aditya Mehrotra / mbed-dev

Biomimetics MBED Library w/ Added Support for CAN3

Dependents:   CAN_TEST SPIne_Plus_DYNO_SENSORS SPIne_Plus_v2 SPIne_Plus_Dyno_v2

cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armcc.h@0:083111ae2a11, 2020-11-26 (annotated)

Committer:
saloutos
Date:
Thu Nov 26 04:08:56 2020 +0000
Revision:
0:083111ae2a11
first commit of leaned mbed dev lib

Who changed what in which revision?

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saloutos 0:083111ae2a11 1 /**************************************************************************//**
saloutos 0:083111ae2a11 2 * @file cmsis_armcc.h
saloutos 0:083111ae2a11 3 * @brief CMSIS compiler ARMCC (ARM compiler V5) header file
saloutos 0:083111ae2a11 4 * @version V5.0.2
saloutos 0:083111ae2a11 5 * @date 13. February 2017
saloutos 0:083111ae2a11 6 ******************************************************************************/
saloutos 0:083111ae2a11 7 /*
saloutos 0:083111ae2a11 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
saloutos 0:083111ae2a11 9 *
saloutos 0:083111ae2a11 10 * SPDX-License-Identifier: Apache-2.0
saloutos 0:083111ae2a11 11 *
saloutos 0:083111ae2a11 12 * Licensed under the Apache License, Version 2.0 (the License); you may
saloutos 0:083111ae2a11 13 * not use this file except in compliance with the License.
saloutos 0:083111ae2a11 14 * You may obtain a copy of the License at
saloutos 0:083111ae2a11 15 *
saloutos 0:083111ae2a11 16 * www.apache.org/licenses/LICENSE-2.0
saloutos 0:083111ae2a11 17 *
saloutos 0:083111ae2a11 18 * Unless required by applicable law or agreed to in writing, software
saloutos 0:083111ae2a11 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
saloutos 0:083111ae2a11 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
saloutos 0:083111ae2a11 21 * See the License for the specific language governing permissions and
saloutos 0:083111ae2a11 22 * limitations under the License.
saloutos 0:083111ae2a11 23 */
saloutos 0:083111ae2a11 24
saloutos 0:083111ae2a11 25 #ifndef __CMSIS_ARMCC_H
saloutos 0:083111ae2a11 26 #define __CMSIS_ARMCC_H
saloutos 0:083111ae2a11 27
saloutos 0:083111ae2a11 28
saloutos 0:083111ae2a11 29 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
saloutos 0:083111ae2a11 30 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
saloutos 0:083111ae2a11 31 #endif
saloutos 0:083111ae2a11 32
saloutos 0:083111ae2a11 33 /* CMSIS compiler control architecture macros */
saloutos 0:083111ae2a11 34 #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
saloutos 0:083111ae2a11 35 (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
saloutos 0:083111ae2a11 36 #define __ARM_ARCH_6M__ 1
saloutos 0:083111ae2a11 37 #endif
saloutos 0:083111ae2a11 38
saloutos 0:083111ae2a11 39 #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
saloutos 0:083111ae2a11 40 #define __ARM_ARCH_7M__ 1
saloutos 0:083111ae2a11 41 #endif
saloutos 0:083111ae2a11 42
saloutos 0:083111ae2a11 43 #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
saloutos 0:083111ae2a11 44 #define __ARM_ARCH_7EM__ 1
saloutos 0:083111ae2a11 45 #endif
saloutos 0:083111ae2a11 46
saloutos 0:083111ae2a11 47 /* __ARM_ARCH_8M_BASE__ not applicable */
saloutos 0:083111ae2a11 48 /* __ARM_ARCH_8M_MAIN__ not applicable */
saloutos 0:083111ae2a11 49
saloutos 0:083111ae2a11 50
saloutos 0:083111ae2a11 51 /* CMSIS compiler specific defines */
saloutos 0:083111ae2a11 52 #ifndef __ASM
saloutos 0:083111ae2a11 53 #define __ASM __asm
saloutos 0:083111ae2a11 54 #endif
saloutos 0:083111ae2a11 55 #ifndef __INLINE
saloutos 0:083111ae2a11 56 #define __INLINE __inline
saloutos 0:083111ae2a11 57 #endif
saloutos 0:083111ae2a11 58 #ifndef __STATIC_INLINE
saloutos 0:083111ae2a11 59 #define __STATIC_INLINE static __inline
saloutos 0:083111ae2a11 60 #endif
saloutos 0:083111ae2a11 61 #ifndef __NO_RETURN
saloutos 0:083111ae2a11 62 #define __NO_RETURN __declspec(noreturn)
saloutos 0:083111ae2a11 63 #endif
saloutos 0:083111ae2a11 64 #ifndef __USED
saloutos 0:083111ae2a11 65 #define __USED __attribute__((used))
saloutos 0:083111ae2a11 66 #endif
saloutos 0:083111ae2a11 67 #ifndef __WEAK
saloutos 0:083111ae2a11 68 #define __WEAK __attribute__((weak))
saloutos 0:083111ae2a11 69 #endif
saloutos 0:083111ae2a11 70 #ifndef __PACKED
saloutos 0:083111ae2a11 71 #define __PACKED __attribute__((packed))
saloutos 0:083111ae2a11 72 #endif
saloutos 0:083111ae2a11 73 #ifndef __PACKED_STRUCT
saloutos 0:083111ae2a11 74 #define __PACKED_STRUCT __packed struct
saloutos 0:083111ae2a11 75 #endif
saloutos 0:083111ae2a11 76 #ifndef __UNALIGNED_UINT32 /* deprecated */
saloutos 0:083111ae2a11 77 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
saloutos 0:083111ae2a11 78 #endif
saloutos 0:083111ae2a11 79 #ifndef __UNALIGNED_UINT16_WRITE
saloutos 0:083111ae2a11 80 #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
saloutos 0:083111ae2a11 81 #endif
saloutos 0:083111ae2a11 82 #ifndef __UNALIGNED_UINT16_READ
saloutos 0:083111ae2a11 83 #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
saloutos 0:083111ae2a11 84 #endif
saloutos 0:083111ae2a11 85 #ifndef __UNALIGNED_UINT32_WRITE
saloutos 0:083111ae2a11 86 #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
saloutos 0:083111ae2a11 87 #endif
saloutos 0:083111ae2a11 88 #ifndef __UNALIGNED_UINT32_READ
saloutos 0:083111ae2a11 89 #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
saloutos 0:083111ae2a11 90 #endif
saloutos 0:083111ae2a11 91 #ifndef __ALIGNED
saloutos 0:083111ae2a11 92 #define __ALIGNED(x) __attribute__((aligned(x)))
saloutos 0:083111ae2a11 93 #endif
saloutos 0:083111ae2a11 94
saloutos 0:083111ae2a11 95
saloutos 0:083111ae2a11 96 /* ########################### Core Function Access ########################### */
saloutos 0:083111ae2a11 97 /** \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 98 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
saloutos 0:083111ae2a11 99 @{
saloutos 0:083111ae2a11 100 */
saloutos 0:083111ae2a11 101
saloutos 0:083111ae2a11 102 /**
saloutos 0:083111ae2a11 103 \brief Enable IRQ Interrupts
saloutos 0:083111ae2a11 104 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
saloutos 0:083111ae2a11 105 Can only be executed in Privileged modes.
saloutos 0:083111ae2a11 106 */
saloutos 0:083111ae2a11 107 /* intrinsic void __enable_irq(); */
saloutos 0:083111ae2a11 108
saloutos 0:083111ae2a11 109
saloutos 0:083111ae2a11 110 /**
saloutos 0:083111ae2a11 111 \brief Disable IRQ Interrupts
saloutos 0:083111ae2a11 112 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
saloutos 0:083111ae2a11 113 Can only be executed in Privileged modes.
saloutos 0:083111ae2a11 114 */
saloutos 0:083111ae2a11 115 /* intrinsic void __disable_irq(); */
saloutos 0:083111ae2a11 116
saloutos 0:083111ae2a11 117 /**
saloutos 0:083111ae2a11 118 \brief Get Control Register
saloutos 0:083111ae2a11 119 \details Returns the content of the Control Register.
saloutos 0:083111ae2a11 120 \return Control Register value
saloutos 0:083111ae2a11 121 */
saloutos 0:083111ae2a11 122 __STATIC_INLINE uint32_t __get_CONTROL(void)
saloutos 0:083111ae2a11 123 {
saloutos 0:083111ae2a11 124 register uint32_t __regControl __ASM("control");
saloutos 0:083111ae2a11 125 return(__regControl);
saloutos 0:083111ae2a11 126 }
saloutos 0:083111ae2a11 127
saloutos 0:083111ae2a11 128
saloutos 0:083111ae2a11 129 /**
saloutos 0:083111ae2a11 130 \brief Set Control Register
saloutos 0:083111ae2a11 131 \details Writes the given value to the Control Register.
saloutos 0:083111ae2a11 132 \param [in] control Control Register value to set
saloutos 0:083111ae2a11 133 */
saloutos 0:083111ae2a11 134 __STATIC_INLINE void __set_CONTROL(uint32_t control)
saloutos 0:083111ae2a11 135 {
saloutos 0:083111ae2a11 136 register uint32_t __regControl __ASM("control");
saloutos 0:083111ae2a11 137 __regControl = control;
saloutos 0:083111ae2a11 138 }
saloutos 0:083111ae2a11 139
saloutos 0:083111ae2a11 140
saloutos 0:083111ae2a11 141 /**
saloutos 0:083111ae2a11 142 \brief Get IPSR Register
saloutos 0:083111ae2a11 143 \details Returns the content of the IPSR Register.
saloutos 0:083111ae2a11 144 \return IPSR Register value
saloutos 0:083111ae2a11 145 */
saloutos 0:083111ae2a11 146 __STATIC_INLINE uint32_t __get_IPSR(void)
saloutos 0:083111ae2a11 147 {
saloutos 0:083111ae2a11 148 register uint32_t __regIPSR __ASM("ipsr");
saloutos 0:083111ae2a11 149 return(__regIPSR);
saloutos 0:083111ae2a11 150 }
saloutos 0:083111ae2a11 151
saloutos 0:083111ae2a11 152
saloutos 0:083111ae2a11 153 /**
saloutos 0:083111ae2a11 154 \brief Get APSR Register
saloutos 0:083111ae2a11 155 \details Returns the content of the APSR Register.
saloutos 0:083111ae2a11 156 \return APSR Register value
saloutos 0:083111ae2a11 157 */
saloutos 0:083111ae2a11 158 __STATIC_INLINE uint32_t __get_APSR(void)
saloutos 0:083111ae2a11 159 {
saloutos 0:083111ae2a11 160 register uint32_t __regAPSR __ASM("apsr");
saloutos 0:083111ae2a11 161 return(__regAPSR);
saloutos 0:083111ae2a11 162 }
saloutos 0:083111ae2a11 163
saloutos 0:083111ae2a11 164
saloutos 0:083111ae2a11 165 /**
saloutos 0:083111ae2a11 166 \brief Get xPSR Register
saloutos 0:083111ae2a11 167 \details Returns the content of the xPSR Register.
saloutos 0:083111ae2a11 168 \return xPSR Register value
saloutos 0:083111ae2a11 169 */
saloutos 0:083111ae2a11 170 __STATIC_INLINE uint32_t __get_xPSR(void)
saloutos 0:083111ae2a11 171 {
saloutos 0:083111ae2a11 172 register uint32_t __regXPSR __ASM("xpsr");
saloutos 0:083111ae2a11 173 return(__regXPSR);
saloutos 0:083111ae2a11 174 }
saloutos 0:083111ae2a11 175
saloutos 0:083111ae2a11 176
saloutos 0:083111ae2a11 177 /**
saloutos 0:083111ae2a11 178 \brief Get Process Stack Pointer
saloutos 0:083111ae2a11 179 \details Returns the current value of the Process Stack Pointer (PSP).
saloutos 0:083111ae2a11 180 \return PSP Register value
saloutos 0:083111ae2a11 181 */
saloutos 0:083111ae2a11 182 __STATIC_INLINE uint32_t __get_PSP(void)
saloutos 0:083111ae2a11 183 {
saloutos 0:083111ae2a11 184 register uint32_t __regProcessStackPointer __ASM("psp");
saloutos 0:083111ae2a11 185 return(__regProcessStackPointer);
saloutos 0:083111ae2a11 186 }
saloutos 0:083111ae2a11 187
saloutos 0:083111ae2a11 188
saloutos 0:083111ae2a11 189 /**
saloutos 0:083111ae2a11 190 \brief Set Process Stack Pointer
saloutos 0:083111ae2a11 191 \details Assigns the given value to the Process Stack Pointer (PSP).
saloutos 0:083111ae2a11 192 \param [in] topOfProcStack Process Stack Pointer value to set
saloutos 0:083111ae2a11 193 */
saloutos 0:083111ae2a11 194 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
saloutos 0:083111ae2a11 195 {
saloutos 0:083111ae2a11 196 register uint32_t __regProcessStackPointer __ASM("psp");
saloutos 0:083111ae2a11 197 __regProcessStackPointer = topOfProcStack;
saloutos 0:083111ae2a11 198 }
saloutos 0:083111ae2a11 199
saloutos 0:083111ae2a11 200
saloutos 0:083111ae2a11 201 /**
saloutos 0:083111ae2a11 202 \brief Get Main Stack Pointer
saloutos 0:083111ae2a11 203 \details Returns the current value of the Main Stack Pointer (MSP).
saloutos 0:083111ae2a11 204 \return MSP Register value
saloutos 0:083111ae2a11 205 */
saloutos 0:083111ae2a11 206 __STATIC_INLINE uint32_t __get_MSP(void)
saloutos 0:083111ae2a11 207 {
saloutos 0:083111ae2a11 208 register uint32_t __regMainStackPointer __ASM("msp");
saloutos 0:083111ae2a11 209 return(__regMainStackPointer);
saloutos 0:083111ae2a11 210 }
saloutos 0:083111ae2a11 211
saloutos 0:083111ae2a11 212
saloutos 0:083111ae2a11 213 /**
saloutos 0:083111ae2a11 214 \brief Set Main Stack Pointer
saloutos 0:083111ae2a11 215 \details Assigns the given value to the Main Stack Pointer (MSP).
saloutos 0:083111ae2a11 216 \param [in] topOfMainStack Main Stack Pointer value to set
saloutos 0:083111ae2a11 217 */
saloutos 0:083111ae2a11 218 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
saloutos 0:083111ae2a11 219 {
saloutos 0:083111ae2a11 220 register uint32_t __regMainStackPointer __ASM("msp");
saloutos 0:083111ae2a11 221 __regMainStackPointer = topOfMainStack;
saloutos 0:083111ae2a11 222 }
saloutos 0:083111ae2a11 223
saloutos 0:083111ae2a11 224
saloutos 0:083111ae2a11 225 /**
saloutos 0:083111ae2a11 226 \brief Get Priority Mask
saloutos 0:083111ae2a11 227 \details Returns the current state of the priority mask bit from the Priority Mask Register.
saloutos 0:083111ae2a11 228 \return Priority Mask value
saloutos 0:083111ae2a11 229 */
saloutos 0:083111ae2a11 230 __STATIC_INLINE uint32_t __get_PRIMASK(void)
saloutos 0:083111ae2a11 231 {
saloutos 0:083111ae2a11 232 register uint32_t __regPriMask __ASM("primask");
saloutos 0:083111ae2a11 233 return(__regPriMask);
saloutos 0:083111ae2a11 234 }
saloutos 0:083111ae2a11 235
saloutos 0:083111ae2a11 236
saloutos 0:083111ae2a11 237 /**
saloutos 0:083111ae2a11 238 \brief Set Priority Mask
saloutos 0:083111ae2a11 239 \details Assigns the given value to the Priority Mask Register.
saloutos 0:083111ae2a11 240 \param [in] priMask Priority Mask
saloutos 0:083111ae2a11 241 */
saloutos 0:083111ae2a11 242 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
saloutos 0:083111ae2a11 243 {
saloutos 0:083111ae2a11 244 register uint32_t __regPriMask __ASM("primask");
saloutos 0:083111ae2a11 245 __regPriMask = (priMask);
saloutos 0:083111ae2a11 246 }
saloutos 0:083111ae2a11 247
saloutos 0:083111ae2a11 248
saloutos 0:083111ae2a11 249 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
saloutos 0:083111ae2a11 250 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
saloutos 0:083111ae2a11 251
saloutos 0:083111ae2a11 252 /**
saloutos 0:083111ae2a11 253 \brief Enable FIQ
saloutos 0:083111ae2a11 254 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
saloutos 0:083111ae2a11 255 Can only be executed in Privileged modes.
saloutos 0:083111ae2a11 256 */
saloutos 0:083111ae2a11 257 #define __enable_fault_irq __enable_fiq
saloutos 0:083111ae2a11 258
saloutos 0:083111ae2a11 259
saloutos 0:083111ae2a11 260 /**
saloutos 0:083111ae2a11 261 \brief Disable FIQ
saloutos 0:083111ae2a11 262 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
saloutos 0:083111ae2a11 263 Can only be executed in Privileged modes.
saloutos 0:083111ae2a11 264 */
saloutos 0:083111ae2a11 265 #define __disable_fault_irq __disable_fiq
saloutos 0:083111ae2a11 266
saloutos 0:083111ae2a11 267
saloutos 0:083111ae2a11 268 /**
saloutos 0:083111ae2a11 269 \brief Get Base Priority
saloutos 0:083111ae2a11 270 \details Returns the current value of the Base Priority register.
saloutos 0:083111ae2a11 271 \return Base Priority register value
saloutos 0:083111ae2a11 272 */
saloutos 0:083111ae2a11 273 __STATIC_INLINE uint32_t __get_BASEPRI(void)
saloutos 0:083111ae2a11 274 {
saloutos 0:083111ae2a11 275 register uint32_t __regBasePri __ASM("basepri");
saloutos 0:083111ae2a11 276 return(__regBasePri);
saloutos 0:083111ae2a11 277 }
saloutos 0:083111ae2a11 278
saloutos 0:083111ae2a11 279
saloutos 0:083111ae2a11 280 /**
saloutos 0:083111ae2a11 281 \brief Set Base Priority
saloutos 0:083111ae2a11 282 \details Assigns the given value to the Base Priority register.
saloutos 0:083111ae2a11 283 \param [in] basePri Base Priority value to set
saloutos 0:083111ae2a11 284 */
saloutos 0:083111ae2a11 285 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
saloutos 0:083111ae2a11 286 {
saloutos 0:083111ae2a11 287 register uint32_t __regBasePri __ASM("basepri");
saloutos 0:083111ae2a11 288 __regBasePri = (basePri & 0xFFU);
saloutos 0:083111ae2a11 289 }
saloutos 0:083111ae2a11 290
saloutos 0:083111ae2a11 291
saloutos 0:083111ae2a11 292 /**
saloutos 0:083111ae2a11 293 \brief Set Base Priority with condition
saloutos 0:083111ae2a11 294 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
saloutos 0:083111ae2a11 295 or the new value increases the BASEPRI priority level.
saloutos 0:083111ae2a11 296 \param [in] basePri Base Priority value to set
saloutos 0:083111ae2a11 297 */
saloutos 0:083111ae2a11 298 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
saloutos 0:083111ae2a11 299 {
saloutos 0:083111ae2a11 300 register uint32_t __regBasePriMax __ASM("basepri_max");
saloutos 0:083111ae2a11 301 __regBasePriMax = (basePri & 0xFFU);
saloutos 0:083111ae2a11 302 }
saloutos 0:083111ae2a11 303
saloutos 0:083111ae2a11 304
saloutos 0:083111ae2a11 305 /**
saloutos 0:083111ae2a11 306 \brief Get Fault Mask
saloutos 0:083111ae2a11 307 \details Returns the current value of the Fault Mask register.
saloutos 0:083111ae2a11 308 \return Fault Mask register value
saloutos 0:083111ae2a11 309 */
saloutos 0:083111ae2a11 310 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
saloutos 0:083111ae2a11 311 {
saloutos 0:083111ae2a11 312 register uint32_t __regFaultMask __ASM("faultmask");
saloutos 0:083111ae2a11 313 return(__regFaultMask);
saloutos 0:083111ae2a11 314 }
saloutos 0:083111ae2a11 315
saloutos 0:083111ae2a11 316
saloutos 0:083111ae2a11 317 /**
saloutos 0:083111ae2a11 318 \brief Set Fault Mask
saloutos 0:083111ae2a11 319 \details Assigns the given value to the Fault Mask register.
saloutos 0:083111ae2a11 320 \param [in] faultMask Fault Mask value to set
saloutos 0:083111ae2a11 321 */
saloutos 0:083111ae2a11 322 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
saloutos 0:083111ae2a11 323 {
saloutos 0:083111ae2a11 324 register uint32_t __regFaultMask __ASM("faultmask");
saloutos 0:083111ae2a11 325 __regFaultMask = (faultMask & (uint32_t)1U);
saloutos 0:083111ae2a11 326 }
saloutos 0:083111ae2a11 327
saloutos 0:083111ae2a11 328 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
saloutos 0:083111ae2a11 329 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
saloutos 0:083111ae2a11 330
saloutos 0:083111ae2a11 331
saloutos 0:083111ae2a11 332 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
saloutos 0:083111ae2a11 333
saloutos 0:083111ae2a11 334 /**
saloutos 0:083111ae2a11 335 \brief Get FPSCR
saloutos 0:083111ae2a11 336 \details Returns the current value of the Floating Point Status/Control register.
saloutos 0:083111ae2a11 337 \return Floating Point Status/Control register value
saloutos 0:083111ae2a11 338 */
saloutos 0:083111ae2a11 339 __STATIC_INLINE uint32_t __get_FPSCR(void)
saloutos 0:083111ae2a11 340 {
saloutos 0:083111ae2a11 341 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
saloutos 0:083111ae2a11 342 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
saloutos 0:083111ae2a11 343 register uint32_t __regfpscr __ASM("fpscr");
saloutos 0:083111ae2a11 344 return(__regfpscr);
saloutos 0:083111ae2a11 345 #else
saloutos 0:083111ae2a11 346 return(0U);
saloutos 0:083111ae2a11 347 #endif
saloutos 0:083111ae2a11 348 }
saloutos 0:083111ae2a11 349
saloutos 0:083111ae2a11 350
saloutos 0:083111ae2a11 351 /**
saloutos 0:083111ae2a11 352 \brief Set FPSCR
saloutos 0:083111ae2a11 353 \details Assigns the given value to the Floating Point Status/Control register.
saloutos 0:083111ae2a11 354 \param [in] fpscr Floating Point Status/Control value to set
saloutos 0:083111ae2a11 355 */
saloutos 0:083111ae2a11 356 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
saloutos 0:083111ae2a11 357 {
saloutos 0:083111ae2a11 358 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
saloutos 0:083111ae2a11 359 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
saloutos 0:083111ae2a11 360 register uint32_t __regfpscr __ASM("fpscr");
saloutos 0:083111ae2a11 361 __regfpscr = (fpscr);
saloutos 0:083111ae2a11 362 #else
saloutos 0:083111ae2a11 363 (void)fpscr;
saloutos 0:083111ae2a11 364 #endif
saloutos 0:083111ae2a11 365 }
saloutos 0:083111ae2a11 366
saloutos 0:083111ae2a11 367 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
saloutos 0:083111ae2a11 368
saloutos 0:083111ae2a11 369
saloutos 0:083111ae2a11 370
saloutos 0:083111ae2a11 371 /*@} end of CMSIS_Core_RegAccFunctions */
saloutos 0:083111ae2a11 372
saloutos 0:083111ae2a11 373
saloutos 0:083111ae2a11 374 /* ########################## Core Instruction Access ######################### */
saloutos 0:083111ae2a11 375 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
saloutos 0:083111ae2a11 376 Access to dedicated instructions
saloutos 0:083111ae2a11 377 @{
saloutos 0:083111ae2a11 378 */
saloutos 0:083111ae2a11 379
saloutos 0:083111ae2a11 380 /**
saloutos 0:083111ae2a11 381 \brief No Operation
saloutos 0:083111ae2a11 382 \details No Operation does nothing. This instruction can be used for code alignment purposes.
saloutos 0:083111ae2a11 383 */
saloutos 0:083111ae2a11 384 #define __NOP __nop
saloutos 0:083111ae2a11 385
saloutos 0:083111ae2a11 386
saloutos 0:083111ae2a11 387 /**
saloutos 0:083111ae2a11 388 \brief Wait For Interrupt
saloutos 0:083111ae2a11 389 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
saloutos 0:083111ae2a11 390 */
saloutos 0:083111ae2a11 391 #define __WFI __wfi
saloutos 0:083111ae2a11 392
saloutos 0:083111ae2a11 393
saloutos 0:083111ae2a11 394 /**
saloutos 0:083111ae2a11 395 \brief Wait For Event
saloutos 0:083111ae2a11 396 \details Wait For Event is a hint instruction that permits the processor to enter
saloutos 0:083111ae2a11 397 a low-power state until one of a number of events occurs.
saloutos 0:083111ae2a11 398 */
saloutos 0:083111ae2a11 399 #define __WFE __wfe
saloutos 0:083111ae2a11 400
saloutos 0:083111ae2a11 401
saloutos 0:083111ae2a11 402 /**
saloutos 0:083111ae2a11 403 \brief Send Event
saloutos 0:083111ae2a11 404 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
saloutos 0:083111ae2a11 405 */
saloutos 0:083111ae2a11 406 #define __SEV __sev
saloutos 0:083111ae2a11 407
saloutos 0:083111ae2a11 408
saloutos 0:083111ae2a11 409 /**
saloutos 0:083111ae2a11 410 \brief Instruction Synchronization Barrier
saloutos 0:083111ae2a11 411 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
saloutos 0:083111ae2a11 412 so that all instructions following the ISB are fetched from cache or memory,
saloutos 0:083111ae2a11 413 after the instruction has been completed.
saloutos 0:083111ae2a11 414 */
saloutos 0:083111ae2a11 415 #define __ISB() do {\
saloutos 0:083111ae2a11 416 __schedule_barrier();\
saloutos 0:083111ae2a11 417 __isb(0xF);\
saloutos 0:083111ae2a11 418 __schedule_barrier();\
saloutos 0:083111ae2a11 419 } while (0U)
saloutos 0:083111ae2a11 420
saloutos 0:083111ae2a11 421 /**
saloutos 0:083111ae2a11 422 \brief Data Synchronization Barrier
saloutos 0:083111ae2a11 423 \details Acts as a special kind of Data Memory Barrier.
saloutos 0:083111ae2a11 424 It completes when all explicit memory accesses before this instruction complete.
saloutos 0:083111ae2a11 425 */
saloutos 0:083111ae2a11 426 #define __DSB() do {\
saloutos 0:083111ae2a11 427 __schedule_barrier();\
saloutos 0:083111ae2a11 428 __dsb(0xF);\
saloutos 0:083111ae2a11 429 __schedule_barrier();\
saloutos 0:083111ae2a11 430 } while (0U)
saloutos 0:083111ae2a11 431
saloutos 0:083111ae2a11 432 /**
saloutos 0:083111ae2a11 433 \brief Data Memory Barrier
saloutos 0:083111ae2a11 434 \details Ensures the apparent order of the explicit memory operations before
saloutos 0:083111ae2a11 435 and after the instruction, without ensuring their completion.
saloutos 0:083111ae2a11 436 */
saloutos 0:083111ae2a11 437 #define __DMB() do {\
saloutos 0:083111ae2a11 438 __schedule_barrier();\
saloutos 0:083111ae2a11 439 __dmb(0xF);\
saloutos 0:083111ae2a11 440 __schedule_barrier();\
saloutos 0:083111ae2a11 441 } while (0U)
saloutos 0:083111ae2a11 442
saloutos 0:083111ae2a11 443 /**
saloutos 0:083111ae2a11 444 \brief Reverse byte order (32 bit)
saloutos 0:083111ae2a11 445 \details Reverses the byte order in integer value.
saloutos 0:083111ae2a11 446 \param [in] value Value to reverse
saloutos 0:083111ae2a11 447 \return Reversed value
saloutos 0:083111ae2a11 448 */
saloutos 0:083111ae2a11 449 #define __REV __rev
saloutos 0:083111ae2a11 450
saloutos 0:083111ae2a11 451
saloutos 0:083111ae2a11 452 /**
saloutos 0:083111ae2a11 453 \brief Reverse byte order (16 bit)
saloutos 0:083111ae2a11 454 \details Reverses the byte order in two unsigned short values.
saloutos 0:083111ae2a11 455 \param [in] value Value to reverse
saloutos 0:083111ae2a11 456 \return Reversed value
saloutos 0:083111ae2a11 457 */
saloutos 0:083111ae2a11 458 #ifndef __NO_EMBEDDED_ASM
saloutos 0:083111ae2a11 459 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
saloutos 0:083111ae2a11 460 {
saloutos 0:083111ae2a11 461 rev16 r0, r0
saloutos 0:083111ae2a11 462 bx lr
saloutos 0:083111ae2a11 463 }
saloutos 0:083111ae2a11 464 #endif
saloutos 0:083111ae2a11 465
saloutos 0:083111ae2a11 466
saloutos 0:083111ae2a11 467 /**
saloutos 0:083111ae2a11 468 \brief Reverse byte order in signed short value
saloutos 0:083111ae2a11 469 \details Reverses the byte order in a signed short value with sign extension to integer.
saloutos 0:083111ae2a11 470 \param [in] value Value to reverse
saloutos 0:083111ae2a11 471 \return Reversed value
saloutos 0:083111ae2a11 472 */
saloutos 0:083111ae2a11 473 #ifndef __NO_EMBEDDED_ASM
saloutos 0:083111ae2a11 474 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
saloutos 0:083111ae2a11 475 {
saloutos 0:083111ae2a11 476 revsh r0, r0
saloutos 0:083111ae2a11 477 bx lr
saloutos 0:083111ae2a11 478 }
saloutos 0:083111ae2a11 479 #endif
saloutos 0:083111ae2a11 480
saloutos 0:083111ae2a11 481
saloutos 0:083111ae2a11 482 /**
saloutos 0:083111ae2a11 483 \brief Rotate Right in unsigned value (32 bit)
saloutos 0:083111ae2a11 484 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
saloutos 0:083111ae2a11 485 \param [in] op1 Value to rotate
saloutos 0:083111ae2a11 486 \param [in] op2 Number of Bits to rotate
saloutos 0:083111ae2a11 487 \return Rotated value
saloutos 0:083111ae2a11 488 */
saloutos 0:083111ae2a11 489 #define __ROR __ror
saloutos 0:083111ae2a11 490
saloutos 0:083111ae2a11 491
saloutos 0:083111ae2a11 492 /**
saloutos 0:083111ae2a11 493 \brief Breakpoint
saloutos 0:083111ae2a11 494 \details Causes the processor to enter Debug state.
saloutos 0:083111ae2a11 495 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
saloutos 0:083111ae2a11 496 \param [in] value is ignored by the processor.
saloutos 0:083111ae2a11 497 If required, a debugger can use it to store additional information about the breakpoint.
saloutos 0:083111ae2a11 498 */
saloutos 0:083111ae2a11 499 #define __BKPT(value) __breakpoint(value)
saloutos 0:083111ae2a11 500
saloutos 0:083111ae2a11 501
saloutos 0:083111ae2a11 502 /**
saloutos 0:083111ae2a11 503 \brief Reverse bit order of value
saloutos 0:083111ae2a11 504 \details Reverses the bit order of the given value.
saloutos 0:083111ae2a11 505 \param [in] value Value to reverse
saloutos 0:083111ae2a11 506 \return Reversed value
saloutos 0:083111ae2a11 507 */
saloutos 0:083111ae2a11 508 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
saloutos 0:083111ae2a11 509 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
saloutos 0:083111ae2a11 510 #define __RBIT __rbit
saloutos 0:083111ae2a11 511 #else
saloutos 0:083111ae2a11 512 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
saloutos 0:083111ae2a11 513 {
saloutos 0:083111ae2a11 514 uint32_t result;
saloutos 0:083111ae2a11 515 int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
saloutos 0:083111ae2a11 516
saloutos 0:083111ae2a11 517 result = value; /* r will be reversed bits of v; first get LSB of v */
saloutos 0:083111ae2a11 518 for (value >>= 1U; value; value >>= 1U)
saloutos 0:083111ae2a11 519 {
saloutos 0:083111ae2a11 520 result <<= 1U;
saloutos 0:083111ae2a11 521 result |= value & 1U;
saloutos 0:083111ae2a11 522 s--;
saloutos 0:083111ae2a11 523 }
saloutos 0:083111ae2a11 524 result <<= s; /* shift when v's highest bits are zero */
saloutos 0:083111ae2a11 525 return(result);
saloutos 0:083111ae2a11 526 }
saloutos 0:083111ae2a11 527 #endif
saloutos 0:083111ae2a11 528
saloutos 0:083111ae2a11 529
saloutos 0:083111ae2a11 530 /**
saloutos 0:083111ae2a11 531 \brief Count leading zeros
saloutos 0:083111ae2a11 532 \details Counts the number of leading zeros of a data value.
saloutos 0:083111ae2a11 533 \param [in] value Value to count the leading zeros
saloutos 0:083111ae2a11 534 \return number of leading zeros in value
saloutos 0:083111ae2a11 535 */
saloutos 0:083111ae2a11 536 #define __CLZ __clz
saloutos 0:083111ae2a11 537
saloutos 0:083111ae2a11 538
saloutos 0:083111ae2a11 539 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
saloutos 0:083111ae2a11 540 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
saloutos 0:083111ae2a11 541
saloutos 0:083111ae2a11 542 /**
saloutos 0:083111ae2a11 543 \brief LDR Exclusive (8 bit)
saloutos 0:083111ae2a11 544 \details Executes a exclusive LDR instruction for 8 bit value.
saloutos 0:083111ae2a11 545 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 546 \return value of type uint8_t at (*ptr)
saloutos 0:083111ae2a11 547 */
saloutos 0:083111ae2a11 548 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
saloutos 0:083111ae2a11 549 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
saloutos 0:083111ae2a11 550 #else
saloutos 0:083111ae2a11 551 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
saloutos 0:083111ae2a11 552 #endif
saloutos 0:083111ae2a11 553
saloutos 0:083111ae2a11 554
saloutos 0:083111ae2a11 555 /**
saloutos 0:083111ae2a11 556 \brief LDR Exclusive (16 bit)
saloutos 0:083111ae2a11 557 \details Executes a exclusive LDR instruction for 16 bit values.
saloutos 0:083111ae2a11 558 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 559 \return value of type uint16_t at (*ptr)
saloutos 0:083111ae2a11 560 */
saloutos 0:083111ae2a11 561 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
saloutos 0:083111ae2a11 562 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
saloutos 0:083111ae2a11 563 #else
saloutos 0:083111ae2a11 564 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
saloutos 0:083111ae2a11 565 #endif
saloutos 0:083111ae2a11 566
saloutos 0:083111ae2a11 567
saloutos 0:083111ae2a11 568 /**
saloutos 0:083111ae2a11 569 \brief LDR Exclusive (32 bit)
saloutos 0:083111ae2a11 570 \details Executes a exclusive LDR instruction for 32 bit values.
saloutos 0:083111ae2a11 571 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 572 \return value of type uint32_t at (*ptr)
saloutos 0:083111ae2a11 573 */
saloutos 0:083111ae2a11 574 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
saloutos 0:083111ae2a11 575 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
saloutos 0:083111ae2a11 576 #else
saloutos 0:083111ae2a11 577 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
saloutos 0:083111ae2a11 578 #endif
saloutos 0:083111ae2a11 579
saloutos 0:083111ae2a11 580
saloutos 0:083111ae2a11 581 /**
saloutos 0:083111ae2a11 582 \brief STR Exclusive (8 bit)
saloutos 0:083111ae2a11 583 \details Executes a exclusive STR instruction for 8 bit values.
saloutos 0:083111ae2a11 584 \param [in] value Value to store
saloutos 0:083111ae2a11 585 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 586 \return 0 Function succeeded
saloutos 0:083111ae2a11 587 \return 1 Function failed
saloutos 0:083111ae2a11 588 */
saloutos 0:083111ae2a11 589 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
saloutos 0:083111ae2a11 590 #define __STREXB(value, ptr) __strex(value, ptr)
saloutos 0:083111ae2a11 591 #else
saloutos 0:083111ae2a11 592 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
saloutos 0:083111ae2a11 593 #endif
saloutos 0:083111ae2a11 594
saloutos 0:083111ae2a11 595
saloutos 0:083111ae2a11 596 /**
saloutos 0:083111ae2a11 597 \brief STR Exclusive (16 bit)
saloutos 0:083111ae2a11 598 \details Executes a exclusive STR instruction for 16 bit values.
saloutos 0:083111ae2a11 599 \param [in] value Value to store
saloutos 0:083111ae2a11 600 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 601 \return 0 Function succeeded
saloutos 0:083111ae2a11 602 \return 1 Function failed
saloutos 0:083111ae2a11 603 */
saloutos 0:083111ae2a11 604 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
saloutos 0:083111ae2a11 605 #define __STREXH(value, ptr) __strex(value, ptr)
saloutos 0:083111ae2a11 606 #else
saloutos 0:083111ae2a11 607 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
saloutos 0:083111ae2a11 608 #endif
saloutos 0:083111ae2a11 609
saloutos 0:083111ae2a11 610
saloutos 0:083111ae2a11 611 /**
saloutos 0:083111ae2a11 612 \brief STR Exclusive (32 bit)
saloutos 0:083111ae2a11 613 \details Executes a exclusive STR instruction for 32 bit values.
saloutos 0:083111ae2a11 614 \param [in] value Value to store
saloutos 0:083111ae2a11 615 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 616 \return 0 Function succeeded
saloutos 0:083111ae2a11 617 \return 1 Function failed
saloutos 0:083111ae2a11 618 */
saloutos 0:083111ae2a11 619 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
saloutos 0:083111ae2a11 620 #define __STREXW(value, ptr) __strex(value, ptr)
saloutos 0:083111ae2a11 621 #else
saloutos 0:083111ae2a11 622 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
saloutos 0:083111ae2a11 623 #endif
saloutos 0:083111ae2a11 624
saloutos 0:083111ae2a11 625
saloutos 0:083111ae2a11 626 /**
saloutos 0:083111ae2a11 627 \brief Remove the exclusive lock
saloutos 0:083111ae2a11 628 \details Removes the exclusive lock which is created by LDREX.
saloutos 0:083111ae2a11 629 */
saloutos 0:083111ae2a11 630 #define __CLREX __clrex
saloutos 0:083111ae2a11 631
saloutos 0:083111ae2a11 632
saloutos 0:083111ae2a11 633 /**
saloutos 0:083111ae2a11 634 \brief Signed Saturate
saloutos 0:083111ae2a11 635 \details Saturates a signed value.
saloutos 0:083111ae2a11 636 \param [in] value Value to be saturated
saloutos 0:083111ae2a11 637 \param [in] sat Bit position to saturate to (1..32)
saloutos 0:083111ae2a11 638 \return Saturated value
saloutos 0:083111ae2a11 639 */
saloutos 0:083111ae2a11 640 #define __SSAT __ssat
saloutos 0:083111ae2a11 641
saloutos 0:083111ae2a11 642
saloutos 0:083111ae2a11 643 /**
saloutos 0:083111ae2a11 644 \brief Unsigned Saturate
saloutos 0:083111ae2a11 645 \details Saturates an unsigned value.
saloutos 0:083111ae2a11 646 \param [in] value Value to be saturated
saloutos 0:083111ae2a11 647 \param [in] sat Bit position to saturate to (0..31)
saloutos 0:083111ae2a11 648 \return Saturated value
saloutos 0:083111ae2a11 649 */
saloutos 0:083111ae2a11 650 #define __USAT __usat
saloutos 0:083111ae2a11 651
saloutos 0:083111ae2a11 652
saloutos 0:083111ae2a11 653 /**
saloutos 0:083111ae2a11 654 \brief Rotate Right with Extend (32 bit)
saloutos 0:083111ae2a11 655 \details Moves each bit of a bitstring right by one bit.
saloutos 0:083111ae2a11 656 The carry input is shifted in at the left end of the bitstring.
saloutos 0:083111ae2a11 657 \param [in] value Value to rotate
saloutos 0:083111ae2a11 658 \return Rotated value
saloutos 0:083111ae2a11 659 */
saloutos 0:083111ae2a11 660 #ifndef __NO_EMBEDDED_ASM
saloutos 0:083111ae2a11 661 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
saloutos 0:083111ae2a11 662 {
saloutos 0:083111ae2a11 663 rrx r0, r0
saloutos 0:083111ae2a11 664 bx lr
saloutos 0:083111ae2a11 665 }
saloutos 0:083111ae2a11 666 #endif
saloutos 0:083111ae2a11 667
saloutos 0:083111ae2a11 668
saloutos 0:083111ae2a11 669 /**
saloutos 0:083111ae2a11 670 \brief LDRT Unprivileged (8 bit)
saloutos 0:083111ae2a11 671 \details Executes a Unprivileged LDRT instruction for 8 bit value.
saloutos 0:083111ae2a11 672 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 673 \return value of type uint8_t at (*ptr)
saloutos 0:083111ae2a11 674 */
saloutos 0:083111ae2a11 675 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
saloutos 0:083111ae2a11 676
saloutos 0:083111ae2a11 677
saloutos 0:083111ae2a11 678 /**
saloutos 0:083111ae2a11 679 \brief LDRT Unprivileged (16 bit)
saloutos 0:083111ae2a11 680 \details Executes a Unprivileged LDRT instruction for 16 bit values.
saloutos 0:083111ae2a11 681 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 682 \return value of type uint16_t at (*ptr)
saloutos 0:083111ae2a11 683 */
saloutos 0:083111ae2a11 684 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
saloutos 0:083111ae2a11 685
saloutos 0:083111ae2a11 686
saloutos 0:083111ae2a11 687 /**
saloutos 0:083111ae2a11 688 \brief LDRT Unprivileged (32 bit)
saloutos 0:083111ae2a11 689 \details Executes a Unprivileged LDRT instruction for 32 bit values.
saloutos 0:083111ae2a11 690 \param [in] ptr Pointer to data
saloutos 0:083111ae2a11 691 \return value of type uint32_t at (*ptr)
saloutos 0:083111ae2a11 692 */
saloutos 0:083111ae2a11 693 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
saloutos 0:083111ae2a11 694
saloutos 0:083111ae2a11 695
saloutos 0:083111ae2a11 696 /**
saloutos 0:083111ae2a11 697 \brief STRT Unprivileged (8 bit)
saloutos 0:083111ae2a11 698 \details Executes a Unprivileged STRT instruction for 8 bit values.
saloutos 0:083111ae2a11 699 \param [in] value Value to store
saloutos 0:083111ae2a11 700 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 701 */
saloutos 0:083111ae2a11 702 #define __STRBT(value, ptr) __strt(value, ptr)
saloutos 0:083111ae2a11 703
saloutos 0:083111ae2a11 704
saloutos 0:083111ae2a11 705 /**
saloutos 0:083111ae2a11 706 \brief STRT Unprivileged (16 bit)
saloutos 0:083111ae2a11 707 \details Executes a Unprivileged STRT instruction for 16 bit values.
saloutos 0:083111ae2a11 708 \param [in] value Value to store
saloutos 0:083111ae2a11 709 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 710 */
saloutos 0:083111ae2a11 711 #define __STRHT(value, ptr) __strt(value, ptr)
saloutos 0:083111ae2a11 712
saloutos 0:083111ae2a11 713
saloutos 0:083111ae2a11 714 /**
saloutos 0:083111ae2a11 715 \brief STRT Unprivileged (32 bit)
saloutos 0:083111ae2a11 716 \details Executes a Unprivileged STRT instruction for 32 bit values.
saloutos 0:083111ae2a11 717 \param [in] value Value to store
saloutos 0:083111ae2a11 718 \param [in] ptr Pointer to location
saloutos 0:083111ae2a11 719 */
saloutos 0:083111ae2a11 720 #define __STRT(value, ptr) __strt(value, ptr)
saloutos 0:083111ae2a11 721
saloutos 0:083111ae2a11 722 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
saloutos 0:083111ae2a11 723 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
saloutos 0:083111ae2a11 724
saloutos 0:083111ae2a11 725 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
saloutos 0:083111ae2a11 726
saloutos 0:083111ae2a11 727
saloutos 0:083111ae2a11 728 /* ################### Compiler specific Intrinsics ########################### */
saloutos 0:083111ae2a11 729 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
saloutos 0:083111ae2a11 730 Access to dedicated SIMD instructions
saloutos 0:083111ae2a11 731 @{
saloutos 0:083111ae2a11 732 */
saloutos 0:083111ae2a11 733
saloutos 0:083111ae2a11 734 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
saloutos 0:083111ae2a11 735
saloutos 0:083111ae2a11 736 #define __SADD8 __sadd8
saloutos 0:083111ae2a11 737 #define __QADD8 __qadd8
saloutos 0:083111ae2a11 738 #define __SHADD8 __shadd8
saloutos 0:083111ae2a11 739 #define __UADD8 __uadd8
saloutos 0:083111ae2a11 740 #define __UQADD8 __uqadd8
saloutos 0:083111ae2a11 741 #define __UHADD8 __uhadd8
saloutos 0:083111ae2a11 742 #define __SSUB8 __ssub8
saloutos 0:083111ae2a11 743 #define __QSUB8 __qsub8
saloutos 0:083111ae2a11 744 #define __SHSUB8 __shsub8
saloutos 0:083111ae2a11 745 #define __USUB8 __usub8
saloutos 0:083111ae2a11 746 #define __UQSUB8 __uqsub8
saloutos 0:083111ae2a11 747 #define __UHSUB8 __uhsub8
saloutos 0:083111ae2a11 748 #define __SADD16 __sadd16
saloutos 0:083111ae2a11 749 #define __QADD16 __qadd16
saloutos 0:083111ae2a11 750 #define __SHADD16 __shadd16
saloutos 0:083111ae2a11 751 #define __UADD16 __uadd16
saloutos 0:083111ae2a11 752 #define __UQADD16 __uqadd16
saloutos 0:083111ae2a11 753 #define __UHADD16 __uhadd16
saloutos 0:083111ae2a11 754 #define __SSUB16 __ssub16
saloutos 0:083111ae2a11 755 #define __QSUB16 __qsub16
saloutos 0:083111ae2a11 756 #define __SHSUB16 __shsub16
saloutos 0:083111ae2a11 757 #define __USUB16 __usub16
saloutos 0:083111ae2a11 758 #define __UQSUB16 __uqsub16
saloutos 0:083111ae2a11 759 #define __UHSUB16 __uhsub16
saloutos 0:083111ae2a11 760 #define __SASX __sasx
saloutos 0:083111ae2a11 761 #define __QASX __qasx
saloutos 0:083111ae2a11 762 #define __SHASX __shasx
saloutos 0:083111ae2a11 763 #define __UASX __uasx
saloutos 0:083111ae2a11 764 #define __UQASX __uqasx
saloutos 0:083111ae2a11 765 #define __UHASX __uhasx
saloutos 0:083111ae2a11 766 #define __SSAX __ssax
saloutos 0:083111ae2a11 767 #define __QSAX __qsax
saloutos 0:083111ae2a11 768 #define __SHSAX __shsax
saloutos 0:083111ae2a11 769 #define __USAX __usax
saloutos 0:083111ae2a11 770 #define __UQSAX __uqsax
saloutos 0:083111ae2a11 771 #define __UHSAX __uhsax
saloutos 0:083111ae2a11 772 #define __USAD8 __usad8
saloutos 0:083111ae2a11 773 #define __USADA8 __usada8
saloutos 0:083111ae2a11 774 #define __SSAT16 __ssat16
saloutos 0:083111ae2a11 775 #define __USAT16 __usat16
saloutos 0:083111ae2a11 776 #define __UXTB16 __uxtb16
saloutos 0:083111ae2a11 777 #define __UXTAB16 __uxtab16
saloutos 0:083111ae2a11 778 #define __SXTB16 __sxtb16
saloutos 0:083111ae2a11 779 #define __SXTAB16 __sxtab16
saloutos 0:083111ae2a11 780 #define __SMUAD __smuad
saloutos 0:083111ae2a11 781 #define __SMUADX __smuadx
saloutos 0:083111ae2a11 782 #define __SMLAD __smlad
saloutos 0:083111ae2a11 783 #define __SMLADX __smladx
saloutos 0:083111ae2a11 784 #define __SMLALD __smlald
saloutos 0:083111ae2a11 785 #define __SMLALDX __smlaldx
saloutos 0:083111ae2a11 786 #define __SMUSD __smusd
saloutos 0:083111ae2a11 787 #define __SMUSDX __smusdx
saloutos 0:083111ae2a11 788 #define __SMLSD __smlsd
saloutos 0:083111ae2a11 789 #define __SMLSDX __smlsdx
saloutos 0:083111ae2a11 790 #define __SMLSLD __smlsld
saloutos 0:083111ae2a11 791 #define __SMLSLDX __smlsldx
saloutos 0:083111ae2a11 792 #define __SEL __sel
saloutos 0:083111ae2a11 793 #define __QADD __qadd
saloutos 0:083111ae2a11 794 #define __QSUB __qsub
saloutos 0:083111ae2a11 795
saloutos 0:083111ae2a11 796 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
saloutos 0:083111ae2a11 797 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
saloutos 0:083111ae2a11 798
saloutos 0:083111ae2a11 799 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
saloutos 0:083111ae2a11 800 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
saloutos 0:083111ae2a11 801
saloutos 0:083111ae2a11 802 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
saloutos 0:083111ae2a11 803 ((int64_t)(ARG3) << 32U) ) >> 32U))
saloutos 0:083111ae2a11 804
saloutos 0:083111ae2a11 805 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
saloutos 0:083111ae2a11 806 /*@} end of group CMSIS_SIMD_intrinsics */
saloutos 0:083111ae2a11 807
saloutos 0:083111ae2a11 808
saloutos 0:083111ae2a11 809 #endif /* __CMSIS_ARMCC_H */