Aditya Mehrotra / mbed-dev

Biomimetics MBED Library w/ Added Support for CAN3

Dependents:   CAN_TEST SPIne_Plus_DYNO_SENSORS SPIne_Plus_v2 SPIne_Plus_Dyno_v2

cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armclang.h@0:083111ae2a11, 2020-11-26 (annotated)

Committer:
saloutos
Date:
Thu Nov 26 04:08:56 2020 +0000
Revision:
0:083111ae2a11
first commit of leaned mbed dev lib

Who changed what in which revision?

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saloutos 0:083111ae2a11 1 /**************************************************************************//**
saloutos 0:083111ae2a11 2 * @file cmsis_armclang.h
saloutos 0:083111ae2a11 3 * @brief CMSIS compiler specific macros, functions, instructions
saloutos 0:083111ae2a11 4 * @version V1.00
saloutos 0:083111ae2a11 5 * @date 05. Apr 2017
saloutos 0:083111ae2a11 6 ******************************************************************************/
saloutos 0:083111ae2a11 7 /*
saloutos 0:083111ae2a11 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
saloutos 0:083111ae2a11 9 *
saloutos 0:083111ae2a11 10 * SPDX-License-Identifier: Apache-2.0
saloutos 0:083111ae2a11 11 *
saloutos 0:083111ae2a11 12 * Licensed under the Apache License, Version 2.0 (the License); you may
saloutos 0:083111ae2a11 13 * not use this file except in compliance with the License.
saloutos 0:083111ae2a11 14 * You may obtain a copy of the License at
saloutos 0:083111ae2a11 15 *
saloutos 0:083111ae2a11 16 * www.apache.org/licenses/LICENSE-2.0
saloutos 0:083111ae2a11 17 *
saloutos 0:083111ae2a11 18 * Unless required by applicable law or agreed to in writing, software
saloutos 0:083111ae2a11 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
saloutos 0:083111ae2a11 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
saloutos 0:083111ae2a11 21 * See the License for the specific language governing permissions and
saloutos 0:083111ae2a11 22 * limitations under the License.
saloutos 0:083111ae2a11 23 */
saloutos 0:083111ae2a11 24
saloutos 0:083111ae2a11 25 #ifndef __CMSIS_ARMCLANG_H
saloutos 0:083111ae2a11 26 #define __CMSIS_ARMCLANG_H
saloutos 0:083111ae2a11 27
saloutos 0:083111ae2a11 28 #ifndef __ARM_COMPAT_H
saloutos 0:083111ae2a11 29 #include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
saloutos 0:083111ae2a11 30 #endif
saloutos 0:083111ae2a11 31
saloutos 0:083111ae2a11 32 /* CMSIS compiler specific defines */
saloutos 0:083111ae2a11 33 #ifndef __ASM
saloutos 0:083111ae2a11 34 #define __ASM __asm
saloutos 0:083111ae2a11 35 #endif
saloutos 0:083111ae2a11 36 #ifndef __INLINE
saloutos 0:083111ae2a11 37 #define __INLINE __inline
saloutos 0:083111ae2a11 38 #endif
saloutos 0:083111ae2a11 39 #ifndef __STATIC_INLINE
saloutos 0:083111ae2a11 40 #define __STATIC_INLINE static __inline
saloutos 0:083111ae2a11 41 #endif
saloutos 0:083111ae2a11 42 #ifndef __STATIC_ASM
saloutos 0:083111ae2a11 43 #define __STATIC_ASM static __asm
saloutos 0:083111ae2a11 44 #endif
saloutos 0:083111ae2a11 45 #ifndef __NO_RETURN
saloutos 0:083111ae2a11 46 #define __NO_RETURN __declspec(noreturn)
saloutos 0:083111ae2a11 47 #endif
saloutos 0:083111ae2a11 48 #ifndef __USED
saloutos 0:083111ae2a11 49 #define __USED __attribute__((used))
saloutos 0:083111ae2a11 50 #endif
saloutos 0:083111ae2a11 51 #ifndef __WEAK
saloutos 0:083111ae2a11 52 #define __WEAK __attribute__((weak))
saloutos 0:083111ae2a11 53 #endif
saloutos 0:083111ae2a11 54 #ifndef __UNALIGNED_UINT32
saloutos 0:083111ae2a11 55 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
saloutos 0:083111ae2a11 56 #endif
saloutos 0:083111ae2a11 57 #ifndef __ALIGNED
saloutos 0:083111ae2a11 58 #define __ALIGNED(x) __attribute__((aligned(x)))
saloutos 0:083111ae2a11 59 #endif
saloutos 0:083111ae2a11 60 #ifndef __PACKED
saloutos 0:083111ae2a11 61 #define __PACKED __attribute__((packed))
saloutos 0:083111ae2a11 62 #endif
saloutos 0:083111ae2a11 63
saloutos 0:083111ae2a11 64
saloutos 0:083111ae2a11 65 /* ########################### Core Function Access ########################### */
saloutos 0:083111ae2a11 66
saloutos 0:083111ae2a11 67 /**
saloutos 0:083111ae2a11 68 \brief Get FPSCR
saloutos 0:083111ae2a11 69 \return Floating Point Status/Control register value
saloutos 0:083111ae2a11 70 */
saloutos 0:083111ae2a11 71 __STATIC_INLINE uint32_t __get_FPSCR(void)
saloutos 0:083111ae2a11 72 {
saloutos 0:083111ae2a11 73 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
saloutos 0:083111ae2a11 74 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
saloutos 0:083111ae2a11 75 uint32_t result;
saloutos 0:083111ae2a11 76 __ASM volatile("MRS %0, fpscr" : "=r" (result) );
saloutos 0:083111ae2a11 77 return(result);
saloutos 0:083111ae2a11 78 #else
saloutos 0:083111ae2a11 79 return(0U);
saloutos 0:083111ae2a11 80 #endif
saloutos 0:083111ae2a11 81 }
saloutos 0:083111ae2a11 82
saloutos 0:083111ae2a11 83 /**
saloutos 0:083111ae2a11 84 \brief Set FPSCR
saloutos 0:083111ae2a11 85 \param [in] fpscr Floating Point Status/Control value to set
saloutos 0:083111ae2a11 86 */
saloutos 0:083111ae2a11 87 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
saloutos 0:083111ae2a11 88 {
saloutos 0:083111ae2a11 89 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
saloutos 0:083111ae2a11 90 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
saloutos 0:083111ae2a11 91 __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) : "memory");
saloutos 0:083111ae2a11 92 #else
saloutos 0:083111ae2a11 93 (void)fpscr;
saloutos 0:083111ae2a11 94 #endif
saloutos 0:083111ae2a11 95 }
saloutos 0:083111ae2a11 96
saloutos 0:083111ae2a11 97 /* ########################## Core Instruction Access ######################### */
saloutos 0:083111ae2a11 98 /**
saloutos 0:083111ae2a11 99 \brief No Operation
saloutos 0:083111ae2a11 100 */
saloutos 0:083111ae2a11 101 #define __NOP __builtin_arm_nop
saloutos 0:083111ae2a11 102
saloutos 0:083111ae2a11 103 /**
saloutos 0:083111ae2a11 104 \brief Wait For Interrupt
saloutos 0:083111ae2a11 105 */
saloutos 0:083111ae2a11 106 #define __WFI __builtin_arm_wfi
saloutos 0:083111ae2a11 107
saloutos 0:083111ae2a11 108 /**
saloutos 0:083111ae2a11 109 \brief Wait For Event
saloutos 0:083111ae2a11 110 */
saloutos 0:083111ae2a11 111 #define __WFE __builtin_arm_wfe
saloutos 0:083111ae2a11 112
saloutos 0:083111ae2a11 113 /**
saloutos 0:083111ae2a11 114 \brief Send Event
saloutos 0:083111ae2a11 115 */
saloutos 0:083111ae2a11 116 #define __SEV __builtin_arm_sev
saloutos 0:083111ae2a11 117
saloutos 0:083111ae2a11 118 /**
saloutos 0:083111ae2a11 119 \brief Instruction Synchronization Barrier
saloutos 0:083111ae2a11 120 */
saloutos 0:083111ae2a11 121 #define __ISB() do {\
saloutos 0:083111ae2a11 122 __schedule_barrier();\
saloutos 0:083111ae2a11 123 __builtin_arm_isb(0xF);\
saloutos 0:083111ae2a11 124 __schedule_barrier();\
saloutos 0:083111ae2a11 125 } while (0U)
saloutos 0:083111ae2a11 126
saloutos 0:083111ae2a11 127 /**
saloutos 0:083111ae2a11 128 \brief Data Synchronization Barrier
saloutos 0:083111ae2a11 129 */
saloutos 0:083111ae2a11 130 #define __DSB() do {\
saloutos 0:083111ae2a11 131 __schedule_barrier();\
saloutos 0:083111ae2a11 132 __builtin_arm_dsb(0xF);\
saloutos 0:083111ae2a11 133 __schedule_barrier();\
saloutos 0:083111ae2a11 134 } while (0U)
saloutos 0:083111ae2a11 135
saloutos 0:083111ae2a11 136 /**
saloutos 0:083111ae2a11 137 \brief Data Memory Barrier
saloutos 0:083111ae2a11 138 */
saloutos 0:083111ae2a11 139 #define __DMB() do {\
saloutos 0:083111ae2a11 140 __schedule_barrier();\
saloutos 0:083111ae2a11 141 __builtin_arm_dmb(0xF);\
saloutos 0:083111ae2a11 142 __schedule_barrier();\
saloutos 0:083111ae2a11 143 } while (0U)
saloutos 0:083111ae2a11 144
saloutos 0:083111ae2a11 145 /**
saloutos 0:083111ae2a11 146 \brief Reverse byte order (32 bit)
saloutos 0:083111ae2a11 147 \param [in] value Value to reverse
saloutos 0:083111ae2a11 148 \return Reversed value
saloutos 0:083111ae2a11 149 */
saloutos 0:083111ae2a11 150 #define __REV __builtin_bswap32
saloutos 0:083111ae2a11 151
saloutos 0:083111ae2a11 152 /**
saloutos 0:083111ae2a11 153 \brief Reverse byte order (16 bit)
saloutos 0:083111ae2a11 154 \param [in] value Value to reverse
saloutos 0:083111ae2a11 155 \return Reversed value
saloutos 0:083111ae2a11 156 */
saloutos 0:083111ae2a11 157 #ifndef __NO_EMBEDDED_ASM
saloutos 0:083111ae2a11 158 __attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
saloutos 0:083111ae2a11 159 {
saloutos 0:083111ae2a11 160 uint32_t result;
saloutos 0:083111ae2a11 161 __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
saloutos 0:083111ae2a11 162 return result;
saloutos 0:083111ae2a11 163 }
saloutos 0:083111ae2a11 164 #endif
saloutos 0:083111ae2a11 165
saloutos 0:083111ae2a11 166 /**
saloutos 0:083111ae2a11 167 \brief Reverse byte order in signed short value
saloutos 0:083111ae2a11 168 \param [in] value Value to reverse
saloutos 0:083111ae2a11 169 \return Reversed value
saloutos 0:083111ae2a11 170 */
saloutos 0:083111ae2a11 171 #ifndef __NO_EMBEDDED_ASM
saloutos 0:083111ae2a11 172 __attribute__((section(".revsh_text"))) __STATIC_INLINE int32_t __REVSH(int32_t value)
saloutos 0:083111ae2a11 173 {
saloutos 0:083111ae2a11 174 int32_t result;
saloutos 0:083111ae2a11 175 __ASM volatile("revsh %0, %1" : "=r" (result) : "r" (value));
saloutos 0:083111ae2a11 176 return result;
saloutos 0:083111ae2a11 177 }
saloutos 0:083111ae2a11 178 #endif
saloutos 0:083111ae2a11 179
saloutos 0:083111ae2a11 180 /**
saloutos 0:083111ae2a11 181 \brief Rotate Right in unsigned value (32 bit)
saloutos 0:083111ae2a11 182 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
saloutos 0:083111ae2a11 183 \param [in] op1 Value to rotate
saloutos 0:083111ae2a11 184 \param [in] op2 Number of Bits to rotate
saloutos 0:083111ae2a11 185 \return Rotated value
saloutos 0:083111ae2a11 186 */
saloutos 0:083111ae2a11 187 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
saloutos 0:083111ae2a11 188 {
saloutos 0:083111ae2a11 189 return (op1 >> op2) | (op1 << (32U - op2));
saloutos 0:083111ae2a11 190 }
saloutos 0:083111ae2a11 191
saloutos 0:083111ae2a11 192 /**
saloutos 0:083111ae2a11 193 \brief Breakpoint
saloutos 0:083111ae2a11 194 \param [in] value is ignored by the processor.
saloutos 0:083111ae2a11 195 If required, a debugger can use it to store additional information about the breakpoint.
saloutos 0:083111ae2a11 196 */
saloutos 0:083111ae2a11 197 #define __BKPT(value) __ASM volatile ("bkpt "#value)
saloutos 0:083111ae2a11 198
saloutos 0:083111ae2a11 199 /**
saloutos 0:083111ae2a11 200 \brief Reverse bit order of value
saloutos 0:083111ae2a11 201 \param [in] value Value to reverse
saloutos 0:083111ae2a11 202 \return Reversed value
saloutos 0:083111ae2a11 203 */
saloutos 0:083111ae2a11 204 #define __RBIT __builtin_arm_rbit
saloutos 0:083111ae2a11 205
saloutos 0:083111ae2a11 206 /**
saloutos 0:083111ae2a11 207 \brief Count leading zeros
saloutos 0:083111ae2a11 208 \param [in] value Value to count the leading zeros
saloutos 0:083111ae2a11 209 \return number of leading zeros in value
saloutos 0:083111ae2a11 210 */
saloutos 0:083111ae2a11 211 #define __CLZ __builtin_clz
saloutos 0:083111ae2a11 212
saloutos 0:083111ae2a11 213 /** \brief Get CPSR Register
saloutos 0:083111ae2a11 214 \return CPSR Register value
saloutos 0:083111ae2a11 215 */
saloutos 0:083111ae2a11 216 __STATIC_INLINE uint32_t __get_CPSR(void)
saloutos 0:083111ae2a11 217 {
saloutos 0:083111ae2a11 218 uint32_t result;
saloutos 0:083111ae2a11 219 __ASM volatile("MRS %0, cpsr" : "=r" (result) );
saloutos 0:083111ae2a11 220 return(result);
saloutos 0:083111ae2a11 221 }
saloutos 0:083111ae2a11 222
saloutos 0:083111ae2a11 223 /** \brief Get Mode
saloutos 0:083111ae2a11 224 \return Processor Mode
saloutos 0:083111ae2a11 225 */
saloutos 0:083111ae2a11 226 __STATIC_INLINE uint32_t __get_mode(void) {
saloutos 0:083111ae2a11 227 return (__get_CPSR() & 0x1FU);
saloutos 0:083111ae2a11 228 }
saloutos 0:083111ae2a11 229
saloutos 0:083111ae2a11 230 /** \brief Set Mode
saloutos 0:083111ae2a11 231 \param [in] mode Mode value to set
saloutos 0:083111ae2a11 232 */
saloutos 0:083111ae2a11 233 __STATIC_INLINE void __set_mode(uint32_t mode) {
saloutos 0:083111ae2a11 234 __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
saloutos 0:083111ae2a11 235 }
saloutos 0:083111ae2a11 236
saloutos 0:083111ae2a11 237 /** \brief Set Stack Pointer
saloutos 0:083111ae2a11 238 \param [in] stack Stack Pointer value to set
saloutos 0:083111ae2a11 239 */
saloutos 0:083111ae2a11 240 __STATIC_INLINE void __set_SP(uint32_t stack)
saloutos 0:083111ae2a11 241 {
saloutos 0:083111ae2a11 242 __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
saloutos 0:083111ae2a11 243 }
saloutos 0:083111ae2a11 244
saloutos 0:083111ae2a11 245 /** \brief Set Process Stack Pointer
saloutos 0:083111ae2a11 246 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
saloutos 0:083111ae2a11 247 */
saloutos 0:083111ae2a11 248 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
saloutos 0:083111ae2a11 249 {
saloutos 0:083111ae2a11 250 __ASM volatile(
saloutos 0:083111ae2a11 251 ".preserve8 \n"
saloutos 0:083111ae2a11 252 "BIC r0, r0, #7 \n" // ensure stack is 8-byte aligned
saloutos 0:083111ae2a11 253 "MRS r1, cpsr \n"
saloutos 0:083111ae2a11 254 "CPS #0x1F \n" // no effect in USR mode
saloutos 0:083111ae2a11 255 "MOV sp, r0 \n"
saloutos 0:083111ae2a11 256 "MSR cpsr_c, r1 \n" // no effect in USR mode
saloutos 0:083111ae2a11 257 "ISB"
saloutos 0:083111ae2a11 258 );
saloutos 0:083111ae2a11 259 }
saloutos 0:083111ae2a11 260
saloutos 0:083111ae2a11 261 /** \brief Set User Mode
saloutos 0:083111ae2a11 262 */
saloutos 0:083111ae2a11 263 __STATIC_INLINE void __set_CPS_USR(void)
saloutos 0:083111ae2a11 264 {
saloutos 0:083111ae2a11 265 __ASM volatile("CPS #0x10");
saloutos 0:083111ae2a11 266 }
saloutos 0:083111ae2a11 267
saloutos 0:083111ae2a11 268 /** \brief Get FPEXC
saloutos 0:083111ae2a11 269 \return Floating Point Exception Control register value
saloutos 0:083111ae2a11 270 */
saloutos 0:083111ae2a11 271 __STATIC_INLINE uint32_t __get_FPEXC(void)
saloutos 0:083111ae2a11 272 {
saloutos 0:083111ae2a11 273 #if (__FPU_PRESENT == 1)
saloutos 0:083111ae2a11 274 uint32_t result;
saloutos 0:083111ae2a11 275 __ASM volatile("MRS %0, fpexc" : "=r" (result) );
saloutos 0:083111ae2a11 276 return(result);
saloutos 0:083111ae2a11 277 #else
saloutos 0:083111ae2a11 278 return(0);
saloutos 0:083111ae2a11 279 #endif
saloutos 0:083111ae2a11 280 }
saloutos 0:083111ae2a11 281
saloutos 0:083111ae2a11 282 /** \brief Set FPEXC
saloutos 0:083111ae2a11 283 \param [in] fpexc Floating Point Exception Control value to set
saloutos 0:083111ae2a11 284 */
saloutos 0:083111ae2a11 285 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
saloutos 0:083111ae2a11 286 {
saloutos 0:083111ae2a11 287 #if (__FPU_PRESENT == 1)
saloutos 0:083111ae2a11 288 __ASM volatile ("MSR fpexc, %0" : : "r" (fpexc) : "memory");
saloutos 0:083111ae2a11 289 #endif
saloutos 0:083111ae2a11 290 }
saloutos 0:083111ae2a11 291
saloutos 0:083111ae2a11 292 /** \brief Get CPACR
saloutos 0:083111ae2a11 293 \return Coprocessor Access Control register value
saloutos 0:083111ae2a11 294 */
saloutos 0:083111ae2a11 295 __STATIC_INLINE uint32_t __get_CPACR(void)
saloutos 0:083111ae2a11 296 {
saloutos 0:083111ae2a11 297 uint32_t result;
saloutos 0:083111ae2a11 298 __ASM volatile("MRC p15, 0, %0, c1, c0, 2" : "=r"(result));
saloutos 0:083111ae2a11 299 return result;
saloutos 0:083111ae2a11 300 }
saloutos 0:083111ae2a11 301
saloutos 0:083111ae2a11 302 /** \brief Set CPACR
saloutos 0:083111ae2a11 303 \param [in] cpacr Coprocessor Acccess Control value to set
saloutos 0:083111ae2a11 304 */
saloutos 0:083111ae2a11 305 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
saloutos 0:083111ae2a11 306 {
saloutos 0:083111ae2a11 307 __ASM volatile("MCR p15, 0, %0, c1, c0, 2" : : "r"(cpacr) : "memory");
saloutos 0:083111ae2a11 308 }
saloutos 0:083111ae2a11 309
saloutos 0:083111ae2a11 310 /** \brief Get CBAR
saloutos 0:083111ae2a11 311 \return Configuration Base Address register value
saloutos 0:083111ae2a11 312 */
saloutos 0:083111ae2a11 313 __STATIC_INLINE uint32_t __get_CBAR() {
saloutos 0:083111ae2a11 314 uint32_t result;
saloutos 0:083111ae2a11 315 __ASM volatile("MRC p15, 4, %0, c15, c0, 0" : "=r"(result));
saloutos 0:083111ae2a11 316 return result;
saloutos 0:083111ae2a11 317 }
saloutos 0:083111ae2a11 318
saloutos 0:083111ae2a11 319 /** \brief Get TTBR0
saloutos 0:083111ae2a11 320
saloutos 0:083111ae2a11 321 This function returns the value of the Translation Table Base Register 0.
saloutos 0:083111ae2a11 322
saloutos 0:083111ae2a11 323 \return Translation Table Base Register 0 value
saloutos 0:083111ae2a11 324 */
saloutos 0:083111ae2a11 325 __STATIC_INLINE uint32_t __get_TTBR0() {
saloutos 0:083111ae2a11 326 uint32_t result;
saloutos 0:083111ae2a11 327 __ASM volatile("MRC p15, 0, %0, c2, c0, 0" : "=r"(result));
saloutos 0:083111ae2a11 328 return result;
saloutos 0:083111ae2a11 329 }
saloutos 0:083111ae2a11 330
saloutos 0:083111ae2a11 331 /** \brief Set TTBR0
saloutos 0:083111ae2a11 332
saloutos 0:083111ae2a11 333 This function assigns the given value to the Translation Table Base Register 0.
saloutos 0:083111ae2a11 334
saloutos 0:083111ae2a11 335 \param [in] ttbr0 Translation Table Base Register 0 value to set
saloutos 0:083111ae2a11 336 */
saloutos 0:083111ae2a11 337 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
saloutos 0:083111ae2a11 338 __ASM volatile("MCR p15, 0, %0, c2, c0, 0" : : "r"(ttbr0) : "memory");
saloutos 0:083111ae2a11 339 }
saloutos 0:083111ae2a11 340
saloutos 0:083111ae2a11 341 /** \brief Get DACR
saloutos 0:083111ae2a11 342
saloutos 0:083111ae2a11 343 This function returns the value of the Domain Access Control Register.
saloutos 0:083111ae2a11 344
saloutos 0:083111ae2a11 345 \return Domain Access Control Register value
saloutos 0:083111ae2a11 346 */
saloutos 0:083111ae2a11 347 __STATIC_INLINE uint32_t __get_DACR() {
saloutos 0:083111ae2a11 348 uint32_t result;
saloutos 0:083111ae2a11 349 __ASM volatile("MRC p15, 0, %0, c3, c0, 0" : "=r"(result));
saloutos 0:083111ae2a11 350 return result;
saloutos 0:083111ae2a11 351 }
saloutos 0:083111ae2a11 352
saloutos 0:083111ae2a11 353 /** \brief Set DACR
saloutos 0:083111ae2a11 354
saloutos 0:083111ae2a11 355 This function assigns the given value to the Domain Access Control Register.
saloutos 0:083111ae2a11 356
saloutos 0:083111ae2a11 357 \param [in] dacr Domain Access Control Register value to set
saloutos 0:083111ae2a11 358 */
saloutos 0:083111ae2a11 359 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
saloutos 0:083111ae2a11 360 __ASM volatile("MCR p15, 0, %0, c3, c0, 0" : : "r"(dacr) : "memory");
saloutos 0:083111ae2a11 361 }
saloutos 0:083111ae2a11 362
saloutos 0:083111ae2a11 363 /** \brief Set SCTLR
saloutos 0:083111ae2a11 364
saloutos 0:083111ae2a11 365 This function assigns the given value to the System Control Register.
saloutos 0:083111ae2a11 366
saloutos 0:083111ae2a11 367 \param [in] sctlr System Control Register value to set
saloutos 0:083111ae2a11 368 */
saloutos 0:083111ae2a11 369 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
saloutos 0:083111ae2a11 370 {
saloutos 0:083111ae2a11 371 __ASM volatile("MCR p15, 0, %0, c1, c0, 0" : : "r"(sctlr) : "memory");
saloutos 0:083111ae2a11 372 }
saloutos 0:083111ae2a11 373
saloutos 0:083111ae2a11 374 /** \brief Get SCTLR
saloutos 0:083111ae2a11 375 \return System Control Register value
saloutos 0:083111ae2a11 376 */
saloutos 0:083111ae2a11 377 __STATIC_INLINE uint32_t __get_SCTLR() {
saloutos 0:083111ae2a11 378 uint32_t result;
saloutos 0:083111ae2a11 379 __ASM volatile("MRC p15, 0, %0, c1, c0, 0" : "=r"(result));
saloutos 0:083111ae2a11 380 return result;
saloutos 0:083111ae2a11 381 }
saloutos 0:083111ae2a11 382
saloutos 0:083111ae2a11 383 /** \brief Set ACTRL
saloutos 0:083111ae2a11 384 \param [in] actrl Auxiliary Control Register value to set
saloutos 0:083111ae2a11 385 */
saloutos 0:083111ae2a11 386 __STATIC_INLINE void __set_ACTRL(uint32_t actrl)
saloutos 0:083111ae2a11 387 {
saloutos 0:083111ae2a11 388 __ASM volatile("MCR p15, 0, %0, c1, c0, 1" : : "r"(actrl) : "memory");
saloutos 0:083111ae2a11 389 }
saloutos 0:083111ae2a11 390
saloutos 0:083111ae2a11 391 /** \brief Get ACTRL
saloutos 0:083111ae2a11 392 \return Auxiliary Control Register value
saloutos 0:083111ae2a11 393 */
saloutos 0:083111ae2a11 394 __STATIC_INLINE uint32_t __get_ACTRL(void)
saloutos 0:083111ae2a11 395 {
saloutos 0:083111ae2a11 396 uint32_t result;
saloutos 0:083111ae2a11 397 __ASM volatile("MRC p15, 0, %0, c1, c0, 1" : "=r"(result));
saloutos 0:083111ae2a11 398 return result;
saloutos 0:083111ae2a11 399 }
saloutos 0:083111ae2a11 400
saloutos 0:083111ae2a11 401 /** \brief Get MPIDR
saloutos 0:083111ae2a11 402
saloutos 0:083111ae2a11 403 This function returns the value of the Multiprocessor Affinity Register.
saloutos 0:083111ae2a11 404
saloutos 0:083111ae2a11 405 \return Multiprocessor Affinity Register value
saloutos 0:083111ae2a11 406 */
saloutos 0:083111ae2a11 407 __STATIC_INLINE uint32_t __get_MPIDR(void)
saloutos 0:083111ae2a11 408 {
saloutos 0:083111ae2a11 409 uint32_t result;
saloutos 0:083111ae2a11 410 __ASM volatile("MRC p15, 0, %0, c0, c0, 5" : "=r"(result));
saloutos 0:083111ae2a11 411 return result;
saloutos 0:083111ae2a11 412 }
saloutos 0:083111ae2a11 413
saloutos 0:083111ae2a11 414 /** \brief Get VBAR
saloutos 0:083111ae2a11 415
saloutos 0:083111ae2a11 416 This function returns the value of the Vector Base Address Register.
saloutos 0:083111ae2a11 417
saloutos 0:083111ae2a11 418 \return Vector Base Address Register
saloutos 0:083111ae2a11 419 */
saloutos 0:083111ae2a11 420 __STATIC_INLINE uint32_t __get_VBAR(void)
saloutos 0:083111ae2a11 421 {
saloutos 0:083111ae2a11 422 uint32_t result;
saloutos 0:083111ae2a11 423 __ASM volatile("MRC p15, 0, %0, c12, c0, 0" : "=r"(result));
saloutos 0:083111ae2a11 424 return result;
saloutos 0:083111ae2a11 425 }
saloutos 0:083111ae2a11 426
saloutos 0:083111ae2a11 427 /** \brief Set VBAR
saloutos 0:083111ae2a11 428
saloutos 0:083111ae2a11 429 This function assigns the given value to the Vector Base Address Register.
saloutos 0:083111ae2a11 430
saloutos 0:083111ae2a11 431 \param [in] vbar Vector Base Address Register value to set
saloutos 0:083111ae2a11 432 */
saloutos 0:083111ae2a11 433 __STATIC_INLINE void __set_VBAR(uint32_t vbar)
saloutos 0:083111ae2a11 434 {
saloutos 0:083111ae2a11 435 __ASM volatile("MCR p15, 0, %0, c12, c0, 1" : : "r"(vbar) : "memory");
saloutos 0:083111ae2a11 436 }
saloutos 0:083111ae2a11 437
saloutos 0:083111ae2a11 438 /** \brief Set CNTP_TVAL
saloutos 0:083111ae2a11 439
saloutos 0:083111ae2a11 440 This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
saloutos 0:083111ae2a11 441
saloutos 0:083111ae2a11 442 \param [in] value CNTP_TVAL Register value to set
saloutos 0:083111ae2a11 443 */
saloutos 0:083111ae2a11 444 __STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
saloutos 0:083111ae2a11 445 __ASM volatile("MCR p15, 0, %0, c14, c2, 0" : : "r"(value) : "memory");
saloutos 0:083111ae2a11 446 }
saloutos 0:083111ae2a11 447
saloutos 0:083111ae2a11 448 /** \brief Get CNTP_TVAL
saloutos 0:083111ae2a11 449
saloutos 0:083111ae2a11 450 This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
saloutos 0:083111ae2a11 451
saloutos 0:083111ae2a11 452 \return CNTP_TVAL Register value
saloutos 0:083111ae2a11 453 */
saloutos 0:083111ae2a11 454 __STATIC_INLINE uint32_t __get_CNTP_TVAL() {
saloutos 0:083111ae2a11 455 uint32_t result;
saloutos 0:083111ae2a11 456 __ASM volatile("MRC p15, 0, %0, c14, c2, 0" : "=r"(result));
saloutos 0:083111ae2a11 457 return result;
saloutos 0:083111ae2a11 458 }
saloutos 0:083111ae2a11 459
saloutos 0:083111ae2a11 460 /** \brief Set CNTP_CTL
saloutos 0:083111ae2a11 461
saloutos 0:083111ae2a11 462 This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
saloutos 0:083111ae2a11 463
saloutos 0:083111ae2a11 464 \param [in] value CNTP_CTL Register value to set
saloutos 0:083111ae2a11 465 */
saloutos 0:083111ae2a11 466 __STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
saloutos 0:083111ae2a11 467 __ASM volatile("MCR p15, 0, %0, c14, c2, 1" : : "r"(value) : "memory");
saloutos 0:083111ae2a11 468 }
saloutos 0:083111ae2a11 469
saloutos 0:083111ae2a11 470 /** \brief Set TLBIALL
saloutos 0:083111ae2a11 471
saloutos 0:083111ae2a11 472 TLB Invalidate All
saloutos 0:083111ae2a11 473 */
saloutos 0:083111ae2a11 474 __STATIC_INLINE void __set_TLBIALL(uint32_t value) {
saloutos 0:083111ae2a11 475 __ASM volatile("MCR p15, 0, %0, c8, c7, 0" : : "r"(value) : "memory");
saloutos 0:083111ae2a11 476 }
saloutos 0:083111ae2a11 477
saloutos 0:083111ae2a11 478 /** \brief Set BPIALL.
saloutos 0:083111ae2a11 479
saloutos 0:083111ae2a11 480 Branch Predictor Invalidate All
saloutos 0:083111ae2a11 481 */
saloutos 0:083111ae2a11 482 __STATIC_INLINE void __set_BPIALL(uint32_t value) {
saloutos 0:083111ae2a11 483 __ASM volatile("MCR p15, 0, %0, c7, c5, 6" : : "r"(value) : "memory");
saloutos 0:083111ae2a11 484 }
saloutos 0:083111ae2a11 485
saloutos 0:083111ae2a11 486 /** \brief Set ICIALLU
saloutos 0:083111ae2a11 487
saloutos 0:083111ae2a11 488 Instruction Cache Invalidate All
saloutos 0:083111ae2a11 489 */
saloutos 0:083111ae2a11 490 __STATIC_INLINE void __set_ICIALLU(uint32_t value) {
saloutos 0:083111ae2a11 491 __ASM volatile("MCR p15, 0, %0, c7, c5, 0" : : "r"(value) : "memory");
saloutos 0:083111ae2a11 492 }
saloutos 0:083111ae2a11 493
saloutos 0:083111ae2a11 494 /** \brief Set DCCMVAC
saloutos 0:083111ae2a11 495
saloutos 0:083111ae2a11 496 Data cache clean
saloutos 0:083111ae2a11 497 */
saloutos 0:083111ae2a11 498 __STATIC_INLINE void __set_DCCMVAC(uint32_t value) {
saloutos 0:083111ae2a11 499 __ASM volatile("MCR p15, 0, %0, c7, c10, 1" : : "r"(value) : "memory");
saloutos 0:083111ae2a11 500 }
saloutos 0:083111ae2a11 501
saloutos 0:083111ae2a11 502 /** \brief Set DCIMVAC
saloutos 0:083111ae2a11 503
saloutos 0:083111ae2a11 504 Data cache invalidate
saloutos 0:083111ae2a11 505 */
saloutos 0:083111ae2a11 506 __STATIC_INLINE void __set_DCIMVAC(uint32_t value) {
saloutos 0:083111ae2a11 507 __ASM volatile("MCR p15, 0, %0, c7, c6, 1" : : "r"(value) : "memory");
saloutos 0:083111ae2a11 508 }
saloutos 0:083111ae2a11 509
saloutos 0:083111ae2a11 510 /** \brief Set DCCIMVAC
saloutos 0:083111ae2a11 511
saloutos 0:083111ae2a11 512 Data cache clean and invalidate
saloutos 0:083111ae2a11 513 */
saloutos 0:083111ae2a11 514 __STATIC_INLINE void __set_DCCIMVAC(uint32_t value) {
saloutos 0:083111ae2a11 515 __ASM volatile("MCR p15, 0, %0, c7, c14, 1" : : "r"(value) : "memory");
saloutos 0:083111ae2a11 516 }
saloutos 0:083111ae2a11 517
saloutos 0:083111ae2a11 518 /** \brief Clean and Invalidate the entire data or unified cache
saloutos 0:083111ae2a11 519
saloutos 0:083111ae2a11 520 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
saloutos 0:083111ae2a11 521 */
saloutos 0:083111ae2a11 522 __STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) {
saloutos 0:083111ae2a11 523 __ASM volatile(
saloutos 0:083111ae2a11 524 " PUSH {R4-R11} \n"
saloutos 0:083111ae2a11 525
saloutos 0:083111ae2a11 526 " MRC p15, 1, R6, c0, c0, 1 \n" // Read CLIDR
saloutos 0:083111ae2a11 527 " ANDS R3, R6, #0x07000000 \n" // Extract coherency level
saloutos 0:083111ae2a11 528 " MOV R3, R3, LSR #23 \n" // Total cache levels << 1
saloutos 0:083111ae2a11 529 " BEQ Finished \n" // If 0, no need to clean
saloutos 0:083111ae2a11 530
saloutos 0:083111ae2a11 531 " MOV R10, #0 \n" // R10 holds current cache level << 1
saloutos 0:083111ae2a11 532 "Loop1: ADD R2, R10, R10, LSR #1 \n" // R2 holds cache "Set" position
saloutos 0:083111ae2a11 533 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
saloutos 0:083111ae2a11 534 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
saloutos 0:083111ae2a11 535 " CMP R1, #2 \n"
saloutos 0:083111ae2a11 536 " BLT Skip \n" // No cache or only instruction cache at this level
saloutos 0:083111ae2a11 537
saloutos 0:083111ae2a11 538 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
saloutos 0:083111ae2a11 539 " ISB \n" // ISB to sync the change to the CacheSizeID reg
saloutos 0:083111ae2a11 540 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
saloutos 0:083111ae2a11 541 " AND R2, R1, #7 \n" // Extract the line length field
saloutos 0:083111ae2a11 542 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
saloutos 0:083111ae2a11 543 " LDR R4, =0x3FF \n"
saloutos 0:083111ae2a11 544 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
saloutos 0:083111ae2a11 545 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
saloutos 0:083111ae2a11 546 " LDR R7, =0x7FFF \n"
saloutos 0:083111ae2a11 547 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
saloutos 0:083111ae2a11 548
saloutos 0:083111ae2a11 549 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
saloutos 0:083111ae2a11 550
saloutos 0:083111ae2a11 551 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
saloutos 0:083111ae2a11 552 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
saloutos 0:083111ae2a11 553 " CMP R0, #0 \n"
saloutos 0:083111ae2a11 554 " BNE Dccsw \n"
saloutos 0:083111ae2a11 555 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
saloutos 0:083111ae2a11 556 " B cont \n"
saloutos 0:083111ae2a11 557 "Dccsw: CMP R0, #1 \n"
saloutos 0:083111ae2a11 558 " BNE Dccisw \n"
saloutos 0:083111ae2a11 559 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
saloutos 0:083111ae2a11 560 " B cont \n"
saloutos 0:083111ae2a11 561 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW. Clean and Invalidate by Set/Way
saloutos 0:083111ae2a11 562 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
saloutos 0:083111ae2a11 563 " BGE Loop3 \n"
saloutos 0:083111ae2a11 564 " SUBS R7, R7, #1 \n" // Decrement the Set number
saloutos 0:083111ae2a11 565 " BGE Loop2 \n"
saloutos 0:083111ae2a11 566 "Skip: ADD R10, R10, #2 \n" // Increment the cache number
saloutos 0:083111ae2a11 567 " CMP R3, R10 \n"
saloutos 0:083111ae2a11 568 " BGT Loop1 \n"
saloutos 0:083111ae2a11 569
saloutos 0:083111ae2a11 570 "Finished: \n"
saloutos 0:083111ae2a11 571 " DSB \n"
saloutos 0:083111ae2a11 572 " POP {R4-R11} "
saloutos 0:083111ae2a11 573 );
saloutos 0:083111ae2a11 574 }
saloutos 0:083111ae2a11 575
saloutos 0:083111ae2a11 576 /** \brief Enable Floating Point Unit
saloutos 0:083111ae2a11 577
saloutos 0:083111ae2a11 578 Critical section, called from undef handler, so systick is disabled
saloutos 0:083111ae2a11 579 */
saloutos 0:083111ae2a11 580 __STATIC_INLINE void __FPU_Enable(void) {
saloutos 0:083111ae2a11 581 __ASM volatile(
saloutos 0:083111ae2a11 582 //Permit access to VFP/NEON, registers by modifying CPACR
saloutos 0:083111ae2a11 583 " MRC p15,0,R1,c1,c0,2 \n"
saloutos 0:083111ae2a11 584 " ORR R1,R1,#0x00F00000 \n"
saloutos 0:083111ae2a11 585 " MCR p15,0,R1,c1,c0,2 \n"
saloutos 0:083111ae2a11 586
saloutos 0:083111ae2a11 587 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
saloutos 0:083111ae2a11 588 " ISB \n"
saloutos 0:083111ae2a11 589
saloutos 0:083111ae2a11 590 //Enable VFP/NEON
saloutos 0:083111ae2a11 591 " VMRS R1,FPEXC \n"
saloutos 0:083111ae2a11 592 " ORR R1,R1,#0x40000000 \n"
saloutos 0:083111ae2a11 593 " VMSR FPEXC,R1 \n"
saloutos 0:083111ae2a11 594
saloutos 0:083111ae2a11 595 //Initialise VFP/NEON registers to 0
saloutos 0:083111ae2a11 596 " MOV R2,#0 \n"
saloutos 0:083111ae2a11 597 #if 0 // TODO: Initialize FPU registers according to available register count
saloutos 0:083111ae2a11 598 ".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16 \n"
saloutos 0:083111ae2a11 599 //Initialise D16 registers to 0
saloutos 0:083111ae2a11 600 " VMOV D0, R2,R2 \n"
saloutos 0:083111ae2a11 601 " VMOV D1, R2,R2 \n"
saloutos 0:083111ae2a11 602 " VMOV D2, R2,R2 \n"
saloutos 0:083111ae2a11 603 " VMOV D3, R2,R2 \n"
saloutos 0:083111ae2a11 604 " VMOV D4, R2,R2 \n"
saloutos 0:083111ae2a11 605 " VMOV D5, R2,R2 \n"
saloutos 0:083111ae2a11 606 " VMOV D6, R2,R2 \n"
saloutos 0:083111ae2a11 607 " VMOV D7, R2,R2 \n"
saloutos 0:083111ae2a11 608 " VMOV D8, R2,R2 \n"
saloutos 0:083111ae2a11 609 " VMOV D9, R2,R2 \n"
saloutos 0:083111ae2a11 610 " VMOV D10,R2,R2 \n"
saloutos 0:083111ae2a11 611 " VMOV D11,R2,R2 \n"
saloutos 0:083111ae2a11 612 " VMOV D12,R2,R2 \n"
saloutos 0:083111ae2a11 613 " VMOV D13,R2,R2 \n"
saloutos 0:083111ae2a11 614 " VMOV D14,R2,R2 \n"
saloutos 0:083111ae2a11 615 " VMOV D15,R2,R2 \n"
saloutos 0:083111ae2a11 616 ".endif \n"
saloutos 0:083111ae2a11 617
saloutos 0:083111ae2a11 618 ".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 \n"
saloutos 0:083111ae2a11 619 //Initialise D32 registers to 0
saloutos 0:083111ae2a11 620 " VMOV D16,R2,R2 \n"
saloutos 0:083111ae2a11 621 " VMOV D17,R2,R2 \n"
saloutos 0:083111ae2a11 622 " VMOV D18,R2,R2 \n"
saloutos 0:083111ae2a11 623 " VMOV D19,R2,R2 \n"
saloutos 0:083111ae2a11 624 " VMOV D20,R2,R2 \n"
saloutos 0:083111ae2a11 625 " VMOV D21,R2,R2 \n"
saloutos 0:083111ae2a11 626 " VMOV D22,R2,R2 \n"
saloutos 0:083111ae2a11 627 " VMOV D23,R2,R2 \n"
saloutos 0:083111ae2a11 628 " VMOV D24,R2,R2 \n"
saloutos 0:083111ae2a11 629 " VMOV D25,R2,R2 \n"
saloutos 0:083111ae2a11 630 " VMOV D26,R2,R2 \n"
saloutos 0:083111ae2a11 631 " VMOV D27,R2,R2 \n"
saloutos 0:083111ae2a11 632 " VMOV D28,R2,R2 \n"
saloutos 0:083111ae2a11 633 " VMOV D29,R2,R2 \n"
saloutos 0:083111ae2a11 634 " VMOV D30,R2,R2 \n"
saloutos 0:083111ae2a11 635 " VMOV D31,R2,R2 \n"
saloutos 0:083111ae2a11 636 ".endif \n"
saloutos 0:083111ae2a11 637 #endif
saloutos 0:083111ae2a11 638 //Initialise FPSCR to a known state
saloutos 0:083111ae2a11 639 " VMRS R2,FPSCR \n"
saloutos 0:083111ae2a11 640 " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
saloutos 0:083111ae2a11 641 " AND R2,R2,R3 \n"
saloutos 0:083111ae2a11 642 " VMSR FPSCR,R2 "
saloutos 0:083111ae2a11 643 );
saloutos 0:083111ae2a11 644 }
saloutos 0:083111ae2a11 645
saloutos 0:083111ae2a11 646 #endif /* __CMSIS_ARMCC_H */