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targets/cmsis/core_cm4.h@0:38ccae254a29, 2014-10-18 (annotated)

Committer:: mega64
Date:: Sat Oct 18 02:40:17 2014 +0000
Revision:: 0:38ccae254a29

only for STM32F030F4

Who changed what in which revision?

User	Revision	Line number	New contents of line
mega64	0:38ccae254a29	1	/************************************************************************//
mega64	0:38ccae254a29	2	* @file core_cm4.h
mega64	0:38ccae254a29	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
mega64	0:38ccae254a29	4	* @version V3.20
mega64	0:38ccae254a29	5	* @date 25. February 2013
mega64	0:38ccae254a29	6	*
mega64	0:38ccae254a29	7	* @note
mega64	0:38ccae254a29	8	*
mega64	0:38ccae254a29	9	******************************************************************************/
mega64	0:38ccae254a29	10	/* Copyright (c) 2009 - 2013 ARM LIMITED
mega64	0:38ccae254a29	11
mega64	0:38ccae254a29	12	All rights reserved.
mega64	0:38ccae254a29	13	Redistribution and use in source and binary forms, with or without
mega64	0:38ccae254a29	14	modification, are permitted provided that the following conditions are met:
mega64	0:38ccae254a29	15	- Redistributions of source code must retain the above copyright
mega64	0:38ccae254a29	16	notice, this list of conditions and the following disclaimer.
mega64	0:38ccae254a29	17	- Redistributions in binary form must reproduce the above copyright
mega64	0:38ccae254a29	18	notice, this list of conditions and the following disclaimer in the
mega64	0:38ccae254a29	19	documentation and/or other materials provided with the distribution.
mega64	0:38ccae254a29	20	- Neither the name of ARM nor the names of its contributors may be used
mega64	0:38ccae254a29	21	to endorse or promote products derived from this software without
mega64	0:38ccae254a29	22	specific prior written permission.
mega64	0:38ccae254a29	23	*
mega64	0:38ccae254a29	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mega64	0:38ccae254a29	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mega64	0:38ccae254a29	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mega64	0:38ccae254a29	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mega64	0:38ccae254a29	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mega64	0:38ccae254a29	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mega64	0:38ccae254a29	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mega64	0:38ccae254a29	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mega64	0:38ccae254a29	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mega64	0:38ccae254a29	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mega64	0:38ccae254a29	34	POSSIBILITY OF SUCH DAMAGE.
mega64	0:38ccae254a29	35	---------------------------------------------------------------------------*/
mega64	0:38ccae254a29	36
mega64	0:38ccae254a29	37
mega64	0:38ccae254a29	38	#if defined ( __ICCARM__ )
mega64	0:38ccae254a29	39	#pragma system_include /* treat file as system include file for MISRA check */
mega64	0:38ccae254a29	40	#endif
mega64	0:38ccae254a29	41
mega64	0:38ccae254a29	42	#ifdef __cplusplus
mega64	0:38ccae254a29	43	extern "C" {
mega64	0:38ccae254a29	44	#endif
mega64	0:38ccae254a29	45
mega64	0:38ccae254a29	46	#ifndef __CORE_CM4_H_GENERIC
mega64	0:38ccae254a29	47	#define __CORE_CM4_H_GENERIC
mega64	0:38ccae254a29	48
mega64	0:38ccae254a29	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mega64	0:38ccae254a29	50	CMSIS violates the following MISRA-C:2004 rules:
mega64	0:38ccae254a29	51
mega64	0:38ccae254a29	52	\li Required Rule 8.5, object/function definition in header file.<br>
mega64	0:38ccae254a29	53	Function definitions in header files are used to allow 'inlining'.
mega64	0:38ccae254a29	54
mega64	0:38ccae254a29	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mega64	0:38ccae254a29	56	Unions are used for effective representation of core registers.
mega64	0:38ccae254a29	57
mega64	0:38ccae254a29	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
mega64	0:38ccae254a29	59	Function-like macros are used to allow more efficient code.
mega64	0:38ccae254a29	60	*/
mega64	0:38ccae254a29	61
mega64	0:38ccae254a29	62
mega64	0:38ccae254a29	63	/*******************************************************************************
mega64	0:38ccae254a29	64	* CMSIS definitions
mega64	0:38ccae254a29	65	******************************************************************************/
mega64	0:38ccae254a29	66	/** \ingroup Cortex_M4
mega64	0:38ccae254a29	67	@{
mega64	0:38ccae254a29	68	*/
mega64	0:38ccae254a29	69
mega64	0:38ccae254a29	70	/* CMSIS CM4 definitions */
mega64	0:38ccae254a29	71	#define __CM4_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
mega64	0:38ccae254a29	72	#define __CM4_CMSIS_VERSION_SUB (0x20) /!< [15:0] CMSIS HAL sub version /
mega64	0:38ccae254a29	73	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) \| \
mega64	0:38ccae254a29	74	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
mega64	0:38ccae254a29	75
mega64	0:38ccae254a29	76	#define __CORTEX_M (0x04) /!< Cortex-M Core /
mega64	0:38ccae254a29	77
mega64	0:38ccae254a29	78
mega64	0:38ccae254a29	79	#if defined ( __CC_ARM )
mega64	0:38ccae254a29	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
mega64	0:38ccae254a29	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
mega64	0:38ccae254a29	82	#define __STATIC_INLINE static __inline
mega64	0:38ccae254a29	83
mega64	0:38ccae254a29	84	#elif defined ( __ICCARM__ )
mega64	0:38ccae254a29	85	#define __ASM __asm /!< asm keyword for IAR Compiler /
mega64	0:38ccae254a29	86	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
mega64	0:38ccae254a29	87	#define __STATIC_INLINE static inline
mega64	0:38ccae254a29	88
mega64	0:38ccae254a29	89	#elif defined ( __TMS470__ )
mega64	0:38ccae254a29	90	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
mega64	0:38ccae254a29	91	#define __STATIC_INLINE static inline
mega64	0:38ccae254a29	92
mega64	0:38ccae254a29	93	#elif defined ( __GNUC__ )
mega64	0:38ccae254a29	94	#define __ASM __asm /!< asm keyword for GNU Compiler /
mega64	0:38ccae254a29	95	#define __INLINE inline /!< inline keyword for GNU Compiler /
mega64	0:38ccae254a29	96	#define __STATIC_INLINE static inline
mega64	0:38ccae254a29	97
mega64	0:38ccae254a29	98	#elif defined ( __TASKING__ )
mega64	0:38ccae254a29	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
mega64	0:38ccae254a29	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
mega64	0:38ccae254a29	101	#define __STATIC_INLINE static inline
mega64	0:38ccae254a29	102
mega64	0:38ccae254a29	103	#endif
mega64	0:38ccae254a29	104
mega64	0:38ccae254a29	105	/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
mega64	0:38ccae254a29	106	*/
mega64	0:38ccae254a29	107	#if defined ( __CC_ARM )
mega64	0:38ccae254a29	108	#if defined __TARGET_FPU_VFP
mega64	0:38ccae254a29	109	#if (__FPU_PRESENT == 1)
mega64	0:38ccae254a29	110	#define __FPU_USED 1
mega64	0:38ccae254a29	111	#else
mega64	0:38ccae254a29	112	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64	0:38ccae254a29	113	#define __FPU_USED 0
mega64	0:38ccae254a29	114	#endif
mega64	0:38ccae254a29	115	#else
mega64	0:38ccae254a29	116	#define __FPU_USED 0
mega64	0:38ccae254a29	117	#endif
mega64	0:38ccae254a29	118
mega64	0:38ccae254a29	119	#elif defined ( __ICCARM__ )
mega64	0:38ccae254a29	120	#if defined __ARMVFP__
mega64	0:38ccae254a29	121	#if (__FPU_PRESENT == 1)
mega64	0:38ccae254a29	122	#define __FPU_USED 1
mega64	0:38ccae254a29	123	#else
mega64	0:38ccae254a29	124	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64	0:38ccae254a29	125	#define __FPU_USED 0
mega64	0:38ccae254a29	126	#endif
mega64	0:38ccae254a29	127	#else
mega64	0:38ccae254a29	128	#define __FPU_USED 0
mega64	0:38ccae254a29	129	#endif
mega64	0:38ccae254a29	130
mega64	0:38ccae254a29	131	#elif defined ( __TMS470__ )
mega64	0:38ccae254a29	132	#if defined __TI_VFP_SUPPORT__
mega64	0:38ccae254a29	133	#if (__FPU_PRESENT == 1)
mega64	0:38ccae254a29	134	#define __FPU_USED 1
mega64	0:38ccae254a29	135	#else
mega64	0:38ccae254a29	136	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64	0:38ccae254a29	137	#define __FPU_USED 0
mega64	0:38ccae254a29	138	#endif
mega64	0:38ccae254a29	139	#else
mega64	0:38ccae254a29	140	#define __FPU_USED 0
mega64	0:38ccae254a29	141	#endif
mega64	0:38ccae254a29	142
mega64	0:38ccae254a29	143	#elif defined ( __GNUC__ )
mega64	0:38ccae254a29	144	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
mega64	0:38ccae254a29	145	#if (__FPU_PRESENT == 1)
mega64	0:38ccae254a29	146	#define __FPU_USED 1
mega64	0:38ccae254a29	147	#else
mega64	0:38ccae254a29	148	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64	0:38ccae254a29	149	#define __FPU_USED 0
mega64	0:38ccae254a29	150	#endif
mega64	0:38ccae254a29	151	#else
mega64	0:38ccae254a29	152	#define __FPU_USED 0
mega64	0:38ccae254a29	153	#endif
mega64	0:38ccae254a29	154
mega64	0:38ccae254a29	155	#elif defined ( __TASKING__ )
mega64	0:38ccae254a29	156	#if defined __FPU_VFP__
mega64	0:38ccae254a29	157	#if (__FPU_PRESENT == 1)
mega64	0:38ccae254a29	158	#define __FPU_USED 1
mega64	0:38ccae254a29	159	#else
mega64	0:38ccae254a29	160	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64	0:38ccae254a29	161	#define __FPU_USED 0
mega64	0:38ccae254a29	162	#endif
mega64	0:38ccae254a29	163	#else
mega64	0:38ccae254a29	164	#define __FPU_USED 0
mega64	0:38ccae254a29	165	#endif
mega64	0:38ccae254a29	166	#endif
mega64	0:38ccae254a29	167
mega64	0:38ccae254a29	168	#include <stdint.h> /* standard types definitions */
mega64	0:38ccae254a29	169	#include <core_cmInstr.h> /* Core Instruction Access */
mega64	0:38ccae254a29	170	#include <core_cmFunc.h> /* Core Function Access */
mega64	0:38ccae254a29	171	#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
mega64	0:38ccae254a29	172
mega64	0:38ccae254a29	173	#endif /* __CORE_CM4_H_GENERIC */
mega64	0:38ccae254a29	174
mega64	0:38ccae254a29	175	#ifndef __CMSIS_GENERIC
mega64	0:38ccae254a29	176
mega64	0:38ccae254a29	177	#ifndef __CORE_CM4_H_DEPENDANT
mega64	0:38ccae254a29	178	#define __CORE_CM4_H_DEPENDANT
mega64	0:38ccae254a29	179
mega64	0:38ccae254a29	180	/* check device defines and use defaults */
mega64	0:38ccae254a29	181	#if defined __CHECK_DEVICE_DEFINES
mega64	0:38ccae254a29	182	#ifndef __CM4_REV
mega64	0:38ccae254a29	183	#define __CM4_REV 0x0000
mega64	0:38ccae254a29	184	#warning "__CM4_REV not defined in device header file; using default!"
mega64	0:38ccae254a29	185	#endif
mega64	0:38ccae254a29	186
mega64	0:38ccae254a29	187	#ifndef __FPU_PRESENT
mega64	0:38ccae254a29	188	#define __FPU_PRESENT 0
mega64	0:38ccae254a29	189	#warning "__FPU_PRESENT not defined in device header file; using default!"
mega64	0:38ccae254a29	190	#endif
mega64	0:38ccae254a29	191
mega64	0:38ccae254a29	192	#ifndef __MPU_PRESENT
mega64	0:38ccae254a29	193	#define __MPU_PRESENT 0
mega64	0:38ccae254a29	194	#warning "__MPU_PRESENT not defined in device header file; using default!"
mega64	0:38ccae254a29	195	#endif
mega64	0:38ccae254a29	196
mega64	0:38ccae254a29	197	#ifndef __NVIC_PRIO_BITS
mega64	0:38ccae254a29	198	#define __NVIC_PRIO_BITS 4
mega64	0:38ccae254a29	199	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mega64	0:38ccae254a29	200	#endif
mega64	0:38ccae254a29	201
mega64	0:38ccae254a29	202	#ifndef __Vendor_SysTickConfig
mega64	0:38ccae254a29	203	#define __Vendor_SysTickConfig 0
mega64	0:38ccae254a29	204	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mega64	0:38ccae254a29	205	#endif
mega64	0:38ccae254a29	206	#endif
mega64	0:38ccae254a29	207
mega64	0:38ccae254a29	208	/* IO definitions (access restrictions to peripheral registers) */
mega64	0:38ccae254a29	209	/**
mega64	0:38ccae254a29	210	\defgroup CMSIS_glob_defs CMSIS Global Defines
mega64	0:38ccae254a29	211
mega64	0:38ccae254a29	212	<strong>IO Type Qualifiers</strong> are used
mega64	0:38ccae254a29	213	\li to specify the access to peripheral variables.
mega64	0:38ccae254a29	214	\li for automatic generation of peripheral register debug information.
mega64	0:38ccae254a29	215	*/
mega64	0:38ccae254a29	216	#ifdef __cplusplus
mega64	0:38ccae254a29	217	#define __I volatile /!< Defines 'read only' permissions /
mega64	0:38ccae254a29	218	#else
mega64	0:38ccae254a29	219	#define __I volatile const /!< Defines 'read only' permissions /
mega64	0:38ccae254a29	220	#endif
mega64	0:38ccae254a29	221	#define __O volatile /!< Defines 'write only' permissions /
mega64	0:38ccae254a29	222	#define __IO volatile /!< Defines 'read / write' permissions /
mega64	0:38ccae254a29	223
mega64	0:38ccae254a29	224	/@} end of group Cortex_M4 /
mega64	0:38ccae254a29	225
mega64	0:38ccae254a29	226
mega64	0:38ccae254a29	227
mega64	0:38ccae254a29	228	/*******************************************************************************
mega64	0:38ccae254a29	229	* Register Abstraction
mega64	0:38ccae254a29	230	Core Register contain:
mega64	0:38ccae254a29	231	- Core Register
mega64	0:38ccae254a29	232	- Core NVIC Register
mega64	0:38ccae254a29	233	- Core SCB Register
mega64	0:38ccae254a29	234	- Core SysTick Register
mega64	0:38ccae254a29	235	- Core Debug Register
mega64	0:38ccae254a29	236	- Core MPU Register
mega64	0:38ccae254a29	237	- Core FPU Register
mega64	0:38ccae254a29	238	******************************************************************************/
mega64	0:38ccae254a29	239	/** \defgroup CMSIS_core_register Defines and Type Definitions
mega64	0:38ccae254a29	240	\brief Type definitions and defines for Cortex-M processor based devices.
mega64	0:38ccae254a29	241	*/
mega64	0:38ccae254a29	242
mega64	0:38ccae254a29	243	/** \ingroup CMSIS_core_register
mega64	0:38ccae254a29	244	\defgroup CMSIS_CORE Status and Control Registers
mega64	0:38ccae254a29	245	\brief Core Register type definitions.
mega64	0:38ccae254a29	246	@{
mega64	0:38ccae254a29	247	*/
mega64	0:38ccae254a29	248
mega64	0:38ccae254a29	249	/** \brief Union type to access the Application Program Status Register (APSR).
mega64	0:38ccae254a29	250	*/
mega64	0:38ccae254a29	251	typedef union
mega64	0:38ccae254a29	252	{
mega64	0:38ccae254a29	253	struct
mega64	0:38ccae254a29	254	{
mega64	0:38ccae254a29	255	#if (__CORTEX_M != 0x04)
mega64	0:38ccae254a29	256	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
mega64	0:38ccae254a29	257	#else
mega64	0:38ccae254a29	258	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
mega64	0:38ccae254a29	259	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
mega64	0:38ccae254a29	260	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
mega64	0:38ccae254a29	261	#endif
mega64	0:38ccae254a29	262	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
mega64	0:38ccae254a29	263	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
mega64	0:38ccae254a29	264	uint32_t C:1; /!< bit: 29 Carry condition code flag /
mega64	0:38ccae254a29	265	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
mega64	0:38ccae254a29	266	uint32_t N:1; /!< bit: 31 Negative condition code flag /
mega64	0:38ccae254a29	267	} b; /!< Structure used for bit access /
mega64	0:38ccae254a29	268	uint32_t w; /!< Type used for word access /
mega64	0:38ccae254a29	269	} APSR_Type;
mega64	0:38ccae254a29	270
mega64	0:38ccae254a29	271
mega64	0:38ccae254a29	272	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
mega64	0:38ccae254a29	273	*/
mega64	0:38ccae254a29	274	typedef union
mega64	0:38ccae254a29	275	{
mega64	0:38ccae254a29	276	struct
mega64	0:38ccae254a29	277	{
mega64	0:38ccae254a29	278	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
mega64	0:38ccae254a29	279	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
mega64	0:38ccae254a29	280	} b; /!< Structure used for bit access /
mega64	0:38ccae254a29	281	uint32_t w; /!< Type used for word access /
mega64	0:38ccae254a29	282	} IPSR_Type;
mega64	0:38ccae254a29	283
mega64	0:38ccae254a29	284
mega64	0:38ccae254a29	285	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mega64	0:38ccae254a29	286	*/
mega64	0:38ccae254a29	287	typedef union
mega64	0:38ccae254a29	288	{
mega64	0:38ccae254a29	289	struct
mega64	0:38ccae254a29	290	{
mega64	0:38ccae254a29	291	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
mega64	0:38ccae254a29	292	#if (__CORTEX_M != 0x04)
mega64	0:38ccae254a29	293	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
mega64	0:38ccae254a29	294	#else
mega64	0:38ccae254a29	295	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
mega64	0:38ccae254a29	296	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
mega64	0:38ccae254a29	297	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
mega64	0:38ccae254a29	298	#endif
mega64	0:38ccae254a29	299	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
mega64	0:38ccae254a29	300	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
mega64	0:38ccae254a29	301	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
mega64	0:38ccae254a29	302	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
mega64	0:38ccae254a29	303	uint32_t C:1; /!< bit: 29 Carry condition code flag /
mega64	0:38ccae254a29	304	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
mega64	0:38ccae254a29	305	uint32_t N:1; /!< bit: 31 Negative condition code flag /
mega64	0:38ccae254a29	306	} b; /!< Structure used for bit access /
mega64	0:38ccae254a29	307	uint32_t w; /!< Type used for word access /
mega64	0:38ccae254a29	308	} xPSR_Type;
mega64	0:38ccae254a29	309
mega64	0:38ccae254a29	310
mega64	0:38ccae254a29	311	/** \brief Union type to access the Control Registers (CONTROL).
mega64	0:38ccae254a29	312	*/
mega64	0:38ccae254a29	313	typedef union
mega64	0:38ccae254a29	314	{
mega64	0:38ccae254a29	315	struct
mega64	0:38ccae254a29	316	{
mega64	0:38ccae254a29	317	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
mega64	0:38ccae254a29	318	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
mega64	0:38ccae254a29	319	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
mega64	0:38ccae254a29	320	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
mega64	0:38ccae254a29	321	} b; /!< Structure used for bit access /
mega64	0:38ccae254a29	322	uint32_t w; /!< Type used for word access /
mega64	0:38ccae254a29	323	} CONTROL_Type;
mega64	0:38ccae254a29	324
mega64	0:38ccae254a29	325	/@} end of group CMSIS_CORE /
mega64	0:38ccae254a29	326
mega64	0:38ccae254a29	327
mega64	0:38ccae254a29	328	/** \ingroup CMSIS_core_register
mega64	0:38ccae254a29	329	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mega64	0:38ccae254a29	330	\brief Type definitions for the NVIC Registers
mega64	0:38ccae254a29	331	@{
mega64	0:38ccae254a29	332	*/
mega64	0:38ccae254a29	333
mega64	0:38ccae254a29	334	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mega64	0:38ccae254a29	335	*/
mega64	0:38ccae254a29	336	typedef struct
mega64	0:38ccae254a29	337	{
mega64	0:38ccae254a29	338	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
mega64	0:38ccae254a29	339	uint32_t RESERVED0[24];
mega64	0:38ccae254a29	340	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
mega64	0:38ccae254a29	341	uint32_t RSERVED1[24];
mega64	0:38ccae254a29	342	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
mega64	0:38ccae254a29	343	uint32_t RESERVED2[24];
mega64	0:38ccae254a29	344	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
mega64	0:38ccae254a29	345	uint32_t RESERVED3[24];
mega64	0:38ccae254a29	346	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
mega64	0:38ccae254a29	347	uint32_t RESERVED4[56];
mega64	0:38ccae254a29	348	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
mega64	0:38ccae254a29	349	uint32_t RESERVED5[644];
mega64	0:38ccae254a29	350	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
mega64	0:38ccae254a29	351	} NVIC_Type;
mega64	0:38ccae254a29	352
mega64	0:38ccae254a29	353	/* Software Triggered Interrupt Register Definitions */
mega64	0:38ccae254a29	354	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
mega64	0:38ccae254a29	355	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
mega64	0:38ccae254a29	356
mega64	0:38ccae254a29	357	/@} end of group CMSIS_NVIC /
mega64	0:38ccae254a29	358
mega64	0:38ccae254a29	359
mega64	0:38ccae254a29	360	/** \ingroup CMSIS_core_register
mega64	0:38ccae254a29	361	\defgroup CMSIS_SCB System Control Block (SCB)
mega64	0:38ccae254a29	362	\brief Type definitions for the System Control Block Registers
mega64	0:38ccae254a29	363	@{
mega64	0:38ccae254a29	364	*/
mega64	0:38ccae254a29	365
mega64	0:38ccae254a29	366	/** \brief Structure type to access the System Control Block (SCB).
mega64	0:38ccae254a29	367	*/
mega64	0:38ccae254a29	368	typedef struct
mega64	0:38ccae254a29	369	{
mega64	0:38ccae254a29	370	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
mega64	0:38ccae254a29	371	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
mega64	0:38ccae254a29	372	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
mega64	0:38ccae254a29	373	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
mega64	0:38ccae254a29	374	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
mega64	0:38ccae254a29	375	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
mega64	0:38ccae254a29	376	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
mega64	0:38ccae254a29	377	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
mega64	0:38ccae254a29	378	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
mega64	0:38ccae254a29	379	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
mega64	0:38ccae254a29	380	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
mega64	0:38ccae254a29	381	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
mega64	0:38ccae254a29	382	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
mega64	0:38ccae254a29	383	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
mega64	0:38ccae254a29	384	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
mega64	0:38ccae254a29	385	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
mega64	0:38ccae254a29	386	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
mega64	0:38ccae254a29	387	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
mega64	0:38ccae254a29	388	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
mega64	0:38ccae254a29	389	uint32_t RESERVED0[5];
mega64	0:38ccae254a29	390	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
mega64	0:38ccae254a29	391	} SCB_Type;
mega64	0:38ccae254a29	392
mega64	0:38ccae254a29	393	/* SCB CPUID Register Definitions */
mega64	0:38ccae254a29	394	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
mega64	0:38ccae254a29	395	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
mega64	0:38ccae254a29	396
mega64	0:38ccae254a29	397	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
mega64	0:38ccae254a29	398	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
mega64	0:38ccae254a29	399
mega64	0:38ccae254a29	400	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
mega64	0:38ccae254a29	401	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
mega64	0:38ccae254a29	402
mega64	0:38ccae254a29	403	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
mega64	0:38ccae254a29	404	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
mega64	0:38ccae254a29	405
mega64	0:38ccae254a29	406	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
mega64	0:38ccae254a29	407	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
mega64	0:38ccae254a29	408
mega64	0:38ccae254a29	409	/* SCB Interrupt Control State Register Definitions */
mega64	0:38ccae254a29	410	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
mega64	0:38ccae254a29	411	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
mega64	0:38ccae254a29	412
mega64	0:38ccae254a29	413	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
mega64	0:38ccae254a29	414	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
mega64	0:38ccae254a29	415
mega64	0:38ccae254a29	416	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
mega64	0:38ccae254a29	417	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
mega64	0:38ccae254a29	418
mega64	0:38ccae254a29	419	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
mega64	0:38ccae254a29	420	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
mega64	0:38ccae254a29	421
mega64	0:38ccae254a29	422	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
mega64	0:38ccae254a29	423	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
mega64	0:38ccae254a29	424
mega64	0:38ccae254a29	425	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
mega64	0:38ccae254a29	426	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
mega64	0:38ccae254a29	427
mega64	0:38ccae254a29	428	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
mega64	0:38ccae254a29	429	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
mega64	0:38ccae254a29	430
mega64	0:38ccae254a29	431	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
mega64	0:38ccae254a29	432	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
mega64	0:38ccae254a29	433
mega64	0:38ccae254a29	434	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
mega64	0:38ccae254a29	435	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
mega64	0:38ccae254a29	436
mega64	0:38ccae254a29	437	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
mega64	0:38ccae254a29	438	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
mega64	0:38ccae254a29	439
mega64	0:38ccae254a29	440	/* SCB Vector Table Offset Register Definitions */
mega64	0:38ccae254a29	441	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
mega64	0:38ccae254a29	442	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
mega64	0:38ccae254a29	443
mega64	0:38ccae254a29	444	/* SCB Application Interrupt and Reset Control Register Definitions */
mega64	0:38ccae254a29	445	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
mega64	0:38ccae254a29	446	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
mega64	0:38ccae254a29	447
mega64	0:38ccae254a29	448	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
mega64	0:38ccae254a29	449	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
mega64	0:38ccae254a29	450
mega64	0:38ccae254a29	451	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
mega64	0:38ccae254a29	452	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
mega64	0:38ccae254a29	453
mega64	0:38ccae254a29	454	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
mega64	0:38ccae254a29	455	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
mega64	0:38ccae254a29	456
mega64	0:38ccae254a29	457	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
mega64	0:38ccae254a29	458	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
mega64	0:38ccae254a29	459
mega64	0:38ccae254a29	460	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
mega64	0:38ccae254a29	461	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
mega64	0:38ccae254a29	462
mega64	0:38ccae254a29	463	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
mega64	0:38ccae254a29	464	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
mega64	0:38ccae254a29	465
mega64	0:38ccae254a29	466	/* SCB System Control Register Definitions */
mega64	0:38ccae254a29	467	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
mega64	0:38ccae254a29	468	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
mega64	0:38ccae254a29	469
mega64	0:38ccae254a29	470	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
mega64	0:38ccae254a29	471	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
mega64	0:38ccae254a29	472
mega64	0:38ccae254a29	473	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
mega64	0:38ccae254a29	474	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
mega64	0:38ccae254a29	475
mega64	0:38ccae254a29	476	/* SCB Configuration Control Register Definitions */
mega64	0:38ccae254a29	477	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
mega64	0:38ccae254a29	478	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
mega64	0:38ccae254a29	479
mega64	0:38ccae254a29	480	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
mega64	0:38ccae254a29	481	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
mega64	0:38ccae254a29	482
mega64	0:38ccae254a29	483	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
mega64	0:38ccae254a29	484	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
mega64	0:38ccae254a29	485
mega64	0:38ccae254a29	486	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
mega64	0:38ccae254a29	487	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
mega64	0:38ccae254a29	488
mega64	0:38ccae254a29	489	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
mega64	0:38ccae254a29	490	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
mega64	0:38ccae254a29	491
mega64	0:38ccae254a29	492	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
mega64	0:38ccae254a29	493	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
mega64	0:38ccae254a29	494
mega64	0:38ccae254a29	495	/* SCB System Handler Control and State Register Definitions */
mega64	0:38ccae254a29	496	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
mega64	0:38ccae254a29	497	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
mega64	0:38ccae254a29	498
mega64	0:38ccae254a29	499	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
mega64	0:38ccae254a29	500	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
mega64	0:38ccae254a29	501
mega64	0:38ccae254a29	502	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
mega64	0:38ccae254a29	503	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
mega64	0:38ccae254a29	504
mega64	0:38ccae254a29	505	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
mega64	0:38ccae254a29	506	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
mega64	0:38ccae254a29	507
mega64	0:38ccae254a29	508	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
mega64	0:38ccae254a29	509	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
mega64	0:38ccae254a29	510
mega64	0:38ccae254a29	511	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
mega64	0:38ccae254a29	512	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
mega64	0:38ccae254a29	513
mega64	0:38ccae254a29	514	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
mega64	0:38ccae254a29	515	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
mega64	0:38ccae254a29	516
mega64	0:38ccae254a29	517	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
mega64	0:38ccae254a29	518	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
mega64	0:38ccae254a29	519
mega64	0:38ccae254a29	520	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
mega64	0:38ccae254a29	521	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
mega64	0:38ccae254a29	522
mega64	0:38ccae254a29	523	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
mega64	0:38ccae254a29	524	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
mega64	0:38ccae254a29	525
mega64	0:38ccae254a29	526	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
mega64	0:38ccae254a29	527	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
mega64	0:38ccae254a29	528
mega64	0:38ccae254a29	529	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
mega64	0:38ccae254a29	530	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
mega64	0:38ccae254a29	531
mega64	0:38ccae254a29	532	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
mega64	0:38ccae254a29	533	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
mega64	0:38ccae254a29	534
mega64	0:38ccae254a29	535	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
mega64	0:38ccae254a29	536	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
mega64	0:38ccae254a29	537
mega64	0:38ccae254a29	538	/* SCB Configurable Fault Status Registers Definitions */
mega64	0:38ccae254a29	539	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
mega64	0:38ccae254a29	540	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
mega64	0:38ccae254a29	541
mega64	0:38ccae254a29	542	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
mega64	0:38ccae254a29	543	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
mega64	0:38ccae254a29	544
mega64	0:38ccae254a29	545	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
mega64	0:38ccae254a29	546	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
mega64	0:38ccae254a29	547
mega64	0:38ccae254a29	548	/* SCB Hard Fault Status Registers Definitions */
mega64	0:38ccae254a29	549	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
mega64	0:38ccae254a29	550	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
mega64	0:38ccae254a29	551
mega64	0:38ccae254a29	552	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
mega64	0:38ccae254a29	553	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
mega64	0:38ccae254a29	554
mega64	0:38ccae254a29	555	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
mega64	0:38ccae254a29	556	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
mega64	0:38ccae254a29	557
mega64	0:38ccae254a29	558	/* SCB Debug Fault Status Register Definitions */
mega64	0:38ccae254a29	559	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
mega64	0:38ccae254a29	560	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
mega64	0:38ccae254a29	561
mega64	0:38ccae254a29	562	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
mega64	0:38ccae254a29	563	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
mega64	0:38ccae254a29	564
mega64	0:38ccae254a29	565	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
mega64	0:38ccae254a29	566	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
mega64	0:38ccae254a29	567
mega64	0:38ccae254a29	568	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
mega64	0:38ccae254a29	569	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
mega64	0:38ccae254a29	570
mega64	0:38ccae254a29	571	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
mega64	0:38ccae254a29	572	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
mega64	0:38ccae254a29	573
mega64	0:38ccae254a29	574	/@} end of group CMSIS_SCB /
mega64	0:38ccae254a29	575
mega64	0:38ccae254a29	576
mega64	0:38ccae254a29	577	/** \ingroup CMSIS_core_register
mega64	0:38ccae254a29	578	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
mega64	0:38ccae254a29	579	\brief Type definitions for the System Control and ID Register not in the SCB
mega64	0:38ccae254a29	580	@{
mega64	0:38ccae254a29	581	*/
mega64	0:38ccae254a29	582
mega64	0:38ccae254a29	583	/** \brief Structure type to access the System Control and ID Register not in the SCB.
mega64	0:38ccae254a29	584	*/
mega64	0:38ccae254a29	585	typedef struct
mega64	0:38ccae254a29	586	{
mega64	0:38ccae254a29	587	uint32_t RESERVED0[1];
mega64	0:38ccae254a29	588	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
mega64	0:38ccae254a29	589	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
mega64	0:38ccae254a29	590	} SCnSCB_Type;
mega64	0:38ccae254a29	591
mega64	0:38ccae254a29	592	/* Interrupt Controller Type Register Definitions */
mega64	0:38ccae254a29	593	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
mega64	0:38ccae254a29	594	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
mega64	0:38ccae254a29	595
mega64	0:38ccae254a29	596	/* Auxiliary Control Register Definitions */
mega64	0:38ccae254a29	597	#define SCnSCB_ACTLR_DISOOFP_Pos 9 /!< ACTLR: DISOOFP Position /
mega64	0:38ccae254a29	598	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
mega64	0:38ccae254a29	599
mega64	0:38ccae254a29	600	#define SCnSCB_ACTLR_DISFPCA_Pos 8 /!< ACTLR: DISFPCA Position /
mega64	0:38ccae254a29	601	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
mega64	0:38ccae254a29	602
mega64	0:38ccae254a29	603	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
mega64	0:38ccae254a29	604	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
mega64	0:38ccae254a29	605
mega64	0:38ccae254a29	606	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
mega64	0:38ccae254a29	607	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
mega64	0:38ccae254a29	608
mega64	0:38ccae254a29	609	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
mega64	0:38ccae254a29	610	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
mega64	0:38ccae254a29	611
mega64	0:38ccae254a29	612	/@} end of group CMSIS_SCnotSCB /
mega64	0:38ccae254a29	613
mega64	0:38ccae254a29	614
mega64	0:38ccae254a29	615	/** \ingroup CMSIS_core_register
mega64	0:38ccae254a29	616	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
mega64	0:38ccae254a29	617	\brief Type definitions for the System Timer Registers.
mega64	0:38ccae254a29	618	@{
mega64	0:38ccae254a29	619	*/
mega64	0:38ccae254a29	620
mega64	0:38ccae254a29	621	/** \brief Structure type to access the System Timer (SysTick).
mega64	0:38ccae254a29	622	*/
mega64	0:38ccae254a29	623	typedef struct
mega64	0:38ccae254a29	624	{
mega64	0:38ccae254a29	625	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
mega64	0:38ccae254a29	626	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
mega64	0:38ccae254a29	627	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
mega64	0:38ccae254a29	628	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
mega64	0:38ccae254a29	629	} SysTick_Type;
mega64	0:38ccae254a29	630
mega64	0:38ccae254a29	631	/* SysTick Control / Status Register Definitions */
mega64	0:38ccae254a29	632	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
mega64	0:38ccae254a29	633	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
mega64	0:38ccae254a29	634
mega64	0:38ccae254a29	635	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
mega64	0:38ccae254a29	636	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
mega64	0:38ccae254a29	637
mega64	0:38ccae254a29	638	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
mega64	0:38ccae254a29	639	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
mega64	0:38ccae254a29	640
mega64	0:38ccae254a29	641	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
mega64	0:38ccae254a29	642	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
mega64	0:38ccae254a29	643
mega64	0:38ccae254a29	644	/* SysTick Reload Register Definitions */
mega64	0:38ccae254a29	645	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
mega64	0:38ccae254a29	646	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
mega64	0:38ccae254a29	647
mega64	0:38ccae254a29	648	/* SysTick Current Register Definitions */
mega64	0:38ccae254a29	649	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
mega64	0:38ccae254a29	650	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
mega64	0:38ccae254a29	651
mega64	0:38ccae254a29	652	/* SysTick Calibration Register Definitions */
mega64	0:38ccae254a29	653	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
mega64	0:38ccae254a29	654	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
mega64	0:38ccae254a29	655
mega64	0:38ccae254a29	656	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
mega64	0:38ccae254a29	657	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
mega64	0:38ccae254a29	658
mega64	0:38ccae254a29	659	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
mega64	0:38ccae254a29	660	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
mega64	0:38ccae254a29	661
mega64	0:38ccae254a29	662	/@} end of group CMSIS_SysTick /
mega64	0:38ccae254a29	663
mega64	0:38ccae254a29	664
mega64	0:38ccae254a29	665	/** \ingroup CMSIS_core_register
mega64	0:38ccae254a29	666	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
mega64	0:38ccae254a29	667	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
mega64	0:38ccae254a29	668	@{
mega64	0:38ccae254a29	669	*/
mega64	0:38ccae254a29	670
mega64	0:38ccae254a29	671	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
mega64	0:38ccae254a29	672	*/
mega64	0:38ccae254a29	673	typedef struct
mega64	0:38ccae254a29	674	{
mega64	0:38ccae254a29	675	__O union
mega64	0:38ccae254a29	676	{
mega64	0:38ccae254a29	677	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
mega64	0:38ccae254a29	678	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
mega64	0:38ccae254a29	679	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
mega64	0:38ccae254a29	680	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
mega64	0:38ccae254a29	681	uint32_t RESERVED0[864];
mega64	0:38ccae254a29	682	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
mega64	0:38ccae254a29	683	uint32_t RESERVED1[15];
mega64	0:38ccae254a29	684	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
mega64	0:38ccae254a29	685	uint32_t RESERVED2[15];
mega64	0:38ccae254a29	686	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
mega64	0:38ccae254a29	687	uint32_t RESERVED3[29];
mega64	0:38ccae254a29	688	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
mega64	0:38ccae254a29	689	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
mega64	0:38ccae254a29	690	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
mega64	0:38ccae254a29	691	uint32_t RESERVED4[43];
mega64	0:38ccae254a29	692	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
mega64	0:38ccae254a29	693	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
mega64	0:38ccae254a29	694	uint32_t RESERVED5[6];
mega64	0:38ccae254a29	695	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
mega64	0:38ccae254a29	696	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
mega64	0:38ccae254a29	697	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
mega64	0:38ccae254a29	698	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
mega64	0:38ccae254a29	699	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
mega64	0:38ccae254a29	700	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
mega64	0:38ccae254a29	701	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
mega64	0:38ccae254a29	702	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
mega64	0:38ccae254a29	703	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
mega64	0:38ccae254a29	704	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
mega64	0:38ccae254a29	705	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
mega64	0:38ccae254a29	706	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
mega64	0:38ccae254a29	707	} ITM_Type;
mega64	0:38ccae254a29	708
mega64	0:38ccae254a29	709	/* ITM Trace Privilege Register Definitions */
mega64	0:38ccae254a29	710	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
mega64	0:38ccae254a29	711	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
mega64	0:38ccae254a29	712
mega64	0:38ccae254a29	713	/* ITM Trace Control Register Definitions */
mega64	0:38ccae254a29	714	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
mega64	0:38ccae254a29	715	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
mega64	0:38ccae254a29	716
mega64	0:38ccae254a29	717	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
mega64	0:38ccae254a29	718	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
mega64	0:38ccae254a29	719
mega64	0:38ccae254a29	720	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
mega64	0:38ccae254a29	721	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
mega64	0:38ccae254a29	722
mega64	0:38ccae254a29	723	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
mega64	0:38ccae254a29	724	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
mega64	0:38ccae254a29	725
mega64	0:38ccae254a29	726	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
mega64	0:38ccae254a29	727	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
mega64	0:38ccae254a29	728
mega64	0:38ccae254a29	729	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
mega64	0:38ccae254a29	730	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
mega64	0:38ccae254a29	731
mega64	0:38ccae254a29	732	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
mega64	0:38ccae254a29	733	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
mega64	0:38ccae254a29	734
mega64	0:38ccae254a29	735	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
mega64	0:38ccae254a29	736	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
mega64	0:38ccae254a29	737
mega64	0:38ccae254a29	738	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
mega64	0:38ccae254a29	739	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
mega64	0:38ccae254a29	740
mega64	0:38ccae254a29	741	/* ITM Integration Write Register Definitions */
mega64	0:38ccae254a29	742	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
mega64	0:38ccae254a29	743	#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
mega64	0:38ccae254a29	744
mega64	0:38ccae254a29	745	/* ITM Integration Read Register Definitions */
mega64	0:38ccae254a29	746	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
mega64	0:38ccae254a29	747	#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
mega64	0:38ccae254a29	748
mega64	0:38ccae254a29	749	/* ITM Integration Mode Control Register Definitions */
mega64	0:38ccae254a29	750	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
mega64	0:38ccae254a29	751	#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
mega64	0:38ccae254a29	752
mega64	0:38ccae254a29	753	/* ITM Lock Status Register Definitions */
mega64	0:38ccae254a29	754	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
mega64	0:38ccae254a29	755	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
mega64	0:38ccae254a29	756
mega64	0:38ccae254a29	757	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
mega64	0:38ccae254a29	758	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
mega64	0:38ccae254a29	759
mega64	0:38ccae254a29	760	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
mega64	0:38ccae254a29	761	#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
mega64	0:38ccae254a29	762
mega64	0:38ccae254a29	763	/@}/ /* end of group CMSIS_ITM */
mega64	0:38ccae254a29	764
mega64	0:38ccae254a29	765
mega64	0:38ccae254a29	766	/** \ingroup CMSIS_core_register
mega64	0:38ccae254a29	767	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
mega64	0:38ccae254a29	768	\brief Type definitions for the Data Watchpoint and Trace (DWT)
mega64	0:38ccae254a29	769	@{
mega64	0:38ccae254a29	770	*/
mega64	0:38ccae254a29	771
mega64	0:38ccae254a29	772	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
mega64	0:38ccae254a29	773	*/
mega64	0:38ccae254a29	774	typedef struct
mega64	0:38ccae254a29	775	{
mega64	0:38ccae254a29	776	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
mega64	0:38ccae254a29	777	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
mega64	0:38ccae254a29	778	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
mega64	0:38ccae254a29	779	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
mega64	0:38ccae254a29	780	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
mega64	0:38ccae254a29	781	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
mega64	0:38ccae254a29	782	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
mega64	0:38ccae254a29	783	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
mega64	0:38ccae254a29	784	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
mega64	0:38ccae254a29	785	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
mega64	0:38ccae254a29	786	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
mega64	0:38ccae254a29	787	uint32_t RESERVED0[1];
mega64	0:38ccae254a29	788	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
mega64	0:38ccae254a29	789	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
mega64	0:38ccae254a29	790	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
mega64	0:38ccae254a29	791	uint32_t RESERVED1[1];
mega64	0:38ccae254a29	792	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
mega64	0:38ccae254a29	793	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
mega64	0:38ccae254a29	794	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
mega64	0:38ccae254a29	795	uint32_t RESERVED2[1];
mega64	0:38ccae254a29	796	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
mega64	0:38ccae254a29	797	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
mega64	0:38ccae254a29	798	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
mega64	0:38ccae254a29	799	} DWT_Type;
mega64	0:38ccae254a29	800
mega64	0:38ccae254a29	801	/* DWT Control Register Definitions */
mega64	0:38ccae254a29	802	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
mega64	0:38ccae254a29	803	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
mega64	0:38ccae254a29	804
mega64	0:38ccae254a29	805	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
mega64	0:38ccae254a29	806	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
mega64	0:38ccae254a29	807
mega64	0:38ccae254a29	808	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
mega64	0:38ccae254a29	809	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
mega64	0:38ccae254a29	810
mega64	0:38ccae254a29	811	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
mega64	0:38ccae254a29	812	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
mega64	0:38ccae254a29	813
mega64	0:38ccae254a29	814	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
mega64	0:38ccae254a29	815	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
mega64	0:38ccae254a29	816
mega64	0:38ccae254a29	817	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
mega64	0:38ccae254a29	818	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
mega64	0:38ccae254a29	819
mega64	0:38ccae254a29	820	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
mega64	0:38ccae254a29	821	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
mega64	0:38ccae254a29	822
mega64	0:38ccae254a29	823	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
mega64	0:38ccae254a29	824	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
mega64	0:38ccae254a29	825
mega64	0:38ccae254a29	826	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
mega64	0:38ccae254a29	827	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
mega64	0:38ccae254a29	828
mega64	0:38ccae254a29	829	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
mega64	0:38ccae254a29	830	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
mega64	0:38ccae254a29	831
mega64	0:38ccae254a29	832	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
mega64	0:38ccae254a29	833	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
mega64	0:38ccae254a29	834
mega64	0:38ccae254a29	835	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
mega64	0:38ccae254a29	836	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
mega64	0:38ccae254a29	837
mega64	0:38ccae254a29	838	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
mega64	0:38ccae254a29	839	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
mega64	0:38ccae254a29	840
mega64	0:38ccae254a29	841	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
mega64	0:38ccae254a29	842	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
mega64	0:38ccae254a29	843
mega64	0:38ccae254a29	844	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
mega64	0:38ccae254a29	845	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
mega64	0:38ccae254a29	846
mega64	0:38ccae254a29	847	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
mega64	0:38ccae254a29	848	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
mega64	0:38ccae254a29	849
mega64	0:38ccae254a29	850	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
mega64	0:38ccae254a29	851	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
mega64	0:38ccae254a29	852
mega64	0:38ccae254a29	853	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
mega64	0:38ccae254a29	854	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /!< DWT CTRL: CYCCNTENA Mask /
mega64	0:38ccae254a29	855
mega64	0:38ccae254a29	856	/* DWT CPI Count Register Definitions */
mega64	0:38ccae254a29	857	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
mega64	0:38ccae254a29	858	#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /!< DWT CPICNT: CPICNT Mask /
mega64	0:38ccae254a29	859
mega64	0:38ccae254a29	860	/* DWT Exception Overhead Count Register Definitions */
mega64	0:38ccae254a29	861	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
mega64	0:38ccae254a29	862	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /!< DWT EXCCNT: EXCCNT Mask /
mega64	0:38ccae254a29	863
mega64	0:38ccae254a29	864	/* DWT Sleep Count Register Definitions */
mega64	0:38ccae254a29	865	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
mega64	0:38ccae254a29	866	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /!< DWT SLEEPCNT: SLEEPCNT Mask /
mega64	0:38ccae254a29	867
mega64	0:38ccae254a29	868	/* DWT LSU Count Register Definitions */
mega64	0:38ccae254a29	869	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
mega64	0:38ccae254a29	870	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /!< DWT LSUCNT: LSUCNT Mask /
mega64	0:38ccae254a29	871
mega64	0:38ccae254a29	872	/* DWT Folded-instruction Count Register Definitions */
mega64	0:38ccae254a29	873	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
mega64	0:38ccae254a29	874	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /!< DWT FOLDCNT: FOLDCNT Mask /
mega64	0:38ccae254a29	875
mega64	0:38ccae254a29	876	/* DWT Comparator Mask Register Definitions */
mega64	0:38ccae254a29	877	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
mega64	0:38ccae254a29	878	#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /!< DWT MASK: MASK Mask /
mega64	0:38ccae254a29	879
mega64	0:38ccae254a29	880	/* DWT Comparator Function Register Definitions */
mega64	0:38ccae254a29	881	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
mega64	0:38ccae254a29	882	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
mega64	0:38ccae254a29	883
mega64	0:38ccae254a29	884	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
mega64	0:38ccae254a29	885	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
mega64	0:38ccae254a29	886
mega64	0:38ccae254a29	887	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
mega64	0:38ccae254a29	888	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
mega64	0:38ccae254a29	889
mega64	0:38ccae254a29	890	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
mega64	0:38ccae254a29	891	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
mega64	0:38ccae254a29	892
mega64	0:38ccae254a29	893	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
mega64	0:38ccae254a29	894	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
mega64	0:38ccae254a29	895
mega64	0:38ccae254a29	896	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
mega64	0:38ccae254a29	897	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
mega64	0:38ccae254a29	898
mega64	0:38ccae254a29	899	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
mega64	0:38ccae254a29	900	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
mega64	0:38ccae254a29	901
mega64	0:38ccae254a29	902	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
mega64	0:38ccae254a29	903	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
mega64	0:38ccae254a29	904
mega64	0:38ccae254a29	905	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
mega64	0:38ccae254a29	906	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /!< DWT FUNCTION: FUNCTION Mask /
mega64	0:38ccae254a29	907
mega64	0:38ccae254a29	908	/@}/ /* end of group CMSIS_DWT */
mega64	0:38ccae254a29	909
mega64	0:38ccae254a29	910
mega64	0:38ccae254a29	911	/** \ingroup CMSIS_core_register
mega64	0:38ccae254a29	912	\defgroup CMSIS_TPI Trace Port Interface (TPI)
mega64	0:38ccae254a29	913	\brief Type definitions for the Trace Port Interface (TPI)
mega64	0:38ccae254a29	914	@{
mega64	0:38ccae254a29	915	*/
mega64	0:38ccae254a29	916
mega64	0:38ccae254a29	917	/** \brief Structure type to access the Trace Port Interface Register (TPI).
mega64	0:38ccae254a29	918	*/
mega64	0:38ccae254a29	919	typedef struct
mega64	0:38ccae254a29	920	{
mega64	0:38ccae254a29	921	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
mega64	0:38ccae254a29	922	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
mega64	0:38ccae254a29	923	uint32_t RESERVED0[2];
mega64	0:38ccae254a29	924	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
mega64	0:38ccae254a29	925	uint32_t RESERVED1[55];
mega64	0:38ccae254a29	926	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
mega64	0:38ccae254a29	927	uint32_t RESERVED2[131];
mega64	0:38ccae254a29	928	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
mega64	0:38ccae254a29	929	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
mega64	0:38ccae254a29	930	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
mega64	0:38ccae254a29	931	uint32_t RESERVED3[759];
mega64	0:38ccae254a29	932	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
mega64	0:38ccae254a29	933	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
mega64	0:38ccae254a29	934	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
mega64	0:38ccae254a29	935	uint32_t RESERVED4[1];
mega64	0:38ccae254a29	936	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
mega64	0:38ccae254a29	937	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
mega64	0:38ccae254a29	938	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
mega64	0:38ccae254a29	939	uint32_t RESERVED5[39];
mega64	0:38ccae254a29	940	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
mega64	0:38ccae254a29	941	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
mega64	0:38ccae254a29	942	uint32_t RESERVED7[8];
mega64	0:38ccae254a29	943	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
mega64	0:38ccae254a29	944	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
mega64	0:38ccae254a29	945	} TPI_Type;
mega64	0:38ccae254a29	946
mega64	0:38ccae254a29	947	/* TPI Asynchronous Clock Prescaler Register Definitions */
mega64	0:38ccae254a29	948	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
mega64	0:38ccae254a29	949	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /!< TPI ACPR: PRESCALER Mask /
mega64	0:38ccae254a29	950
mega64	0:38ccae254a29	951	/* TPI Selected Pin Protocol Register Definitions */
mega64	0:38ccae254a29	952	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
mega64	0:38ccae254a29	953	#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /!< TPI SPPR: TXMODE Mask /
mega64	0:38ccae254a29	954
mega64	0:38ccae254a29	955	/* TPI Formatter and Flush Status Register Definitions */
mega64	0:38ccae254a29	956	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
mega64	0:38ccae254a29	957	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
mega64	0:38ccae254a29	958
mega64	0:38ccae254a29	959	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
mega64	0:38ccae254a29	960	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
mega64	0:38ccae254a29	961
mega64	0:38ccae254a29	962	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
mega64	0:38ccae254a29	963	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
mega64	0:38ccae254a29	964
mega64	0:38ccae254a29	965	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
mega64	0:38ccae254a29	966	#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /!< TPI FFSR: FlInProg Mask /
mega64	0:38ccae254a29	967
mega64	0:38ccae254a29	968	/* TPI Formatter and Flush Control Register Definitions */
mega64	0:38ccae254a29	969	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
mega64	0:38ccae254a29	970	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
mega64	0:38ccae254a29	971
mega64	0:38ccae254a29	972	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
mega64	0:38ccae254a29	973	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
mega64	0:38ccae254a29	974
mega64	0:38ccae254a29	975	/* TPI TRIGGER Register Definitions */
mega64	0:38ccae254a29	976	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
mega64	0:38ccae254a29	977	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /!< TPI TRIGGER: TRIGGER Mask /
mega64	0:38ccae254a29	978
mega64	0:38ccae254a29	979	/* TPI Integration ETM Data Register Definitions (FIFO0) */
mega64	0:38ccae254a29	980	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
mega64	0:38ccae254a29	981	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
mega64	0:38ccae254a29	982
mega64	0:38ccae254a29	983	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
mega64	0:38ccae254a29	984	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
mega64	0:38ccae254a29	985
mega64	0:38ccae254a29	986	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
mega64	0:38ccae254a29	987	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
mega64	0:38ccae254a29	988
mega64	0:38ccae254a29	989	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
mega64	0:38ccae254a29	990	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
mega64	0:38ccae254a29	991
mega64	0:38ccae254a29	992	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
mega64	0:38ccae254a29	993	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
mega64	0:38ccae254a29	994
mega64	0:38ccae254a29	995	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
mega64	0:38ccae254a29	996	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
mega64	0:38ccae254a29	997
mega64	0:38ccae254a29	998	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
mega64	0:38ccae254a29	999	#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /!< TPI FIFO0: ETM0 Mask /
mega64	0:38ccae254a29	1000
mega64	0:38ccae254a29	1001	/* TPI ITATBCTR2 Register Definitions */
mega64	0:38ccae254a29	1002	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
mega64	0:38ccae254a29	1003	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /!< TPI ITATBCTR2: ATREADY Mask /
mega64	0:38ccae254a29	1004
mega64	0:38ccae254a29	1005	/* TPI Integration ITM Data Register Definitions (FIFO1) */
mega64	0:38ccae254a29	1006	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
mega64	0:38ccae254a29	1007	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
mega64	0:38ccae254a29	1008
mega64	0:38ccae254a29	1009	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
mega64	0:38ccae254a29	1010	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
mega64	0:38ccae254a29	1011
mega64	0:38ccae254a29	1012	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
mega64	0:38ccae254a29	1013	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
mega64	0:38ccae254a29	1014
mega64	0:38ccae254a29	1015	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
mega64	0:38ccae254a29	1016	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
mega64	0:38ccae254a29	1017
mega64	0:38ccae254a29	1018	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
mega64	0:38ccae254a29	1019	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
mega64	0:38ccae254a29	1020
mega64	0:38ccae254a29	1021	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
mega64	0:38ccae254a29	1022	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
mega64	0:38ccae254a29	1023
mega64	0:38ccae254a29	1024	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
mega64	0:38ccae254a29	1025	#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /!< TPI FIFO1: ITM0 Mask /
mega64	0:38ccae254a29	1026
mega64	0:38ccae254a29	1027	/* TPI ITATBCTR0 Register Definitions */
mega64	0:38ccae254a29	1028	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
mega64	0:38ccae254a29	1029	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /!< TPI ITATBCTR0: ATREADY Mask /
mega64	0:38ccae254a29	1030
mega64	0:38ccae254a29	1031	/* TPI Integration Mode Control Register Definitions */
mega64	0:38ccae254a29	1032	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
mega64	0:38ccae254a29	1033	#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /!< TPI ITCTRL: Mode Mask /
mega64	0:38ccae254a29	1034
mega64	0:38ccae254a29	1035	/* TPI DEVID Register Definitions */
mega64	0:38ccae254a29	1036	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
mega64	0:38ccae254a29	1037	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
mega64	0:38ccae254a29	1038
mega64	0:38ccae254a29	1039	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
mega64	0:38ccae254a29	1040	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
mega64	0:38ccae254a29	1041
mega64	0:38ccae254a29	1042	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
mega64	0:38ccae254a29	1043	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
mega64	0:38ccae254a29	1044
mega64	0:38ccae254a29	1045	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
mega64	0:38ccae254a29	1046	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
mega64	0:38ccae254a29	1047
mega64	0:38ccae254a29	1048	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
mega64	0:38ccae254a29	1049	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
mega64	0:38ccae254a29	1050
mega64	0:38ccae254a29	1051	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
mega64	0:38ccae254a29	1052	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /!< TPI DEVID: NrTraceInput Mask /
mega64	0:38ccae254a29	1053
mega64	0:38ccae254a29	1054	/* TPI DEVTYPE Register Definitions */
mega64	0:38ccae254a29	1055	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
mega64	0:38ccae254a29	1056	#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /!< TPI DEVTYPE: SubType Mask /
mega64	0:38ccae254a29	1057
mega64	0:38ccae254a29	1058	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
mega64	0:38ccae254a29	1059	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
mega64	0:38ccae254a29	1060
mega64	0:38ccae254a29	1061	/@}/ /* end of group CMSIS_TPI */
mega64	0:38ccae254a29	1062
mega64	0:38ccae254a29	1063
mega64	0:38ccae254a29	1064	#if (__MPU_PRESENT == 1)
mega64	0:38ccae254a29	1065	/** \ingroup CMSIS_core_register
mega64	0:38ccae254a29	1066	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
mega64	0:38ccae254a29	1067	\brief Type definitions for the Memory Protection Unit (MPU)
mega64	0:38ccae254a29	1068	@{
mega64	0:38ccae254a29	1069	*/
mega64	0:38ccae254a29	1070
mega64	0:38ccae254a29	1071	/** \brief Structure type to access the Memory Protection Unit (MPU).
mega64	0:38ccae254a29	1072	*/
mega64	0:38ccae254a29	1073	typedef struct
mega64	0:38ccae254a29	1074	{
mega64	0:38ccae254a29	1075	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
mega64	0:38ccae254a29	1076	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
mega64	0:38ccae254a29	1077	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
mega64	0:38ccae254a29	1078	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
mega64	0:38ccae254a29	1079	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
mega64	0:38ccae254a29	1080	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
mega64	0:38ccae254a29	1081	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
mega64	0:38ccae254a29	1082	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
mega64	0:38ccae254a29	1083	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
mega64	0:38ccae254a29	1084	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
mega64	0:38ccae254a29	1085	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
mega64	0:38ccae254a29	1086	} MPU_Type;
mega64	0:38ccae254a29	1087
mega64	0:38ccae254a29	1088	/* MPU Type Register */
mega64	0:38ccae254a29	1089	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
mega64	0:38ccae254a29	1090	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
mega64	0:38ccae254a29	1091
mega64	0:38ccae254a29	1092	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
mega64	0:38ccae254a29	1093	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
mega64	0:38ccae254a29	1094
mega64	0:38ccae254a29	1095	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
mega64	0:38ccae254a29	1096	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
mega64	0:38ccae254a29	1097
mega64	0:38ccae254a29	1098	/* MPU Control Register */
mega64	0:38ccae254a29	1099	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
mega64	0:38ccae254a29	1100	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
mega64	0:38ccae254a29	1101
mega64	0:38ccae254a29	1102	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
mega64	0:38ccae254a29	1103	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
mega64	0:38ccae254a29	1104
mega64	0:38ccae254a29	1105	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
mega64	0:38ccae254a29	1106	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
mega64	0:38ccae254a29	1107
mega64	0:38ccae254a29	1108	/* MPU Region Number Register */
mega64	0:38ccae254a29	1109	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
mega64	0:38ccae254a29	1110	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
mega64	0:38ccae254a29	1111
mega64	0:38ccae254a29	1112	/* MPU Region Base Address Register */
mega64	0:38ccae254a29	1113	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
mega64	0:38ccae254a29	1114	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
mega64	0:38ccae254a29	1115
mega64	0:38ccae254a29	1116	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
mega64	0:38ccae254a29	1117	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
mega64	0:38ccae254a29	1118
mega64	0:38ccae254a29	1119	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
mega64	0:38ccae254a29	1120	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
mega64	0:38ccae254a29	1121
mega64	0:38ccae254a29	1122	/* MPU Region Attribute and Size Register */
mega64	0:38ccae254a29	1123	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
mega64	0:38ccae254a29	1124	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
mega64	0:38ccae254a29	1125
mega64	0:38ccae254a29	1126	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
mega64	0:38ccae254a29	1127	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
mega64	0:38ccae254a29	1128
mega64	0:38ccae254a29	1129	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
mega64	0:38ccae254a29	1130	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
mega64	0:38ccae254a29	1131
mega64	0:38ccae254a29	1132	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
mega64	0:38ccae254a29	1133	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
mega64	0:38ccae254a29	1134
mega64	0:38ccae254a29	1135	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
mega64	0:38ccae254a29	1136	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
mega64	0:38ccae254a29	1137
mega64	0:38ccae254a29	1138	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
mega64	0:38ccae254a29	1139	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
mega64	0:38ccae254a29	1140
mega64	0:38ccae254a29	1141	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
mega64	0:38ccae254a29	1142	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
mega64	0:38ccae254a29	1143
mega64	0:38ccae254a29	1144	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
mega64	0:38ccae254a29	1145	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
mega64	0:38ccae254a29	1146
mega64	0:38ccae254a29	1147	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
mega64	0:38ccae254a29	1148	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
mega64	0:38ccae254a29	1149
mega64	0:38ccae254a29	1150	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
mega64	0:38ccae254a29	1151	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
mega64	0:38ccae254a29	1152
mega64	0:38ccae254a29	1153	/@} end of group CMSIS_MPU /
mega64	0:38ccae254a29	1154	#endif
mega64	0:38ccae254a29	1155
mega64	0:38ccae254a29	1156
mega64	0:38ccae254a29	1157	#if (__FPU_PRESENT == 1)
mega64	0:38ccae254a29	1158	/** \ingroup CMSIS_core_register
mega64	0:38ccae254a29	1159	\defgroup CMSIS_FPU Floating Point Unit (FPU)
mega64	0:38ccae254a29	1160	\brief Type definitions for the Floating Point Unit (FPU)
mega64	0:38ccae254a29	1161	@{
mega64	0:38ccae254a29	1162	*/
mega64	0:38ccae254a29	1163
mega64	0:38ccae254a29	1164	/** \brief Structure type to access the Floating Point Unit (FPU).
mega64	0:38ccae254a29	1165	*/
mega64	0:38ccae254a29	1166	typedef struct
mega64	0:38ccae254a29	1167	{
mega64	0:38ccae254a29	1168	uint32_t RESERVED0[1];
mega64	0:38ccae254a29	1169	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
mega64	0:38ccae254a29	1170	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
mega64	0:38ccae254a29	1171	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
mega64	0:38ccae254a29	1172	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
mega64	0:38ccae254a29	1173	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
mega64	0:38ccae254a29	1174	} FPU_Type;
mega64	0:38ccae254a29	1175
mega64	0:38ccae254a29	1176	/* Floating-Point Context Control Register */
mega64	0:38ccae254a29	1177	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
mega64	0:38ccae254a29	1178	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
mega64	0:38ccae254a29	1179
mega64	0:38ccae254a29	1180	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
mega64	0:38ccae254a29	1181	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
mega64	0:38ccae254a29	1182
mega64	0:38ccae254a29	1183	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
mega64	0:38ccae254a29	1184	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
mega64	0:38ccae254a29	1185
mega64	0:38ccae254a29	1186	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
mega64	0:38ccae254a29	1187	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
mega64	0:38ccae254a29	1188
mega64	0:38ccae254a29	1189	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
mega64	0:38ccae254a29	1190	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
mega64	0:38ccae254a29	1191
mega64	0:38ccae254a29	1192	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
mega64	0:38ccae254a29	1193	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
mega64	0:38ccae254a29	1194
mega64	0:38ccae254a29	1195	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
mega64	0:38ccae254a29	1196	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
mega64	0:38ccae254a29	1197
mega64	0:38ccae254a29	1198	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
mega64	0:38ccae254a29	1199	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
mega64	0:38ccae254a29	1200
mega64	0:38ccae254a29	1201	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
mega64	0:38ccae254a29	1202	#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /!< FPCCR: Lazy state preservation active bit Mask /
mega64	0:38ccae254a29	1203
mega64	0:38ccae254a29	1204	/* Floating-Point Context Address Register */
mega64	0:38ccae254a29	1205	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
mega64	0:38ccae254a29	1206	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
mega64	0:38ccae254a29	1207
mega64	0:38ccae254a29	1208	/* Floating-Point Default Status Control Register */
mega64	0:38ccae254a29	1209	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
mega64	0:38ccae254a29	1210	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
mega64	0:38ccae254a29	1211
mega64	0:38ccae254a29	1212	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
mega64	0:38ccae254a29	1213	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
mega64	0:38ccae254a29	1214
mega64	0:38ccae254a29	1215	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
mega64	0:38ccae254a29	1216	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
mega64	0:38ccae254a29	1217
mega64	0:38ccae254a29	1218	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
mega64	0:38ccae254a29	1219	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
mega64	0:38ccae254a29	1220
mega64	0:38ccae254a29	1221	/* Media and FP Feature Register 0 */
mega64	0:38ccae254a29	1222	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
mega64	0:38ccae254a29	1223	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
mega64	0:38ccae254a29	1224
mega64	0:38ccae254a29	1225	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
mega64	0:38ccae254a29	1226	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
mega64	0:38ccae254a29	1227
mega64	0:38ccae254a29	1228	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
mega64	0:38ccae254a29	1229	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
mega64	0:38ccae254a29	1230
mega64	0:38ccae254a29	1231	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
mega64	0:38ccae254a29	1232	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
mega64	0:38ccae254a29	1233
mega64	0:38ccae254a29	1234	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
mega64	0:38ccae254a29	1235	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
mega64	0:38ccae254a29	1236
mega64	0:38ccae254a29	1237	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
mega64	0:38ccae254a29	1238	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
mega64	0:38ccae254a29	1239
mega64	0:38ccae254a29	1240	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
mega64	0:38ccae254a29	1241	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
mega64	0:38ccae254a29	1242
mega64	0:38ccae254a29	1243	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
mega64	0:38ccae254a29	1244	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /!< MVFR0: A_SIMD registers bits Mask /
mega64	0:38ccae254a29	1245
mega64	0:38ccae254a29	1246	/* Media and FP Feature Register 1 */
mega64	0:38ccae254a29	1247	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
mega64	0:38ccae254a29	1248	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
mega64	0:38ccae254a29	1249
mega64	0:38ccae254a29	1250	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
mega64	0:38ccae254a29	1251	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
mega64	0:38ccae254a29	1252
mega64	0:38ccae254a29	1253	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
mega64	0:38ccae254a29	1254	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
mega64	0:38ccae254a29	1255
mega64	0:38ccae254a29	1256	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
mega64	0:38ccae254a29	1257	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /!< MVFR1: FtZ mode bits Mask /
mega64	0:38ccae254a29	1258
mega64	0:38ccae254a29	1259	/@} end of group CMSIS_FPU /
mega64	0:38ccae254a29	1260	#endif
mega64	0:38ccae254a29	1261
mega64	0:38ccae254a29	1262
mega64	0:38ccae254a29	1263	/** \ingroup CMSIS_core_register
mega64	0:38ccae254a29	1264	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mega64	0:38ccae254a29	1265	\brief Type definitions for the Core Debug Registers
mega64	0:38ccae254a29	1266	@{
mega64	0:38ccae254a29	1267	*/
mega64	0:38ccae254a29	1268
mega64	0:38ccae254a29	1269	/** \brief Structure type to access the Core Debug Register (CoreDebug).
mega64	0:38ccae254a29	1270	*/
mega64	0:38ccae254a29	1271	typedef struct
mega64	0:38ccae254a29	1272	{
mega64	0:38ccae254a29	1273	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
mega64	0:38ccae254a29	1274	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
mega64	0:38ccae254a29	1275	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
mega64	0:38ccae254a29	1276	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
mega64	0:38ccae254a29	1277	} CoreDebug_Type;
mega64	0:38ccae254a29	1278
mega64	0:38ccae254a29	1279	/* Debug Halting Control and Status Register */
mega64	0:38ccae254a29	1280	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
mega64	0:38ccae254a29	1281	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
mega64	0:38ccae254a29	1282
mega64	0:38ccae254a29	1283	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
mega64	0:38ccae254a29	1284	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
mega64	0:38ccae254a29	1285
mega64	0:38ccae254a29	1286	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
mega64	0:38ccae254a29	1287	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
mega64	0:38ccae254a29	1288
mega64	0:38ccae254a29	1289	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
mega64	0:38ccae254a29	1290	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
mega64	0:38ccae254a29	1291
mega64	0:38ccae254a29	1292	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
mega64	0:38ccae254a29	1293	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
mega64	0:38ccae254a29	1294
mega64	0:38ccae254a29	1295	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
mega64	0:38ccae254a29	1296	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
mega64	0:38ccae254a29	1297
mega64	0:38ccae254a29	1298	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
mega64	0:38ccae254a29	1299	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
mega64	0:38ccae254a29	1300
mega64	0:38ccae254a29	1301	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
mega64	0:38ccae254a29	1302	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
mega64	0:38ccae254a29	1303
mega64	0:38ccae254a29	1304	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
mega64	0:38ccae254a29	1305	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
mega64	0:38ccae254a29	1306
mega64	0:38ccae254a29	1307	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
mega64	0:38ccae254a29	1308	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
mega64	0:38ccae254a29	1309
mega64	0:38ccae254a29	1310	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
mega64	0:38ccae254a29	1311	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
mega64	0:38ccae254a29	1312
mega64	0:38ccae254a29	1313	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
mega64	0:38ccae254a29	1314	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
mega64	0:38ccae254a29	1315
mega64	0:38ccae254a29	1316	/* Debug Core Register Selector Register */
mega64	0:38ccae254a29	1317	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
mega64	0:38ccae254a29	1318	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
mega64	0:38ccae254a29	1319
mega64	0:38ccae254a29	1320	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
mega64	0:38ccae254a29	1321	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
mega64	0:38ccae254a29	1322
mega64	0:38ccae254a29	1323	/* Debug Exception and Monitor Control Register */
mega64	0:38ccae254a29	1324	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
mega64	0:38ccae254a29	1325	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
mega64	0:38ccae254a29	1326
mega64	0:38ccae254a29	1327	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
mega64	0:38ccae254a29	1328	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
mega64	0:38ccae254a29	1329
mega64	0:38ccae254a29	1330	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
mega64	0:38ccae254a29	1331	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
mega64	0:38ccae254a29	1332
mega64	0:38ccae254a29	1333	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
mega64	0:38ccae254a29	1334	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
mega64	0:38ccae254a29	1335
mega64	0:38ccae254a29	1336	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
mega64	0:38ccae254a29	1337	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
mega64	0:38ccae254a29	1338
mega64	0:38ccae254a29	1339	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
mega64	0:38ccae254a29	1340	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
mega64	0:38ccae254a29	1341
mega64	0:38ccae254a29	1342	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
mega64	0:38ccae254a29	1343	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
mega64	0:38ccae254a29	1344
mega64	0:38ccae254a29	1345	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
mega64	0:38ccae254a29	1346	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
mega64	0:38ccae254a29	1347
mega64	0:38ccae254a29	1348	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
mega64	0:38ccae254a29	1349	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
mega64	0:38ccae254a29	1350
mega64	0:38ccae254a29	1351	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
mega64	0:38ccae254a29	1352	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
mega64	0:38ccae254a29	1353
mega64	0:38ccae254a29	1354	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
mega64	0:38ccae254a29	1355	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
mega64	0:38ccae254a29	1356
mega64	0:38ccae254a29	1357	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
mega64	0:38ccae254a29	1358	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
mega64	0:38ccae254a29	1359
mega64	0:38ccae254a29	1360	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
mega64	0:38ccae254a29	1361	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
mega64	0:38ccae254a29	1362
mega64	0:38ccae254a29	1363	/@} end of group CMSIS_CoreDebug /
mega64	0:38ccae254a29	1364
mega64	0:38ccae254a29	1365
mega64	0:38ccae254a29	1366	/** \ingroup CMSIS_core_register
mega64	0:38ccae254a29	1367	\defgroup CMSIS_core_base Core Definitions
mega64	0:38ccae254a29	1368	\brief Definitions for base addresses, unions, and structures.
mega64	0:38ccae254a29	1369	@{
mega64	0:38ccae254a29	1370	*/
mega64	0:38ccae254a29	1371
mega64	0:38ccae254a29	1372	/* Memory mapping of Cortex-M4 Hardware */
mega64	0:38ccae254a29	1373	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
mega64	0:38ccae254a29	1374	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
mega64	0:38ccae254a29	1375	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
mega64	0:38ccae254a29	1376	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
mega64	0:38ccae254a29	1377	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
mega64	0:38ccae254a29	1378	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
mega64	0:38ccae254a29	1379	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
mega64	0:38ccae254a29	1380	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
mega64	0:38ccae254a29	1381
mega64	0:38ccae254a29	1382	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
mega64	0:38ccae254a29	1383	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
mega64	0:38ccae254a29	1384	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
mega64	0:38ccae254a29	1385	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
mega64	0:38ccae254a29	1386	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
mega64	0:38ccae254a29	1387	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
mega64	0:38ccae254a29	1388	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
mega64	0:38ccae254a29	1389	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
mega64	0:38ccae254a29	1390
mega64	0:38ccae254a29	1391	#if (__MPU_PRESENT == 1)
mega64	0:38ccae254a29	1392	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
mega64	0:38ccae254a29	1393	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
mega64	0:38ccae254a29	1394	#endif
mega64	0:38ccae254a29	1395
mega64	0:38ccae254a29	1396	#if (__FPU_PRESENT == 1)
mega64	0:38ccae254a29	1397	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
mega64	0:38ccae254a29	1398	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
mega64	0:38ccae254a29	1399	#endif
mega64	0:38ccae254a29	1400
mega64	0:38ccae254a29	1401	/@} /
mega64	0:38ccae254a29	1402
mega64	0:38ccae254a29	1403
mega64	0:38ccae254a29	1404
mega64	0:38ccae254a29	1405	/*******************************************************************************
mega64	0:38ccae254a29	1406	* Hardware Abstraction Layer
mega64	0:38ccae254a29	1407	Core Function Interface contains:
mega64	0:38ccae254a29	1408	- Core NVIC Functions
mega64	0:38ccae254a29	1409	- Core SysTick Functions
mega64	0:38ccae254a29	1410	- Core Debug Functions
mega64	0:38ccae254a29	1411	- Core Register Access Functions
mega64	0:38ccae254a29	1412	******************************************************************************/
mega64	0:38ccae254a29	1413	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mega64	0:38ccae254a29	1414	*/
mega64	0:38ccae254a29	1415
mega64	0:38ccae254a29	1416
mega64	0:38ccae254a29	1417
mega64	0:38ccae254a29	1418	/* ########################## NVIC functions #################################### */
mega64	0:38ccae254a29	1419	/** \ingroup CMSIS_Core_FunctionInterface
mega64	0:38ccae254a29	1420	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
mega64	0:38ccae254a29	1421	\brief Functions that manage interrupts and exceptions via the NVIC.
mega64	0:38ccae254a29	1422	@{
mega64	0:38ccae254a29	1423	*/
mega64	0:38ccae254a29	1424
mega64	0:38ccae254a29	1425	/** \brief Set Priority Grouping
mega64	0:38ccae254a29	1426
mega64	0:38ccae254a29	1427	The function sets the priority grouping field using the required unlock sequence.
mega64	0:38ccae254a29	1428	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
mega64	0:38ccae254a29	1429	Only values from 0..7 are used.
mega64	0:38ccae254a29	1430	In case of a conflict between priority grouping and available
mega64	0:38ccae254a29	1431	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mega64	0:38ccae254a29	1432
mega64	0:38ccae254a29	1433	\param [in] PriorityGroup Priority grouping field.
mega64	0:38ccae254a29	1434	*/
mega64	0:38ccae254a29	1435	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
mega64	0:38ccae254a29	1436	{
mega64	0:38ccae254a29	1437	uint32_t reg_value;
mega64	0:38ccae254a29	1438	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
mega64	0:38ccae254a29	1439
mega64	0:38ccae254a29	1440	reg_value = SCB->AIRCR; /* read old register configuration */
mega64	0:38ccae254a29	1441	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
mega64	0:38ccae254a29	1442	reg_value = (reg_value \|
mega64	0:38ccae254a29	1443	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
mega64	0:38ccae254a29	1444	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
mega64	0:38ccae254a29	1445	SCB->AIRCR = reg_value;
mega64	0:38ccae254a29	1446	}
mega64	0:38ccae254a29	1447
mega64	0:38ccae254a29	1448
mega64	0:38ccae254a29	1449	/** \brief Get Priority Grouping
mega64	0:38ccae254a29	1450
mega64	0:38ccae254a29	1451	The function reads the priority grouping field from the NVIC Interrupt Controller.
mega64	0:38ccae254a29	1452
mega64	0:38ccae254a29	1453	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
mega64	0:38ccae254a29	1454	*/
mega64	0:38ccae254a29	1455	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
mega64	0:38ccae254a29	1456	{
mega64	0:38ccae254a29	1457	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
mega64	0:38ccae254a29	1458	}
mega64	0:38ccae254a29	1459
mega64	0:38ccae254a29	1460
mega64	0:38ccae254a29	1461	/** \brief Enable External Interrupt
mega64	0:38ccae254a29	1462
mega64	0:38ccae254a29	1463	The function enables a device-specific interrupt in the NVIC interrupt controller.
mega64	0:38ccae254a29	1464
mega64	0:38ccae254a29	1465	\param [in] IRQn External interrupt number. Value cannot be negative.
mega64	0:38ccae254a29	1466	*/
mega64	0:38ccae254a29	1467	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mega64	0:38ccae254a29	1468	{
mega64	0:38ccae254a29	1469	/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
mega64	0:38ccae254a29	1470	NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
mega64	0:38ccae254a29	1471	}
mega64	0:38ccae254a29	1472
mega64	0:38ccae254a29	1473
mega64	0:38ccae254a29	1474	/** \brief Disable External Interrupt
mega64	0:38ccae254a29	1475
mega64	0:38ccae254a29	1476	The function disables a device-specific interrupt in the NVIC interrupt controller.
mega64	0:38ccae254a29	1477
mega64	0:38ccae254a29	1478	\param [in] IRQn External interrupt number. Value cannot be negative.
mega64	0:38ccae254a29	1479	*/
mega64	0:38ccae254a29	1480	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mega64	0:38ccae254a29	1481	{
mega64	0:38ccae254a29	1482	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
mega64	0:38ccae254a29	1483	}
mega64	0:38ccae254a29	1484
mega64	0:38ccae254a29	1485
mega64	0:38ccae254a29	1486	/** \brief Get Pending Interrupt
mega64	0:38ccae254a29	1487
mega64	0:38ccae254a29	1488	The function reads the pending register in the NVIC and returns the pending bit
mega64	0:38ccae254a29	1489	for the specified interrupt.
mega64	0:38ccae254a29	1490
mega64	0:38ccae254a29	1491	\param [in] IRQn Interrupt number.
mega64	0:38ccae254a29	1492
mega64	0:38ccae254a29	1493	\return 0 Interrupt status is not pending.
mega64	0:38ccae254a29	1494	\return 1 Interrupt status is pending.
mega64	0:38ccae254a29	1495	*/
mega64	0:38ccae254a29	1496	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mega64	0:38ccae254a29	1497	{
mega64	0:38ccae254a29	1498	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
mega64	0:38ccae254a29	1499	}
mega64	0:38ccae254a29	1500
mega64	0:38ccae254a29	1501
mega64	0:38ccae254a29	1502	/** \brief Set Pending Interrupt
mega64	0:38ccae254a29	1503
mega64	0:38ccae254a29	1504	The function sets the pending bit of an external interrupt.
mega64	0:38ccae254a29	1505
mega64	0:38ccae254a29	1506	\param [in] IRQn Interrupt number. Value cannot be negative.
mega64	0:38ccae254a29	1507	*/
mega64	0:38ccae254a29	1508	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mega64	0:38ccae254a29	1509	{
mega64	0:38ccae254a29	1510	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
mega64	0:38ccae254a29	1511	}
mega64	0:38ccae254a29	1512
mega64	0:38ccae254a29	1513
mega64	0:38ccae254a29	1514	/** \brief Clear Pending Interrupt
mega64	0:38ccae254a29	1515
mega64	0:38ccae254a29	1516	The function clears the pending bit of an external interrupt.
mega64	0:38ccae254a29	1517
mega64	0:38ccae254a29	1518	\param [in] IRQn External interrupt number. Value cannot be negative.
mega64	0:38ccae254a29	1519	*/
mega64	0:38ccae254a29	1520	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mega64	0:38ccae254a29	1521	{
mega64	0:38ccae254a29	1522	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
mega64	0:38ccae254a29	1523	}
mega64	0:38ccae254a29	1524
mega64	0:38ccae254a29	1525
mega64	0:38ccae254a29	1526	/** \brief Get Active Interrupt
mega64	0:38ccae254a29	1527
mega64	0:38ccae254a29	1528	The function reads the active register in NVIC and returns the active bit.
mega64	0:38ccae254a29	1529
mega64	0:38ccae254a29	1530	\param [in] IRQn Interrupt number.
mega64	0:38ccae254a29	1531
mega64	0:38ccae254a29	1532	\return 0 Interrupt status is not active.
mega64	0:38ccae254a29	1533	\return 1 Interrupt status is active.
mega64	0:38ccae254a29	1534	*/
mega64	0:38ccae254a29	1535	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
mega64	0:38ccae254a29	1536	{
mega64	0:38ccae254a29	1537	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
mega64	0:38ccae254a29	1538	}
mega64	0:38ccae254a29	1539
mega64	0:38ccae254a29	1540
mega64	0:38ccae254a29	1541	/** \brief Set Interrupt Priority
mega64	0:38ccae254a29	1542
mega64	0:38ccae254a29	1543	The function sets the priority of an interrupt.
mega64	0:38ccae254a29	1544
mega64	0:38ccae254a29	1545	\note The priority cannot be set for every core interrupt.
mega64	0:38ccae254a29	1546
mega64	0:38ccae254a29	1547	\param [in] IRQn Interrupt number.
mega64	0:38ccae254a29	1548	\param [in] priority Priority to set.
mega64	0:38ccae254a29	1549	*/
mega64	0:38ccae254a29	1550	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mega64	0:38ccae254a29	1551	{
mega64	0:38ccae254a29	1552	if(IRQn < 0) {
mega64	0:38ccae254a29	1553	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
mega64	0:38ccae254a29	1554	else {
mega64	0:38ccae254a29	1555	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
mega64	0:38ccae254a29	1556	}
mega64	0:38ccae254a29	1557
mega64	0:38ccae254a29	1558
mega64	0:38ccae254a29	1559	/** \brief Get Interrupt Priority
mega64	0:38ccae254a29	1560
mega64	0:38ccae254a29	1561	The function reads the priority of an interrupt. The interrupt
mega64	0:38ccae254a29	1562	number can be positive to specify an external (device specific)
mega64	0:38ccae254a29	1563	interrupt, or negative to specify an internal (core) interrupt.
mega64	0:38ccae254a29	1564
mega64	0:38ccae254a29	1565
mega64	0:38ccae254a29	1566	\param [in] IRQn Interrupt number.
mega64	0:38ccae254a29	1567	\return Interrupt Priority. Value is aligned automatically to the implemented
mega64	0:38ccae254a29	1568	priority bits of the microcontroller.
mega64	0:38ccae254a29	1569	*/
mega64	0:38ccae254a29	1570	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mega64	0:38ccae254a29	1571	{
mega64	0:38ccae254a29	1572
mega64	0:38ccae254a29	1573	if(IRQn < 0) {
mega64	0:38ccae254a29	1574	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
mega64	0:38ccae254a29	1575	else {
mega64	0:38ccae254a29	1576	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
mega64	0:38ccae254a29	1577	}
mega64	0:38ccae254a29	1578
mega64	0:38ccae254a29	1579
mega64	0:38ccae254a29	1580	/** \brief Encode Priority
mega64	0:38ccae254a29	1581
mega64	0:38ccae254a29	1582	The function encodes the priority for an interrupt with the given priority group,
mega64	0:38ccae254a29	1583	preemptive priority value, and subpriority value.
mega64	0:38ccae254a29	1584	In case of a conflict between priority grouping and available
mega64	0:38ccae254a29	1585	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
mega64	0:38ccae254a29	1586
mega64	0:38ccae254a29	1587	\param [in] PriorityGroup Used priority group.
mega64	0:38ccae254a29	1588	\param [in] PreemptPriority Preemptive priority value (starting from 0).
mega64	0:38ccae254a29	1589	\param [in] SubPriority Subpriority value (starting from 0).
mega64	0:38ccae254a29	1590	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
mega64	0:38ccae254a29	1591	*/
mega64	0:38ccae254a29	1592	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
mega64	0:38ccae254a29	1593	{
mega64	0:38ccae254a29	1594	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
mega64	0:38ccae254a29	1595	uint32_t PreemptPriorityBits;
mega64	0:38ccae254a29	1596	uint32_t SubPriorityBits;
mega64	0:38ccae254a29	1597
mega64	0:38ccae254a29	1598	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
mega64	0:38ccae254a29	1599	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
mega64	0:38ccae254a29	1600
mega64	0:38ccae254a29	1601	return (
mega64	0:38ccae254a29	1602	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
mega64	0:38ccae254a29	1603	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
mega64	0:38ccae254a29	1604	);
mega64	0:38ccae254a29	1605	}
mega64	0:38ccae254a29	1606
mega64	0:38ccae254a29	1607
mega64	0:38ccae254a29	1608	/** \brief Decode Priority
mega64	0:38ccae254a29	1609
mega64	0:38ccae254a29	1610	The function decodes an interrupt priority value with a given priority group to
mega64	0:38ccae254a29	1611	preemptive priority value and subpriority value.
mega64	0:38ccae254a29	1612	In case of a conflict between priority grouping and available
mega64	0:38ccae254a29	1613	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
mega64	0:38ccae254a29	1614
mega64	0:38ccae254a29	1615	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
mega64	0:38ccae254a29	1616	\param [in] PriorityGroup Used priority group.
mega64	0:38ccae254a29	1617	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
mega64	0:38ccae254a29	1618	\param [out] pSubPriority Subpriority value (starting from 0).
mega64	0:38ccae254a29	1619	*/
mega64	0:38ccae254a29	1620	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
mega64	0:38ccae254a29	1621	{
mega64	0:38ccae254a29	1622	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
mega64	0:38ccae254a29	1623	uint32_t PreemptPriorityBits;
mega64	0:38ccae254a29	1624	uint32_t SubPriorityBits;
mega64	0:38ccae254a29	1625
mega64	0:38ccae254a29	1626	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
mega64	0:38ccae254a29	1627	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
mega64	0:38ccae254a29	1628
mega64	0:38ccae254a29	1629	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
mega64	0:38ccae254a29	1630	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
mega64	0:38ccae254a29	1631	}
mega64	0:38ccae254a29	1632
mega64	0:38ccae254a29	1633
mega64	0:38ccae254a29	1634	/** \brief System Reset
mega64	0:38ccae254a29	1635
mega64	0:38ccae254a29	1636	The function initiates a system reset request to reset the MCU.
mega64	0:38ccae254a29	1637	*/
mega64	0:38ccae254a29	1638	__STATIC_INLINE void NVIC_SystemReset(void)
mega64	0:38ccae254a29	1639	{
mega64	0:38ccae254a29	1640	__DSB(); /* Ensure all outstanding memory accesses included
mega64	0:38ccae254a29	1641	buffered write are completed before reset */
mega64	0:38ccae254a29	1642	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
mega64	0:38ccae254a29	1643	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
mega64	0:38ccae254a29	1644	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
mega64	0:38ccae254a29	1645	__DSB(); /* Ensure completion of memory access */
mega64	0:38ccae254a29	1646	while(1); /* wait until reset */
mega64	0:38ccae254a29	1647	}
mega64	0:38ccae254a29	1648
mega64	0:38ccae254a29	1649	/@} end of CMSIS_Core_NVICFunctions /
mega64	0:38ccae254a29	1650
mega64	0:38ccae254a29	1651
mega64	0:38ccae254a29	1652
mega64	0:38ccae254a29	1653	/* ################################## SysTick function ############################################ */
mega64	0:38ccae254a29	1654	/** \ingroup CMSIS_Core_FunctionInterface
mega64	0:38ccae254a29	1655	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mega64	0:38ccae254a29	1656	\brief Functions that configure the System.
mega64	0:38ccae254a29	1657	@{
mega64	0:38ccae254a29	1658	*/
mega64	0:38ccae254a29	1659
mega64	0:38ccae254a29	1660	#if (__Vendor_SysTickConfig == 0)
mega64	0:38ccae254a29	1661
mega64	0:38ccae254a29	1662	/** \brief System Tick Configuration
mega64	0:38ccae254a29	1663
mega64	0:38ccae254a29	1664	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mega64	0:38ccae254a29	1665	Counter is in free running mode to generate periodic interrupts.
mega64	0:38ccae254a29	1666
mega64	0:38ccae254a29	1667	\param [in] ticks Number of ticks between two interrupts.
mega64	0:38ccae254a29	1668
mega64	0:38ccae254a29	1669	\return 0 Function succeeded.
mega64	0:38ccae254a29	1670	\return 1 Function failed.
mega64	0:38ccae254a29	1671
mega64	0:38ccae254a29	1672	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mega64	0:38ccae254a29	1673	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mega64	0:38ccae254a29	1674	must contain a vendor-specific implementation of this function.
mega64	0:38ccae254a29	1675
mega64	0:38ccae254a29	1676	*/
mega64	0:38ccae254a29	1677	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mega64	0:38ccae254a29	1678	{
mega64	0:38ccae254a29	1679	if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
mega64	0:38ccae254a29	1680
mega64	0:38ccae254a29	1681	SysTick->LOAD = ticks - 1; /* set reload register */
mega64	0:38ccae254a29	1682	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
mega64	0:38ccae254a29	1683	SysTick->VAL = 0; /* Load the SysTick Counter Value */
mega64	0:38ccae254a29	1684	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
mega64	0:38ccae254a29	1685	SysTick_CTRL_TICKINT_Msk \|
mega64	0:38ccae254a29	1686	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mega64	0:38ccae254a29	1687	return (0); /* Function successful */
mega64	0:38ccae254a29	1688	}
mega64	0:38ccae254a29	1689
mega64	0:38ccae254a29	1690	#endif
mega64	0:38ccae254a29	1691
mega64	0:38ccae254a29	1692	/@} end of CMSIS_Core_SysTickFunctions /
mega64	0:38ccae254a29	1693
mega64	0:38ccae254a29	1694
mega64	0:38ccae254a29	1695
mega64	0:38ccae254a29	1696	/* ##################################### Debug In/Output function ########################################### */
mega64	0:38ccae254a29	1697	/** \ingroup CMSIS_Core_FunctionInterface
mega64	0:38ccae254a29	1698	\defgroup CMSIS_core_DebugFunctions ITM Functions
mega64	0:38ccae254a29	1699	\brief Functions that access the ITM debug interface.
mega64	0:38ccae254a29	1700	@{
mega64	0:38ccae254a29	1701	*/
mega64	0:38ccae254a29	1702
mega64	0:38ccae254a29	1703	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
mega64	0:38ccae254a29	1704	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
mega64	0:38ccae254a29	1705
mega64	0:38ccae254a29	1706
mega64	0:38ccae254a29	1707	/** \brief ITM Send Character
mega64	0:38ccae254a29	1708
mega64	0:38ccae254a29	1709	The function transmits a character via the ITM channel 0, and
mega64	0:38ccae254a29	1710	\li Just returns when no debugger is connected that has booked the output.
mega64	0:38ccae254a29	1711	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
mega64	0:38ccae254a29	1712
mega64	0:38ccae254a29	1713	\param [in] ch Character to transmit.
mega64	0:38ccae254a29	1714
mega64	0:38ccae254a29	1715	\returns Character to transmit.
mega64	0:38ccae254a29	1716	*/
mega64	0:38ccae254a29	1717	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
mega64	0:38ccae254a29	1718	{
mega64	0:38ccae254a29	1719	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
mega64	0:38ccae254a29	1720	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
mega64	0:38ccae254a29	1721	{
mega64	0:38ccae254a29	1722	while (ITM->PORT[0].u32 == 0);
mega64	0:38ccae254a29	1723	ITM->PORT[0].u8 = (uint8_t) ch;
mega64	0:38ccae254a29	1724	}
mega64	0:38ccae254a29	1725	return (ch);
mega64	0:38ccae254a29	1726	}
mega64	0:38ccae254a29	1727
mega64	0:38ccae254a29	1728
mega64	0:38ccae254a29	1729	/** \brief ITM Receive Character
mega64	0:38ccae254a29	1730
mega64	0:38ccae254a29	1731	The function inputs a character via the external variable \ref ITM_RxBuffer.
mega64	0:38ccae254a29	1732
mega64	0:38ccae254a29	1733	\return Received character.
mega64	0:38ccae254a29	1734	\return -1 No character pending.
mega64	0:38ccae254a29	1735	*/
mega64	0:38ccae254a29	1736	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
mega64	0:38ccae254a29	1737	int32_t ch = -1; /* no character available */
mega64	0:38ccae254a29	1738
mega64	0:38ccae254a29	1739	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
mega64	0:38ccae254a29	1740	ch = ITM_RxBuffer;
mega64	0:38ccae254a29	1741	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
mega64	0:38ccae254a29	1742	}
mega64	0:38ccae254a29	1743
mega64	0:38ccae254a29	1744	return (ch);
mega64	0:38ccae254a29	1745	}
mega64	0:38ccae254a29	1746
mega64	0:38ccae254a29	1747
mega64	0:38ccae254a29	1748	/** \brief ITM Check Character
mega64	0:38ccae254a29	1749
mega64	0:38ccae254a29	1750	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
mega64	0:38ccae254a29	1751
mega64	0:38ccae254a29	1752	\return 0 No character available.
mega64	0:38ccae254a29	1753	\return 1 Character available.
mega64	0:38ccae254a29	1754	*/
mega64	0:38ccae254a29	1755	__STATIC_INLINE int32_t ITM_CheckChar (void) {
mega64	0:38ccae254a29	1756
mega64	0:38ccae254a29	1757	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
mega64	0:38ccae254a29	1758	return (0); /* no character available */
mega64	0:38ccae254a29	1759	} else {
mega64	0:38ccae254a29	1760	return (1); /* character available */
mega64	0:38ccae254a29	1761	}
mega64	0:38ccae254a29	1762	}
mega64	0:38ccae254a29	1763
mega64	0:38ccae254a29	1764	/@} end of CMSIS_core_DebugFunctions /
mega64	0:38ccae254a29	1765
mega64	0:38ccae254a29	1766	#endif /* __CORE_CM4_H_DEPENDANT */
mega64	0:38ccae254a29	1767
mega64	0:38ccae254a29	1768	#endif /* __CMSIS_GENERIC */
mega64	0:38ccae254a29	1769
mega64	0:38ccae254a29	1770	#ifdef __cplusplus
mega64	0:38ccae254a29	1771	}
mega64	0:38ccae254a29	1772	#endif

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Type:	Library
Created:	01 Feb 2018
Imports:	8
Forks:	0
Commits:	13
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Followers:	2

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