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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/stm32f0xx_hal_can.c@0:38ccae254a29, 2014-10-18 (annotated)

Committer:
mega64
Date:
Sat Oct 18 02:40:17 2014 +0000
Revision:
0:38ccae254a29
only for STM32F030F4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mega64 0:38ccae254a29 1 /**
mega64 0:38ccae254a29 2 ******************************************************************************
mega64 0:38ccae254a29 3 * @file stm32f0xx_hal_can.c
mega64 0:38ccae254a29 4 * @author MCD Application Team
mega64 0:38ccae254a29 5 * @version V1.1.0
mega64 0:38ccae254a29 6 * @date 03-Oct-2014
mega64 0:38ccae254a29 7 * @brief CAN HAL module driver.
mega64 0:38ccae254a29 8 * This file provides firmware functions to manage the following
mega64 0:38ccae254a29 9 * functionalities of the Controller Area Network (CAN) peripheral:
mega64 0:38ccae254a29 10 * + Initialization and de-initialization functions
mega64 0:38ccae254a29 11 * + IO operation functions
mega64 0:38ccae254a29 12 * + Peripheral Control functions
mega64 0:38ccae254a29 13 * + Peripheral State and Error functions
mega64 0:38ccae254a29 14 *
mega64 0:38ccae254a29 15 @verbatim
mega64 0:38ccae254a29 16 ==============================================================================
mega64 0:38ccae254a29 17 ##### How to use this driver #####
mega64 0:38ccae254a29 18 ==============================================================================
mega64 0:38ccae254a29 19 [..]
mega64 0:38ccae254a29 20 (#) Enable the CAN controller interface clock using __CAN_CLK_ENABLE();
mega64 0:38ccae254a29 21
mega64 0:38ccae254a29 22 (#) CAN pins configuration
mega64 0:38ccae254a29 23 (++) Enable the clock for the CAN GPIOs using the following function:
mega64 0:38ccae254a29 24 __GPIOx_CLK_ENABLE();
mega64 0:38ccae254a29 25 (++) Connect and configure the involved CAN pins to AF9 using the
mega64 0:38ccae254a29 26 following function HAL_GPIO_Init();
mega64 0:38ccae254a29 27
mega64 0:38ccae254a29 28 (#) Initialise and configure the CAN using HAL_CAN_Init() function.
mega64 0:38ccae254a29 29
mega64 0:38ccae254a29 30 (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
mega64 0:38ccae254a29 31
mega64 0:38ccae254a29 32 (#) Receive a CAN frame using HAL_CAN_Receive() function.
mega64 0:38ccae254a29 33
mega64 0:38ccae254a29 34 *** Polling mode IO operation ***
mega64 0:38ccae254a29 35 =================================
mega64 0:38ccae254a29 36 [..]
mega64 0:38ccae254a29 37 (+) Start the CAN peripheral transmission and wait the end of this operation
mega64 0:38ccae254a29 38 using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
mega64 0:38ccae254a29 39 according to his end application
mega64 0:38ccae254a29 40 (+) Start the CAN peripheral reception and wait the end of this operation
mega64 0:38ccae254a29 41 using HAL_CAN_Receive(), at this stage user can specify the value of timeout
mega64 0:38ccae254a29 42 according to his end application
mega64 0:38ccae254a29 43
mega64 0:38ccae254a29 44 *** Interrupt mode IO operation ***
mega64 0:38ccae254a29 45 ===================================
mega64 0:38ccae254a29 46 [..]
mega64 0:38ccae254a29 47 (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
mega64 0:38ccae254a29 48 (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
mega64 0:38ccae254a29 49 (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
mega64 0:38ccae254a29 50 (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
mega64 0:38ccae254a29 51 add his own code by customization of function pointer HAL_CAN_TxCpltCallback
mega64 0:38ccae254a29 52 (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
mega64 0:38ccae254a29 53 add his own code by customization of function pointer HAL_CAN_ErrorCallback
mega64 0:38ccae254a29 54
mega64 0:38ccae254a29 55 *** CAN HAL driver macros list ***
mega64 0:38ccae254a29 56 =============================================
mega64 0:38ccae254a29 57 [..]
mega64 0:38ccae254a29 58 Below the list of most used macros in CAN HAL driver.
mega64 0:38ccae254a29 59
mega64 0:38ccae254a29 60 (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
mega64 0:38ccae254a29 61 (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
mega64 0:38ccae254a29 62 (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
mega64 0:38ccae254a29 63 (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
mega64 0:38ccae254a29 64 (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
mega64 0:38ccae254a29 65
mega64 0:38ccae254a29 66 [..]
mega64 0:38ccae254a29 67 (@) You can refer to the CAN HAL driver header file for more useful macros
mega64 0:38ccae254a29 68
mega64 0:38ccae254a29 69 @endverbatim
mega64 0:38ccae254a29 70
mega64 0:38ccae254a29 71 ******************************************************************************
mega64 0:38ccae254a29 72 * @attention
mega64 0:38ccae254a29 73 *
mega64 0:38ccae254a29 74 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mega64 0:38ccae254a29 75 *
mega64 0:38ccae254a29 76 * Redistribution and use in source and binary forms, with or without modification,
mega64 0:38ccae254a29 77 * are permitted provided that the following conditions are met:
mega64 0:38ccae254a29 78 * 1. Redistributions of source code must retain the above copyright notice,
mega64 0:38ccae254a29 79 * this list of conditions and the following disclaimer.
mega64 0:38ccae254a29 80 * 2. Redistributions in binary form must reproduce the above copyright notice,
mega64 0:38ccae254a29 81 * this list of conditions and the following disclaimer in the documentation
mega64 0:38ccae254a29 82 * and/or other materials provided with the distribution.
mega64 0:38ccae254a29 83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mega64 0:38ccae254a29 84 * may be used to endorse or promote products derived from this software
mega64 0:38ccae254a29 85 * without specific prior written permission.
mega64 0:38ccae254a29 86 *
mega64 0:38ccae254a29 87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mega64 0:38ccae254a29 88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mega64 0:38ccae254a29 89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mega64 0:38ccae254a29 90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mega64 0:38ccae254a29 91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mega64 0:38ccae254a29 92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mega64 0:38ccae254a29 93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mega64 0:38ccae254a29 94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mega64 0:38ccae254a29 95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mega64 0:38ccae254a29 96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mega64 0:38ccae254a29 97 *
mega64 0:38ccae254a29 98 ******************************************************************************
mega64 0:38ccae254a29 99 */
mega64 0:38ccae254a29 100
mega64 0:38ccae254a29 101 /* Includes ------------------------------------------------------------------*/
mega64 0:38ccae254a29 102 #include "stm32f0xx_hal.h"
mega64 0:38ccae254a29 103
mega64 0:38ccae254a29 104 /** @addtogroup STM32F0xx_HAL_Driver
mega64 0:38ccae254a29 105 * @{
mega64 0:38ccae254a29 106 */
mega64 0:38ccae254a29 107
mega64 0:38ccae254a29 108 /** @defgroup CAN CAN HAL Module Driver
mega64 0:38ccae254a29 109 * @brief CAN driver modules
mega64 0:38ccae254a29 110 * @{
mega64 0:38ccae254a29 111 */
mega64 0:38ccae254a29 112
mega64 0:38ccae254a29 113 #ifdef HAL_CAN_MODULE_ENABLED
mega64 0:38ccae254a29 114
mega64 0:38ccae254a29 115 #if defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx)
mega64 0:38ccae254a29 116
mega64 0:38ccae254a29 117 /* Private typedef -----------------------------------------------------------*/
mega64 0:38ccae254a29 118 /* Private define ------------------------------------------------------------*/
mega64 0:38ccae254a29 119 /** @defgroup CAN_Private_Constants CAN Private Constants
mega64 0:38ccae254a29 120 * @{
mega64 0:38ccae254a29 121 */
mega64 0:38ccae254a29 122 #define HAL_CAN_DEFAULT_TIMEOUT 10
mega64 0:38ccae254a29 123 /**
mega64 0:38ccae254a29 124 * @}
mega64 0:38ccae254a29 125 */
mega64 0:38ccae254a29 126 /* Private macro -------------------------------------------------------------*/
mega64 0:38ccae254a29 127 /* Private variables ---------------------------------------------------------*/
mega64 0:38ccae254a29 128 /* Private function prototypes -----------------------------------------------*/
mega64 0:38ccae254a29 129 /** @defgroup CAN_Private_Functions CAN Private Functions
mega64 0:38ccae254a29 130 * @{
mega64 0:38ccae254a29 131 */
mega64 0:38ccae254a29 132 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
mega64 0:38ccae254a29 133 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
mega64 0:38ccae254a29 134 /**
mega64 0:38ccae254a29 135 * @}
mega64 0:38ccae254a29 136 */
mega64 0:38ccae254a29 137
mega64 0:38ccae254a29 138 /* Exported functions ---------------------------------------------------------*/
mega64 0:38ccae254a29 139
mega64 0:38ccae254a29 140 /** @defgroup CAN_Exported_Functions CAN Exported Functions
mega64 0:38ccae254a29 141 * @{
mega64 0:38ccae254a29 142 */
mega64 0:38ccae254a29 143
mega64 0:38ccae254a29 144 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
mega64 0:38ccae254a29 145 * @brief Initialization and Configuration functions
mega64 0:38ccae254a29 146 *
mega64 0:38ccae254a29 147 @verbatim
mega64 0:38ccae254a29 148 ==============================================================================
mega64 0:38ccae254a29 149 ##### Initialization and de-initialization functions #####
mega64 0:38ccae254a29 150 ==============================================================================
mega64 0:38ccae254a29 151 [..] This section provides functions allowing to:
mega64 0:38ccae254a29 152 (+) Initialize and configure the CAN.
mega64 0:38ccae254a29 153 (+) De-initialize the CAN.
mega64 0:38ccae254a29 154
mega64 0:38ccae254a29 155 @endverbatim
mega64 0:38ccae254a29 156 * @{
mega64 0:38ccae254a29 157 */
mega64 0:38ccae254a29 158
mega64 0:38ccae254a29 159 /**
mega64 0:38ccae254a29 160 * @brief Initializes the CAN peripheral according to the specified
mega64 0:38ccae254a29 161 * parameters in the CAN_InitStruct.
mega64 0:38ccae254a29 162 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 163 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 164 * @retval HAL status
mega64 0:38ccae254a29 165 */
mega64 0:38ccae254a29 166 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
mega64 0:38ccae254a29 167 {
mega64 0:38ccae254a29 168 uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
mega64 0:38ccae254a29 169 uint32_t tickstart = 0;
mega64 0:38ccae254a29 170
mega64 0:38ccae254a29 171 /* Check CAN handle */
mega64 0:38ccae254a29 172 if(hcan == NULL)
mega64 0:38ccae254a29 173 {
mega64 0:38ccae254a29 174 return HAL_ERROR;
mega64 0:38ccae254a29 175 }
mega64 0:38ccae254a29 176
mega64 0:38ccae254a29 177 /* Check the parameters */
mega64 0:38ccae254a29 178 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
mega64 0:38ccae254a29 179 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
mega64 0:38ccae254a29 180 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
mega64 0:38ccae254a29 181 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
mega64 0:38ccae254a29 182 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
mega64 0:38ccae254a29 183 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
mega64 0:38ccae254a29 184 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
mega64 0:38ccae254a29 185 assert_param(IS_CAN_MODE(hcan->Init.Mode));
mega64 0:38ccae254a29 186 assert_param(IS_CAN_SJW(hcan->Init.SJW));
mega64 0:38ccae254a29 187 assert_param(IS_CAN_BS1(hcan->Init.BS1));
mega64 0:38ccae254a29 188 assert_param(IS_CAN_BS2(hcan->Init.BS2));
mega64 0:38ccae254a29 189 assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
mega64 0:38ccae254a29 190
mega64 0:38ccae254a29 191 if(hcan->State == HAL_CAN_STATE_RESET)
mega64 0:38ccae254a29 192 {
mega64 0:38ccae254a29 193 /* Init the low level hardware */
mega64 0:38ccae254a29 194 HAL_CAN_MspInit(hcan);
mega64 0:38ccae254a29 195 }
mega64 0:38ccae254a29 196
mega64 0:38ccae254a29 197 /* Initialize the CAN state*/
mega64 0:38ccae254a29 198 hcan->State = HAL_CAN_STATE_BUSY;
mega64 0:38ccae254a29 199
mega64 0:38ccae254a29 200 /* Exit from sleep mode */
mega64 0:38ccae254a29 201 hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
mega64 0:38ccae254a29 202
mega64 0:38ccae254a29 203 /* Request initialisation */
mega64 0:38ccae254a29 204 hcan->Instance->MCR |= CAN_MCR_INRQ ;
mega64 0:38ccae254a29 205
mega64 0:38ccae254a29 206 /* Get tickstart */
mega64 0:38ccae254a29 207 tickstart = HAL_GetTick();
mega64 0:38ccae254a29 208
mega64 0:38ccae254a29 209 /* Wait the acknowledge */
mega64 0:38ccae254a29 210 while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
mega64 0:38ccae254a29 211 {
mega64 0:38ccae254a29 212 if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
mega64 0:38ccae254a29 213 {
mega64 0:38ccae254a29 214 hcan->State= HAL_CAN_STATE_TIMEOUT;
mega64 0:38ccae254a29 215 return HAL_TIMEOUT;
mega64 0:38ccae254a29 216 }
mega64 0:38ccae254a29 217 }
mega64 0:38ccae254a29 218
mega64 0:38ccae254a29 219 /* Check acknowledge */
mega64 0:38ccae254a29 220 if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
mega64 0:38ccae254a29 221 {
mega64 0:38ccae254a29 222 /* Set the time triggered communication mode */
mega64 0:38ccae254a29 223 if (hcan->Init.TTCM == ENABLE)
mega64 0:38ccae254a29 224 {
mega64 0:38ccae254a29 225 hcan->Instance->MCR |= CAN_MCR_TTCM;
mega64 0:38ccae254a29 226 }
mega64 0:38ccae254a29 227 else
mega64 0:38ccae254a29 228 {
mega64 0:38ccae254a29 229 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
mega64 0:38ccae254a29 230 }
mega64 0:38ccae254a29 231
mega64 0:38ccae254a29 232 /* Set the automatic bus-off management */
mega64 0:38ccae254a29 233 if (hcan->Init.ABOM == ENABLE)
mega64 0:38ccae254a29 234 {
mega64 0:38ccae254a29 235 hcan->Instance->MCR |= CAN_MCR_ABOM;
mega64 0:38ccae254a29 236 }
mega64 0:38ccae254a29 237 else
mega64 0:38ccae254a29 238 {
mega64 0:38ccae254a29 239 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
mega64 0:38ccae254a29 240 }
mega64 0:38ccae254a29 241
mega64 0:38ccae254a29 242 /* Set the automatic wake-up mode */
mega64 0:38ccae254a29 243 if (hcan->Init.AWUM == ENABLE)
mega64 0:38ccae254a29 244 {
mega64 0:38ccae254a29 245 hcan->Instance->MCR |= CAN_MCR_AWUM;
mega64 0:38ccae254a29 246 }
mega64 0:38ccae254a29 247 else
mega64 0:38ccae254a29 248 {
mega64 0:38ccae254a29 249 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
mega64 0:38ccae254a29 250 }
mega64 0:38ccae254a29 251
mega64 0:38ccae254a29 252 /* Set the no automatic retransmission */
mega64 0:38ccae254a29 253 if (hcan->Init.NART == ENABLE)
mega64 0:38ccae254a29 254 {
mega64 0:38ccae254a29 255 hcan->Instance->MCR |= CAN_MCR_NART;
mega64 0:38ccae254a29 256 }
mega64 0:38ccae254a29 257 else
mega64 0:38ccae254a29 258 {
mega64 0:38ccae254a29 259 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
mega64 0:38ccae254a29 260 }
mega64 0:38ccae254a29 261
mega64 0:38ccae254a29 262 /* Set the receive FIFO locked mode */
mega64 0:38ccae254a29 263 if (hcan->Init.RFLM == ENABLE)
mega64 0:38ccae254a29 264 {
mega64 0:38ccae254a29 265 hcan->Instance->MCR |= CAN_MCR_RFLM;
mega64 0:38ccae254a29 266 }
mega64 0:38ccae254a29 267 else
mega64 0:38ccae254a29 268 {
mega64 0:38ccae254a29 269 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
mega64 0:38ccae254a29 270 }
mega64 0:38ccae254a29 271
mega64 0:38ccae254a29 272 /* Set the transmit FIFO priority */
mega64 0:38ccae254a29 273 if (hcan->Init.TXFP == ENABLE)
mega64 0:38ccae254a29 274 {
mega64 0:38ccae254a29 275 hcan->Instance->MCR |= CAN_MCR_TXFP;
mega64 0:38ccae254a29 276 }
mega64 0:38ccae254a29 277 else
mega64 0:38ccae254a29 278 {
mega64 0:38ccae254a29 279 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
mega64 0:38ccae254a29 280 }
mega64 0:38ccae254a29 281
mega64 0:38ccae254a29 282 /* Set the bit timing register */
mega64 0:38ccae254a29 283 hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
mega64 0:38ccae254a29 284 ((uint32_t)hcan->Init.SJW) | \
mega64 0:38ccae254a29 285 ((uint32_t)hcan->Init.BS1) | \
mega64 0:38ccae254a29 286 ((uint32_t)hcan->Init.BS2) | \
mega64 0:38ccae254a29 287 ((uint32_t)hcan->Init.Prescaler - 1);
mega64 0:38ccae254a29 288
mega64 0:38ccae254a29 289 /* Request leave initialisation */
mega64 0:38ccae254a29 290 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
mega64 0:38ccae254a29 291
mega64 0:38ccae254a29 292 /* Get timeout */
mega64 0:38ccae254a29 293 tickstart = HAL_GetTick();
mega64 0:38ccae254a29 294
mega64 0:38ccae254a29 295 /* Wait the acknowledge */
mega64 0:38ccae254a29 296 while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
mega64 0:38ccae254a29 297 {
mega64 0:38ccae254a29 298 if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
mega64 0:38ccae254a29 299 {
mega64 0:38ccae254a29 300 hcan->State= HAL_CAN_STATE_TIMEOUT;
mega64 0:38ccae254a29 301 return HAL_TIMEOUT;
mega64 0:38ccae254a29 302 }
mega64 0:38ccae254a29 303 }
mega64 0:38ccae254a29 304
mega64 0:38ccae254a29 305 /* Check acknowledged */
mega64 0:38ccae254a29 306 if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
mega64 0:38ccae254a29 307 {
mega64 0:38ccae254a29 308 status = CAN_INITSTATUS_SUCCESS;
mega64 0:38ccae254a29 309 }
mega64 0:38ccae254a29 310 }
mega64 0:38ccae254a29 311
mega64 0:38ccae254a29 312 if(status == CAN_INITSTATUS_SUCCESS)
mega64 0:38ccae254a29 313 {
mega64 0:38ccae254a29 314 /* Set CAN error code to none */
mega64 0:38ccae254a29 315 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
mega64 0:38ccae254a29 316
mega64 0:38ccae254a29 317 /* Initialize the CAN state */
mega64 0:38ccae254a29 318 hcan->State = HAL_CAN_STATE_READY;
mega64 0:38ccae254a29 319
mega64 0:38ccae254a29 320 /* Return function status */
mega64 0:38ccae254a29 321 return HAL_OK;
mega64 0:38ccae254a29 322 }
mega64 0:38ccae254a29 323 else
mega64 0:38ccae254a29 324 {
mega64 0:38ccae254a29 325 /* Initialize the CAN state */
mega64 0:38ccae254a29 326 hcan->State = HAL_CAN_STATE_ERROR;
mega64 0:38ccae254a29 327
mega64 0:38ccae254a29 328 /* Return function status */
mega64 0:38ccae254a29 329 return HAL_ERROR;
mega64 0:38ccae254a29 330 }
mega64 0:38ccae254a29 331 }
mega64 0:38ccae254a29 332
mega64 0:38ccae254a29 333 /**
mega64 0:38ccae254a29 334 * @brief Configures the CAN reception filter according to the specified
mega64 0:38ccae254a29 335 * parameters in the CAN_FilterInitStruct.
mega64 0:38ccae254a29 336 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 337 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 338 * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
mega64 0:38ccae254a29 339 * contains the filter configuration information.
mega64 0:38ccae254a29 340 * @retval None
mega64 0:38ccae254a29 341 */
mega64 0:38ccae254a29 342 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
mega64 0:38ccae254a29 343 {
mega64 0:38ccae254a29 344 uint32_t filternbrbitpos = 0;
mega64 0:38ccae254a29 345
mega64 0:38ccae254a29 346 /* Check the parameters */
mega64 0:38ccae254a29 347 assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
mega64 0:38ccae254a29 348 assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
mega64 0:38ccae254a29 349 assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
mega64 0:38ccae254a29 350 assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
mega64 0:38ccae254a29 351 assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
mega64 0:38ccae254a29 352 assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
mega64 0:38ccae254a29 353
mega64 0:38ccae254a29 354 filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
mega64 0:38ccae254a29 355
mega64 0:38ccae254a29 356 /* Initialisation mode for the filter */
mega64 0:38ccae254a29 357 hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT;
mega64 0:38ccae254a29 358
mega64 0:38ccae254a29 359 /* Filter Deactivation */
mega64 0:38ccae254a29 360 hcan->Instance->FA1R &= ~(uint32_t)filternbrbitpos;
mega64 0:38ccae254a29 361
mega64 0:38ccae254a29 362 /* Filter Scale */
mega64 0:38ccae254a29 363 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
mega64 0:38ccae254a29 364 {
mega64 0:38ccae254a29 365 /* 16-bit scale for the filter */
mega64 0:38ccae254a29 366 hcan->Instance->FS1R &= ~(uint32_t)filternbrbitpos;
mega64 0:38ccae254a29 367
mega64 0:38ccae254a29 368 /* First 16-bit identifier and First 16-bit mask */
mega64 0:38ccae254a29 369 /* Or First 16-bit identifier and Second 16-bit identifier */
mega64 0:38ccae254a29 370 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
mega64 0:38ccae254a29 371 ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
mega64 0:38ccae254a29 372 (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
mega64 0:38ccae254a29 373
mega64 0:38ccae254a29 374 /* Second 16-bit identifier and Second 16-bit mask */
mega64 0:38ccae254a29 375 /* Or Third 16-bit identifier and Fourth 16-bit identifier */
mega64 0:38ccae254a29 376 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
mega64 0:38ccae254a29 377 ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
mega64 0:38ccae254a29 378 (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
mega64 0:38ccae254a29 379 }
mega64 0:38ccae254a29 380
mega64 0:38ccae254a29 381 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
mega64 0:38ccae254a29 382 {
mega64 0:38ccae254a29 383 /* 32-bit scale for the filter */
mega64 0:38ccae254a29 384 hcan->Instance->FS1R |= filternbrbitpos;
mega64 0:38ccae254a29 385 /* 32-bit identifier or First 32-bit identifier */
mega64 0:38ccae254a29 386 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
mega64 0:38ccae254a29 387 ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
mega64 0:38ccae254a29 388 (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
mega64 0:38ccae254a29 389 /* 32-bit mask or Second 32-bit identifier */
mega64 0:38ccae254a29 390 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
mega64 0:38ccae254a29 391 ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
mega64 0:38ccae254a29 392 (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
mega64 0:38ccae254a29 393 }
mega64 0:38ccae254a29 394
mega64 0:38ccae254a29 395 /* Filter Mode */
mega64 0:38ccae254a29 396 if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
mega64 0:38ccae254a29 397 {
mega64 0:38ccae254a29 398 /*Id/Mask mode for the filter*/
mega64 0:38ccae254a29 399 hcan->Instance->FM1R &= ~(uint32_t)filternbrbitpos;
mega64 0:38ccae254a29 400 }
mega64 0:38ccae254a29 401 else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
mega64 0:38ccae254a29 402 {
mega64 0:38ccae254a29 403 /*Identifier list mode for the filter*/
mega64 0:38ccae254a29 404 hcan->Instance->FM1R |= (uint32_t)filternbrbitpos;
mega64 0:38ccae254a29 405 }
mega64 0:38ccae254a29 406
mega64 0:38ccae254a29 407 /* Filter FIFO assignment */
mega64 0:38ccae254a29 408 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
mega64 0:38ccae254a29 409 {
mega64 0:38ccae254a29 410 /* FIFO 0 assignation for the filter */
mega64 0:38ccae254a29 411 hcan->Instance->FFA1R &= ~(uint32_t)filternbrbitpos;
mega64 0:38ccae254a29 412 }
mega64 0:38ccae254a29 413
mega64 0:38ccae254a29 414 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
mega64 0:38ccae254a29 415 {
mega64 0:38ccae254a29 416 /* FIFO 1 assignation for the filter */
mega64 0:38ccae254a29 417 hcan->Instance->FFA1R |= (uint32_t)filternbrbitpos;
mega64 0:38ccae254a29 418 }
mega64 0:38ccae254a29 419
mega64 0:38ccae254a29 420 /* Filter activation */
mega64 0:38ccae254a29 421 if (sFilterConfig->FilterActivation == ENABLE)
mega64 0:38ccae254a29 422 {
mega64 0:38ccae254a29 423 hcan->Instance->FA1R |= filternbrbitpos;
mega64 0:38ccae254a29 424 }
mega64 0:38ccae254a29 425
mega64 0:38ccae254a29 426 /* Leave the initialisation mode for the filter */
mega64 0:38ccae254a29 427 hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_FINIT);
mega64 0:38ccae254a29 428
mega64 0:38ccae254a29 429 /* Return function status */
mega64 0:38ccae254a29 430 return HAL_OK;
mega64 0:38ccae254a29 431 }
mega64 0:38ccae254a29 432
mega64 0:38ccae254a29 433 /**
mega64 0:38ccae254a29 434 * @brief Deinitializes the CANx peripheral registers to their default reset values.
mega64 0:38ccae254a29 435 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 436 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 437 * @retval HAL status
mega64 0:38ccae254a29 438 */
mega64 0:38ccae254a29 439 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
mega64 0:38ccae254a29 440 {
mega64 0:38ccae254a29 441 /* Check CAN handle */
mega64 0:38ccae254a29 442 if(hcan == NULL)
mega64 0:38ccae254a29 443 {
mega64 0:38ccae254a29 444 return HAL_ERROR;
mega64 0:38ccae254a29 445 }
mega64 0:38ccae254a29 446
mega64 0:38ccae254a29 447 /* Check the parameters */
mega64 0:38ccae254a29 448 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
mega64 0:38ccae254a29 449
mega64 0:38ccae254a29 450 /* Change CAN state */
mega64 0:38ccae254a29 451 hcan->State = HAL_CAN_STATE_BUSY;
mega64 0:38ccae254a29 452
mega64 0:38ccae254a29 453 /* DeInit the low level hardware */
mega64 0:38ccae254a29 454 HAL_CAN_MspDeInit(hcan);
mega64 0:38ccae254a29 455
mega64 0:38ccae254a29 456 /* Change CAN state */
mega64 0:38ccae254a29 457 hcan->State = HAL_CAN_STATE_RESET;
mega64 0:38ccae254a29 458
mega64 0:38ccae254a29 459 /* Release Lock */
mega64 0:38ccae254a29 460 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 461
mega64 0:38ccae254a29 462 /* Return function status */
mega64 0:38ccae254a29 463 return HAL_OK;
mega64 0:38ccae254a29 464 }
mega64 0:38ccae254a29 465
mega64 0:38ccae254a29 466 /**
mega64 0:38ccae254a29 467 * @brief Initializes the CAN MSP.
mega64 0:38ccae254a29 468 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 469 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 470 * @retval None
mega64 0:38ccae254a29 471 */
mega64 0:38ccae254a29 472 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
mega64 0:38ccae254a29 473 {
mega64 0:38ccae254a29 474 /* NOTE : This function Should not be modified, when the callback is needed,
mega64 0:38ccae254a29 475 the HAL_CAN_MspInit could be implemented in the user file
mega64 0:38ccae254a29 476 */
mega64 0:38ccae254a29 477 }
mega64 0:38ccae254a29 478
mega64 0:38ccae254a29 479 /**
mega64 0:38ccae254a29 480 * @brief DeInitializes the CAN MSP.
mega64 0:38ccae254a29 481 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 482 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 483 * @retval None
mega64 0:38ccae254a29 484 */
mega64 0:38ccae254a29 485 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
mega64 0:38ccae254a29 486 {
mega64 0:38ccae254a29 487 /* NOTE : This function Should not be modified, when the callback is needed,
mega64 0:38ccae254a29 488 the HAL_CAN_MspDeInit could be implemented in the user file
mega64 0:38ccae254a29 489 */
mega64 0:38ccae254a29 490 }
mega64 0:38ccae254a29 491
mega64 0:38ccae254a29 492 /**
mega64 0:38ccae254a29 493 * @}
mega64 0:38ccae254a29 494 */
mega64 0:38ccae254a29 495
mega64 0:38ccae254a29 496 /** @defgroup CAN_Exported_Functions_Group2 I/O operation functions
mega64 0:38ccae254a29 497 * @brief I/O operation functions
mega64 0:38ccae254a29 498 *
mega64 0:38ccae254a29 499 @verbatim
mega64 0:38ccae254a29 500 ==============================================================================
mega64 0:38ccae254a29 501 ##### IO operation functions #####
mega64 0:38ccae254a29 502 ==============================================================================
mega64 0:38ccae254a29 503 [..] This section provides functions allowing to:
mega64 0:38ccae254a29 504 (+) Transmit a CAN frame message.
mega64 0:38ccae254a29 505 (+) Receive a CAN frame message.
mega64 0:38ccae254a29 506 (+) Enter CAN peripheral in sleep mode.
mega64 0:38ccae254a29 507 (+) Wake up the CAN peripheral from sleep mode.
mega64 0:38ccae254a29 508
mega64 0:38ccae254a29 509 @endverbatim
mega64 0:38ccae254a29 510 * @{
mega64 0:38ccae254a29 511 */
mega64 0:38ccae254a29 512
mega64 0:38ccae254a29 513 /**
mega64 0:38ccae254a29 514 * @brief Initiates and transmits a CAN frame message.
mega64 0:38ccae254a29 515 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 516 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 517 * @param Timeout: Timeout duration.
mega64 0:38ccae254a29 518 * @retval HAL status
mega64 0:38ccae254a29 519 */
mega64 0:38ccae254a29 520 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
mega64 0:38ccae254a29 521 {
mega64 0:38ccae254a29 522 uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
mega64 0:38ccae254a29 523 uint32_t tickstart = 0;
mega64 0:38ccae254a29 524
mega64 0:38ccae254a29 525 /* Check the parameters */
mega64 0:38ccae254a29 526 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
mega64 0:38ccae254a29 527 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
mega64 0:38ccae254a29 528 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
mega64 0:38ccae254a29 529
mega64 0:38ccae254a29 530 /* Process locked */
mega64 0:38ccae254a29 531 __HAL_LOCK(hcan);
mega64 0:38ccae254a29 532
mega64 0:38ccae254a29 533 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
mega64 0:38ccae254a29 534 {
mega64 0:38ccae254a29 535 /* Change CAN state */
mega64 0:38ccae254a29 536 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
mega64 0:38ccae254a29 537 }
mega64 0:38ccae254a29 538 else
mega64 0:38ccae254a29 539 {
mega64 0:38ccae254a29 540 /* Change CAN state */
mega64 0:38ccae254a29 541 hcan->State = HAL_CAN_STATE_BUSY_TX;
mega64 0:38ccae254a29 542 }
mega64 0:38ccae254a29 543
mega64 0:38ccae254a29 544 /* Select one empty transmit mailbox */
mega64 0:38ccae254a29 545 if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
mega64 0:38ccae254a29 546 {
mega64 0:38ccae254a29 547 transmitmailbox = 0;
mega64 0:38ccae254a29 548 }
mega64 0:38ccae254a29 549 else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
mega64 0:38ccae254a29 550 {
mega64 0:38ccae254a29 551 transmitmailbox = 1;
mega64 0:38ccae254a29 552 }
mega64 0:38ccae254a29 553 else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
mega64 0:38ccae254a29 554 {
mega64 0:38ccae254a29 555 transmitmailbox = 2;
mega64 0:38ccae254a29 556 }
mega64 0:38ccae254a29 557
mega64 0:38ccae254a29 558 if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
mega64 0:38ccae254a29 559 {
mega64 0:38ccae254a29 560 /* Set up the Id */
mega64 0:38ccae254a29 561 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
mega64 0:38ccae254a29 562 if (hcan->pTxMsg->IDE == CAN_ID_STD)
mega64 0:38ccae254a29 563 {
mega64 0:38ccae254a29 564 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
mega64 0:38ccae254a29 565 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
mega64 0:38ccae254a29 566 hcan->pTxMsg->RTR);
mega64 0:38ccae254a29 567 }
mega64 0:38ccae254a29 568 else
mega64 0:38ccae254a29 569 {
mega64 0:38ccae254a29 570 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
mega64 0:38ccae254a29 571 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
mega64 0:38ccae254a29 572 hcan->pTxMsg->IDE | \
mega64 0:38ccae254a29 573 hcan->pTxMsg->RTR);
mega64 0:38ccae254a29 574 }
mega64 0:38ccae254a29 575
mega64 0:38ccae254a29 576 /* Set up the DLC */
mega64 0:38ccae254a29 577 hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
mega64 0:38ccae254a29 578 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
mega64 0:38ccae254a29 579 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
mega64 0:38ccae254a29 580
mega64 0:38ccae254a29 581 /* Set up the data field */
mega64 0:38ccae254a29 582 hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
mega64 0:38ccae254a29 583 ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
mega64 0:38ccae254a29 584 ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
mega64 0:38ccae254a29 585 ((uint32_t)hcan->pTxMsg->Data[0]));
mega64 0:38ccae254a29 586 hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
mega64 0:38ccae254a29 587 ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
mega64 0:38ccae254a29 588 ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
mega64 0:38ccae254a29 589 ((uint32_t)hcan->pTxMsg->Data[4]));
mega64 0:38ccae254a29 590 /* Request transmission */
mega64 0:38ccae254a29 591 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
mega64 0:38ccae254a29 592
mega64 0:38ccae254a29 593 /* Get timeout */
mega64 0:38ccae254a29 594 tickstart = HAL_GetTick();
mega64 0:38ccae254a29 595
mega64 0:38ccae254a29 596 /* Check End of transmission flag */
mega64 0:38ccae254a29 597 while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
mega64 0:38ccae254a29 598 {
mega64 0:38ccae254a29 599 /* Check for the Timeout */
mega64 0:38ccae254a29 600 if(Timeout != HAL_MAX_DELAY)
mega64 0:38ccae254a29 601 {
mega64 0:38ccae254a29 602 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
mega64 0:38ccae254a29 603 {
mega64 0:38ccae254a29 604 hcan->State = HAL_CAN_STATE_TIMEOUT;
mega64 0:38ccae254a29 605 /* Process unlocked */
mega64 0:38ccae254a29 606 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 607 return HAL_TIMEOUT;
mega64 0:38ccae254a29 608 }
mega64 0:38ccae254a29 609 }
mega64 0:38ccae254a29 610 }
mega64 0:38ccae254a29 611 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
mega64 0:38ccae254a29 612 {
mega64 0:38ccae254a29 613 /* Change CAN state */
mega64 0:38ccae254a29 614 hcan->State = HAL_CAN_STATE_BUSY_RX;
mega64 0:38ccae254a29 615 }
mega64 0:38ccae254a29 616 else
mega64 0:38ccae254a29 617 {
mega64 0:38ccae254a29 618 /* Change CAN state */
mega64 0:38ccae254a29 619 hcan->State = HAL_CAN_STATE_READY;
mega64 0:38ccae254a29 620 }
mega64 0:38ccae254a29 621
mega64 0:38ccae254a29 622 /* Process unlocked */
mega64 0:38ccae254a29 623 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 624
mega64 0:38ccae254a29 625 /* Return function status */
mega64 0:38ccae254a29 626 return HAL_OK;
mega64 0:38ccae254a29 627 }
mega64 0:38ccae254a29 628 else
mega64 0:38ccae254a29 629 {
mega64 0:38ccae254a29 630 /* Change CAN state */
mega64 0:38ccae254a29 631 hcan->State = HAL_CAN_STATE_ERROR;
mega64 0:38ccae254a29 632
mega64 0:38ccae254a29 633 /* Process unlocked */
mega64 0:38ccae254a29 634 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 635
mega64 0:38ccae254a29 636 /* Return function status */
mega64 0:38ccae254a29 637 return HAL_ERROR;
mega64 0:38ccae254a29 638 }
mega64 0:38ccae254a29 639 }
mega64 0:38ccae254a29 640
mega64 0:38ccae254a29 641 /**
mega64 0:38ccae254a29 642 * @brief Initiates and transmits a CAN frame message.
mega64 0:38ccae254a29 643 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 644 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 645 * @retval HAL status
mega64 0:38ccae254a29 646 */
mega64 0:38ccae254a29 647 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
mega64 0:38ccae254a29 648 {
mega64 0:38ccae254a29 649 uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
mega64 0:38ccae254a29 650
mega64 0:38ccae254a29 651 /* Check the parameters */
mega64 0:38ccae254a29 652 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
mega64 0:38ccae254a29 653 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
mega64 0:38ccae254a29 654 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
mega64 0:38ccae254a29 655
mega64 0:38ccae254a29 656 if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX))
mega64 0:38ccae254a29 657 {
mega64 0:38ccae254a29 658 /* Process Locked */
mega64 0:38ccae254a29 659 __HAL_LOCK(hcan);
mega64 0:38ccae254a29 660
mega64 0:38ccae254a29 661 /* Select one empty transmit mailbox */
mega64 0:38ccae254a29 662 if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
mega64 0:38ccae254a29 663 {
mega64 0:38ccae254a29 664 transmitmailbox = 0;
mega64 0:38ccae254a29 665 }
mega64 0:38ccae254a29 666 else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
mega64 0:38ccae254a29 667 {
mega64 0:38ccae254a29 668 transmitmailbox = 1;
mega64 0:38ccae254a29 669 }
mega64 0:38ccae254a29 670 else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
mega64 0:38ccae254a29 671 {
mega64 0:38ccae254a29 672 transmitmailbox = 2;
mega64 0:38ccae254a29 673 }
mega64 0:38ccae254a29 674
mega64 0:38ccae254a29 675 if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
mega64 0:38ccae254a29 676 {
mega64 0:38ccae254a29 677 /* Set up the Id */
mega64 0:38ccae254a29 678 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
mega64 0:38ccae254a29 679 if(hcan->pTxMsg->IDE == CAN_ID_STD)
mega64 0:38ccae254a29 680 {
mega64 0:38ccae254a29 681 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
mega64 0:38ccae254a29 682 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
mega64 0:38ccae254a29 683 hcan->pTxMsg->RTR);
mega64 0:38ccae254a29 684 }
mega64 0:38ccae254a29 685 else
mega64 0:38ccae254a29 686 {
mega64 0:38ccae254a29 687 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
mega64 0:38ccae254a29 688 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
mega64 0:38ccae254a29 689 hcan->pTxMsg->IDE | \
mega64 0:38ccae254a29 690 hcan->pTxMsg->RTR);
mega64 0:38ccae254a29 691 }
mega64 0:38ccae254a29 692
mega64 0:38ccae254a29 693 /* Set up the DLC */
mega64 0:38ccae254a29 694 hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
mega64 0:38ccae254a29 695 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
mega64 0:38ccae254a29 696 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
mega64 0:38ccae254a29 697
mega64 0:38ccae254a29 698 /* Set up the data field */
mega64 0:38ccae254a29 699 hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
mega64 0:38ccae254a29 700 ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
mega64 0:38ccae254a29 701 ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
mega64 0:38ccae254a29 702 ((uint32_t)hcan->pTxMsg->Data[0]));
mega64 0:38ccae254a29 703 hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
mega64 0:38ccae254a29 704 ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
mega64 0:38ccae254a29 705 ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
mega64 0:38ccae254a29 706 ((uint32_t)hcan->pTxMsg->Data[4]));
mega64 0:38ccae254a29 707
mega64 0:38ccae254a29 708 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
mega64 0:38ccae254a29 709 {
mega64 0:38ccae254a29 710 /* Change CAN state */
mega64 0:38ccae254a29 711 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
mega64 0:38ccae254a29 712 }
mega64 0:38ccae254a29 713 else
mega64 0:38ccae254a29 714 {
mega64 0:38ccae254a29 715 /* Change CAN state */
mega64 0:38ccae254a29 716 hcan->State = HAL_CAN_STATE_BUSY_TX;
mega64 0:38ccae254a29 717 }
mega64 0:38ccae254a29 718
mega64 0:38ccae254a29 719 /* Set CAN error code to none */
mega64 0:38ccae254a29 720 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
mega64 0:38ccae254a29 721
mega64 0:38ccae254a29 722 /* Process Unlocked */
mega64 0:38ccae254a29 723 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 724
mega64 0:38ccae254a29 725 /* Enable Error warning Interrupt */
mega64 0:38ccae254a29 726 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
mega64 0:38ccae254a29 727
mega64 0:38ccae254a29 728 /* Enable Error passive Interrupt */
mega64 0:38ccae254a29 729 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
mega64 0:38ccae254a29 730
mega64 0:38ccae254a29 731 /* Enable Bus-off Interrupt */
mega64 0:38ccae254a29 732 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
mega64 0:38ccae254a29 733
mega64 0:38ccae254a29 734 /* Enable Last error code Interrupt */
mega64 0:38ccae254a29 735 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
mega64 0:38ccae254a29 736
mega64 0:38ccae254a29 737 /* Enable Error Interrupt */
mega64 0:38ccae254a29 738 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
mega64 0:38ccae254a29 739
mega64 0:38ccae254a29 740 /* Enable Transmit mailbox empty Interrupt */
mega64 0:38ccae254a29 741 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
mega64 0:38ccae254a29 742
mega64 0:38ccae254a29 743 /* Request transmission */
mega64 0:38ccae254a29 744 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
mega64 0:38ccae254a29 745 }
mega64 0:38ccae254a29 746 }
mega64 0:38ccae254a29 747 else
mega64 0:38ccae254a29 748 {
mega64 0:38ccae254a29 749 return HAL_BUSY;
mega64 0:38ccae254a29 750 }
mega64 0:38ccae254a29 751
mega64 0:38ccae254a29 752 return HAL_OK;
mega64 0:38ccae254a29 753 }
mega64 0:38ccae254a29 754
mega64 0:38ccae254a29 755 /**
mega64 0:38ccae254a29 756 * @brief Receives a correct CAN frame.
mega64 0:38ccae254a29 757 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 758 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 759 * @param FIFONumber: FIFO number.
mega64 0:38ccae254a29 760 * @param Timeout: Timeout duration.
mega64 0:38ccae254a29 761 * @retval HAL status
mega64 0:38ccae254a29 762 * @retval None
mega64 0:38ccae254a29 763 */
mega64 0:38ccae254a29 764 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
mega64 0:38ccae254a29 765 {
mega64 0:38ccae254a29 766 uint32_t tickstart = 0;
mega64 0:38ccae254a29 767
mega64 0:38ccae254a29 768 /* Check the parameters */
mega64 0:38ccae254a29 769 assert_param(IS_CAN_FIFO(FIFONumber));
mega64 0:38ccae254a29 770
mega64 0:38ccae254a29 771 /* Process locked */
mega64 0:38ccae254a29 772 __HAL_LOCK(hcan);
mega64 0:38ccae254a29 773
mega64 0:38ccae254a29 774 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
mega64 0:38ccae254a29 775 {
mega64 0:38ccae254a29 776 /* Change CAN state */
mega64 0:38ccae254a29 777 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
mega64 0:38ccae254a29 778 }
mega64 0:38ccae254a29 779 else
mega64 0:38ccae254a29 780 {
mega64 0:38ccae254a29 781 /* Change CAN state */
mega64 0:38ccae254a29 782 hcan->State = HAL_CAN_STATE_BUSY_RX;
mega64 0:38ccae254a29 783 }
mega64 0:38ccae254a29 784
mega64 0:38ccae254a29 785 /* Get timeout */
mega64 0:38ccae254a29 786 tickstart = HAL_GetTick();
mega64 0:38ccae254a29 787
mega64 0:38ccae254a29 788 /* Check pending message */
mega64 0:38ccae254a29 789 while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
mega64 0:38ccae254a29 790 {
mega64 0:38ccae254a29 791 /* Check for the Timeout */
mega64 0:38ccae254a29 792 if(Timeout != HAL_MAX_DELAY)
mega64 0:38ccae254a29 793 {
mega64 0:38ccae254a29 794 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
mega64 0:38ccae254a29 795 {
mega64 0:38ccae254a29 796 hcan->State = HAL_CAN_STATE_TIMEOUT;
mega64 0:38ccae254a29 797 /* Process unlocked */
mega64 0:38ccae254a29 798 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 799 return HAL_TIMEOUT;
mega64 0:38ccae254a29 800 }
mega64 0:38ccae254a29 801 }
mega64 0:38ccae254a29 802 }
mega64 0:38ccae254a29 803
mega64 0:38ccae254a29 804 /* Get the Id */
mega64 0:38ccae254a29 805 hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
mega64 0:38ccae254a29 806 if (hcan->pRxMsg->IDE == CAN_ID_STD)
mega64 0:38ccae254a29 807 {
mega64 0:38ccae254a29 808 hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
mega64 0:38ccae254a29 809 }
mega64 0:38ccae254a29 810 else
mega64 0:38ccae254a29 811 {
mega64 0:38ccae254a29 812 hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
mega64 0:38ccae254a29 813 }
mega64 0:38ccae254a29 814
mega64 0:38ccae254a29 815 hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
mega64 0:38ccae254a29 816 /* Get the DLC */
mega64 0:38ccae254a29 817 hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
mega64 0:38ccae254a29 818 /* Get the FMI */
mega64 0:38ccae254a29 819 hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
mega64 0:38ccae254a29 820 /* Get the data field */
mega64 0:38ccae254a29 821 hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
mega64 0:38ccae254a29 822 hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
mega64 0:38ccae254a29 823 hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
mega64 0:38ccae254a29 824 hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
mega64 0:38ccae254a29 825 hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
mega64 0:38ccae254a29 826 hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
mega64 0:38ccae254a29 827 hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
mega64 0:38ccae254a29 828 hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
mega64 0:38ccae254a29 829
mega64 0:38ccae254a29 830 /* Release the FIFO */
mega64 0:38ccae254a29 831 if(FIFONumber == CAN_FIFO0)
mega64 0:38ccae254a29 832 {
mega64 0:38ccae254a29 833 /* Release FIFO0 */
mega64 0:38ccae254a29 834 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
mega64 0:38ccae254a29 835 }
mega64 0:38ccae254a29 836 else /* FIFONumber == CAN_FIFO1 */
mega64 0:38ccae254a29 837 {
mega64 0:38ccae254a29 838 /* Release FIFO1 */
mega64 0:38ccae254a29 839 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
mega64 0:38ccae254a29 840 }
mega64 0:38ccae254a29 841
mega64 0:38ccae254a29 842 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
mega64 0:38ccae254a29 843 {
mega64 0:38ccae254a29 844 /* Change CAN state */
mega64 0:38ccae254a29 845 hcan->State = HAL_CAN_STATE_BUSY_TX;
mega64 0:38ccae254a29 846 }
mega64 0:38ccae254a29 847 else
mega64 0:38ccae254a29 848 {
mega64 0:38ccae254a29 849 /* Change CAN state */
mega64 0:38ccae254a29 850 hcan->State = HAL_CAN_STATE_READY;
mega64 0:38ccae254a29 851 }
mega64 0:38ccae254a29 852
mega64 0:38ccae254a29 853 /* Process unlocked */
mega64 0:38ccae254a29 854 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 855
mega64 0:38ccae254a29 856 /* Return function status */
mega64 0:38ccae254a29 857 return HAL_OK;
mega64 0:38ccae254a29 858 }
mega64 0:38ccae254a29 859
mega64 0:38ccae254a29 860 /**
mega64 0:38ccae254a29 861 * @brief Receives a correct CAN frame.
mega64 0:38ccae254a29 862 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 863 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 864 * @param FIFONumber: FIFO number.
mega64 0:38ccae254a29 865 * @retval HAL status
mega64 0:38ccae254a29 866 * @retval None
mega64 0:38ccae254a29 867 */
mega64 0:38ccae254a29 868 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
mega64 0:38ccae254a29 869 {
mega64 0:38ccae254a29 870 /* Check the parameters */
mega64 0:38ccae254a29 871 assert_param(IS_CAN_FIFO(FIFONumber));
mega64 0:38ccae254a29 872
mega64 0:38ccae254a29 873 if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX))
mega64 0:38ccae254a29 874 {
mega64 0:38ccae254a29 875 /* Process locked */
mega64 0:38ccae254a29 876 __HAL_LOCK(hcan);
mega64 0:38ccae254a29 877
mega64 0:38ccae254a29 878 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
mega64 0:38ccae254a29 879 {
mega64 0:38ccae254a29 880 /* Change CAN state */
mega64 0:38ccae254a29 881 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
mega64 0:38ccae254a29 882 }
mega64 0:38ccae254a29 883 else
mega64 0:38ccae254a29 884 {
mega64 0:38ccae254a29 885 /* Change CAN state */
mega64 0:38ccae254a29 886 hcan->State = HAL_CAN_STATE_BUSY_RX;
mega64 0:38ccae254a29 887 }
mega64 0:38ccae254a29 888
mega64 0:38ccae254a29 889 /* Set CAN error code to none */
mega64 0:38ccae254a29 890 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
mega64 0:38ccae254a29 891
mega64 0:38ccae254a29 892 /* Enable Error warning Interrupt */
mega64 0:38ccae254a29 893 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
mega64 0:38ccae254a29 894
mega64 0:38ccae254a29 895 /* Enable Error passive Interrupt */
mega64 0:38ccae254a29 896 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
mega64 0:38ccae254a29 897
mega64 0:38ccae254a29 898 /* Enable Bus-off Interrupt */
mega64 0:38ccae254a29 899 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
mega64 0:38ccae254a29 900
mega64 0:38ccae254a29 901 /* Enable Last error code Interrupt */
mega64 0:38ccae254a29 902 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
mega64 0:38ccae254a29 903
mega64 0:38ccae254a29 904 /* Enable Error Interrupt */
mega64 0:38ccae254a29 905 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
mega64 0:38ccae254a29 906
mega64 0:38ccae254a29 907 /* Process unlocked */
mega64 0:38ccae254a29 908 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 909
mega64 0:38ccae254a29 910 if(FIFONumber == CAN_FIFO0)
mega64 0:38ccae254a29 911 {
mega64 0:38ccae254a29 912 /* Enable FIFO 0 message pending Interrupt */
mega64 0:38ccae254a29 913 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
mega64 0:38ccae254a29 914 }
mega64 0:38ccae254a29 915 else
mega64 0:38ccae254a29 916 {
mega64 0:38ccae254a29 917 /* Enable FIFO 1 message pending Interrupt */
mega64 0:38ccae254a29 918 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
mega64 0:38ccae254a29 919 }
mega64 0:38ccae254a29 920
mega64 0:38ccae254a29 921 }
mega64 0:38ccae254a29 922 else
mega64 0:38ccae254a29 923 {
mega64 0:38ccae254a29 924 return HAL_BUSY;
mega64 0:38ccae254a29 925 }
mega64 0:38ccae254a29 926
mega64 0:38ccae254a29 927 /* Return function status */
mega64 0:38ccae254a29 928 return HAL_OK;
mega64 0:38ccae254a29 929 }
mega64 0:38ccae254a29 930
mega64 0:38ccae254a29 931 /**
mega64 0:38ccae254a29 932 * @brief Enters the Sleep (low power) mode.
mega64 0:38ccae254a29 933 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 934 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 935 * @retval HAL status.
mega64 0:38ccae254a29 936 */
mega64 0:38ccae254a29 937 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
mega64 0:38ccae254a29 938 {
mega64 0:38ccae254a29 939 uint32_t tickstart = 0;
mega64 0:38ccae254a29 940
mega64 0:38ccae254a29 941 /* Process locked */
mega64 0:38ccae254a29 942 __HAL_LOCK(hcan);
mega64 0:38ccae254a29 943
mega64 0:38ccae254a29 944 /* Change CAN state */
mega64 0:38ccae254a29 945 hcan->State = HAL_CAN_STATE_BUSY;
mega64 0:38ccae254a29 946
mega64 0:38ccae254a29 947 /* Request Sleep mode */
mega64 0:38ccae254a29 948 hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
mega64 0:38ccae254a29 949
mega64 0:38ccae254a29 950 /* Sleep mode status */
mega64 0:38ccae254a29 951 if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
mega64 0:38ccae254a29 952 {
mega64 0:38ccae254a29 953 /* Process unlocked */
mega64 0:38ccae254a29 954 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 955
mega64 0:38ccae254a29 956 /* Return function status */
mega64 0:38ccae254a29 957 return HAL_ERROR;
mega64 0:38ccae254a29 958 }
mega64 0:38ccae254a29 959
mega64 0:38ccae254a29 960 /* Get timeout */
mega64 0:38ccae254a29 961 tickstart = HAL_GetTick();
mega64 0:38ccae254a29 962
mega64 0:38ccae254a29 963 /* Wait the acknowledge */
mega64 0:38ccae254a29 964 while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
mega64 0:38ccae254a29 965 {
mega64 0:38ccae254a29 966 if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
mega64 0:38ccae254a29 967 {
mega64 0:38ccae254a29 968 hcan->State = HAL_CAN_STATE_TIMEOUT;
mega64 0:38ccae254a29 969 /* Process unlocked */
mega64 0:38ccae254a29 970 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 971 return HAL_TIMEOUT;
mega64 0:38ccae254a29 972 }
mega64 0:38ccae254a29 973 }
mega64 0:38ccae254a29 974
mega64 0:38ccae254a29 975 /* Change CAN state */
mega64 0:38ccae254a29 976 hcan->State = HAL_CAN_STATE_READY;
mega64 0:38ccae254a29 977
mega64 0:38ccae254a29 978 /* Process unlocked */
mega64 0:38ccae254a29 979 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 980
mega64 0:38ccae254a29 981 /* Return function status */
mega64 0:38ccae254a29 982 return HAL_OK;
mega64 0:38ccae254a29 983 }
mega64 0:38ccae254a29 984
mega64 0:38ccae254a29 985 /**
mega64 0:38ccae254a29 986 * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
mega64 0:38ccae254a29 987 * is in the normal mode.
mega64 0:38ccae254a29 988 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 989 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 990 * @retval HAL status.
mega64 0:38ccae254a29 991 */
mega64 0:38ccae254a29 992 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
mega64 0:38ccae254a29 993 {
mega64 0:38ccae254a29 994 uint32_t tickstart = 0;
mega64 0:38ccae254a29 995
mega64 0:38ccae254a29 996 /* Process locked */
mega64 0:38ccae254a29 997 __HAL_LOCK(hcan);
mega64 0:38ccae254a29 998
mega64 0:38ccae254a29 999 /* Change CAN state */
mega64 0:38ccae254a29 1000 hcan->State = HAL_CAN_STATE_BUSY;
mega64 0:38ccae254a29 1001
mega64 0:38ccae254a29 1002 /* Wake up request */
mega64 0:38ccae254a29 1003 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
mega64 0:38ccae254a29 1004
mega64 0:38ccae254a29 1005 /* Get timeout */
mega64 0:38ccae254a29 1006 tickstart = HAL_GetTick();
mega64 0:38ccae254a29 1007
mega64 0:38ccae254a29 1008 /* Sleep mode status */
mega64 0:38ccae254a29 1009 while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
mega64 0:38ccae254a29 1010 {
mega64 0:38ccae254a29 1011 if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
mega64 0:38ccae254a29 1012 {
mega64 0:38ccae254a29 1013 hcan->State= HAL_CAN_STATE_TIMEOUT;
mega64 0:38ccae254a29 1014 /* Process unlocked */
mega64 0:38ccae254a29 1015 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 1016 return HAL_TIMEOUT;
mega64 0:38ccae254a29 1017 }
mega64 0:38ccae254a29 1018 }
mega64 0:38ccae254a29 1019 if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
mega64 0:38ccae254a29 1020 {
mega64 0:38ccae254a29 1021 /* Process unlocked */
mega64 0:38ccae254a29 1022 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 1023
mega64 0:38ccae254a29 1024 /* Return function status */
mega64 0:38ccae254a29 1025 return HAL_ERROR;
mega64 0:38ccae254a29 1026 }
mega64 0:38ccae254a29 1027
mega64 0:38ccae254a29 1028 /* Change CAN state */
mega64 0:38ccae254a29 1029 hcan->State = HAL_CAN_STATE_READY;
mega64 0:38ccae254a29 1030
mega64 0:38ccae254a29 1031 /* Process unlocked */
mega64 0:38ccae254a29 1032 __HAL_UNLOCK(hcan);
mega64 0:38ccae254a29 1033
mega64 0:38ccae254a29 1034 /* Return function status */
mega64 0:38ccae254a29 1035 return HAL_OK;
mega64 0:38ccae254a29 1036 }
mega64 0:38ccae254a29 1037
mega64 0:38ccae254a29 1038 /**
mega64 0:38ccae254a29 1039 * @brief Handles CAN interrupt request
mega64 0:38ccae254a29 1040 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 1041 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 1042 * @retval None
mega64 0:38ccae254a29 1043 */
mega64 0:38ccae254a29 1044 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
mega64 0:38ccae254a29 1045 {
mega64 0:38ccae254a29 1046 /* Check End of transmission flag */
mega64 0:38ccae254a29 1047 if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
mega64 0:38ccae254a29 1048 {
mega64 0:38ccae254a29 1049 if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
mega64 0:38ccae254a29 1050 (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
mega64 0:38ccae254a29 1051 (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
mega64 0:38ccae254a29 1052 {
mega64 0:38ccae254a29 1053 /* Call transmit function */
mega64 0:38ccae254a29 1054 CAN_Transmit_IT(hcan);
mega64 0:38ccae254a29 1055 }
mega64 0:38ccae254a29 1056 }
mega64 0:38ccae254a29 1057
mega64 0:38ccae254a29 1058 /* Check End of reception flag for FIFO0 */
mega64 0:38ccae254a29 1059 if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
mega64 0:38ccae254a29 1060 (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0))
mega64 0:38ccae254a29 1061 {
mega64 0:38ccae254a29 1062 /* Call receive function */
mega64 0:38ccae254a29 1063 CAN_Receive_IT(hcan, CAN_FIFO0);
mega64 0:38ccae254a29 1064 }
mega64 0:38ccae254a29 1065
mega64 0:38ccae254a29 1066 /* Check End of reception flag for FIFO1 */
mega64 0:38ccae254a29 1067 if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
mega64 0:38ccae254a29 1068 (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0))
mega64 0:38ccae254a29 1069 {
mega64 0:38ccae254a29 1070 /* Call receive function */
mega64 0:38ccae254a29 1071 CAN_Receive_IT(hcan, CAN_FIFO1);
mega64 0:38ccae254a29 1072 }
mega64 0:38ccae254a29 1073
mega64 0:38ccae254a29 1074 /* Check Error Warning Flag */
mega64 0:38ccae254a29 1075 if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) &&
mega64 0:38ccae254a29 1076 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
mega64 0:38ccae254a29 1077 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
mega64 0:38ccae254a29 1078 {
mega64 0:38ccae254a29 1079 /* Set CAN error code to EWG error */
mega64 0:38ccae254a29 1080 hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
mega64 0:38ccae254a29 1081 /* No need for clear of Error Warning Flag as read-only */
mega64 0:38ccae254a29 1082 }
mega64 0:38ccae254a29 1083
mega64 0:38ccae254a29 1084 /* Check Error Passive Flag */
mega64 0:38ccae254a29 1085 if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) &&
mega64 0:38ccae254a29 1086 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
mega64 0:38ccae254a29 1087 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
mega64 0:38ccae254a29 1088 {
mega64 0:38ccae254a29 1089 /* Set CAN error code to EPV error */
mega64 0:38ccae254a29 1090 hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
mega64 0:38ccae254a29 1091 /* No need for clear of Error Passive Flag as read-only */
mega64 0:38ccae254a29 1092 }
mega64 0:38ccae254a29 1093
mega64 0:38ccae254a29 1094 /* Check Bus-Off Flag */
mega64 0:38ccae254a29 1095 if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) &&
mega64 0:38ccae254a29 1096 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
mega64 0:38ccae254a29 1097 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
mega64 0:38ccae254a29 1098 {
mega64 0:38ccae254a29 1099 /* Set CAN error code to BOF error */
mega64 0:38ccae254a29 1100 hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
mega64 0:38ccae254a29 1101 /* No need for clear of Bus-Off Flag as read-only */
mega64 0:38ccae254a29 1102 }
mega64 0:38ccae254a29 1103
mega64 0:38ccae254a29 1104 /* Check Last error code Flag */
mega64 0:38ccae254a29 1105 if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
mega64 0:38ccae254a29 1106 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) &&
mega64 0:38ccae254a29 1107 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
mega64 0:38ccae254a29 1108 {
mega64 0:38ccae254a29 1109 switch(hcan->Instance->ESR & CAN_ESR_LEC)
mega64 0:38ccae254a29 1110 {
mega64 0:38ccae254a29 1111 case(CAN_ESR_LEC_0):
mega64 0:38ccae254a29 1112 /* Set CAN error code to STF error */
mega64 0:38ccae254a29 1113 hcan->ErrorCode |= HAL_CAN_ERROR_STF;
mega64 0:38ccae254a29 1114 break;
mega64 0:38ccae254a29 1115 case(CAN_ESR_LEC_1):
mega64 0:38ccae254a29 1116 /* Set CAN error code to FOR error */
mega64 0:38ccae254a29 1117 hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
mega64 0:38ccae254a29 1118 break;
mega64 0:38ccae254a29 1119 case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
mega64 0:38ccae254a29 1120 /* Set CAN error code to ACK error */
mega64 0:38ccae254a29 1121 hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
mega64 0:38ccae254a29 1122 break;
mega64 0:38ccae254a29 1123 case(CAN_ESR_LEC_2):
mega64 0:38ccae254a29 1124 /* Set CAN error code to BR error */
mega64 0:38ccae254a29 1125 hcan->ErrorCode |= HAL_CAN_ERROR_BR;
mega64 0:38ccae254a29 1126 break;
mega64 0:38ccae254a29 1127 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
mega64 0:38ccae254a29 1128 /* Set CAN error code to BD error */
mega64 0:38ccae254a29 1129 hcan->ErrorCode |= HAL_CAN_ERROR_BD;
mega64 0:38ccae254a29 1130 break;
mega64 0:38ccae254a29 1131 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
mega64 0:38ccae254a29 1132 /* Set CAN error code to CRC error */
mega64 0:38ccae254a29 1133 hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
mega64 0:38ccae254a29 1134 break;
mega64 0:38ccae254a29 1135 default:
mega64 0:38ccae254a29 1136 break;
mega64 0:38ccae254a29 1137 }
mega64 0:38ccae254a29 1138
mega64 0:38ccae254a29 1139 /* Clear Last error code Flag */
mega64 0:38ccae254a29 1140 hcan->Instance->ESR &= ~(CAN_ESR_LEC);
mega64 0:38ccae254a29 1141 }
mega64 0:38ccae254a29 1142
mega64 0:38ccae254a29 1143 /* Call the Error call Back in case of Errors */
mega64 0:38ccae254a29 1144 if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
mega64 0:38ccae254a29 1145 {
mega64 0:38ccae254a29 1146 /* Set the CAN state ready to be able to start again the process */
mega64 0:38ccae254a29 1147 hcan->State = HAL_CAN_STATE_READY;
mega64 0:38ccae254a29 1148 /* Call Error callback function */
mega64 0:38ccae254a29 1149 HAL_CAN_ErrorCallback(hcan);
mega64 0:38ccae254a29 1150 }
mega64 0:38ccae254a29 1151 }
mega64 0:38ccae254a29 1152
mega64 0:38ccae254a29 1153 /**
mega64 0:38ccae254a29 1154 * @brief Transmission complete callback in non blocking mode
mega64 0:38ccae254a29 1155 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 1156 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 1157 * @retval None
mega64 0:38ccae254a29 1158 */
mega64 0:38ccae254a29 1159 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
mega64 0:38ccae254a29 1160 {
mega64 0:38ccae254a29 1161 /* NOTE : This function Should not be modified, when the callback is needed,
mega64 0:38ccae254a29 1162 the HAL_CAN_TxCpltCallback could be implemented in the user file
mega64 0:38ccae254a29 1163 */
mega64 0:38ccae254a29 1164 }
mega64 0:38ccae254a29 1165
mega64 0:38ccae254a29 1166 /**
mega64 0:38ccae254a29 1167 * @brief Transmission complete callback in non blocking mode
mega64 0:38ccae254a29 1168 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 1169 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 1170 * @retval None
mega64 0:38ccae254a29 1171 */
mega64 0:38ccae254a29 1172 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
mega64 0:38ccae254a29 1173 {
mega64 0:38ccae254a29 1174 /* NOTE : This function Should not be modified, when the callback is needed,
mega64 0:38ccae254a29 1175 the HAL_CAN_RxCpltCallback could be implemented in the user file
mega64 0:38ccae254a29 1176 */
mega64 0:38ccae254a29 1177 }
mega64 0:38ccae254a29 1178
mega64 0:38ccae254a29 1179 /**
mega64 0:38ccae254a29 1180 * @brief Error CAN callback.
mega64 0:38ccae254a29 1181 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 1182 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 1183 * @retval None
mega64 0:38ccae254a29 1184 */
mega64 0:38ccae254a29 1185 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
mega64 0:38ccae254a29 1186 {
mega64 0:38ccae254a29 1187 /* NOTE : This function Should not be modified, when the callback is needed,
mega64 0:38ccae254a29 1188 the HAL_CAN_ErrorCallback could be implemented in the user file
mega64 0:38ccae254a29 1189 */
mega64 0:38ccae254a29 1190 }
mega64 0:38ccae254a29 1191
mega64 0:38ccae254a29 1192 /**
mega64 0:38ccae254a29 1193 * @}
mega64 0:38ccae254a29 1194 */
mega64 0:38ccae254a29 1195
mega64 0:38ccae254a29 1196 /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
mega64 0:38ccae254a29 1197 * @brief CAN Peripheral State functions
mega64 0:38ccae254a29 1198 *
mega64 0:38ccae254a29 1199 @verbatim
mega64 0:38ccae254a29 1200 ==============================================================================
mega64 0:38ccae254a29 1201 ##### Peripheral State and Error functions #####
mega64 0:38ccae254a29 1202 ==============================================================================
mega64 0:38ccae254a29 1203 [..]
mega64 0:38ccae254a29 1204 This subsection provides functions allowing to :
mega64 0:38ccae254a29 1205 (+) Check the CAN state.
mega64 0:38ccae254a29 1206 (+) Check CAN Errors detected during interrupt process
mega64 0:38ccae254a29 1207
mega64 0:38ccae254a29 1208 @endverbatim
mega64 0:38ccae254a29 1209 * @{
mega64 0:38ccae254a29 1210 */
mega64 0:38ccae254a29 1211
mega64 0:38ccae254a29 1212 /**
mega64 0:38ccae254a29 1213 * @brief return the CAN state
mega64 0:38ccae254a29 1214 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 1215 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 1216 * @retval HAL state
mega64 0:38ccae254a29 1217 */
mega64 0:38ccae254a29 1218 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
mega64 0:38ccae254a29 1219 {
mega64 0:38ccae254a29 1220 /* Return CAN state */
mega64 0:38ccae254a29 1221 return hcan->State;
mega64 0:38ccae254a29 1222 }
mega64 0:38ccae254a29 1223
mega64 0:38ccae254a29 1224 /**
mega64 0:38ccae254a29 1225 * @brief Return the CAN error code
mega64 0:38ccae254a29 1226 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 1227 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 1228 * @retval CAN Error Code
mega64 0:38ccae254a29 1229 */
mega64 0:38ccae254a29 1230 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
mega64 0:38ccae254a29 1231 {
mega64 0:38ccae254a29 1232 return hcan->ErrorCode;
mega64 0:38ccae254a29 1233 }
mega64 0:38ccae254a29 1234
mega64 0:38ccae254a29 1235 /**
mega64 0:38ccae254a29 1236 * @}
mega64 0:38ccae254a29 1237 */
mega64 0:38ccae254a29 1238
mega64 0:38ccae254a29 1239 /**
mega64 0:38ccae254a29 1240 * @}
mega64 0:38ccae254a29 1241 */
mega64 0:38ccae254a29 1242
mega64 0:38ccae254a29 1243 /** @addtogroup CAN_Private_Functions CAN Private Functions
mega64 0:38ccae254a29 1244 * @brief CAN Frame message Rx/Tx functions
mega64 0:38ccae254a29 1245 *
mega64 0:38ccae254a29 1246 * @{
mega64 0:38ccae254a29 1247 */
mega64 0:38ccae254a29 1248
mega64 0:38ccae254a29 1249 /**
mega64 0:38ccae254a29 1250 * @brief Initiates and transmits a CAN frame message.
mega64 0:38ccae254a29 1251 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 1252 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 1253 * @retval HAL status
mega64 0:38ccae254a29 1254 */
mega64 0:38ccae254a29 1255 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
mega64 0:38ccae254a29 1256 {
mega64 0:38ccae254a29 1257 /* Disable Transmit mailbox empty Interrupt */
mega64 0:38ccae254a29 1258 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
mega64 0:38ccae254a29 1259
mega64 0:38ccae254a29 1260 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
mega64 0:38ccae254a29 1261 {
mega64 0:38ccae254a29 1262 /* Disable Error warning Interrupt */
mega64 0:38ccae254a29 1263 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
mega64 0:38ccae254a29 1264
mega64 0:38ccae254a29 1265 /* Disable Error passive Interrupt */
mega64 0:38ccae254a29 1266 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
mega64 0:38ccae254a29 1267
mega64 0:38ccae254a29 1268 /* Disable Bus-off Interrupt */
mega64 0:38ccae254a29 1269 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
mega64 0:38ccae254a29 1270
mega64 0:38ccae254a29 1271 /* Disable Last error code Interrupt */
mega64 0:38ccae254a29 1272 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
mega64 0:38ccae254a29 1273
mega64 0:38ccae254a29 1274 /* Disable Error Interrupt */
mega64 0:38ccae254a29 1275 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
mega64 0:38ccae254a29 1276 }
mega64 0:38ccae254a29 1277
mega64 0:38ccae254a29 1278 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
mega64 0:38ccae254a29 1279 {
mega64 0:38ccae254a29 1280 /* Change CAN state */
mega64 0:38ccae254a29 1281 hcan->State = HAL_CAN_STATE_BUSY_RX;
mega64 0:38ccae254a29 1282 }
mega64 0:38ccae254a29 1283 else
mega64 0:38ccae254a29 1284 {
mega64 0:38ccae254a29 1285 /* Change CAN state */
mega64 0:38ccae254a29 1286 hcan->State = HAL_CAN_STATE_READY;
mega64 0:38ccae254a29 1287 }
mega64 0:38ccae254a29 1288
mega64 0:38ccae254a29 1289 /* Transmission complete callback */
mega64 0:38ccae254a29 1290 HAL_CAN_TxCpltCallback(hcan);
mega64 0:38ccae254a29 1291
mega64 0:38ccae254a29 1292 return HAL_OK;
mega64 0:38ccae254a29 1293 }
mega64 0:38ccae254a29 1294
mega64 0:38ccae254a29 1295 /**
mega64 0:38ccae254a29 1296 * @brief Receives a correct CAN frame.
mega64 0:38ccae254a29 1297 * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
mega64 0:38ccae254a29 1298 * the configuration information for the specified CAN.
mega64 0:38ccae254a29 1299 * @param FIFONumber: Specify the FIFO number
mega64 0:38ccae254a29 1300 * @retval HAL status
mega64 0:38ccae254a29 1301 * @retval None
mega64 0:38ccae254a29 1302 */
mega64 0:38ccae254a29 1303 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
mega64 0:38ccae254a29 1304 {
mega64 0:38ccae254a29 1305 /* Get the Id */
mega64 0:38ccae254a29 1306 hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
mega64 0:38ccae254a29 1307 if (hcan->pRxMsg->IDE == CAN_ID_STD)
mega64 0:38ccae254a29 1308 {
mega64 0:38ccae254a29 1309 hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
mega64 0:38ccae254a29 1310 }
mega64 0:38ccae254a29 1311 else
mega64 0:38ccae254a29 1312 {
mega64 0:38ccae254a29 1313 hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
mega64 0:38ccae254a29 1314 }
mega64 0:38ccae254a29 1315
mega64 0:38ccae254a29 1316 hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
mega64 0:38ccae254a29 1317 /* Get the DLC */
mega64 0:38ccae254a29 1318 hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
mega64 0:38ccae254a29 1319 /* Get the FMI */
mega64 0:38ccae254a29 1320 hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
mega64 0:38ccae254a29 1321 /* Get the data field */
mega64 0:38ccae254a29 1322 hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
mega64 0:38ccae254a29 1323 hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
mega64 0:38ccae254a29 1324 hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
mega64 0:38ccae254a29 1325 hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
mega64 0:38ccae254a29 1326 hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
mega64 0:38ccae254a29 1327 hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
mega64 0:38ccae254a29 1328 hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
mega64 0:38ccae254a29 1329 hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
mega64 0:38ccae254a29 1330 /* Release the FIFO */
mega64 0:38ccae254a29 1331 /* Release FIFO0 */
mega64 0:38ccae254a29 1332 if (FIFONumber == CAN_FIFO0)
mega64 0:38ccae254a29 1333 {
mega64 0:38ccae254a29 1334 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
mega64 0:38ccae254a29 1335
mega64 0:38ccae254a29 1336 /* Disable FIFO 0 message pending Interrupt */
mega64 0:38ccae254a29 1337 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
mega64 0:38ccae254a29 1338 }
mega64 0:38ccae254a29 1339 /* Release FIFO1 */
mega64 0:38ccae254a29 1340 else /* FIFONumber == CAN_FIFO1 */
mega64 0:38ccae254a29 1341 {
mega64 0:38ccae254a29 1342 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
mega64 0:38ccae254a29 1343
mega64 0:38ccae254a29 1344 /* Disable FIFO 1 message pending Interrupt */
mega64 0:38ccae254a29 1345 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
mega64 0:38ccae254a29 1346 }
mega64 0:38ccae254a29 1347
mega64 0:38ccae254a29 1348 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
mega64 0:38ccae254a29 1349 {
mega64 0:38ccae254a29 1350 /* Disable Error warning Interrupt */
mega64 0:38ccae254a29 1351 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
mega64 0:38ccae254a29 1352
mega64 0:38ccae254a29 1353 /* Disable Error passive Interrupt */
mega64 0:38ccae254a29 1354 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
mega64 0:38ccae254a29 1355
mega64 0:38ccae254a29 1356 /* Disable Bus-off Interrupt */
mega64 0:38ccae254a29 1357 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
mega64 0:38ccae254a29 1358
mega64 0:38ccae254a29 1359 /* Disable Last error code Interrupt */
mega64 0:38ccae254a29 1360 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
mega64 0:38ccae254a29 1361
mega64 0:38ccae254a29 1362 /* Disable Error Interrupt */
mega64 0:38ccae254a29 1363 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
mega64 0:38ccae254a29 1364 }
mega64 0:38ccae254a29 1365
mega64 0:38ccae254a29 1366 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
mega64 0:38ccae254a29 1367 {
mega64 0:38ccae254a29 1368 /* Disable CAN state */
mega64 0:38ccae254a29 1369 hcan->State = HAL_CAN_STATE_BUSY_TX;
mega64 0:38ccae254a29 1370 }
mega64 0:38ccae254a29 1371 else
mega64 0:38ccae254a29 1372 {
mega64 0:38ccae254a29 1373 /* Change CAN state */
mega64 0:38ccae254a29 1374 hcan->State = HAL_CAN_STATE_READY;
mega64 0:38ccae254a29 1375 }
mega64 0:38ccae254a29 1376
mega64 0:38ccae254a29 1377 /* Receive complete callback */
mega64 0:38ccae254a29 1378 HAL_CAN_RxCpltCallback(hcan);
mega64 0:38ccae254a29 1379
mega64 0:38ccae254a29 1380 /* Return function status */
mega64 0:38ccae254a29 1381 return HAL_OK;
mega64 0:38ccae254a29 1382 }
mega64 0:38ccae254a29 1383
mega64 0:38ccae254a29 1384 /**
mega64 0:38ccae254a29 1385 * @}
mega64 0:38ccae254a29 1386 */
mega64 0:38ccae254a29 1387
mega64 0:38ccae254a29 1388 #endif /* defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) */
mega64 0:38ccae254a29 1389
mega64 0:38ccae254a29 1390 #endif /* HAL_CAN_MODULE_ENABLED */
mega64 0:38ccae254a29 1391 /**
mega64 0:38ccae254a29 1392 * @}
mega64 0:38ccae254a29 1393 */
mega64 0:38ccae254a29 1394
mega64 0:38ccae254a29 1395 /**
mega64 0:38ccae254a29 1396 * @}
mega64 0:38ccae254a29 1397 */
mega64 0:38ccae254a29 1398
mega64 0:38ccae254a29 1399 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/