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CMSIS
Modules | |
| Stm32f4xx | |
Variables | |
| __IO uint32_t | CR1 |
| __IO uint32_t | CR2 |
| __IO uint32_t | SMPR1 |
| __IO uint32_t | SMPR2 |
| __IO uint32_t | JOFR1 |
| __IO uint32_t | JOFR2 |
| __IO uint32_t | JOFR3 |
| __IO uint32_t | JOFR4 |
| __IO uint32_t | HTR |
| __IO uint32_t | LTR |
| __IO uint32_t | SQR1 |
| __IO uint32_t | SQR2 |
| __IO uint32_t | SQR3 |
| __IO uint32_t | JSQR |
| __IO uint32_t | JDR1 |
| __IO uint32_t | JDR2 |
| __IO uint32_t | JDR3 |
| __IO uint32_t | JDR4 |
| __IO uint32_t | DR |
| __IO uint32_t | CCR |
| __IO uint32_t | CDR |
| __IO uint32_t | TDTR |
| __IO uint32_t | TDLR |
| __IO uint32_t | TDHR |
| __IO uint32_t | RDTR |
| __IO uint32_t | RDLR |
| __IO uint32_t | RDHR |
| __IO uint32_t | FR2 |
| __IO uint32_t | MSR |
| __IO uint32_t | TSR |
| __IO uint32_t | RF0R |
| __IO uint32_t | RF1R |
| __IO uint32_t | IER |
| __IO uint32_t | ESR |
| __IO uint32_t | BTR |
| uint32_t | RESERVED0 [88] |
| CAN_TxMailBox_TypeDef | sTxMailBox [3] |
| CAN_FIFOMailBox_TypeDef | sFIFOMailBox [2] |
| uint32_t | RESERVED1 [12] |
| __IO uint32_t | FMR |
| __IO uint32_t | FM1R |
| uint32_t | RESERVED2 |
| __IO uint32_t | FS1R |
| uint32_t | RESERVED3 |
| __IO uint32_t | FFA1R |
| uint32_t | RESERVED4 |
| __IO uint32_t | FA1R |
| uint32_t | RESERVED5 [8] |
| CAN_FilterRegister_TypeDef | sFilterRegister [28] |
| __IO uint32_t | CFGR |
| __IO uint32_t | TXDR |
| __IO uint32_t | RXDR |
| __IO uint32_t | ISR |
| __IO uint32_t | IER |
| __IO uint8_t | IDR |
| uint8_t | RESERVED0 |
| uint16_t | RESERVED1 |
| __IO uint32_t | CR |
| __IO uint32_t | SWTRIGR |
| __IO uint32_t | DHR12R1 |
| __IO uint32_t | DHR12L1 |
| __IO uint32_t | DHR8R1 |
| __IO uint32_t | DHR12R2 |
| __IO uint32_t | DHR12L2 |
| __IO uint32_t | DHR8R2 |
| __IO uint32_t | DHR12RD |
| __IO uint32_t | DHR12LD |
| __IO uint32_t | DHR8RD |
| __IO uint32_t | DOR1 |
| __IO uint32_t | DOR2 |
| __IO uint32_t | SR |
| __IO uint32_t | FLTCR2 |
| __IO uint32_t | FLTISR |
| __IO uint32_t | FLTICR |
| __IO uint32_t | FLTJCHGR |
| __IO uint32_t | FLTFCR |
| __IO uint32_t | FLTJDATAR |
| __IO uint32_t | FLTRDATAR |
| __IO uint32_t | FLTAWHTR |
| __IO uint32_t | FLTAWLTR |
| __IO uint32_t | FLTAWSR |
| __IO uint32_t | FLTAWCFR |
| __IO uint32_t | FLTEXMAX |
| __IO uint32_t | FLTEXMIN |
| __IO uint32_t | FLTCNVTIMR |
| __IO uint32_t | CHCFGR2 |
| __IO uint32_t | CHAWSCDR |
| __IO uint32_t | CHWDATAR |
| __IO uint32_t | CHDATINR |
| __IO uint32_t | CR |
| __IO uint32_t | APB1FZ |
| __IO uint32_t | APB2FZ |
| __IO uint32_t | SR |
| __IO uint32_t | RISR |
| __IO uint32_t | IER |
| __IO uint32_t | MISR |
| __IO uint32_t | ICR |
| __IO uint32_t | ESCR |
| __IO uint32_t | ESUR |
| __IO uint32_t | CWSTRTR |
| __IO uint32_t | CWSIZER |
| __IO uint32_t | DR |
| __IO uint32_t | NDTR |
| __IO uint32_t | PAR |
| __IO uint32_t | M0AR |
| __IO uint32_t | M1AR |
| __IO uint32_t | FCR |
| __IO uint32_t | HISR |
| __IO uint32_t | LIFCR |
| __IO uint32_t | HIFCR |
| __IO uint32_t | ISR |
| __IO uint32_t | IFCR |
| __IO uint32_t | FGMAR |
| __IO uint32_t | FGOR |
| __IO uint32_t | BGMAR |
| __IO uint32_t | BGOR |
| __IO uint32_t | FGPFCCR |
| __IO uint32_t | FGCOLR |
| __IO uint32_t | BGPFCCR |
| __IO uint32_t | BGCOLR |
| __IO uint32_t | FGCMAR |
| __IO uint32_t | BGCMAR |
| __IO uint32_t | OPFCCR |
| __IO uint32_t | OCOLR |
| __IO uint32_t | OMAR |
| __IO uint32_t | OOR |
| __IO uint32_t | NLR |
| __IO uint32_t | LWR |
| __IO uint32_t | AMTCR |
| uint32_t | RESERVED [236] |
| __IO uint32_t | FGCLUT [256] |
| __IO uint32_t | BGCLUT [256] |
| __IO uint32_t | CR |
| __IO uint32_t | CCR |
| __IO uint32_t | LVCIDR |
| __IO uint32_t | LCOLCR |
| __IO uint32_t | LPCR |
| __IO uint32_t | LPMCR |
| uint32_t | RESERVED0 [4] |
| __IO uint32_t | PCR |
| __IO uint32_t | GVCIDR |
| __IO uint32_t | MCR |
| __IO uint32_t | VMCR |
| __IO uint32_t | VPCR |
| __IO uint32_t | VCCR |
| __IO uint32_t | VNPCR |
| __IO uint32_t | VHSACR |
| __IO uint32_t | VHBPCR |
| __IO uint32_t | VLCR |
| __IO uint32_t | VVSACR |
| __IO uint32_t | VVBPCR |
| __IO uint32_t | VVFPCR |
| __IO uint32_t | VVACR |
| __IO uint32_t | LCCR |
| __IO uint32_t | CMCR |
| __IO uint32_t | GHCR |
| __IO uint32_t | GPDR |
| __IO uint32_t | GPSR |
| __IO uint32_t | TCCR [6] |
| __IO uint32_t | TDCR |
| __IO uint32_t | CLCR |
| __IO uint32_t | CLTCR |
| __IO uint32_t | DLTCR |
| __IO uint32_t | PCTLR |
| __IO uint32_t | PCONFR |
| __IO uint32_t | PUCR |
| __IO uint32_t | PTTCR |
| __IO uint32_t | PSR |
| uint32_t | RESERVED1 [2] |
| __IO uint32_t | ISR [2] |
| __IO uint32_t | IER [2] |
| uint32_t | RESERVED2 [3] |
| __IO uint32_t | FIR [2] |
| uint32_t | RESERVED3 [8] |
| __IO uint32_t | VSCR |
| uint32_t | RESERVED4 [2] |
| __IO uint32_t | LCVCIDR |
| __IO uint32_t | LCCCR |
| uint32_t | RESERVED5 |
| __IO uint32_t | LPMCCR |
| uint32_t | RESERVED6 [7] |
| __IO uint32_t | VMCCR |
| __IO uint32_t | VPCCR |
| __IO uint32_t | VCCCR |
| __IO uint32_t | VNPCCR |
| __IO uint32_t | VHSACCR |
| __IO uint32_t | VHBPCCR |
| __IO uint32_t | VLCCR |
| __IO uint32_t | VVSACCR |
| __IO uint32_t | VVBPCCR |
| __IO uint32_t | VVFPCCR |
| __IO uint32_t | VVACCR |
| uint32_t | RESERVED7 [11] |
| __IO uint32_t | TDCCR |
| uint32_t | RESERVED8 [155] |
| __IO uint32_t | WCFGR |
| __IO uint32_t | WCR |
| __IO uint32_t | WIER |
| __IO uint32_t | WISR |
| __IO uint32_t | WIFCR |
| uint32_t | RESERVED9 |
| __IO uint32_t | WPCR [5] |
| uint32_t | RESERVED10 |
| __IO uint32_t | WRPCR |
| __IO uint32_t | EMR |
| __IO uint32_t | RTSR |
| __IO uint32_t | FTSR |
| __IO uint32_t | SWIER |
| __IO uint32_t | PR |
| __IO uint32_t | KEYR |
| __IO uint32_t | OPTKEYR |
| __IO uint32_t | SR |
| __IO uint32_t | CR |
| __IO uint32_t | OPTCR |
| __IO uint32_t | OPTCR1 |
| __IO uint32_t | SR2 |
| __IO uint32_t | PMEM2 |
| __IO uint32_t | PATT2 |
| uint32_t | RESERVED0 |
| __IO uint32_t | ECCR2 |
| __IO uint32_t | SR3 |
| __IO uint32_t | PMEM3 |
| __IO uint32_t | PATT3 |
| uint32_t | RESERVED0 |
| __IO uint32_t | ECCR3 |
| __IO uint32_t | SR4 |
| __IO uint32_t | PMEM4 |
| __IO uint32_t | PATT4 |
| __IO uint32_t | PIO4 |
| __IO uint32_t | SR2 |
| __IO uint32_t | PMEM2 |
| __IO uint32_t | PATT2 |
| uint32_t | RESERVED0 |
| __IO uint32_t | ECCR2 |
| __IO uint32_t | SR3 |
| __IO uint32_t | PMEM3 |
| __IO uint32_t | PATT3 |
| uint32_t | RESERVED0 |
| __IO uint32_t | ECCR3 |
| __IO uint32_t | SR4 |
| __IO uint32_t | PMEM4 |
| __IO uint32_t | PATT4 |
| __IO uint32_t | PIO4 |
| __IO uint32_t | SDTR [2] |
| __IO uint32_t | SDCMR |
| __IO uint32_t | SDRTR |
| __IO uint32_t | SDSR |
| __IO uint32_t | OTYPER |
| __IO uint32_t | OSPEEDR |
| __IO uint32_t | PUPDR |
| __IO uint32_t | IDR |
| __IO uint32_t | ODR |
| __IO uint32_t | BSRR |
| __IO uint32_t | LCKR |
| __IO uint32_t | AFR [2] |
| __IO uint32_t | PMC |
| __IO uint32_t | EXTICR [4] |
| uint32_t | RESERVED |
| __IO uint32_t | CFGR2 |
| __IO uint32_t | CMPCR |
| uint32_t | RESERVED1 [2] |
| __IO uint32_t | CFGR |
| __IO uint32_t | MCHDLYCR |
| uint16_t | RESERVED0 |
| __IO uint16_t | CR2 |
| uint16_t | RESERVED1 |
| __IO uint16_t | OAR1 |
| uint16_t | RESERVED2 |
| __IO uint16_t | OAR2 |
| uint16_t | RESERVED3 |
| __IO uint16_t | DR |
| uint16_t | RESERVED4 |
| __IO uint16_t | SR1 |
| uint16_t | RESERVED5 |
| __IO uint16_t | SR2 |
| uint16_t | RESERVED6 |
| __IO uint16_t | CCR |
| uint16_t | RESERVED7 |
| __IO uint16_t | TRISE |
| uint16_t | RESERVED8 |
| __IO uint16_t | FLTR |
| uint16_t | RESERVED9 |
| __IO uint32_t | CR2 |
| __IO uint32_t | OAR1 |
| __IO uint32_t | OAR2 |
| __IO uint32_t | TIMINGR |
| __IO uint32_t | TIMEOUTR |
| __IO uint32_t | ISR |
| __IO uint32_t | ICR |
| __IO uint32_t | PECR |
| __IO uint32_t | RXDR |
| __IO uint32_t | TXDR |
| __IO uint32_t | PR |
| __IO uint32_t | RLR |
| __IO uint32_t | SR |
| __IO uint32_t | SSCR |
| __IO uint32_t | BPCR |
| __IO uint32_t | AWCR |
| __IO uint32_t | TWCR |
| __IO uint32_t | GCR |
| uint32_t | RESERVED1 [2] |
| __IO uint32_t | SRCR |
| uint32_t | RESERVED2 [1] |
| __IO uint32_t | BCCR |
| uint32_t | RESERVED3 [1] |
| __IO uint32_t | IER |
| __IO uint32_t | ISR |
| __IO uint32_t | ICR |
| __IO uint32_t | LIPCR |
| __IO uint32_t | CPSR |
| __IO uint32_t | CDSR |
| __IO uint32_t | WHPCR |
| __IO uint32_t | WVPCR |
| __IO uint32_t | CKCR |
| __IO uint32_t | PFCR |
| __IO uint32_t | CACR |
| __IO uint32_t | DCCR |
| __IO uint32_t | BFCR |
| uint32_t | RESERVED0 [2] |
| __IO uint32_t | CFBAR |
| __IO uint32_t | CFBLR |
| __IO uint32_t | CFBLNR |
| uint32_t | RESERVED1 [3] |
| __IO uint32_t | CLUTWR |
| __IO uint32_t | CSR |
| __IO uint32_t | PLLCFGR |
| __IO uint32_t | CFGR |
| __IO uint32_t | CIR |
| __IO uint32_t | AHB1RSTR |
| __IO uint32_t | AHB2RSTR |
| __IO uint32_t | AHB3RSTR |
| uint32_t | RESERVED0 |
| __IO uint32_t | APB1RSTR |
| __IO uint32_t | APB2RSTR |
| uint32_t | RESERVED1 [2] |
| __IO uint32_t | AHB1ENR |
| __IO uint32_t | AHB2ENR |
| __IO uint32_t | AHB3ENR |
| uint32_t | RESERVED2 |
| __IO uint32_t | APB1ENR |
| __IO uint32_t | APB2ENR |
| uint32_t | RESERVED3 [2] |
| __IO uint32_t | AHB1LPENR |
| __IO uint32_t | AHB2LPENR |
| __IO uint32_t | AHB3LPENR |
| uint32_t | RESERVED4 |
| __IO uint32_t | APB1LPENR |
| __IO uint32_t | APB2LPENR |
| uint32_t | RESERVED5 [2] |
| __IO uint32_t | BDCR |
| __IO uint32_t | CSR |
| uint32_t | RESERVED6 [2] |
| __IO uint32_t | SSCGR |
| __IO uint32_t | PLLI2SCFGR |
| __IO uint32_t | PLLSAICFGR |
| __IO uint32_t | DCKCFGR |
| __IO uint32_t | CKGATENR |
| __IO uint32_t | DCKCFGR2 |
| __IO uint32_t | DR |
| __IO uint32_t | CR |
| __IO uint32_t | ISR |
| __IO uint32_t | PRER |
| __IO uint32_t | WUTR |
| __IO uint32_t | CALIBR |
| __IO uint32_t | ALRMAR |
| __IO uint32_t | ALRMBR |
| __IO uint32_t | WPR |
| __IO uint32_t | SSR |
| __IO uint32_t | SHIFTR |
| __IO uint32_t | TSTR |
| __IO uint32_t | TSDR |
| __IO uint32_t | TSSSR |
| __IO uint32_t | CALR |
| __IO uint32_t | TAFCR |
| __IO uint32_t | ALRMASSR |
| __IO uint32_t | ALRMBSSR |
| uint32_t | RESERVED7 |
| __IO uint32_t | BKP0R |
| __IO uint32_t | BKP1R |
| __IO uint32_t | BKP2R |
| __IO uint32_t | BKP3R |
| __IO uint32_t | BKP4R |
| __IO uint32_t | BKP5R |
| __IO uint32_t | BKP6R |
| __IO uint32_t | BKP7R |
| __IO uint32_t | BKP8R |
| __IO uint32_t | BKP9R |
| __IO uint32_t | BKP10R |
| __IO uint32_t | BKP11R |
| __IO uint32_t | BKP12R |
| __IO uint32_t | BKP13R |
| __IO uint32_t | BKP14R |
| __IO uint32_t | BKP15R |
| __IO uint32_t | BKP16R |
| __IO uint32_t | BKP17R |
| __IO uint32_t | BKP18R |
| __IO uint32_t | BKP19R |
| __IO uint32_t | CR2 |
| __IO uint32_t | FRCR |
| __IO uint32_t | SLOTR |
| __IO uint32_t | IMR |
| __IO uint32_t | SR |
| __IO uint32_t | CLRFR |
| __IO uint32_t | DR |
| __IO uint32_t | CLKCR |
| __IO uint32_t | ARG |
| __IO uint32_t | CMD |
| __I uint32_t | RESPCMD |
| __I uint32_t | RESP1 |
| __I uint32_t | RESP2 |
| __I uint32_t | RESP3 |
| __I uint32_t | RESP4 |
| __IO uint32_t | DTIMER |
| __IO uint32_t | DLEN |
| __IO uint32_t | DCTRL |
| __I uint32_t | DCOUNT |
| __I uint32_t | STA |
| __IO uint32_t | ICR |
| __IO uint32_t | MASK |
| uint32_t | RESERVED0 [2] |
| __I uint32_t | FIFOCNT |
| uint32_t | RESERVED1 [13] |
| __IO uint32_t | FIFO |
| uint16_t | RESERVED0 |
| __IO uint16_t | CR2 |
| uint16_t | RESERVED1 |
| __IO uint16_t | SR |
| uint16_t | RESERVED2 |
| __IO uint16_t | DR |
| uint16_t | RESERVED3 |
| __IO uint16_t | CRCPR |
| uint16_t | RESERVED4 |
| __IO uint16_t | RXCRCR |
| uint16_t | RESERVED5 |
| __IO uint16_t | TXCRCR |
| uint16_t | RESERVED6 |
| __IO uint16_t | I2SCFGR |
| uint16_t | RESERVED7 |
| __IO uint16_t | I2SPR |
| uint16_t | RESERVED8 |
| __IO uint16_t | IMR |
| uint16_t | RESERVED0 |
| __IO uint32_t | SR |
| __IO uint16_t | IFCR |
| uint16_t | RESERVED1 |
| __IO uint32_t | DR |
| __IO uint32_t | CSR |
| __IO uint32_t | DIR |
| uint16_t | RESERVED2 |
| __IO uint32_t | DCR |
| __IO uint32_t | SR |
| __IO uint32_t | FCR |
| __IO uint32_t | DLR |
| __IO uint32_t | CCR |
| __IO uint32_t | AR |
| __IO uint32_t | ABR |
| __IO uint32_t | DR |
| __IO uint32_t | PSMKR |
| __IO uint32_t | PSMAR |
| __IO uint32_t | PIR |
| __IO uint32_t | LPTR |
| __IO uint16_t | IMR |
| uint16_t | RESERVED0 |
| __IO uint32_t | SR |
| __IO uint16_t | IFCR |
| uint16_t | RESERVED1 |
| __IO uint32_t | DR |
| __IO uint32_t | CSR |
| __IO uint32_t | DIR |
| uint16_t | RESERVED2 |
| uint16_t | RESERVED0 |
| __IO uint16_t | CR2 |
| uint16_t | RESERVED1 |
| __IO uint16_t | SMCR |
| uint16_t | RESERVED2 |
| __IO uint16_t | DIER |
| uint16_t | RESERVED3 |
| __IO uint16_t | SR |
| uint16_t | RESERVED4 |
| __IO uint16_t | EGR |
| uint16_t | RESERVED5 |
| __IO uint16_t | CCMR1 |
| uint16_t | RESERVED6 |
| __IO uint16_t | CCMR2 |
| uint16_t | RESERVED7 |
| __IO uint16_t | CCER |
| uint16_t | RESERVED8 |
| __IO uint32_t | CNT |
| __IO uint16_t | PSC |
| uint16_t | RESERVED9 |
| __IO uint32_t | ARR |
| __IO uint16_t | RCR |
| uint16_t | RESERVED10 |
| __IO uint32_t | CCR1 |
| __IO uint32_t | CCR2 |
| __IO uint32_t | CCR3 |
| __IO uint32_t | CCR4 |
| __IO uint16_t | BDTR |
| uint16_t | RESERVED11 |
| __IO uint16_t | DCR |
| uint16_t | RESERVED12 |
| __IO uint16_t | DMAR |
| uint16_t | RESERVED13 |
| __IO uint16_t | OR |
| uint16_t | RESERVED14 |
| uint16_t | RESERVED0 |
| __IO uint16_t | DR |
| uint16_t | RESERVED1 |
| __IO uint16_t | BRR |
| uint16_t | RESERVED2 |
| __IO uint16_t | CR1 |
| uint16_t | RESERVED3 |
| __IO uint16_t | CR2 |
| uint16_t | RESERVED4 |
| __IO uint16_t | CR3 |
| uint16_t | RESERVED5 |
| __IO uint16_t | GTPR |
| uint16_t | RESERVED6 |
| __IO uint32_t | CFR |
| __IO uint32_t | SR |
| __IO uint32_t | SR |
| __IO uint32_t | DR |
| __IO uint32_t | DOUT |
| __IO uint32_t | DMACR |
| __IO uint32_t | IMSCR |
| __IO uint32_t | RISR |
| __IO uint32_t | MISR |
| __IO uint32_t | K0LR |
| __IO uint32_t | K0RR |
| __IO uint32_t | K1LR |
| __IO uint32_t | K1RR |
| __IO uint32_t | K2LR |
| __IO uint32_t | K2RR |
| __IO uint32_t | K3LR |
| __IO uint32_t | K3RR |
| __IO uint32_t | IV0LR |
| __IO uint32_t | IV0RR |
| __IO uint32_t | IV1LR |
| __IO uint32_t | IV1RR |
| __IO uint32_t | CSGCMCCM0R |
| __IO uint32_t | CSGCMCCM1R |
| __IO uint32_t | CSGCMCCM2R |
| __IO uint32_t | CSGCMCCM3R |
| __IO uint32_t | CSGCMCCM4R |
| __IO uint32_t | CSGCMCCM5R |
| __IO uint32_t | CSGCMCCM6R |
| __IO uint32_t | CSGCMCCM7R |
| __IO uint32_t | CSGCM0R |
| __IO uint32_t | CSGCM1R |
| __IO uint32_t | CSGCM2R |
| __IO uint32_t | CSGCM3R |
| __IO uint32_t | CSGCM4R |
| __IO uint32_t | CSGCM5R |
| __IO uint32_t | CSGCM6R |
| __IO uint32_t | CSGCM7R |
| __IO uint32_t | DIN |
| __IO uint32_t | STR |
| __IO uint32_t | HR [5] |
| __IO uint32_t | IMR |
| __IO uint32_t | SR |
| uint32_t | RESERVED [52] |
| __IO uint32_t | CSR [54] |
| __IO uint32_t | SR |
| __IO uint32_t | DR |
| __IO uint32_t | ICR |
| __IO uint32_t | IER |
| __IO uint32_t | CFGR |
| __IO uint32_t | CR |
| __IO uint32_t | CMP |
| __IO uint32_t | ARR |
| __IO uint32_t | CNT |
| __IO uint32_t | OR |
Variable Documentation
__IO uint32_t ABR [inherited] |
QUADSPI Alternate Bytes register, Address offset: 0x1C
Definition at line 1820 of file stm32f4xx.h.
__IO uint32_t AFR[2] [inherited] |
GPIO alternate function registers, Address offset: 0x20-0x24
Definition at line 1475 of file stm32f4xx.h.
__IO uint32_t AHB1ENR [inherited] |
RCC AHB1 peripheral clock register, Address offset: 0x30
Definition at line 1638 of file stm32f4xx.h.
__IO uint32_t AHB1LPENR [inherited] |
RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50
Definition at line 1645 of file stm32f4xx.h.
__IO uint32_t AHB1RSTR [inherited] |
RCC AHB1 peripheral reset register, Address offset: 0x10
Definition at line 1631 of file stm32f4xx.h.
__IO uint32_t AHB2ENR [inherited] |
RCC AHB2 peripheral clock register, Address offset: 0x34
Definition at line 1639 of file stm32f4xx.h.
__IO uint32_t AHB2LPENR [inherited] |
RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54
Definition at line 1646 of file stm32f4xx.h.
__IO uint32_t AHB2RSTR [inherited] |
RCC AHB2 peripheral reset register, Address offset: 0x14
Definition at line 1632 of file stm32f4xx.h.
__IO uint32_t AHB3ENR [inherited] |
RCC AHB3 peripheral clock register, Address offset: 0x38
Definition at line 1640 of file stm32f4xx.h.
__IO uint32_t AHB3LPENR [inherited] |
RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58
Definition at line 1647 of file stm32f4xx.h.
__IO uint32_t AHB3RSTR [inherited] |
RCC AHB3 peripheral reset register, Address offset: 0x18
Definition at line 1633 of file stm32f4xx.h.
__IO uint32_t ALRMAR [inherited] |
RTC alarm A register, Address offset: 0x1C
Definition at line 1677 of file stm32f4xx.h.
__IO uint32_t ALRMASSR [inherited] |
RTC alarm A sub second register, Address offset: 0x44
Definition at line 1687 of file stm32f4xx.h.
__IO uint32_t ALRMBR [inherited] |
RTC alarm B register, Address offset: 0x20
Definition at line 1678 of file stm32f4xx.h.
__IO uint32_t ALRMBSSR [inherited] |
RTC alarm B sub second register, Address offset: 0x48
Definition at line 1688 of file stm32f4xx.h.
__IO uint32_t AMTCR [inherited] |
DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C
Definition at line 1134 of file stm32f4xx.h.
__IO uint32_t APB1ENR [inherited] |
RCC APB1 peripheral clock enable register, Address offset: 0x40
Definition at line 1642 of file stm32f4xx.h.
__IO uint32_t APB1FZ [inherited] |
Debug MCU APB1 freeze register, Address offset: 0x08
Definition at line 1064 of file stm32f4xx.h.
__IO uint32_t APB1LPENR [inherited] |
RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60
Definition at line 1649 of file stm32f4xx.h.
__IO uint32_t APB1RSTR [inherited] |
RCC APB1 peripheral reset register, Address offset: 0x20
Definition at line 1635 of file stm32f4xx.h.
__IO uint32_t APB2ENR [inherited] |
RCC APB2 peripheral clock enable register, Address offset: 0x44
Definition at line 1643 of file stm32f4xx.h.
__IO uint32_t APB2FZ [inherited] |
Debug MCU APB2 freeze register, Address offset: 0x0C
Definition at line 1065 of file stm32f4xx.h.
__IO uint32_t APB2LPENR [inherited] |
RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64
Definition at line 1650 of file stm32f4xx.h.
__IO uint32_t APB2RSTR [inherited] |
RCC APB2 peripheral reset register, Address offset: 0x24
Definition at line 1636 of file stm32f4xx.h.
__IO uint32_t AR [inherited] |
QUADSPI Address register, Address offset: 0x18
Definition at line 1819 of file stm32f4xx.h.
__IO uint32_t ARG [inherited] |
SDIO argument register, Address offset: 0x08
Definition at line 1742 of file stm32f4xx.h.
__IO uint32_t ARR [inherited] |
TIM auto-reload register, Address offset: 0x2C
Definition at line 1875 of file stm32f4xx.h.
__IO uint32_t ARR [inherited] |
LPTIM Autoreload register, Address offset: 0x18
Definition at line 2017 of file stm32f4xx.h.
__IO uint32_t AWCR [inherited] |
LTDC Active Width Configuration Register, Address offset: 0x10
Definition at line 1572 of file stm32f4xx.h.
__IO uint32_t BCCR [inherited] |
LTDC Background Color Configuration Register, Address offset: 0x2C
Definition at line 1578 of file stm32f4xx.h.
__IO uint32_t BDCR [inherited] |
RCC Backup domain control register, Address offset: 0x70
Definition at line 1652 of file stm32f4xx.h.
__IO uint16_t BDTR [inherited] |
TIM break and dead-time register, Address offset: 0x44
Definition at line 1882 of file stm32f4xx.h.
__IO uint32_t BFCR [inherited] |
LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0
Definition at line 1601 of file stm32f4xx.h.
__IO uint32_t BGCLUT[256] [inherited] |
DMA2D Background CLUT, Address offset:800-BFF
Definition at line 1137 of file stm32f4xx.h.
__IO uint32_t BGCMAR [inherited] |
DMA2D Background CLUT Memory Address Register, Address offset: 0x30
Definition at line 1127 of file stm32f4xx.h.
__IO uint32_t BGCOLR [inherited] |
DMA2D Background Color Register, Address offset: 0x28
Definition at line 1125 of file stm32f4xx.h.
__IO uint32_t BGMAR [inherited] |
DMA2D Background Memory Address Register, Address offset: 0x14
Definition at line 1120 of file stm32f4xx.h.
__IO uint32_t BGOR [inherited] |
DMA2D Background Offset Register, Address offset: 0x18
Definition at line 1121 of file stm32f4xx.h.
__IO uint32_t BGPFCCR [inherited] |
DMA2D Background PFC Control Register, Address offset: 0x24
Definition at line 1124 of file stm32f4xx.h.
__IO uint32_t BKP0R [inherited] |
RTC backup register 1, Address offset: 0x50
Definition at line 1690 of file stm32f4xx.h.
__IO uint32_t BKP10R [inherited] |
RTC backup register 10, Address offset: 0x78
Definition at line 1700 of file stm32f4xx.h.
__IO uint32_t BKP11R [inherited] |
RTC backup register 11, Address offset: 0x7C
Definition at line 1701 of file stm32f4xx.h.
__IO uint32_t BKP12R [inherited] |
RTC backup register 12, Address offset: 0x80
Definition at line 1702 of file stm32f4xx.h.
__IO uint32_t BKP13R [inherited] |
RTC backup register 13, Address offset: 0x84
Definition at line 1703 of file stm32f4xx.h.
__IO uint32_t BKP14R [inherited] |
RTC backup register 14, Address offset: 0x88
Definition at line 1704 of file stm32f4xx.h.
__IO uint32_t BKP15R [inherited] |
RTC backup register 15, Address offset: 0x8C
Definition at line 1705 of file stm32f4xx.h.
__IO uint32_t BKP16R [inherited] |
RTC backup register 16, Address offset: 0x90
Definition at line 1706 of file stm32f4xx.h.
__IO uint32_t BKP17R [inherited] |
RTC backup register 17, Address offset: 0x94
Definition at line 1707 of file stm32f4xx.h.
__IO uint32_t BKP18R [inherited] |
RTC backup register 18, Address offset: 0x98
Definition at line 1708 of file stm32f4xx.h.
__IO uint32_t BKP19R [inherited] |
RTC backup register 19, Address offset: 0x9C
Definition at line 1709 of file stm32f4xx.h.
__IO uint32_t BKP1R [inherited] |
RTC backup register 1, Address offset: 0x54
Definition at line 1691 of file stm32f4xx.h.
__IO uint32_t BKP2R [inherited] |
RTC backup register 2, Address offset: 0x58
Definition at line 1692 of file stm32f4xx.h.
__IO uint32_t BKP3R [inherited] |
RTC backup register 3, Address offset: 0x5C
Definition at line 1693 of file stm32f4xx.h.
__IO uint32_t BKP4R [inherited] |
RTC backup register 4, Address offset: 0x60
Definition at line 1694 of file stm32f4xx.h.
__IO uint32_t BKP5R [inherited] |
RTC backup register 5, Address offset: 0x64
Definition at line 1695 of file stm32f4xx.h.
__IO uint32_t BKP6R [inherited] |
RTC backup register 6, Address offset: 0x68
Definition at line 1696 of file stm32f4xx.h.
__IO uint32_t BKP7R [inherited] |
RTC backup register 7, Address offset: 0x6C
Definition at line 1697 of file stm32f4xx.h.
__IO uint32_t BKP8R [inherited] |
RTC backup register 8, Address offset: 0x70
Definition at line 1698 of file stm32f4xx.h.
__IO uint32_t BKP9R [inherited] |
RTC backup register 9, Address offset: 0x74
Definition at line 1699 of file stm32f4xx.h.
__IO uint32_t BPCR [inherited] |
LTDC Back Porch Configuration Register, Address offset: 0x0C
Definition at line 1571 of file stm32f4xx.h.
__IO uint16_t BRR [inherited] |
USART Baud rate register, Address offset: 0x08
Definition at line 1902 of file stm32f4xx.h.
__IO uint32_t BSRR [inherited] |
GPIO port bit set/reset register, Address offset: 0x18
Definition at line 1473 of file stm32f4xx.h.
__IO uint32_t BTR [inherited] |
CAN bit timing register, Address offset: 0x1C
Definition at line 950 of file stm32f4xx.h.
__IO uint32_t CACR [inherited] |
LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98
Definition at line 1599 of file stm32f4xx.h.
__IO uint32_t CALIBR [inherited] |
RTC calibration register, Address offset: 0x18
Definition at line 1676 of file stm32f4xx.h.
__IO uint32_t CALR [inherited] |
RTC calibration register, Address offset: 0x3C
Definition at line 1685 of file stm32f4xx.h.
__IO uint16_t CCER [inherited] |
TIM capture/compare enable register, Address offset: 0x20
Definition at line 1870 of file stm32f4xx.h.
__IO uint16_t CCMR1 [inherited] |
TIM capture/compare mode register 1, Address offset: 0x18
Definition at line 1866 of file stm32f4xx.h.
__IO uint16_t CCMR2 [inherited] |
TIM capture/compare mode register 2, Address offset: 0x1C
Definition at line 1868 of file stm32f4xx.h.
__IO uint32_t CCR [inherited] |
DSI HOST Clock Control Register, Address offset: 0x08
Definition at line 1149 of file stm32f4xx.h.
__IO uint32_t CCR [inherited] |
QUADSPI Communication Configuration register, Address offset: 0x14
Definition at line 1818 of file stm32f4xx.h.
__IO uint16_t CCR [inherited] |
I2C Clock control register, Address offset: 0x1C
Definition at line 1522 of file stm32f4xx.h.
__IO uint32_t CCR [inherited] |
ADC common control register, Address offset: ADC1 base address + 0x304
Definition at line 897 of file stm32f4xx.h.
__IO uint32_t CCR1 [inherited] |
TIM capture/compare register 1, Address offset: 0x34
Definition at line 1878 of file stm32f4xx.h.
__IO uint32_t CCR2 [inherited] |
TIM capture/compare register 2, Address offset: 0x38
Definition at line 1879 of file stm32f4xx.h.
__IO uint32_t CCR3 [inherited] |
TIM capture/compare register 3, Address offset: 0x3C
Definition at line 1880 of file stm32f4xx.h.
__IO uint32_t CCR4 [inherited] |
TIM capture/compare register 4, Address offset: 0x40
Definition at line 1881 of file stm32f4xx.h.
__IO uint32_t CDR [inherited] |
ADC common regular data register for dual AND triple modes, Address offset: ADC1 base address + 0x308
Definition at line 898 of file stm32f4xx.h.
__IO uint32_t CDSR [inherited] |
LTDC Current Display Status Register, Address offset: 0x48
Definition at line 1585 of file stm32f4xx.h.
__IO uint32_t CFBAR [inherited] |
LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC
Definition at line 1603 of file stm32f4xx.h.
__IO uint32_t CFBLNR [inherited] |
LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4
Definition at line 1605 of file stm32f4xx.h.
__IO uint32_t CFBLR [inherited] |
LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0
Definition at line 1604 of file stm32f4xx.h.
__IO uint32_t CFGR [inherited] |
LPTIM Configuration register, Address offset: 0x0C
Definition at line 2014 of file stm32f4xx.h.
__IO uint32_t CFGR [inherited] |
SYSCFG Configuration register, Address offset: 0x2C
Definition at line 1492 of file stm32f4xx.h.
__IO uint32_t CFGR [inherited] |
RCC clock configuration register, Address offset: 0x08
Definition at line 1629 of file stm32f4xx.h.
__IO uint32_t CFGR [inherited] |
CEC configuration register, Address offset:0x04
Definition at line 974 of file stm32f4xx.h.
__IO uint32_t CFGR2 [inherited] |
Reserved, 0x1C
Definition at line 1489 of file stm32f4xx.h.
__IO uint32_t CFR [inherited] |
WWDG Configuration register, Address offset: 0x04
Definition at line 1921 of file stm32f4xx.h.
__IO uint32_t CHAWSCDR [inherited] |
DFSDM channel analog watchdog and short circuit detector register, Address offset: 0x08
Definition at line 1047 of file stm32f4xx.h.
__IO uint32_t CHCFGR2 [inherited] |
DFSDM channel configuration register2, Address offset: 0x04
Definition at line 1046 of file stm32f4xx.h.
__IO uint32_t CHDATINR [inherited] |
DFSDM channel data input register, Address offset: 0x10
Definition at line 1050 of file stm32f4xx.h.
__IO uint32_t CHWDATAR [inherited] |
DFSDM channel watchdog filter data register, Address offset: 0x0C
Definition at line 1049 of file stm32f4xx.h.
__IO uint32_t CIR [inherited] |
RCC clock interrupt register, Address offset: 0x0C
Definition at line 1630 of file stm32f4xx.h.
__IO uint32_t CKCR [inherited] |
LTDC Layerx Color Keying Configuration Register Address offset: 0x90
Definition at line 1597 of file stm32f4xx.h.
__IO uint32_t CKGATENR [inherited] |
RCC Clocks Gated Enable Register, Address offset: 0x90
Definition at line 1659 of file stm32f4xx.h.
__IO uint32_t CLCR [inherited] |
DSI Host Clock Lane Configuration Register, Address offset: 0x94
Definition at line 1176 of file stm32f4xx.h.
__IO uint32_t CLKCR [inherited] |
SDI clock control register, Address offset: 0x04
Definition at line 1741 of file stm32f4xx.h.
__IO uint32_t CLRFR [inherited] |
SAI block x clear flag register, Address offset: 0x1C
Definition at line 1730 of file stm32f4xx.h.
__IO uint32_t CLTCR [inherited] |
DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98
Definition at line 1177 of file stm32f4xx.h.
__IO uint32_t CLUTWR [inherited] |
LTDC Layerx CLUT Write Register Address offset: 0x144
Definition at line 1607 of file stm32f4xx.h.
__IO uint32_t CMCR [inherited] |
DSI Host Command Mode Configuration Register, Address offset: 0x68
Definition at line 1170 of file stm32f4xx.h.
__IO uint32_t CMD [inherited] |
SDIO command register, Address offset: 0x0C
Definition at line 1743 of file stm32f4xx.h.
__IO uint32_t CMP [inherited] |
LPTIM Compare register, Address offset: 0x14
Definition at line 2016 of file stm32f4xx.h.
__IO uint32_t CMPCR [inherited] |
SYSCFG Compensation cell control register, Address offset: 0x20
Definition at line 1490 of file stm32f4xx.h.
__IO uint32_t CNT [inherited] |
TIM counter register, Address offset: 0x24
Definition at line 1872 of file stm32f4xx.h.
__IO uint32_t CNT [inherited] |
LPTIM Counter register, Address offset: 0x1C
Definition at line 2018 of file stm32f4xx.h.
__IO uint32_t CPSR [inherited] |
LTDC Current Position Status Register, Address offset: 0x44
Definition at line 1584 of file stm32f4xx.h.
__IO uint32_t CR [inherited] |
DSI Host Control Register, Address offset: 0x04
Definition at line 1148 of file stm32f4xx.h.
__IO uint32_t CR [inherited] |
FLASH control register, Address offset: 0x10
Definition at line 1321 of file stm32f4xx.h.
__IO uint32_t CR [inherited] |
LPTIM Control register, Address offset: 0x10
Definition at line 2015 of file stm32f4xx.h.
__IO uint32_t CR [inherited] |
Debug MCU configuration register, Address offset: 0x04
Definition at line 1063 of file stm32f4xx.h.
__IO uint32_t CR [inherited] |
RTC control register, Address offset: 0x08
Definition at line 1672 of file stm32f4xx.h.
__IO uint32_t CR [inherited] |
CRC Control register, Address offset: 0x08
Definition at line 992 of file stm32f4xx.h.
__IO uint16_t CR1 [inherited] |
USART Control register 1, Address offset: 0x0C
Definition at line 1904 of file stm32f4xx.h.
__IO uint32_t CR1 [inherited] |
ADC control register 1, Address offset: 0x04
Definition at line 873 of file stm32f4xx.h.
__IO uint16_t CR2 [inherited] |
TIM control register 2, Address offset: 0x04
Definition at line 1856 of file stm32f4xx.h.
__IO uint16_t CR2 [inherited] |
USART Control register 2, Address offset: 0x10
Definition at line 1906 of file stm32f4xx.h.
__IO uint16_t CR2 [inherited] |
I2C Control register 2, Address offset: 0x04
Definition at line 1510 of file stm32f4xx.h.
__IO uint32_t CR2 [inherited] |
ADC control register 2, Address offset: 0x08
Definition at line 874 of file stm32f4xx.h.
__IO uint32_t CR2 [inherited] |
FMPI2C Control register 2, Address offset: 0x04
Definition at line 1538 of file stm32f4xx.h.
__IO uint32_t CR2 [inherited] |
SAI block x configuration register 2, Address offset: 0x08
Definition at line 1725 of file stm32f4xx.h.
__IO uint16_t CR2 [inherited] |
SPI control register 2, Address offset: 0x04
Definition at line 1770 of file stm32f4xx.h.
__IO uint16_t CR3 [inherited] |
USART Control register 3, Address offset: 0x14
Definition at line 1908 of file stm32f4xx.h.
__IO uint16_t CRCPR [inherited] |
SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10
Definition at line 1776 of file stm32f4xx.h.
__IO uint32_t CSGCM0R [inherited] |
CRYP GCM/GMAC context swap register 0, Address offset: 0x70
Definition at line 1959 of file stm32f4xx.h.
__IO uint32_t CSGCM1R [inherited] |
CRYP GCM/GMAC context swap register 1, Address offset: 0x74
Definition at line 1960 of file stm32f4xx.h.
__IO uint32_t CSGCM2R [inherited] |
CRYP GCM/GMAC context swap register 2, Address offset: 0x78
Definition at line 1961 of file stm32f4xx.h.
__IO uint32_t CSGCM3R [inherited] |
CRYP GCM/GMAC context swap register 3, Address offset: 0x7C
Definition at line 1962 of file stm32f4xx.h.
__IO uint32_t CSGCM4R [inherited] |
CRYP GCM/GMAC context swap register 4, Address offset: 0x80
Definition at line 1963 of file stm32f4xx.h.
__IO uint32_t CSGCM5R [inherited] |
CRYP GCM/GMAC context swap register 5, Address offset: 0x84
Definition at line 1964 of file stm32f4xx.h.
__IO uint32_t CSGCM6R [inherited] |
CRYP GCM/GMAC context swap register 6, Address offset: 0x88
Definition at line 1965 of file stm32f4xx.h.
__IO uint32_t CSGCM7R [inherited] |
CRYP GCM/GMAC context swap register 7, Address offset: 0x8C
Definition at line 1966 of file stm32f4xx.h.
__IO uint32_t CSGCMCCM0R [inherited] |
CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50
Definition at line 1951 of file stm32f4xx.h.
__IO uint32_t CSGCMCCM1R [inherited] |
CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54
Definition at line 1952 of file stm32f4xx.h.
__IO uint32_t CSGCMCCM2R [inherited] |
CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58
Definition at line 1953 of file stm32f4xx.h.
__IO uint32_t CSGCMCCM3R [inherited] |
CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C
Definition at line 1954 of file stm32f4xx.h.
__IO uint32_t CSGCMCCM4R [inherited] |
CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60
Definition at line 1955 of file stm32f4xx.h.
__IO uint32_t CSGCMCCM5R [inherited] |
CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64
Definition at line 1956 of file stm32f4xx.h.
__IO uint32_t CSGCMCCM6R [inherited] |
CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68
Definition at line 1957 of file stm32f4xx.h.
__IO uint32_t CSGCMCCM7R [inherited] |
CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C
Definition at line 1958 of file stm32f4xx.h.
__IO uint32_t CSR [inherited] |
Channel Status register, Address offset: 0x14
Definition at line 1801 of file stm32f4xx.h.
__IO uint32_t CSR [inherited] |
Channel Status register, Address offset: 0x14
Definition at line 1842 of file stm32f4xx.h.
__IO uint32_t CSR [inherited] |
PWR power control/status register, Address offset: 0x04
Definition at line 1618 of file stm32f4xx.h.
__IO uint32_t CSR[54] [inherited] |
HASH context swap registers, Address offset: 0x0F8-0x1CC
Definition at line 1982 of file stm32f4xx.h.
__IO uint32_t CSR [inherited] |
RCC clock control & status register, Address offset: 0x74
Definition at line 1653 of file stm32f4xx.h.
__IO uint32_t CWSIZER [inherited] |
DCMI crop window size, Address offset: 0x24
Definition at line 1083 of file stm32f4xx.h.
__IO uint32_t CWSTRTR [inherited] |
DCMI crop window start, Address offset: 0x20
Definition at line 1082 of file stm32f4xx.h.
__IO uint32_t DCCR [inherited] |
LTDC Layerx Default Color Configuration Register Address offset: 0x9C
Definition at line 1600 of file stm32f4xx.h.
__IO uint32_t DCKCFGR [inherited] |
RCC Dedicated Clocks configuration register, Address offset: 0x8C
Definition at line 1658 of file stm32f4xx.h.
__IO uint32_t DCKCFGR2 [inherited] |
RCC Dedicated Clocks configuration register 2, Address offset: 0x94
Definition at line 1660 of file stm32f4xx.h.
__I uint32_t DCOUNT [inherited] |
SDIO data counter register, Address offset: 0x30
Definition at line 1752 of file stm32f4xx.h.
__IO uint32_t DCR [inherited] |
QUADSPI Device Configuration register, Address offset: 0x04
Definition at line 1814 of file stm32f4xx.h.
__IO uint16_t DCR [inherited] |
TIM DMA control register, Address offset: 0x48
Definition at line 1884 of file stm32f4xx.h.
__IO uint32_t DCTRL [inherited] |
SDIO data control register, Address offset: 0x2C
Definition at line 1751 of file stm32f4xx.h.
__IO uint32_t DHR12L1 [inherited] |
DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C
Definition at line 1004 of file stm32f4xx.h.
__IO uint32_t DHR12L2 [inherited] |
DAC channel2 12-bit left aligned data holding register, Address offset: 0x18
Definition at line 1007 of file stm32f4xx.h.
__IO uint32_t DHR12LD [inherited] |
DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24
Definition at line 1010 of file stm32f4xx.h.
__IO uint32_t DHR12R1 [inherited] |
DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08
Definition at line 1003 of file stm32f4xx.h.
__IO uint32_t DHR12R2 [inherited] |
DAC channel2 12-bit right aligned data holding register, Address offset: 0x14
Definition at line 1006 of file stm32f4xx.h.
__IO uint32_t DHR12RD [inherited] |
Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20
Definition at line 1009 of file stm32f4xx.h.
__IO uint32_t DHR8R1 [inherited] |
DAC channel1 8-bit right aligned data holding register, Address offset: 0x10
Definition at line 1005 of file stm32f4xx.h.
__IO uint32_t DHR8R2 [inherited] |
DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C
Definition at line 1008 of file stm32f4xx.h.
__IO uint32_t DHR8RD [inherited] |
DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28
Definition at line 1011 of file stm32f4xx.h.
__IO uint16_t DIER [inherited] |
TIM DMA/interrupt enable register, Address offset: 0x0C
Definition at line 1860 of file stm32f4xx.h.
__IO uint32_t DIN [inherited] |
HASH data input register, Address offset: 0x04
Definition at line 1976 of file stm32f4xx.h.
__IO uint32_t DIR [inherited] |
Debug Information register, Address offset: 0x18
Definition at line 1802 of file stm32f4xx.h.
__IO uint32_t DIR [inherited] |
Debug Information register, Address offset: 0x18
Definition at line 1843 of file stm32f4xx.h.
__IO uint32_t DLEN [inherited] |
SDIO data length register, Address offset: 0x28
Definition at line 1750 of file stm32f4xx.h.
__IO uint32_t DLR [inherited] |
QUADSPI Data Length register, Address offset: 0x10
Definition at line 1817 of file stm32f4xx.h.
__IO uint32_t DLTCR [inherited] |
DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C
Definition at line 1178 of file stm32f4xx.h.
__IO uint32_t DMACR [inherited] |
CRYP DMA control register, Address offset: 0x10
Definition at line 1935 of file stm32f4xx.h.
__IO uint16_t DMAR [inherited] |
TIM DMA address for full transfer, Address offset: 0x4C
Definition at line 1886 of file stm32f4xx.h.
__IO uint32_t DOR1 [inherited] |
DAC channel1 data output register, Address offset: 0x2C
Definition at line 1012 of file stm32f4xx.h.
__IO uint32_t DOR2 [inherited] |
DAC channel2 data output register, Address offset: 0x30
Definition at line 1013 of file stm32f4xx.h.
__IO uint32_t DOUT [inherited] |
CRYP data output register, Address offset: 0x0C
Definition at line 1934 of file stm32f4xx.h.
__IO uint32_t DR [inherited] |
Data input register, Address offset: 0x10
Definition at line 1841 of file stm32f4xx.h.
__IO uint32_t DR [inherited] |
QUADSPI Data register, Address offset: 0x20
Definition at line 1821 of file stm32f4xx.h.
__IO uint16_t DR [inherited] |
USART Data register, Address offset: 0x04
Definition at line 1900 of file stm32f4xx.h.
__IO uint32_t DR [inherited] |
CRYP data input register, Address offset: 0x08
Definition at line 1933 of file stm32f4xx.h.
__IO uint32_t DR [inherited] |
RNG data register, Address offset: 0x08
Definition at line 2002 of file stm32f4xx.h.
__IO uint16_t DR [inherited] |
I2C Data register, Address offset: 0x10
Definition at line 1516 of file stm32f4xx.h.
__IO uint32_t DR [inherited] |
ADC regular data register, Address offset: 0x4C
Definition at line 891 of file stm32f4xx.h.
__IO uint32_t DR [inherited] |
DCMI data register, Address offset: 0x28
Definition at line 1084 of file stm32f4xx.h.
__IO uint32_t DR [inherited] |
RTC date register, Address offset: 0x04
Definition at line 1671 of file stm32f4xx.h.
__IO uint32_t DR [inherited] |
SAI block x data register, Address offset: 0x20
Definition at line 1731 of file stm32f4xx.h.
__IO uint16_t DR [inherited] |
SPI data register, Address offset: 0x0C
Definition at line 1774 of file stm32f4xx.h.
__IO uint32_t DR [inherited] |
Data input register, Address offset: 0x10
Definition at line 1800 of file stm32f4xx.h.
__IO uint32_t DTIMER [inherited] |
SDIO data timer register, Address offset: 0x24
Definition at line 1749 of file stm32f4xx.h.
__IO uint32_t ECCR2 [inherited] |
NAND Flash ECC result registers 2, Address offset: 0x74
Definition at line 1356 of file stm32f4xx.h.
__IO uint32_t ECCR2 [inherited] |
NAND Flash ECC result registers 2, Address offset: 0x74
Definition at line 1417 of file stm32f4xx.h.
__IO uint32_t ECCR3 [inherited] |
NAND Flash ECC result registers 3, Address offset: 0x94
Definition at line 1370 of file stm32f4xx.h.
__IO uint32_t ECCR3 [inherited] |
NAND Flash ECC result registers 3, Address offset: 0x94
Definition at line 1431 of file stm32f4xx.h.
__IO uint16_t EGR [inherited] |
TIM event generation register, Address offset: 0x14
Definition at line 1864 of file stm32f4xx.h.
__IO uint32_t EMR [inherited] |
EXTI Event mask register, Address offset: 0x04
Definition at line 1304 of file stm32f4xx.h.
__IO uint32_t ESCR [inherited] |
DCMI embedded synchronization code register, Address offset: 0x18
Definition at line 1080 of file stm32f4xx.h.
__IO uint32_t ESR [inherited] |
CAN error status register, Address offset: 0x18
Definition at line 949 of file stm32f4xx.h.
__IO uint32_t ESUR [inherited] |
DCMI embedded synchronization unmask register, Address offset: 0x1C
Definition at line 1081 of file stm32f4xx.h.
__IO uint32_t EXTICR[4] [inherited] |
SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14
Definition at line 1486 of file stm32f4xx.h.
__IO uint32_t FA1R [inherited] |
CAN filter activation register, Address offset: 0x21C
Definition at line 962 of file stm32f4xx.h.
__IO uint32_t FCR [inherited] |
QUADSPI Flag Clear register, Address offset: 0x0C
Definition at line 1816 of file stm32f4xx.h.
__IO uint32_t FCR [inherited] |
DMA stream x FIFO control register
Definition at line 1098 of file stm32f4xx.h.
__IO uint32_t FFA1R [inherited] |
CAN filter FIFO assignment register, Address offset: 0x214
Definition at line 960 of file stm32f4xx.h.
__IO uint32_t FGCLUT[256] [inherited] |
DMA2D Foreground CLUT, Address offset:400-7FF
Definition at line 1136 of file stm32f4xx.h.
__IO uint32_t FGCMAR [inherited] |
DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C
Definition at line 1126 of file stm32f4xx.h.
__IO uint32_t FGCOLR [inherited] |
DMA2D Foreground Color Register, Address offset: 0x20
Definition at line 1123 of file stm32f4xx.h.
__IO uint32_t FGMAR [inherited] |
DMA2D Foreground Memory Address Register, Address offset: 0x0C
Definition at line 1118 of file stm32f4xx.h.
__IO uint32_t FGOR [inherited] |
DMA2D Foreground Offset Register, Address offset: 0x10
Definition at line 1119 of file stm32f4xx.h.
__IO uint32_t FGPFCCR [inherited] |
DMA2D Foreground PFC Control Register, Address offset: 0x1C
Definition at line 1122 of file stm32f4xx.h.
__IO uint32_t FIFO [inherited] |
SDIO data FIFO register, Address offset: 0x80
Definition at line 1759 of file stm32f4xx.h.
__I uint32_t FIFOCNT [inherited] |
SDIO FIFO counter register, Address offset: 0x48
Definition at line 1757 of file stm32f4xx.h.
__IO uint32_t FIR[2] [inherited] |
DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF
Definition at line 1188 of file stm32f4xx.h.
__IO uint32_t FLTAWCFR [inherited] |
DFSDM analog watchdog clear flag register Address offset: 0x12C
Definition at line 1034 of file stm32f4xx.h.
__IO uint32_t FLTAWHTR [inherited] |
DFSDM analog watchdog high threshold register, Address offset: 0x120
Definition at line 1031 of file stm32f4xx.h.
__IO uint32_t FLTAWLTR [inherited] |
DFSDM analog watchdog low threshold register, Address offset: 0x124
Definition at line 1032 of file stm32f4xx.h.
__IO uint32_t FLTAWSR [inherited] |
DFSDM analog watchdog status register Address offset: 0x128
Definition at line 1033 of file stm32f4xx.h.
__IO uint32_t FLTCNVTIMR [inherited] |
DFSDM conversion timer, Address offset: 0x138
Definition at line 1037 of file stm32f4xx.h.
__IO uint32_t FLTCR2 [inherited] |
DFSDM control register2, Address offset: 0x104
Definition at line 1024 of file stm32f4xx.h.
__IO uint32_t FLTEXMAX [inherited] |
DFSDM extreme detector maximum register, Address offset: 0x130
Definition at line 1035 of file stm32f4xx.h.
__IO uint32_t FLTEXMIN [inherited] |
DFSDM extreme detector minimum register Address offset: 0x134
Definition at line 1036 of file stm32f4xx.h.
__IO uint32_t FLTFCR [inherited] |
DFSDM filter control register, Address offset: 0x114
Definition at line 1028 of file stm32f4xx.h.
__IO uint32_t FLTICR [inherited] |
DFSDM interrupt flag clear register, Address offset: 0x10C
Definition at line 1026 of file stm32f4xx.h.
__IO uint32_t FLTISR [inherited] |
DFSDM interrupt and status register, Address offset: 0x108
Definition at line 1025 of file stm32f4xx.h.
__IO uint32_t FLTJCHGR [inherited] |
DFSDM injected channel group selection register, Address offset: 0x110
Definition at line 1027 of file stm32f4xx.h.
__IO uint32_t FLTJDATAR [inherited] |
DFSDM data register for injected group, Address offset: 0x118
Definition at line 1029 of file stm32f4xx.h.
__IO uint16_t FLTR [inherited] |
I2C FLTR register, Address offset: 0x24
Definition at line 1526 of file stm32f4xx.h.
__IO uint32_t FLTRDATAR [inherited] |
DFSDM data register for regular group, Address offset: 0x11C
Definition at line 1030 of file stm32f4xx.h.
__IO uint32_t FM1R [inherited] |
CAN filter mode register, Address offset: 0x204
Definition at line 956 of file stm32f4xx.h.
__IO uint32_t FMR [inherited] |
CAN filter master register, Address offset: 0x200
Definition at line 955 of file stm32f4xx.h.
__IO uint32_t FR2 [inherited] |
CAN Filter bank register 1
Definition at line 934 of file stm32f4xx.h.
__IO uint32_t FRCR [inherited] |
SAI block x frame configuration register, Address offset: 0x0C
Definition at line 1726 of file stm32f4xx.h.
__IO uint32_t FS1R [inherited] |
CAN filter scale register, Address offset: 0x20C
Definition at line 958 of file stm32f4xx.h.
__IO uint32_t FTSR [inherited] |
EXTI Falling trigger selection register, Address offset: 0x0C
Definition at line 1306 of file stm32f4xx.h.
__IO uint32_t GCR [inherited] |
LTDC Global Control Register, Address offset: 0x18
Definition at line 1574 of file stm32f4xx.h.
__IO uint32_t GHCR [inherited] |
DSI Host Generic Header Configuration Register, Address offset: 0x6C
Definition at line 1171 of file stm32f4xx.h.
__IO uint32_t GPDR [inherited] |
DSI Host Generic Payload Data Register, Address offset: 0x70
Definition at line 1172 of file stm32f4xx.h.
__IO uint32_t GPSR [inherited] |
DSI Host Generic Packet Status Register, Address offset: 0x74
Definition at line 1173 of file stm32f4xx.h.
__IO uint16_t GTPR [inherited] |
USART Guard time and prescaler register, Address offset: 0x18
Definition at line 1910 of file stm32f4xx.h.
__IO uint32_t GVCIDR [inherited] |
DSI Host Generic VCID Register, Address offset: 0x30
Definition at line 1156 of file stm32f4xx.h.
__IO uint32_t HIFCR [inherited] |
DMA high interrupt flag clear register, Address offset: 0x0C
Definition at line 1106 of file stm32f4xx.h.
__IO uint32_t HISR [inherited] |
DMA high interrupt status register, Address offset: 0x04
Definition at line 1104 of file stm32f4xx.h.
__IO uint32_t HR[5] [inherited] |
HASH digest registers, Address offset: 0x0C-0x1C
Definition at line 1978 of file stm32f4xx.h.
__IO uint32_t HTR [inherited] |
ADC watchdog higher threshold register, Address offset: 0x24
Definition at line 881 of file stm32f4xx.h.
__IO uint16_t I2SCFGR [inherited] |
SPI_I2S configuration register, Address offset: 0x1C
Definition at line 1782 of file stm32f4xx.h.
__IO uint16_t I2SPR [inherited] |
SPI_I2S prescaler register, Address offset: 0x20
Definition at line 1784 of file stm32f4xx.h.
__IO uint32_t ICR [inherited] |
LPTIM Interrupt Clear register, Address offset: 0x04
Definition at line 2012 of file stm32f4xx.h.
__IO uint32_t ICR [inherited] |
FMPI2C Interrupt clear register, Address offset: 0x1C
Definition at line 1544 of file stm32f4xx.h.
__IO uint32_t ICR [inherited] |
LTDC Interrupt Clear Register, Address offset: 0x3C
Definition at line 1582 of file stm32f4xx.h.
__IO uint32_t ICR [inherited] |
DCMI interrupt clear register, Address offset: 0x14
Definition at line 1079 of file stm32f4xx.h.
__IO uint32_t ICR [inherited] |
SDIO interrupt clear register, Address offset: 0x38
Definition at line 1754 of file stm32f4xx.h.
__IO uint32_t IDR [inherited] |
GPIO port input data register, Address offset: 0x10
Definition at line 1471 of file stm32f4xx.h.
__IO uint8_t IDR [inherited] |
CRC Independent data register, Address offset: 0x04
Definition at line 989 of file stm32f4xx.h.
__IO uint32_t IER [inherited] |
CAN interrupt enable register, Address offset: 0x14
Definition at line 948 of file stm32f4xx.h.
__IO uint32_t IER[2] [inherited] |
DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB
Definition at line 1186 of file stm32f4xx.h.
__IO uint32_t IER [inherited] |
LTDC Interrupt Enable Register, Address offset: 0x34
Definition at line 1580 of file stm32f4xx.h.
__IO uint32_t IER [inherited] |
DCMI interrupt enable register, Address offset: 0x0C
Definition at line 1077 of file stm32f4xx.h.
__IO uint32_t IER [inherited] |
LPTIM Interrupt Enable register, Address offset: 0x08
Definition at line 2013 of file stm32f4xx.h.
__IO uint32_t IER [inherited] |
CEC interrupt enable register, Address offset:0x14
Definition at line 978 of file stm32f4xx.h.
__IO uint16_t IFCR [inherited] |
Interrupt Flag Clear register, Address offset: 0x0C
Definition at line 1839 of file stm32f4xx.h.
__IO uint32_t IFCR [inherited] |
DMA2D Interrupt Flag Clear Register, Address offset: 0x08
Definition at line 1117 of file stm32f4xx.h.
__IO uint16_t IFCR [inherited] |
Interrupt Flag Clear register, Address offset: 0x0C
Definition at line 1798 of file stm32f4xx.h.
__IO uint32_t IMR [inherited] |
HASH interrupt enable register, Address offset: 0x20
Definition at line 1979 of file stm32f4xx.h.
__IO uint32_t IMR [inherited] |
SAI block x interrupt mask register, Address offset: 0x14
Definition at line 1728 of file stm32f4xx.h.
__IO uint16_t IMR [inherited] |
Interrupt mask register, Address offset: 0x04
Definition at line 1836 of file stm32f4xx.h.
__IO uint16_t IMR [inherited] |
Interrupt mask register, Address offset: 0x04
Definition at line 1795 of file stm32f4xx.h.
__IO uint32_t IMSCR [inherited] |
CRYP interrupt mask set/clear register, Address offset: 0x14
Definition at line 1936 of file stm32f4xx.h.
__IO uint32_t ISR[2] [inherited] |
DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3
Definition at line 1185 of file stm32f4xx.h.
__IO uint32_t ISR [inherited] |
FMPI2C Interrupt and status register, Address offset: 0x18
Definition at line 1543 of file stm32f4xx.h.
__IO uint32_t ISR [inherited] |
LTDC Interrupt Status Register, Address offset: 0x38
Definition at line 1581 of file stm32f4xx.h.
__IO uint32_t ISR [inherited] |
RTC initialization and status register, Address offset: 0x0C
Definition at line 1673 of file stm32f4xx.h.
__IO uint32_t ISR [inherited] |
CEC Interrupt and Status Register, Address offset:0x10
Definition at line 977 of file stm32f4xx.h.
__IO uint32_t ISR [inherited] |
DMA2D Interrupt Status Register, Address offset: 0x04
Definition at line 1116 of file stm32f4xx.h.
__IO uint32_t IV0LR [inherited] |
CRYP initialization vector left-word register 0, Address offset: 0x40
Definition at line 1947 of file stm32f4xx.h.
__IO uint32_t IV0RR [inherited] |
CRYP initialization vector right-word register 0, Address offset: 0x44
Definition at line 1948 of file stm32f4xx.h.
__IO uint32_t IV1LR [inherited] |
CRYP initialization vector left-word register 1, Address offset: 0x48
Definition at line 1949 of file stm32f4xx.h.
__IO uint32_t IV1RR [inherited] |
CRYP initialization vector right-word register 1, Address offset: 0x4C
Definition at line 1950 of file stm32f4xx.h.
__IO uint32_t JDR1 [inherited] |
ADC injected data register 1, Address offset: 0x3C
Definition at line 887 of file stm32f4xx.h.
__IO uint32_t JDR2 [inherited] |
ADC injected data register 2, Address offset: 0x40
Definition at line 888 of file stm32f4xx.h.
__IO uint32_t JDR3 [inherited] |
ADC injected data register 3, Address offset: 0x44
Definition at line 889 of file stm32f4xx.h.
__IO uint32_t JDR4 [inherited] |
ADC injected data register 4, Address offset: 0x48
Definition at line 890 of file stm32f4xx.h.
__IO uint32_t JOFR1 [inherited] |
ADC injected channel data offset register 1, Address offset: 0x14
Definition at line 877 of file stm32f4xx.h.
__IO uint32_t JOFR2 [inherited] |
ADC injected channel data offset register 2, Address offset: 0x18
Definition at line 878 of file stm32f4xx.h.
__IO uint32_t JOFR3 [inherited] |
ADC injected channel data offset register 3, Address offset: 0x1C
Definition at line 879 of file stm32f4xx.h.
__IO uint32_t JOFR4 [inherited] |
ADC injected channel data offset register 4, Address offset: 0x20
Definition at line 880 of file stm32f4xx.h.
__IO uint32_t JSQR [inherited] |
ADC injected sequence register, Address offset: 0x38
Definition at line 886 of file stm32f4xx.h.
__IO uint32_t K0LR [inherited] |
CRYP key left register 0, Address offset: 0x20
Definition at line 1939 of file stm32f4xx.h.
__IO uint32_t K0RR [inherited] |
CRYP key right register 0, Address offset: 0x24
Definition at line 1940 of file stm32f4xx.h.
__IO uint32_t K1LR [inherited] |
CRYP key left register 1, Address offset: 0x28
Definition at line 1941 of file stm32f4xx.h.
__IO uint32_t K1RR [inherited] |
CRYP key right register 1, Address offset: 0x2C
Definition at line 1942 of file stm32f4xx.h.
__IO uint32_t K2LR [inherited] |
CRYP key left register 2, Address offset: 0x30
Definition at line 1943 of file stm32f4xx.h.
__IO uint32_t K2RR [inherited] |
CRYP key right register 2, Address offset: 0x34
Definition at line 1944 of file stm32f4xx.h.
__IO uint32_t K3LR [inherited] |
CRYP key left register 3, Address offset: 0x38
Definition at line 1945 of file stm32f4xx.h.
__IO uint32_t K3RR [inherited] |
CRYP key right register 3, Address offset: 0x3C
Definition at line 1946 of file stm32f4xx.h.
__IO uint32_t KEYR [inherited] |
FLASH key register, Address offset: 0x04
Definition at line 1318 of file stm32f4xx.h.
__IO uint32_t LCCCR [inherited] |
DSI Host LTDC Current Color Coding Register, Address offset: 0x110
Definition at line 1193 of file stm32f4xx.h.
__IO uint32_t LCCR [inherited] |
DSI Host LTDC Command Configuration Register, Address offset: 0x64
Definition at line 1169 of file stm32f4xx.h.
__IO uint32_t LCKR [inherited] |
GPIO port configuration lock register, Address offset: 0x1C
Definition at line 1474 of file stm32f4xx.h.
__IO uint32_t LCOLCR [inherited] |
DSI Host LTDC Color Coding Register, Address offset: 0x10
Definition at line 1151 of file stm32f4xx.h.
__IO uint32_t LCVCIDR [inherited] |
DSI Host LTDC Current VCID Register, Address offset: 0x10C
Definition at line 1192 of file stm32f4xx.h.
__IO uint32_t LIFCR [inherited] |
DMA low interrupt flag clear register, Address offset: 0x08
Definition at line 1105 of file stm32f4xx.h.
__IO uint32_t LIPCR [inherited] |
LTDC Line Interrupt Position Configuration Register, Address offset: 0x40
Definition at line 1583 of file stm32f4xx.h.
__IO uint32_t LPCR [inherited] |
DSI Host LTDC Polarity Configuration Register, Address offset: 0x14
Definition at line 1152 of file stm32f4xx.h.
__IO uint32_t LPMCCR [inherited] |
DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118
Definition at line 1195 of file stm32f4xx.h.
__IO uint32_t LPMCR [inherited] |
DSI Host Low-Power Mode Configuration Register, Address offset: 0x18
Definition at line 1153 of file stm32f4xx.h.
__IO uint32_t LPTR [inherited] |
QUADSPI Low Power Timeout register, Address offset: 0x30
Definition at line 1825 of file stm32f4xx.h.
__IO uint32_t LTR [inherited] |
ADC watchdog lower threshold register, Address offset: 0x28
Definition at line 882 of file stm32f4xx.h.
__IO uint32_t LVCIDR [inherited] |
DSI Host LTDC VCID Register, Address offset: 0x0C
Definition at line 1150 of file stm32f4xx.h.
__IO uint32_t LWR [inherited] |
DMA2D Line Watermark Register, Address offset: 0x48
Definition at line 1133 of file stm32f4xx.h.
__IO uint32_t M0AR [inherited] |
DMA stream x memory 0 address register
Definition at line 1096 of file stm32f4xx.h.
__IO uint32_t M1AR [inherited] |
DMA stream x memory 1 address register
Definition at line 1097 of file stm32f4xx.h.
__IO uint32_t MASK [inherited] |
SDIO mask register, Address offset: 0x3C
Definition at line 1755 of file stm32f4xx.h.
__IO uint32_t MCHDLYCR [inherited] |
SYSCFG multi-channel delay register, Address offset: 0x30
Definition at line 1498 of file stm32f4xx.h.
__IO uint32_t MCR [inherited] |
DSI Host Mode Configuration Register, Address offset: 0x34
Definition at line 1157 of file stm32f4xx.h.
__IO uint32_t MISR [inherited] |
CRYP masked interrupt status register, Address offset: 0x1C
Definition at line 1938 of file stm32f4xx.h.
__IO uint32_t MISR [inherited] |
DCMI masked interrupt status register, Address offset: 0x10
Definition at line 1078 of file stm32f4xx.h.
__IO uint32_t MSR [inherited] |
CAN master status register, Address offset: 0x04
Definition at line 944 of file stm32f4xx.h.
__IO uint32_t NDTR [inherited] |
DMA stream x number of data register
Definition at line 1094 of file stm32f4xx.h.
__IO uint32_t NLR [inherited] |
DMA2D Number of Line Register, Address offset: 0x44
Definition at line 1132 of file stm32f4xx.h.
__IO uint16_t OAR1 [inherited] |
I2C Own address register 1, Address offset: 0x08
Definition at line 1512 of file stm32f4xx.h.
__IO uint32_t OAR1 [inherited] |
FMPI2C Own address 1 register, Address offset: 0x08
Definition at line 1539 of file stm32f4xx.h.
__IO uint16_t OAR2 [inherited] |
I2C Own address register 2, Address offset: 0x0C
Definition at line 1514 of file stm32f4xx.h.
__IO uint32_t OAR2 [inherited] |
FMPI2C Own address 2 register, Address offset: 0x0C
Definition at line 1540 of file stm32f4xx.h.
__IO uint32_t OCOLR [inherited] |
DMA2D Output Color Register, Address offset: 0x38
Definition at line 1129 of file stm32f4xx.h.
__IO uint32_t ODR [inherited] |
GPIO port output data register, Address offset: 0x14
Definition at line 1472 of file stm32f4xx.h.
__IO uint32_t OMAR [inherited] |
DMA2D Output Memory Address Register, Address offset: 0x3C
Definition at line 1130 of file stm32f4xx.h.
__IO uint32_t OOR [inherited] |
DMA2D Output Offset Register, Address offset: 0x40
Definition at line 1131 of file stm32f4xx.h.
__IO uint32_t OPFCCR [inherited] |
DMA2D Output PFC Control Register, Address offset: 0x34
Definition at line 1128 of file stm32f4xx.h.
__IO uint32_t OPTCR [inherited] |
FLASH option control register , Address offset: 0x14
Definition at line 1322 of file stm32f4xx.h.
__IO uint32_t OPTCR1 [inherited] |
FLASH option control register 1, Address offset: 0x18
Definition at line 1323 of file stm32f4xx.h.
__IO uint32_t OPTKEYR [inherited] |
FLASH option key register, Address offset: 0x08
Definition at line 1319 of file stm32f4xx.h.
__IO uint32_t OR [inherited] |
LPTIM Option register, Address offset: 0x20
Definition at line 2019 of file stm32f4xx.h.
__IO uint16_t OR [inherited] |
TIM option register, Address offset: 0x50
Definition at line 1888 of file stm32f4xx.h.
__IO uint32_t OSPEEDR [inherited] |
GPIO port output speed register, Address offset: 0x08
Definition at line 1469 of file stm32f4xx.h.
__IO uint32_t OTYPER [inherited] |
GPIO port output type register, Address offset: 0x04
Definition at line 1468 of file stm32f4xx.h.
__IO uint32_t PAR [inherited] |
DMA stream x peripheral address register
Definition at line 1095 of file stm32f4xx.h.
__IO uint32_t PATT2 [inherited] |
NAND Flash Attribute memory space timing register 2, Address offset: 0x6C
Definition at line 1354 of file stm32f4xx.h.
__IO uint32_t PATT2 [inherited] |
NAND Flash Attribute memory space timing register 2, Address offset: 0x6C
Definition at line 1415 of file stm32f4xx.h.
__IO uint32_t PATT3 [inherited] |
NAND Flash Attribute memory space timing register 3, Address offset: 0x8C
Definition at line 1368 of file stm32f4xx.h.
__IO uint32_t PATT3 [inherited] |
NAND Flash Attribute memory space timing register 3, Address offset: 0x8C
Definition at line 1429 of file stm32f4xx.h.
__IO uint32_t PATT4 [inherited] |
PC Card Attribute memory space timing register 4, Address offset: 0xAC
Definition at line 1382 of file stm32f4xx.h.
__IO uint32_t PATT4 [inherited] |
PC Card Attribute memory space timing register 4, Address offset: 0xAC
Definition at line 1443 of file stm32f4xx.h.
__IO uint32_t PCONFR [inherited] |
DSI Host PHY Configuration Register, Address offset: 0xA4
Definition at line 1180 of file stm32f4xx.h.
__IO uint32_t PCR [inherited] |
DSI Host Protocol Configuration Register, Address offset: 0x2C
Definition at line 1155 of file stm32f4xx.h.
__IO uint32_t PCTLR [inherited] |
DSI Host PHY Control Register, Address offset: 0xA0
Definition at line 1179 of file stm32f4xx.h.
__IO uint32_t PECR [inherited] |
FMPI2C PEC register, Address offset: 0x20
Definition at line 1545 of file stm32f4xx.h.
__IO uint32_t PFCR [inherited] |
LTDC Layerx Pixel Format Configuration Register Address offset: 0x94
Definition at line 1598 of file stm32f4xx.h.
__IO uint32_t PIO4 [inherited] |
PC Card I/O space timing register 4, Address offset: 0xB0
Definition at line 1444 of file stm32f4xx.h.
__IO uint32_t PIO4 [inherited] |
PC Card I/O space timing register 4, Address offset: 0xB0
Definition at line 1383 of file stm32f4xx.h.
__IO uint32_t PIR [inherited] |
QUADSPI Polling Interval register, Address offset: 0x2C
Definition at line 1824 of file stm32f4xx.h.
__IO uint32_t PLLCFGR [inherited] |
RCC PLL configuration register, Address offset: 0x04
Definition at line 1628 of file stm32f4xx.h.
__IO uint32_t PLLI2SCFGR [inherited] |
RCC PLLI2S configuration register, Address offset: 0x84
Definition at line 1656 of file stm32f4xx.h.
__IO uint32_t PLLSAICFGR [inherited] |
RCC PLLSAI configuration register, Address offset: 0x88
Definition at line 1657 of file stm32f4xx.h.
__IO uint32_t PMC [inherited] |
SYSCFG peripheral mode configuration register, Address offset: 0x04
Definition at line 1485 of file stm32f4xx.h.
__IO uint32_t PMEM2 [inherited] |
NAND Flash Common memory space timing register 2, Address offset: 0x68
Definition at line 1414 of file stm32f4xx.h.
__IO uint32_t PMEM2 [inherited] |
NAND Flash Common memory space timing register 2, Address offset: 0x68
Definition at line 1353 of file stm32f4xx.h.
__IO uint32_t PMEM3 [inherited] |
NAND Flash Common memory space timing register 3, Address offset: 0x88
Definition at line 1367 of file stm32f4xx.h.
__IO uint32_t PMEM3 [inherited] |
NAND Flash Common memory space timing register 3, Address offset: 0x88
Definition at line 1428 of file stm32f4xx.h.
__IO uint32_t PMEM4 [inherited] |
PC Card Common memory space timing register 4, Address offset: 0xA8
Definition at line 1442 of file stm32f4xx.h.
__IO uint32_t PMEM4 [inherited] |
PC Card Common memory space timing register 4, Address offset: 0xA8
Definition at line 1381 of file stm32f4xx.h.
__IO uint32_t PR [inherited] |
EXTI Pending register, Address offset: 0x14
Definition at line 1308 of file stm32f4xx.h.
__IO uint32_t PR [inherited] |
IWDG Prescaler register, Address offset: 0x04
Definition at line 1558 of file stm32f4xx.h.
__IO uint32_t PRER [inherited] |
RTC prescaler register, Address offset: 0x10
Definition at line 1674 of file stm32f4xx.h.
__IO uint16_t PSC [inherited] |
TIM prescaler, Address offset: 0x28
Definition at line 1873 of file stm32f4xx.h.
__IO uint32_t PSMAR [inherited] |
QUADSPI Polling Status Match register, Address offset: 0x28
Definition at line 1823 of file stm32f4xx.h.
__IO uint32_t PSMKR [inherited] |
QUADSPI Polling Status Mask register, Address offset: 0x24
Definition at line 1822 of file stm32f4xx.h.
__IO uint32_t PSR [inherited] |
DSI Host PHY Status Register, Address offset: 0xB0
Definition at line 1183 of file stm32f4xx.h.
__IO uint32_t PTTCR [inherited] |
DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC
Definition at line 1182 of file stm32f4xx.h.
__IO uint32_t PUCR [inherited] |
DSI Host PHY ULPS Control Register, Address offset: 0xA8
Definition at line 1181 of file stm32f4xx.h.
__IO uint32_t PUPDR [inherited] |
GPIO port pull-up/pull-down register, Address offset: 0x0C
Definition at line 1470 of file stm32f4xx.h.
__IO uint16_t RCR [inherited] |
TIM repetition counter register, Address offset: 0x30
Definition at line 1876 of file stm32f4xx.h.
__IO uint32_t RDHR [inherited] |
CAN receive FIFO mailbox data high register
Definition at line 924 of file stm32f4xx.h.
__IO uint32_t RDLR [inherited] |
CAN receive FIFO mailbox data low register
Definition at line 923 of file stm32f4xx.h.
__IO uint32_t RDTR [inherited] |
CAN receive FIFO mailbox data length control and time stamp register
Definition at line 922 of file stm32f4xx.h.
uint32_t RESERVED [inherited] |
uint32_t RESERVED[52] [inherited] |
Reserved, 0x28-0xF4
Definition at line 1981 of file stm32f4xx.h.
uint32_t RESERVED[236] [inherited] |
Reserved, 0x50-0x3FF
Definition at line 1135 of file stm32f4xx.h.
uint32_t RESERVED0 [inherited] |
Reserved, 0x70
Definition at line 1416 of file stm32f4xx.h.
uint16_t RESERVED0 [inherited] |
Reserved, 0x06
Definition at line 1837 of file stm32f4xx.h.
uint32_t RESERVED0 [inherited] |
Reserved, 0x70
Definition at line 1355 of file stm32f4xx.h.
uint32_t RESERVED0[88] [inherited] |
Reserved, 0x020 - 0x17F
Definition at line 951 of file stm32f4xx.h.
uint16_t RESERVED0 [inherited] |
Reserved, 0x06
Definition at line 1796 of file stm32f4xx.h.
uint32_t RESERVED0 [inherited] |
Reserved, 0x90
Definition at line 1430 of file stm32f4xx.h.
uint32_t RESERVED0[4] [inherited] |
Reserved, 0x1C - 0x2B
Definition at line 1154 of file stm32f4xx.h.
uint16_t RESERVED0 [inherited] |
Reserved, 0x02
Definition at line 1855 of file stm32f4xx.h.
uint16_t RESERVED0 [inherited] |
Reserved, 0x02
Definition at line 1509 of file stm32f4xx.h.
uint32_t RESERVED0[2] [inherited] |
Reserved
Definition at line 1602 of file stm32f4xx.h.
uint32_t RESERVED0 [inherited] |
Reserved, 0x90
Definition at line 1369 of file stm32f4xx.h.
uint32_t RESERVED0 [inherited] |
Reserved, 0x1C
Definition at line 1634 of file stm32f4xx.h.
uint16_t RESERVED0 [inherited] |
Reserved, 0x02
Definition at line 1899 of file stm32f4xx.h.
uint8_t RESERVED0 [inherited] |
Reserved, 0x05
Definition at line 990 of file stm32f4xx.h.
uint16_t RESERVED0 [inherited] |
Reserved, 0x02
Definition at line 1769 of file stm32f4xx.h.
uint32_t RESERVED0[2] [inherited] |
Reserved, 0x40-0x44
Definition at line 1756 of file stm32f4xx.h.
uint16_t RESERVED1 [inherited] |
Reserved, 0x06
Definition at line 1771 of file stm32f4xx.h.
uint16_t RESERVED1 [inherited] |
Reserved, 0x06
Definition at line 1857 of file stm32f4xx.h.
uint32_t RESERVED1[13] [inherited] |
Reserved, 0x4C-0x7C
Definition at line 1758 of file stm32f4xx.h.
uint16_t RESERVED1 [inherited] |
Reserved, 0x06
Definition at line 991 of file stm32f4xx.h.
uint16_t RESERVED1 [inherited] |
Reserved, 0x0E
Definition at line 1840 of file stm32f4xx.h.
uint32_t RESERVED1[12] [inherited] |
Reserved, 0x1D0 - 0x1FF
Definition at line 954 of file stm32f4xx.h.
uint16_t RESERVED1 [inherited] |
Reserved, 0x0E
Definition at line 1799 of file stm32f4xx.h.
uint32_t RESERVED1[2] [inherited] |
Reserved, 0x24-0x28
Definition at line 1491 of file stm32f4xx.h.
uint16_t RESERVED1 [inherited] |
Reserved, 0x06
Definition at line 1511 of file stm32f4xx.h.
uint32_t RESERVED1[2] [inherited] |
Reserved, 0xB4 - 0xBB
Definition at line 1184 of file stm32f4xx.h.
uint32_t RESERVED1[2] [inherited] |
Reserved, 0x1C-0x20
Definition at line 1575 of file stm32f4xx.h.
uint32_t RESERVED1[3] [inherited] |
Reserved
Definition at line 1606 of file stm32f4xx.h.
uint16_t RESERVED1 [inherited] |
Reserved, 0x06
Definition at line 1901 of file stm32f4xx.h.
uint32_t RESERVED1[2] [inherited] |
Reserved, 0x28-0x2C
Definition at line 1637 of file stm32f4xx.h.
uint16_t RESERVED10 [inherited] |
Reserved, 0x32
Definition at line 1877 of file stm32f4xx.h.
uint32_t RESERVED10 [inherited] |
Reserved, 0x42C
Definition at line 1218 of file stm32f4xx.h.
uint16_t RESERVED11 [inherited] |
Reserved, 0x46
Definition at line 1883 of file stm32f4xx.h.
uint16_t RESERVED12 [inherited] |
Reserved, 0x4A
Definition at line 1885 of file stm32f4xx.h.
uint16_t RESERVED13 [inherited] |
Reserved, 0x4E
Definition at line 1887 of file stm32f4xx.h.
uint16_t RESERVED14 [inherited] |
Reserved, 0x52
Definition at line 1889 of file stm32f4xx.h.
uint16_t RESERVED2 [inherited] |
Reserved, 0x0A
Definition at line 1513 of file stm32f4xx.h.
uint16_t RESERVED2 [inherited] |
Reserved, 0x1A
Definition at line 1844 of file stm32f4xx.h.
uint16_t RESERVED2 [inherited] |
Reserved, 0x1A
Definition at line 1803 of file stm32f4xx.h.
uint16_t RESERVED2 [inherited] |
Reserved, 0x0A
Definition at line 1859 of file stm32f4xx.h.
uint32_t RESERVED2 [inherited] |
Reserved, 0x3C
Definition at line 1641 of file stm32f4xx.h.
uint32_t RESERVED2 [inherited] |
Reserved, 0x208
Definition at line 957 of file stm32f4xx.h.
uint32_t RESERVED2[3] [inherited] |
Reserved, 0xD0 - 0xD7
Definition at line 1187 of file stm32f4xx.h.
uint16_t RESERVED2 [inherited] |
Reserved, 0x0A
Definition at line 1773 of file stm32f4xx.h.
uint32_t RESERVED2[1] [inherited] |
Reserved, 0x28
Definition at line 1577 of file stm32f4xx.h.
uint16_t RESERVED2 [inherited] |
Reserved, 0x0A
Definition at line 1903 of file stm32f4xx.h.
uint16_t RESERVED3 [inherited] |
Reserved, 0x0E
Definition at line 1515 of file stm32f4xx.h.
uint32_t RESERVED3[1] [inherited] |
Reserved, 0x30
Definition at line 1579 of file stm32f4xx.h.
uint32_t RESERVED3[8] [inherited] |
Reserved, 0xE0 - 0xFF
Definition at line 1189 of file stm32f4xx.h.
uint32_t RESERVED3 [inherited] |
Reserved, 0x210
Definition at line 959 of file stm32f4xx.h.
uint16_t RESERVED3 [inherited] |
Reserved, 0x0E
Definition at line 1905 of file stm32f4xx.h.
uint16_t RESERVED3 [inherited] |
Reserved, 0x0E
Definition at line 1775 of file stm32f4xx.h.
uint32_t RESERVED3[2] [inherited] |
Reserved, 0x48-0x4C
Definition at line 1644 of file stm32f4xx.h.
uint16_t RESERVED3 [inherited] |
Reserved, 0x0E
Definition at line 1861 of file stm32f4xx.h.
uint16_t RESERVED4 [inherited] |
Reserved, 0x12
Definition at line 1863 of file stm32f4xx.h.
uint16_t RESERVED4 [inherited] |
Reserved, 0x12
Definition at line 1517 of file stm32f4xx.h.
uint16_t RESERVED4 [inherited] |
Reserved, 0x12
Definition at line 1907 of file stm32f4xx.h.
uint32_t RESERVED4[2] [inherited] |
Reserved, 0x104 - 0x10B
Definition at line 1191 of file stm32f4xx.h.
uint32_t RESERVED4 [inherited] |
Reserved, 0x218
Definition at line 961 of file stm32f4xx.h.
uint16_t RESERVED4 [inherited] |
Reserved, 0x12
Definition at line 1777 of file stm32f4xx.h.
uint32_t RESERVED4 [inherited] |
Reserved, 0x5C
Definition at line 1648 of file stm32f4xx.h.
uint16_t RESERVED5 [inherited] |
Reserved, 0x16
Definition at line 1779 of file stm32f4xx.h.
uint16_t RESERVED5 [inherited] |
Reserved, 0x16
Definition at line 1909 of file stm32f4xx.h.
uint16_t RESERVED5 [inherited] |
Reserved, 0x16
Definition at line 1519 of file stm32f4xx.h.
uint32_t RESERVED5 [inherited] |
Reserved, 0x114
Definition at line 1194 of file stm32f4xx.h.
uint16_t RESERVED5 [inherited] |
Reserved, 0x16
Definition at line 1865 of file stm32f4xx.h.
uint32_t RESERVED5[2] [inherited] |
Reserved, 0x68-0x6C
Definition at line 1651 of file stm32f4xx.h.
uint32_t RESERVED5[8] [inherited] |
Reserved, 0x220-0x23F
Definition at line 963 of file stm32f4xx.h.
uint16_t RESERVED6 [inherited] |
Reserved, 0x1A
Definition at line 1911 of file stm32f4xx.h.
uint16_t RESERVED6 [inherited] |
Reserved, 0x1A
Definition at line 1781 of file stm32f4xx.h.
uint16_t RESERVED6 [inherited] |
Reserved, 0x1A
Definition at line 1521 of file stm32f4xx.h.
uint16_t RESERVED6 [inherited] |
Reserved, 0x1A
Definition at line 1867 of file stm32f4xx.h.
uint32_t RESERVED6[7] [inherited] |
Reserved, 0x11C - 0x137
Definition at line 1196 of file stm32f4xx.h.
uint32_t RESERVED6[2] [inherited] |
Reserved, 0x78-0x7C
Definition at line 1654 of file stm32f4xx.h.
uint32_t RESERVED7 [inherited] |
Reserved, 0x4C
Definition at line 1689 of file stm32f4xx.h.
uint32_t RESERVED7[11] [inherited] |
Reserved, 0x164 - 0x18F
Definition at line 1208 of file stm32f4xx.h.
uint16_t RESERVED7 [inherited] |
Reserved, 0x1E
Definition at line 1783 of file stm32f4xx.h.
uint16_t RESERVED7 [inherited] |
Reserved, 0x1E
Definition at line 1523 of file stm32f4xx.h.
uint16_t RESERVED7 [inherited] |
Reserved, 0x1E
Definition at line 1869 of file stm32f4xx.h.
uint16_t RESERVED8 [inherited] |
Reserved, 0x22
Definition at line 1525 of file stm32f4xx.h.
uint32_t RESERVED8[155] [inherited] |
Reserved, 0x194 - 0x3FF
Definition at line 1210 of file stm32f4xx.h.
uint16_t RESERVED8 [inherited] |
Reserved, 0x22
Definition at line 1785 of file stm32f4xx.h.
uint16_t RESERVED8 [inherited] |
Reserved, 0x22
Definition at line 1871 of file stm32f4xx.h.
uint16_t RESERVED9 [inherited] |
Reserved, 0x2A
Definition at line 1874 of file stm32f4xx.h.
uint32_t RESERVED9 [inherited] |
Reserved, 0x414
Definition at line 1216 of file stm32f4xx.h.
uint16_t RESERVED9 [inherited] |
Reserved, 0x26
Definition at line 1527 of file stm32f4xx.h.
__I uint32_t RESP1 [inherited] |
SDIO response 1 register, Address offset: 0x14
Definition at line 1745 of file stm32f4xx.h.
__I uint32_t RESP2 [inherited] |
SDIO response 2 register, Address offset: 0x18
Definition at line 1746 of file stm32f4xx.h.
__I uint32_t RESP3 [inherited] |
SDIO response 3 register, Address offset: 0x1C
Definition at line 1747 of file stm32f4xx.h.
__I uint32_t RESP4 [inherited] |
SDIO response 4 register, Address offset: 0x20
Definition at line 1748 of file stm32f4xx.h.
__I uint32_t RESPCMD [inherited] |
SDIO command response register, Address offset: 0x10
Definition at line 1744 of file stm32f4xx.h.
__IO uint32_t RF0R [inherited] |
CAN receive FIFO 0 register, Address offset: 0x0C
Definition at line 946 of file stm32f4xx.h.
__IO uint32_t RF1R [inherited] |
CAN receive FIFO 1 register, Address offset: 0x10
Definition at line 947 of file stm32f4xx.h.
__IO uint32_t RISR [inherited] |
CRYP raw interrupt status register, Address offset: 0x18
Definition at line 1937 of file stm32f4xx.h.
__IO uint32_t RISR [inherited] |
DCMI raw interrupt status register, Address offset: 0x08
Definition at line 1076 of file stm32f4xx.h.
__IO uint32_t RLR [inherited] |
IWDG Reload register, Address offset: 0x08
Definition at line 1559 of file stm32f4xx.h.
__IO uint32_t RTSR [inherited] |
EXTI Rising trigger selection register, Address offset: 0x08
Definition at line 1305 of file stm32f4xx.h.
__IO uint16_t RXCRCR [inherited] |
SPI RX CRC register (not used in I2S mode), Address offset: 0x14
Definition at line 1778 of file stm32f4xx.h.
__IO uint32_t RXDR [inherited] |
FMPI2C Receive data register, Address offset: 0x24
Definition at line 1546 of file stm32f4xx.h.
__IO uint32_t RXDR [inherited] |
CEC Rx Data Register, Address offset:0x0C
Definition at line 976 of file stm32f4xx.h.
__IO uint32_t SDCMR [inherited] |
SDRAM Command Mode register, Address offset: 0x150
Definition at line 1455 of file stm32f4xx.h.
__IO uint32_t SDRTR [inherited] |
SDRAM Refresh Timer register, Address offset: 0x154
Definition at line 1456 of file stm32f4xx.h.
__IO uint32_t SDSR [inherited] |
SDRAM Status register, Address offset: 0x158
Definition at line 1457 of file stm32f4xx.h.
__IO uint32_t SDTR[2] [inherited] |
SDRAM Timing registers , Address offset: 0x148-0x14C
Definition at line 1454 of file stm32f4xx.h.
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2] [inherited] |
CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC
Definition at line 953 of file stm32f4xx.h.
CAN_FilterRegister_TypeDef sFilterRegister[28] [inherited] |
CAN Filter Register, Address offset: 0x240-0x31C
Definition at line 964 of file stm32f4xx.h.
__IO uint32_t SHIFTR [inherited] |
RTC shift control register, Address offset: 0x2C
Definition at line 1681 of file stm32f4xx.h.
__IO uint32_t SLOTR [inherited] |
SAI block x slot register, Address offset: 0x10
Definition at line 1727 of file stm32f4xx.h.
__IO uint16_t SMCR [inherited] |
TIM slave mode control register, Address offset: 0x08
Definition at line 1858 of file stm32f4xx.h.
__IO uint32_t SMPR1 [inherited] |
ADC sample time register 1, Address offset: 0x0C
Definition at line 875 of file stm32f4xx.h.
__IO uint32_t SMPR2 [inherited] |
ADC sample time register 2, Address offset: 0x10
Definition at line 876 of file stm32f4xx.h.
__IO uint32_t SQR1 [inherited] |
ADC regular sequence register 1, Address offset: 0x2C
Definition at line 883 of file stm32f4xx.h.
__IO uint32_t SQR2 [inherited] |
ADC regular sequence register 2, Address offset: 0x30
Definition at line 884 of file stm32f4xx.h.
__IO uint32_t SQR3 [inherited] |
ADC regular sequence register 3, Address offset: 0x34
Definition at line 885 of file stm32f4xx.h.
__IO uint32_t SR [inherited] |
RNG status register, Address offset: 0x04
Definition at line 2001 of file stm32f4xx.h.
__IO uint32_t SR [inherited] |
SAI block x status register, Address offset: 0x18
Definition at line 1729 of file stm32f4xx.h.
__IO uint32_t SR [inherited] |
FLASH status register, Address offset: 0x0C
Definition at line 1320 of file stm32f4xx.h.
__IO uint32_t SR [inherited] |
DAC status register, Address offset: 0x34
Definition at line 1014 of file stm32f4xx.h.
__IO uint32_t SR [inherited] |
IWDG Status register, Address offset: 0x0C
Definition at line 1560 of file stm32f4xx.h.
__IO uint32_t SR [inherited] |
QUADSPI Status register, Address offset: 0x08
Definition at line 1815 of file stm32f4xx.h.
__IO uint32_t SR [inherited] |
Status register, Address offset: 0x08
Definition at line 1797 of file stm32f4xx.h.
__IO uint32_t SR [inherited] |
Status register, Address offset: 0x08
Definition at line 1838 of file stm32f4xx.h.
__IO uint32_t SR [inherited] |
WWDG Status register, Address offset: 0x08
Definition at line 1922 of file stm32f4xx.h.
__IO uint16_t SR [inherited] |
SPI status register, Address offset: 0x08
Definition at line 1772 of file stm32f4xx.h.
__IO uint32_t SR [inherited] |
DCMI status register, Address offset: 0x04
Definition at line 1075 of file stm32f4xx.h.
__IO uint32_t SR [inherited] |
HASH status register, Address offset: 0x24
Definition at line 1980 of file stm32f4xx.h.
__IO uint32_t SR [inherited] |
CRYP status register, Address offset: 0x04
Definition at line 1932 of file stm32f4xx.h.
__IO uint16_t SR [inherited] |
TIM status register, Address offset: 0x10
Definition at line 1862 of file stm32f4xx.h.
__IO uint16_t SR1 [inherited] |
I2C Status register 1, Address offset: 0x14
Definition at line 1518 of file stm32f4xx.h.
__IO uint32_t SR2 [inherited] |
NAND Flash FIFO status and interrupt register 2, Address offset: 0x64
Definition at line 1352 of file stm32f4xx.h.
__IO uint16_t SR2 [inherited] |
I2C Status register 2, Address offset: 0x18
Definition at line 1520 of file stm32f4xx.h.
__IO uint32_t SR2 [inherited] |
NAND Flash FIFO status and interrupt register 2, Address offset: 0x64
Definition at line 1413 of file stm32f4xx.h.
__IO uint32_t SR3 [inherited] |
NAND Flash FIFO status and interrupt register 3, Address offset: 0x84
Definition at line 1366 of file stm32f4xx.h.
__IO uint32_t SR3 [inherited] |
NAND Flash FIFO status and interrupt register 3, Address offset: 0x84
Definition at line 1427 of file stm32f4xx.h.
__IO uint32_t SR4 [inherited] |
PC Card FIFO status and interrupt register 4, Address offset: 0xA4
Definition at line 1380 of file stm32f4xx.h.
__IO uint32_t SR4 [inherited] |
PC Card FIFO status and interrupt register 4, Address offset: 0xA4
Definition at line 1441 of file stm32f4xx.h.
__IO uint32_t SRCR [inherited] |
LTDC Shadow Reload Configuration Register, Address offset: 0x24
Definition at line 1576 of file stm32f4xx.h.
__IO uint32_t SSCGR [inherited] |
RCC spread spectrum clock generation register, Address offset: 0x80
Definition at line 1655 of file stm32f4xx.h.
__IO uint32_t SSCR [inherited] |
LTDC Synchronization Size Configuration Register, Address offset: 0x08
Definition at line 1570 of file stm32f4xx.h.
__IO uint32_t SSR [inherited] |
RTC sub second register, Address offset: 0x28
Definition at line 1680 of file stm32f4xx.h.
__I uint32_t STA [inherited] |
SDIO status register, Address offset: 0x34
Definition at line 1753 of file stm32f4xx.h.
__IO uint32_t STR [inherited] |
HASH start register, Address offset: 0x08
Definition at line 1977 of file stm32f4xx.h.
CAN_TxMailBox_TypeDef sTxMailBox[3] [inherited] |
CAN Tx MailBox, Address offset: 0x180 - 0x1AC
Definition at line 952 of file stm32f4xx.h.
__IO uint32_t SWIER [inherited] |
EXTI Software interrupt event register, Address offset: 0x10
Definition at line 1307 of file stm32f4xx.h.
__IO uint32_t SWTRIGR [inherited] |
DAC software trigger register, Address offset: 0x04
Definition at line 1002 of file stm32f4xx.h.
__IO uint32_t TAFCR [inherited] |
RTC tamper and alternate function configuration register, Address offset: 0x40
Definition at line 1686 of file stm32f4xx.h.
__IO uint32_t TCCR[6] [inherited] |
DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F
Definition at line 1174 of file stm32f4xx.h.
__IO uint32_t TDCCR [inherited] |
DSI Host 3D Current Configuration Register, Address offset: 0x190
Definition at line 1209 of file stm32f4xx.h.
__IO uint32_t TDCR [inherited] |
DSI Host 3D Configuration Register, Address offset: 0x90
Definition at line 1175 of file stm32f4xx.h.
__IO uint32_t TDHR [inherited] |
CAN mailbox data high register
Definition at line 912 of file stm32f4xx.h.
__IO uint32_t TDLR [inherited] |
CAN mailbox data low register
Definition at line 911 of file stm32f4xx.h.
__IO uint32_t TDTR [inherited] |
CAN mailbox data length control and time stamp register
Definition at line 910 of file stm32f4xx.h.
__IO uint32_t TIMEOUTR [inherited] |
FMPI2C Timeout register, Address offset: 0x14
Definition at line 1542 of file stm32f4xx.h.
__IO uint32_t TIMINGR [inherited] |
FMPI2C Timing register, Address offset: 0x10
Definition at line 1541 of file stm32f4xx.h.
__IO uint16_t TRISE [inherited] |
I2C TRISE register, Address offset: 0x20
Definition at line 1524 of file stm32f4xx.h.
__IO uint32_t TSDR [inherited] |
RTC time stamp date register, Address offset: 0x34
Definition at line 1683 of file stm32f4xx.h.
__IO uint32_t TSR [inherited] |
CAN transmit status register, Address offset: 0x08
Definition at line 945 of file stm32f4xx.h.
__IO uint32_t TSSSR [inherited] |
RTC time-stamp sub second register, Address offset: 0x38
Definition at line 1684 of file stm32f4xx.h.
__IO uint32_t TSTR [inherited] |
RTC time stamp time register, Address offset: 0x30
Definition at line 1682 of file stm32f4xx.h.
__IO uint32_t TWCR [inherited] |
LTDC Total Width Configuration Register, Address offset: 0x14
Definition at line 1573 of file stm32f4xx.h.
__IO uint16_t TXCRCR [inherited] |
SPI TX CRC register (not used in I2S mode), Address offset: 0x18
Definition at line 1780 of file stm32f4xx.h.
__IO uint32_t TXDR [inherited] |
FMPI2C Transmit data register, Address offset: 0x28
Definition at line 1547 of file stm32f4xx.h.
__IO uint32_t TXDR [inherited] |
CEC Tx data register , Address offset:0x08
Definition at line 975 of file stm32f4xx.h.
__IO uint32_t VCCCR [inherited] |
DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140
Definition at line 1199 of file stm32f4xx.h.
__IO uint32_t VCCR [inherited] |
DSI Host Video Chunks Configuration Register, Address offset: 0x40
Definition at line 1160 of file stm32f4xx.h.
__IO uint32_t VHBPCCR [inherited] |
DSI Host Video HBP Current Configuration Register, Address offset: 0x14C
Definition at line 1202 of file stm32f4xx.h.
__IO uint32_t VHBPCR [inherited] |
DSI Host Video HBP Configuration Register, Address offset: 0x4C
Definition at line 1163 of file stm32f4xx.h.
__IO uint32_t VHSACCR [inherited] |
DSI Host Video HSA Current Configuration Register, Address offset: 0x148
Definition at line 1201 of file stm32f4xx.h.
__IO uint32_t VHSACR [inherited] |
DSI Host Video HSA Configuration Register, Address offset: 0x48
Definition at line 1162 of file stm32f4xx.h.
__IO uint32_t VLCCR [inherited] |
DSI Host Video Line Current Configuration Register, Address offset: 0x150
Definition at line 1203 of file stm32f4xx.h.
__IO uint32_t VLCR [inherited] |
DSI Host Video Line Configuration Register, Address offset: 0x50
Definition at line 1164 of file stm32f4xx.h.
__IO uint32_t VMCCR [inherited] |
DSI Host Video Mode Current Configuration Register, Address offset: 0x138
Definition at line 1197 of file stm32f4xx.h.
__IO uint32_t VMCR [inherited] |
DSI Host Video Mode Configuration Register, Address offset: 0x38
Definition at line 1158 of file stm32f4xx.h.
__IO uint32_t VNPCCR [inherited] |
DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144
Definition at line 1200 of file stm32f4xx.h.
__IO uint32_t VNPCR [inherited] |
DSI Host Video Null Packet Configuration Register, Address offset: 0x44
Definition at line 1161 of file stm32f4xx.h.
__IO uint32_t VPCCR [inherited] |
DSI Host Video Packet Current Configuration Register, Address offset: 0x13C
Definition at line 1198 of file stm32f4xx.h.
__IO uint32_t VPCR [inherited] |
DSI Host Video Packet Configuration Register, Address offset: 0x3C
Definition at line 1159 of file stm32f4xx.h.
__IO uint32_t VSCR [inherited] |
DSI Host Video Shadow Control Register, Address offset: 0x100
Definition at line 1190 of file stm32f4xx.h.
__IO uint32_t VVACCR [inherited] |
DSI Host Video VA Current Configuration Register, Address offset: 0x160
Definition at line 1207 of file stm32f4xx.h.
__IO uint32_t VVACR [inherited] |
DSI Host Video VA Configuration Register, Address offset: 0x60
Definition at line 1168 of file stm32f4xx.h.
__IO uint32_t VVBPCCR [inherited] |
DSI Host Video VBP Current Configuration Register, Address offset: 0x158
Definition at line 1205 of file stm32f4xx.h.
__IO uint32_t VVBPCR [inherited] |
DSI Host Video VBP Configuration Register, Address offset: 0x58
Definition at line 1166 of file stm32f4xx.h.
__IO uint32_t VVFPCCR [inherited] |
DSI Host Video VFP Current Configuration Register, Address offset: 0x15C
Definition at line 1206 of file stm32f4xx.h.
__IO uint32_t VVFPCR [inherited] |
DSI Host Video VFP Configuration Register, Address offset: 0x5C
Definition at line 1167 of file stm32f4xx.h.
__IO uint32_t VVSACCR [inherited] |
DSI Host Video VSA Current Configuration Register, Address offset: 0x154
Definition at line 1204 of file stm32f4xx.h.
__IO uint32_t VVSACR [inherited] |
DSI Host Video VSA Configuration Register, Address offset: 0x54
Definition at line 1165 of file stm32f4xx.h.
__IO uint32_t WCFGR [inherited] |
DSI Wrapper Configuration Register, Address offset: 0x400
Definition at line 1211 of file stm32f4xx.h.
__IO uint32_t WCR [inherited] |
DSI Wrapper Control Register, Address offset: 0x404
Definition at line 1212 of file stm32f4xx.h.
__IO uint32_t WHPCR [inherited] |
LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88
Definition at line 1595 of file stm32f4xx.h.
__IO uint32_t WIER [inherited] |
DSI Wrapper Interrupt Enable Register, Address offset: 0x408
Definition at line 1213 of file stm32f4xx.h.
__IO uint32_t WIFCR [inherited] |
DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410
Definition at line 1215 of file stm32f4xx.h.
__IO uint32_t WISR [inherited] |
DSI Wrapper Interrupt and Status Register, Address offset: 0x40C
Definition at line 1214 of file stm32f4xx.h.
__IO uint32_t WPCR[5] [inherited] |
DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B
Definition at line 1217 of file stm32f4xx.h.
__IO uint32_t WPR [inherited] |
RTC write protection register, Address offset: 0x24
Definition at line 1679 of file stm32f4xx.h.
__IO uint32_t WRPCR [inherited] |
DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430
Definition at line 1219 of file stm32f4xx.h.
__IO uint32_t WUTR [inherited] |
RTC wakeup timer register, Address offset: 0x14
Definition at line 1675 of file stm32f4xx.h.
__IO uint32_t WVPCR [inherited] |
LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C
Definition at line 1596 of file stm32f4xx.h.
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