zhang boie
/
mbed-dev-f30333
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
cmsis/core_armv8mml.h@0:bdf663c61a82, 2022-06-14 (annotated)
- Committer:
- abe5b02d-a2d4-4fe9-818e-c4e57c809ea4
- Date:
- Tue Jun 14 09:21:18 2022 +0000
- Revision:
- 0:bdf663c61a82
lib
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1 | /**************************************************************************//** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2 | * @file core_armv8mml.h |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 3 | * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 4 | * @version V5.0.2 |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 5 | * @date 13. February 2017 |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 6 | ******************************************************************************/ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 7 | /* |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 9 | * |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 10 | * SPDX-License-Identifier: Apache-2.0 |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 11 | * |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 13 | * not use this file except in compliance with the License. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 14 | * You may obtain a copy of the License at |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 15 | * |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 16 | * www.apache.org/licenses/LICENSE-2.0 |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 17 | * |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 18 | * Unless required by applicable law or agreed to in writing, software |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 21 | * See the License for the specific language governing permissions and |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 22 | * limitations under the License. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 23 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 24 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 25 | #if defined ( __ICCARM__ ) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 26 | #pragma system_include /* treat file as system include file for MISRA check */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 27 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 28 | #pragma clang system_header /* treat file as system include file */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 29 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 30 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 31 | #ifndef __CORE_ARMV8MML_H_GENERIC |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 32 | #define __CORE_ARMV8MML_H_GENERIC |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 33 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 34 | #include <stdint.h> |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 35 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 36 | #ifdef __cplusplus |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 37 | extern "C" { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 38 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 39 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 40 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 41 | \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 42 | CMSIS violates the following MISRA-C:2004 rules: |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 43 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 44 | \li Required Rule 8.5, object/function definition in header file.<br> |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 45 | Function definitions in header files are used to allow 'inlining'. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 46 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 47 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 48 | Unions are used for effective representation of core registers. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 49 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 50 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 51 | Function-like macros are used to allow more efficient code. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 52 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 53 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 54 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 55 | /******************************************************************************* |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 56 | * CMSIS definitions |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 57 | ******************************************************************************/ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 58 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 59 | \ingroup Cortex_ARMv8MML |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 60 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 61 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 62 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 63 | /* CMSIS ARMv8MML definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 64 | #define __ARMv8MML_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 65 | #define __ARMv8MML_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 66 | #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 67 | __ARMv8MML_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 68 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 69 | #define __CORTEX_M (81U) /*!< Cortex-M Core */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 70 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 71 | /** __FPU_USED indicates whether an FPU is used or not. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 72 | For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 73 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 74 | #if defined ( __CC_ARM ) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 75 | #if defined __TARGET_FPU_VFP |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 76 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 77 | #define __FPU_USED 1U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 78 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 79 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 80 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 81 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 82 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 83 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 84 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 85 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 86 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 87 | #if defined __ARM_PCS_VFP |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 88 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 89 | #define __FPU_USED 1U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 90 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 91 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 92 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 93 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 94 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 95 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 96 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 97 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 98 | #elif defined ( __GNUC__ ) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 99 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 100 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 101 | #define __FPU_USED 1U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 102 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 103 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 104 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 105 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 106 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 107 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 108 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 109 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 110 | #elif defined ( __ICCARM__ ) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 111 | #if defined __ARMVFP__ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 112 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 113 | #define __FPU_USED 1U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 114 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 115 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 116 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 117 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 118 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 119 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 120 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 121 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 122 | #elif defined ( __TI_ARM__ ) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 123 | #if defined __TI_VFP_SUPPORT__ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 124 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 125 | #define __FPU_USED 1U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 126 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 127 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 128 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 129 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 130 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 131 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 132 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 133 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 134 | #elif defined ( __TASKING__ ) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 135 | #if defined __FPU_VFP__ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 136 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 137 | #define __FPU_USED 1U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 138 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 139 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 140 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 141 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 142 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 143 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 144 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 145 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 146 | #elif defined ( __CSMC__ ) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 147 | #if ( __CSMC__ & 0x400U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 148 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 149 | #define __FPU_USED 1U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 150 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 151 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 152 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 153 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 154 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 155 | #define __FPU_USED 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 156 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 157 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 158 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 159 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 160 | #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 161 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 162 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 163 | #ifdef __cplusplus |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 164 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 165 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 166 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 167 | #endif /* __CORE_ARMV8MML_H_GENERIC */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 168 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 169 | #ifndef __CMSIS_GENERIC |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 170 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 171 | #ifndef __CORE_ARMV8MML_H_DEPENDANT |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 172 | #define __CORE_ARMV8MML_H_DEPENDANT |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 173 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 174 | #ifdef __cplusplus |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 175 | extern "C" { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 176 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 177 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 178 | /* check device defines and use defaults */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 179 | #if defined __CHECK_DEVICE_DEFINES |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 180 | #ifndef __ARMv8MML_REV |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 181 | #define __ARMv8MML_REV 0x0000U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 182 | #warning "__ARMv8MML_REV not defined in device header file; using default!" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 183 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 184 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 185 | #ifndef __FPU_PRESENT |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 186 | #define __FPU_PRESENT 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 187 | #warning "__FPU_PRESENT not defined in device header file; using default!" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 188 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 189 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 190 | #ifndef __MPU_PRESENT |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 191 | #define __MPU_PRESENT 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 192 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 193 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 194 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 195 | #ifndef __SAUREGION_PRESENT |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 196 | #define __SAUREGION_PRESENT 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 197 | #warning "__SAUREGION_PRESENT not defined in device header file; using default!" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 198 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 199 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 200 | #ifndef __DSP_PRESENT |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 201 | #define __DSP_PRESENT 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 202 | #warning "__DSP_PRESENT not defined in device header file; using default!" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 203 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 204 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 205 | #ifndef __NVIC_PRIO_BITS |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 206 | #define __NVIC_PRIO_BITS 3U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 207 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 208 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 209 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 210 | #ifndef __Vendor_SysTickConfig |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 211 | #define __Vendor_SysTickConfig 0U |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 212 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 213 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 214 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 215 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 216 | /* IO definitions (access restrictions to peripheral registers) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 217 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 218 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 219 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 220 | <strong>IO Type Qualifiers</strong> are used |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 221 | \li to specify the access to peripheral variables. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 222 | \li for automatic generation of peripheral register debug information. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 223 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 224 | #ifdef __cplusplus |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 225 | #define __I volatile /*!< Defines 'read only' permissions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 226 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 227 | #define __I volatile const /*!< Defines 'read only' permissions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 228 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 229 | #define __O volatile /*!< Defines 'write only' permissions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 230 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 231 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 232 | /* following defines should be used for structure members */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 233 | #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 234 | #define __OM volatile /*! Defines 'write only' structure member permissions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 235 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 236 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 237 | /*@} end of group ARMv8MML */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 238 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 239 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 240 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 241 | /******************************************************************************* |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 242 | * Register Abstraction |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 243 | Core Register contain: |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 244 | - Core Register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 245 | - Core NVIC Register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 246 | - Core SCB Register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 247 | - Core SysTick Register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 248 | - Core Debug Register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 249 | - Core MPU Register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 250 | - Core SAU Register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 251 | - Core FPU Register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 252 | ******************************************************************************/ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 253 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 254 | \defgroup CMSIS_core_register Defines and Type Definitions |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 255 | \brief Type definitions and defines for Cortex-M processor based devices. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 256 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 257 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 258 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 259 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 260 | \defgroup CMSIS_CORE Status and Control Registers |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 261 | \brief Core Register type definitions. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 262 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 263 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 264 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 265 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 266 | \brief Union type to access the Application Program Status Register (APSR). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 267 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 268 | typedef union |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 269 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 270 | struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 271 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 272 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 273 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 274 | uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 275 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 276 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 277 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 278 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 279 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 280 | } b; /*!< Structure used for bit access */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 281 | uint32_t w; /*!< Type used for word access */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 282 | } APSR_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 283 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 284 | /* APSR Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 285 | #define APSR_N_Pos 31U /*!< APSR: N Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 286 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 287 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 288 | #define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 289 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 290 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 291 | #define APSR_C_Pos 29U /*!< APSR: C Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 292 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 293 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 294 | #define APSR_V_Pos 28U /*!< APSR: V Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 295 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 296 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 297 | #define APSR_Q_Pos 27U /*!< APSR: Q Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 298 | #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 299 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 300 | #define APSR_GE_Pos 16U /*!< APSR: GE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 301 | #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 302 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 303 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 304 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 305 | \brief Union type to access the Interrupt Program Status Register (IPSR). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 306 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 307 | typedef union |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 308 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 309 | struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 310 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 311 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 312 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 313 | } b; /*!< Structure used for bit access */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 314 | uint32_t w; /*!< Type used for word access */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 315 | } IPSR_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 316 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 317 | /* IPSR Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 318 | #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 319 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 320 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 321 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 322 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 323 | \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 324 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 325 | typedef union |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 326 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 327 | struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 328 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 329 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 330 | uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 331 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 332 | uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 333 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 334 | uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 335 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 336 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 337 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 338 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 339 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 340 | } b; /*!< Structure used for bit access */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 341 | uint32_t w; /*!< Type used for word access */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 342 | } xPSR_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 343 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 344 | /* xPSR Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 345 | #define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 346 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 347 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 348 | #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 349 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 350 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 351 | #define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 352 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 353 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 354 | #define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 355 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 356 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 357 | #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 358 | #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 359 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 360 | #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 361 | #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 362 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 363 | #define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 364 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 365 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 366 | #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 367 | #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 368 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 369 | #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 370 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 371 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 372 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 373 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 374 | \brief Union type to access the Control Registers (CONTROL). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 375 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 376 | typedef union |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 377 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 378 | struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 379 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 380 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 381 | uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 382 | uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 383 | uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 384 | uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 385 | } b; /*!< Structure used for bit access */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 386 | uint32_t w; /*!< Type used for word access */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 387 | } CONTROL_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 388 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 389 | /* CONTROL Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 390 | #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 391 | #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 392 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 393 | #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 394 | #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 395 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 396 | #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 397 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 398 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 399 | #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 400 | #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 401 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 402 | /*@} end of group CMSIS_CORE */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 403 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 404 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 405 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 406 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 407 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 408 | \brief Type definitions for the NVIC Registers |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 409 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 410 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 411 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 412 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 413 | \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 414 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 415 | typedef struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 416 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 417 | __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 418 | uint32_t RESERVED0[16U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 419 | __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 420 | uint32_t RSERVED1[16U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 421 | __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 422 | uint32_t RESERVED2[16U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 423 | __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 424 | uint32_t RESERVED3[16U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 425 | __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 426 | uint32_t RESERVED4[16U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 427 | __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 428 | uint32_t RESERVED5[16U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 429 | __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 430 | uint32_t RESERVED6[580U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 431 | __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 432 | } NVIC_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 433 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 434 | /* Software Triggered Interrupt Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 435 | #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 436 | #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 437 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 438 | /*@} end of group CMSIS_NVIC */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 439 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 440 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 441 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 442 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 443 | \defgroup CMSIS_SCB System Control Block (SCB) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 444 | \brief Type definitions for the System Control Block Registers |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 445 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 446 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 447 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 448 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 449 | \brief Structure type to access the System Control Block (SCB). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 450 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 451 | typedef struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 452 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 453 | __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 454 | __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 455 | __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 456 | __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 457 | __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 458 | __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 459 | __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 460 | __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 461 | __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 462 | __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 463 | __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 464 | __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 465 | __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 466 | __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 467 | __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 468 | __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 469 | __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 470 | __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 471 | __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 472 | __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 473 | __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 474 | __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 475 | __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 476 | __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 477 | __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 478 | uint32_t RESERVED3[92U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 479 | __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 480 | uint32_t RESERVED4[15U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 481 | __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 482 | __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 483 | __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 484 | uint32_t RESERVED5[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 485 | __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 486 | uint32_t RESERVED6[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 487 | __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 488 | __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 489 | __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 490 | __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 491 | __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 492 | __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 493 | __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 494 | __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 495 | uint32_t RESERVED7[6U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 496 | __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 497 | __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 498 | __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 499 | __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 500 | __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 501 | uint32_t RESERVED8[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 502 | __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 503 | } SCB_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 504 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 505 | /* SCB CPUID Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 506 | #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 507 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 508 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 509 | #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 510 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 511 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 512 | #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 513 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 514 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 515 | #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 516 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 517 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 518 | #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 519 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 520 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 521 | /* SCB Interrupt Control State Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 522 | #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 523 | #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 524 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 525 | #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 526 | #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 527 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 528 | #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 529 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 530 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 531 | #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 532 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 533 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 534 | #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 535 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 536 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 537 | #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 538 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 539 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 540 | #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 541 | #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 542 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 543 | #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 544 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 545 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 546 | #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 547 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 548 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 549 | #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 550 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 551 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 552 | #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 553 | #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 554 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 555 | #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 556 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 557 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 558 | /* SCB Vector Table Offset Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 559 | #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 560 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 561 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 562 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 563 | #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 564 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 565 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 566 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 567 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 568 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 569 | #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 570 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 571 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 572 | #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 573 | #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 574 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 575 | #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 576 | #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 577 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 578 | #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 579 | #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 580 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 581 | #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 582 | #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 583 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 584 | #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 585 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 586 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 587 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 588 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 589 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 590 | /* SCB System Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 591 | #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 592 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 593 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 594 | #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 595 | #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 596 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 597 | #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 598 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 599 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 600 | #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 601 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 602 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 603 | /* SCB Configuration Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 604 | #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 605 | #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 606 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 607 | #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 608 | #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 609 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 610 | #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 611 | #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 612 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 613 | #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 614 | #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 615 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 616 | #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 617 | #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 618 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 619 | #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 620 | #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 621 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 622 | #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 623 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 624 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 625 | #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 626 | #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 627 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 628 | /* SCB System Handler Control and State Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 629 | #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 630 | #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 631 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 632 | #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 633 | #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 634 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 635 | #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 636 | #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 637 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 638 | #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 639 | #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 640 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 641 | #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 642 | #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 643 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 644 | #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 645 | #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 646 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 647 | #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 648 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 649 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 650 | #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 651 | #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 652 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 653 | #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 654 | #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 655 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 656 | #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 657 | #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 658 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 659 | #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 660 | #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 661 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 662 | #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 663 | #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 664 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 665 | #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 666 | #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 667 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 668 | #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 669 | #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 670 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 671 | #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 672 | #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 673 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 674 | #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 675 | #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 676 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 677 | #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 678 | #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 679 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 680 | #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 681 | #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 682 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 683 | #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 684 | #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 685 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 686 | #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 687 | #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 688 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 689 | /* SCB Configurable Fault Status Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 690 | #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 691 | #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 692 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 693 | #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 694 | #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 695 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 696 | #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 697 | #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 698 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 699 | /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 700 | #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 701 | #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 702 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 703 | #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 704 | #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 705 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 706 | #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 707 | #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 708 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 709 | #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 710 | #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 711 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 712 | #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 713 | #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 714 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 715 | #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 716 | #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 717 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 718 | /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 719 | #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 720 | #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 721 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 722 | #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 723 | #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 724 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 725 | #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 726 | #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 727 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 728 | #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 729 | #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 730 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 731 | #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 732 | #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 733 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 734 | #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 735 | #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 736 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 737 | #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 738 | #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 739 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 740 | /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 741 | #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 742 | #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 743 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 744 | #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 745 | #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 746 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 747 | #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 748 | #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 749 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 750 | #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 751 | #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 752 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 753 | #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 754 | #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 755 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 756 | #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 757 | #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 758 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 759 | #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 760 | #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 761 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 762 | /* SCB Hard Fault Status Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 763 | #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 764 | #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 765 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 766 | #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 767 | #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 768 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 769 | #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 770 | #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 771 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 772 | /* SCB Debug Fault Status Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 773 | #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 774 | #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 775 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 776 | #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 777 | #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 778 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 779 | #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 780 | #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 781 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 782 | #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 783 | #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 784 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 785 | #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 786 | #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 787 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 788 | /* SCB Non-Secure Access Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 789 | #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 790 | #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 791 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 792 | #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 793 | #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 794 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 795 | #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 796 | #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 797 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 798 | /* SCB Cache Level ID Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 799 | #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 800 | #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 801 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 802 | #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 803 | #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 804 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 805 | /* SCB Cache Type Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 806 | #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 807 | #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 808 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 809 | #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 810 | #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 811 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 812 | #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 813 | #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 814 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 815 | #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 816 | #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 817 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 818 | #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 819 | #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 820 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 821 | /* SCB Cache Size ID Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 822 | #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 823 | #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 824 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 825 | #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 826 | #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 827 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 828 | #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 829 | #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 830 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 831 | #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 832 | #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 833 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 834 | #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 835 | #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 836 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 837 | #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 838 | #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 839 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 840 | #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 841 | #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 842 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 843 | /* SCB Cache Size Selection Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 844 | #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 845 | #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 846 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 847 | #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 848 | #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 849 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 850 | /* SCB Software Triggered Interrupt Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 851 | #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 852 | #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 853 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 854 | /* SCB D-Cache Invalidate by Set-way Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 855 | #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 856 | #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 857 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 858 | #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 859 | #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 860 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 861 | /* SCB D-Cache Clean by Set-way Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 862 | #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 863 | #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 864 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 865 | #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 866 | #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 867 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 868 | /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 869 | #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 870 | #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 871 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 872 | #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 873 | #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 874 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 875 | /* Instruction Tightly-Coupled Memory Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 876 | #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 877 | #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 878 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 879 | #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 880 | #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 881 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 882 | #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 883 | #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 884 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 885 | #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 886 | #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 887 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 888 | /* Data Tightly-Coupled Memory Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 889 | #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 890 | #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 891 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 892 | #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 893 | #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 894 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 895 | #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 896 | #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 897 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 898 | #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 899 | #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 900 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 901 | /* AHBP Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 902 | #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 903 | #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 904 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 905 | #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 906 | #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 907 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 908 | /* L1 Cache Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 909 | #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 910 | #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 911 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 912 | #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 913 | #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 914 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 915 | #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 916 | #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 917 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 918 | /* AHBS Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 919 | #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 920 | #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 921 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 922 | #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 923 | #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 924 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 925 | #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 926 | #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 927 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 928 | /* Auxiliary Bus Fault Status Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 929 | #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 930 | #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 931 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 932 | #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 933 | #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 934 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 935 | #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 936 | #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 937 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 938 | #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 939 | #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 940 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 941 | #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 942 | #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 943 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 944 | #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 945 | #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 946 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 947 | /*@} end of group CMSIS_SCB */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 948 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 949 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 950 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 951 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 952 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 953 | \brief Type definitions for the System Control and ID Register not in the SCB |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 954 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 955 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 956 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 957 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 958 | \brief Structure type to access the System Control and ID Register not in the SCB. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 959 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 960 | typedef struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 961 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 962 | uint32_t RESERVED0[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 963 | __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 964 | __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 965 | __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 966 | } SCnSCB_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 967 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 968 | /* Interrupt Controller Type Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 969 | #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 970 | #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 971 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 972 | /*@} end of group CMSIS_SCnotSCB */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 973 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 974 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 975 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 976 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 977 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 978 | \brief Type definitions for the System Timer Registers. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 979 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 980 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 981 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 982 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 983 | \brief Structure type to access the System Timer (SysTick). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 984 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 985 | typedef struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 986 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 987 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 988 | __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 989 | __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 990 | __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 991 | } SysTick_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 992 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 993 | /* SysTick Control / Status Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 994 | #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 995 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 996 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 997 | #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 998 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 999 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1000 | #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1001 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1002 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1003 | #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1004 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1005 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1006 | /* SysTick Reload Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1007 | #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1008 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1009 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1010 | /* SysTick Current Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1011 | #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1012 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1013 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1014 | /* SysTick Calibration Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1015 | #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1016 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1017 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1018 | #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1019 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1020 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1021 | #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1022 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1023 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1024 | /*@} end of group CMSIS_SysTick */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1025 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1026 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1027 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1028 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1029 | \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1030 | \brief Type definitions for the Instrumentation Trace Macrocell (ITM) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1031 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1032 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1033 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1034 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1035 | \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1036 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1037 | typedef struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1038 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1039 | __OM union |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1040 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1041 | __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1042 | __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1043 | __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1044 | } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1045 | uint32_t RESERVED0[864U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1046 | __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1047 | uint32_t RESERVED1[15U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1048 | __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1049 | uint32_t RESERVED2[15U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1050 | __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1051 | uint32_t RESERVED3[29U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1052 | __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1053 | __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1054 | __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1055 | uint32_t RESERVED4[43U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1056 | __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1057 | __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1058 | uint32_t RESERVED5[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1059 | __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1060 | uint32_t RESERVED6[4U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1061 | __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1062 | __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1063 | __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1064 | __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1065 | __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1066 | __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1067 | __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1068 | __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1069 | __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1070 | __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1071 | __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1072 | __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1073 | } ITM_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1074 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1075 | /* ITM Stimulus Port Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1076 | #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1077 | #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1078 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1079 | #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1080 | #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1081 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1082 | /* ITM Trace Privilege Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1083 | #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1084 | #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1085 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1086 | /* ITM Trace Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1087 | #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1088 | #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1089 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1090 | #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1091 | #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1092 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1093 | #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1094 | #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1095 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1096 | #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1097 | #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1098 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1099 | #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1100 | #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1101 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1102 | #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1103 | #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1104 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1105 | #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1106 | #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1107 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1108 | #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1109 | #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1110 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1111 | #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1112 | #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1113 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1114 | #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1115 | #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1116 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1117 | /* ITM Integration Write Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1118 | #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1119 | #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1120 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1121 | /* ITM Integration Read Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1122 | #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1123 | #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1124 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1125 | /* ITM Integration Mode Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1126 | #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1127 | #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1128 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1129 | /* ITM Lock Status Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1130 | #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1131 | #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1132 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1133 | #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1134 | #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1135 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1136 | #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1137 | #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1138 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1139 | /*@}*/ /* end of group CMSIS_ITM */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1140 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1141 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1142 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1143 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1144 | \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1145 | \brief Type definitions for the Data Watchpoint and Trace (DWT) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1146 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1147 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1148 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1149 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1150 | \brief Structure type to access the Data Watchpoint and Trace Register (DWT). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1151 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1152 | typedef struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1153 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1154 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1155 | __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1156 | __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1157 | __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1158 | __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1159 | __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1160 | __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1161 | __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1162 | __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1163 | uint32_t RESERVED1[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1164 | __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1165 | uint32_t RESERVED2[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1166 | __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1167 | uint32_t RESERVED3[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1168 | __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1169 | uint32_t RESERVED4[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1170 | __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1171 | uint32_t RESERVED5[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1172 | __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1173 | uint32_t RESERVED6[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1174 | __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1175 | uint32_t RESERVED7[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1176 | __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1177 | uint32_t RESERVED8[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1178 | __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1179 | uint32_t RESERVED9[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1180 | __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1181 | uint32_t RESERVED10[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1182 | __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1183 | uint32_t RESERVED11[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1184 | __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1185 | uint32_t RESERVED12[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1186 | __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1187 | uint32_t RESERVED13[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1188 | __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1189 | uint32_t RESERVED14[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1190 | __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1191 | uint32_t RESERVED15[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1192 | __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1193 | uint32_t RESERVED16[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1194 | __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1195 | uint32_t RESERVED17[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1196 | __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1197 | uint32_t RESERVED18[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1198 | __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1199 | uint32_t RESERVED19[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1200 | __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1201 | uint32_t RESERVED20[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1202 | __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1203 | uint32_t RESERVED21[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1204 | __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1205 | uint32_t RESERVED22[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1206 | __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1207 | uint32_t RESERVED23[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1208 | __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1209 | uint32_t RESERVED24[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1210 | __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1211 | uint32_t RESERVED25[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1212 | __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1213 | uint32_t RESERVED26[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1214 | __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1215 | uint32_t RESERVED27[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1216 | __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1217 | uint32_t RESERVED28[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1218 | __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1219 | uint32_t RESERVED29[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1220 | __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1221 | uint32_t RESERVED30[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1222 | __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1223 | uint32_t RESERVED31[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1224 | __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1225 | uint32_t RESERVED32[934U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1226 | __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1227 | uint32_t RESERVED33[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1228 | __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1229 | } DWT_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1230 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1231 | /* DWT Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1232 | #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1233 | #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1234 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1235 | #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1236 | #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1237 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1238 | #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1239 | #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1240 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1241 | #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1242 | #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1243 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1244 | #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1245 | #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1246 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1247 | #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1248 | #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1249 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1250 | #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1251 | #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1252 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1253 | #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1254 | #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1255 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1256 | #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1257 | #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1258 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1259 | #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1260 | #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1261 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1262 | #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1263 | #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1264 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1265 | #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1266 | #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1267 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1268 | #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1269 | #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1270 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1271 | #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1272 | #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1273 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1274 | #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1275 | #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1276 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1277 | #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1278 | #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1279 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1280 | #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1281 | #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1282 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1283 | #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1284 | #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1285 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1286 | #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1287 | #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1288 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1289 | /* DWT CPI Count Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1290 | #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1291 | #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1292 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1293 | /* DWT Exception Overhead Count Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1294 | #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1295 | #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1296 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1297 | /* DWT Sleep Count Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1298 | #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1299 | #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1300 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1301 | /* DWT LSU Count Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1302 | #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1303 | #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1304 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1305 | /* DWT Folded-instruction Count Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1306 | #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1307 | #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1308 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1309 | /* DWT Comparator Function Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1310 | #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1311 | #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1312 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1313 | #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1314 | #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1315 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1316 | #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1317 | #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1318 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1319 | #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1320 | #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1321 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1322 | #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1323 | #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1324 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1325 | /*@}*/ /* end of group CMSIS_DWT */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1326 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1327 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1328 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1329 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1330 | \defgroup CMSIS_TPI Trace Port Interface (TPI) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1331 | \brief Type definitions for the Trace Port Interface (TPI) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1332 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1333 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1334 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1335 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1336 | \brief Structure type to access the Trace Port Interface Register (TPI). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1337 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1338 | typedef struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1339 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1340 | __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1341 | __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1342 | uint32_t RESERVED0[2U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1343 | __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1344 | uint32_t RESERVED1[55U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1345 | __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1346 | uint32_t RESERVED2[131U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1347 | __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1348 | __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1349 | __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1350 | uint32_t RESERVED3[759U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1351 | __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1352 | __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1353 | __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1354 | uint32_t RESERVED4[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1355 | __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1356 | __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1357 | __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1358 | uint32_t RESERVED5[39U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1359 | __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1360 | __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1361 | uint32_t RESERVED7[8U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1362 | __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1363 | __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1364 | } TPI_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1365 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1366 | /* TPI Asynchronous Clock Prescaler Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1367 | #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1368 | #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1369 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1370 | /* TPI Selected Pin Protocol Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1371 | #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1372 | #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1373 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1374 | /* TPI Formatter and Flush Status Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1375 | #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1376 | #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1377 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1378 | #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1379 | #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1380 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1381 | #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1382 | #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1383 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1384 | #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1385 | #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1386 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1387 | /* TPI Formatter and Flush Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1388 | #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1389 | #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1390 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1391 | #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1392 | #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1393 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1394 | /* TPI TRIGGER Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1395 | #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1396 | #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1397 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1398 | /* TPI Integration ETM Data Register Definitions (FIFO0) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1399 | #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1400 | #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1401 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1402 | #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1403 | #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1404 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1405 | #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1406 | #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1407 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1408 | #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1409 | #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1410 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1411 | #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1412 | #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1413 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1414 | #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1415 | #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1416 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1417 | #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1418 | #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1419 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1420 | /* TPI ITATBCTR2 Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1421 | #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1422 | #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1423 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1424 | /* TPI Integration ITM Data Register Definitions (FIFO1) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1425 | #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1426 | #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1427 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1428 | #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1429 | #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1430 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1431 | #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1432 | #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1433 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1434 | #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1435 | #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1436 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1437 | #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1438 | #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1439 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1440 | #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1441 | #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1442 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1443 | #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1444 | #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1445 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1446 | /* TPI ITATBCTR0 Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1447 | #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1448 | #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1449 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1450 | /* TPI Integration Mode Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1451 | #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1452 | #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1453 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1454 | /* TPI DEVID Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1455 | #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1456 | #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1457 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1458 | #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1459 | #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1460 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1461 | #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1462 | #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1463 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1464 | #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1465 | #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1466 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1467 | #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1468 | #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1469 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1470 | #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1471 | #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1472 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1473 | /* TPI DEVTYPE Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1474 | #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1475 | #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1476 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1477 | #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1478 | #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1479 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1480 | /*@}*/ /* end of group CMSIS_TPI */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1481 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1482 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1483 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1484 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1485 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1486 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1487 | \brief Type definitions for the Memory Protection Unit (MPU) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1488 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1489 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1490 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1491 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1492 | \brief Structure type to access the Memory Protection Unit (MPU). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1493 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1494 | typedef struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1495 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1496 | __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1497 | __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1498 | __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1499 | __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1500 | __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1501 | __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1502 | __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1503 | __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1504 | __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1505 | __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1506 | __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1507 | uint32_t RESERVED0[1]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1508 | __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1509 | __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1510 | } MPU_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1511 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1512 | /* MPU Type Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1513 | #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1514 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1515 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1516 | #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1517 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1518 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1519 | #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1520 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1521 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1522 | /* MPU Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1523 | #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1524 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1525 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1526 | #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1527 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1528 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1529 | #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1530 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1531 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1532 | /* MPU Region Number Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1533 | #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1534 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1535 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1536 | /* MPU Region Base Address Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1537 | #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1538 | #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1539 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1540 | #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1541 | #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1542 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1543 | #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1544 | #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1545 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1546 | #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1547 | #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1548 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1549 | /* MPU Region Limit Address Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1550 | #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1551 | #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1552 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1553 | #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1554 | #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1555 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1556 | #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1557 | #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1558 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1559 | /* MPU Memory Attribute Indirection Register 0 Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1560 | #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1561 | #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1562 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1563 | #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1564 | #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1565 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1566 | #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1567 | #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1568 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1569 | #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1570 | #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1571 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1572 | /* MPU Memory Attribute Indirection Register 1 Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1573 | #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1574 | #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1575 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1576 | #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1577 | #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1578 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1579 | #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1580 | #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1581 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1582 | #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1583 | #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1584 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1585 | /*@} end of group CMSIS_MPU */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1586 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1587 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1588 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1589 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1590 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1591 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1592 | \defgroup CMSIS_SAU Security Attribution Unit (SAU) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1593 | \brief Type definitions for the Security Attribution Unit (SAU) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1594 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1595 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1596 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1597 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1598 | \brief Structure type to access the Security Attribution Unit (SAU). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1599 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1600 | typedef struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1601 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1602 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1603 | __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1604 | #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1605 | __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1606 | __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1607 | __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1608 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1609 | uint32_t RESERVED0[3]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1610 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1611 | __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1612 | __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1613 | } SAU_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1614 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1615 | /* SAU Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1616 | #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1617 | #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1618 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1619 | #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1620 | #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1621 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1622 | /* SAU Type Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1623 | #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1624 | #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1625 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1626 | #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1627 | /* SAU Region Number Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1628 | #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1629 | #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1630 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1631 | /* SAU Region Base Address Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1632 | #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1633 | #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1634 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1635 | /* SAU Region Limit Address Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1636 | #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1637 | #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1638 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1639 | #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1640 | #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1641 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1642 | #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1643 | #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1644 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1645 | #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1646 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1647 | /* Secure Fault Status Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1648 | #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1649 | #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1650 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1651 | #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1652 | #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1653 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1654 | #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1655 | #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1656 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1657 | #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1658 | #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1659 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1660 | #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1661 | #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1662 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1663 | #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1664 | #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1665 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1666 | #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1667 | #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1668 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1669 | #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1670 | #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1671 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1672 | /*@} end of group CMSIS_SAU */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1673 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1674 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1675 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1676 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1677 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1678 | \defgroup CMSIS_FPU Floating Point Unit (FPU) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1679 | \brief Type definitions for the Floating Point Unit (FPU) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1680 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1681 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1682 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1683 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1684 | \brief Structure type to access the Floating Point Unit (FPU). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1685 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1686 | typedef struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1687 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1688 | uint32_t RESERVED0[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1689 | __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1690 | __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1691 | __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1692 | __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1693 | __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1694 | } FPU_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1695 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1696 | /* Floating-Point Context Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1697 | #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1698 | #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1699 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1700 | #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1701 | #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1702 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1703 | #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1704 | #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1705 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1706 | #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1707 | #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1708 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1709 | #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1710 | #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1711 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1712 | #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1713 | #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1714 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1715 | #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1716 | #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1717 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1718 | #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1719 | #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1720 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1721 | #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1722 | #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1723 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1724 | #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1725 | #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1726 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1727 | #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1728 | #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1729 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1730 | #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1731 | #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1732 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1733 | #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1734 | #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1735 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1736 | #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1737 | #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1738 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1739 | #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1740 | #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1741 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1742 | #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1743 | #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1744 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1745 | #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1746 | #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1747 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1748 | /* Floating-Point Context Address Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1749 | #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1750 | #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1751 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1752 | /* Floating-Point Default Status Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1753 | #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1754 | #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1755 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1756 | #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1757 | #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1758 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1759 | #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1760 | #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1761 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1762 | #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1763 | #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1764 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1765 | /* Media and FP Feature Register 0 Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1766 | #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1767 | #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1768 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1769 | #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1770 | #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1771 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1772 | #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1773 | #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1774 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1775 | #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1776 | #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1777 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1778 | #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1779 | #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1780 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1781 | #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1782 | #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1783 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1784 | #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1785 | #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1786 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1787 | #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1788 | #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1789 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1790 | /* Media and FP Feature Register 1 Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1791 | #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1792 | #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1793 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1794 | #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1795 | #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1796 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1797 | #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1798 | #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1799 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1800 | #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1801 | #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1802 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1803 | /*@} end of group CMSIS_FPU */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1804 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1805 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1806 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1807 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1808 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1809 | \brief Type definitions for the Core Debug Registers |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1810 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1811 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1812 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1813 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1814 | \brief Structure type to access the Core Debug Register (CoreDebug). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1815 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1816 | typedef struct |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1817 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1818 | __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1819 | __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1820 | __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1821 | __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1822 | uint32_t RESERVED4[1U]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1823 | __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1824 | __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1825 | } CoreDebug_Type; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1826 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1827 | /* Debug Halting Control and Status Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1828 | #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1829 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1830 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1831 | #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1832 | #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1833 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1834 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1835 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1836 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1837 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1838 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1839 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1840 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1841 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1842 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1843 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1844 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1845 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1846 | #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1847 | #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1848 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1849 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1850 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1851 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1852 | #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1853 | #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1854 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1855 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1856 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1857 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1858 | #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1859 | #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1860 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1861 | #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1862 | #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1863 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1864 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1865 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1866 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1867 | /* Debug Core Register Selector Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1868 | #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1869 | #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1870 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1871 | #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1872 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1873 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1874 | /* Debug Exception and Monitor Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1875 | #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1876 | #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1877 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1878 | #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1879 | #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1880 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1881 | #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1882 | #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1883 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1884 | #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1885 | #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1886 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1887 | #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1888 | #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1889 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1890 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1891 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1892 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1893 | #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1894 | #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1895 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1896 | #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1897 | #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1898 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1899 | #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1900 | #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1901 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1902 | #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1903 | #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1904 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1905 | #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1906 | #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1907 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1908 | #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1909 | #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1910 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1911 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1912 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1913 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1914 | /* Debug Authentication Control Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1915 | #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1916 | #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1917 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1918 | #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1919 | #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1920 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1921 | #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1922 | #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1923 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1924 | #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1925 | #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1926 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1927 | /* Debug Security Control and Status Register Definitions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1928 | #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1929 | #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1930 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1931 | #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1932 | #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1933 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1934 | #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1935 | #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1936 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1937 | /*@} end of group CMSIS_CoreDebug */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1938 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1939 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1940 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1941 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1942 | \defgroup CMSIS_core_bitfield Core register bit field macros |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1943 | \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1944 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1945 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1946 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1947 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1948 | \brief Mask and shift a bit field value for use in a register bit range. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1949 | \param[in] field Name of the register bit field. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1950 | \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1951 | \return Masked and shifted value. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1952 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1953 | #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1954 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1955 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1956 | \brief Mask and shift a register value to extract a bit filed value. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1957 | \param[in] field Name of the register bit field. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1958 | \param[in] value Value of register. This parameter is interpreted as an uint32_t type. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1959 | \return Masked and shifted bit field value. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1960 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1961 | #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1962 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1963 | /*@} end of group CMSIS_core_bitfield */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1964 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1965 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1966 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1967 | \ingroup CMSIS_core_register |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1968 | \defgroup CMSIS_core_base Core Definitions |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1969 | \brief Definitions for base addresses, unions, and structures. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1970 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1971 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1972 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1973 | /* Memory mapping of Core Hardware */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1974 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1975 | #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1976 | #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1977 | #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1978 | #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1979 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1980 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1981 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1982 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1983 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1984 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1985 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1986 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1987 | #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1988 | #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1989 | #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1990 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1991 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1992 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1993 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1994 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1995 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1996 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1997 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1998 | #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 1999 | #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2000 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2001 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2002 | #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2003 | #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2004 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2005 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2006 | #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2007 | #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2008 | #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2009 | #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2010 | #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2011 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2012 | #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2013 | #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2014 | #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2015 | #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2016 | #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2017 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2018 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2019 | #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2020 | #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2021 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2022 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2023 | #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2024 | #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2025 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2026 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2027 | /*@} */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2028 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2029 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2030 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2031 | /******************************************************************************* |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2032 | * Hardware Abstraction Layer |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2033 | Core Function Interface contains: |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2034 | - Core NVIC Functions |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2035 | - Core SysTick Functions |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2036 | - Core Debug Functions |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2037 | - Core Register Access Functions |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2038 | ******************************************************************************/ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2039 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2040 | \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2041 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2042 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2043 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2044 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2045 | /* ########################## NVIC functions #################################### */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2046 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2047 | \ingroup CMSIS_Core_FunctionInterface |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2048 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2049 | \brief Functions that manage interrupts and exceptions via the NVIC. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2050 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2051 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2052 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2053 | #ifdef CMSIS_NVIC_VIRTUAL |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2054 | #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2055 | #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2056 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2057 | #include CMSIS_NVIC_VIRTUAL_HEADER_FILE |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2058 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2059 | #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2060 | #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2061 | #define NVIC_EnableIRQ __NVIC_EnableIRQ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2062 | #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2063 | #define NVIC_DisableIRQ __NVIC_DisableIRQ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2064 | #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2065 | #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2066 | #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2067 | #define NVIC_GetActive __NVIC_GetActive |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2068 | #define NVIC_SetPriority __NVIC_SetPriority |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2069 | #define NVIC_GetPriority __NVIC_GetPriority |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2070 | #define NVIC_SystemReset __NVIC_SystemReset |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2071 | #endif /* CMSIS_NVIC_VIRTUAL */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2072 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2073 | #ifdef CMSIS_VECTAB_VIRTUAL |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2074 | #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2075 | #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2076 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2077 | #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2078 | #else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2079 | #define NVIC_SetVector __NVIC_SetVector |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2080 | #define NVIC_GetVector __NVIC_GetVector |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2081 | #endif /* (CMSIS_VECTAB_VIRTUAL) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2082 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2083 | #define NVIC_USER_IRQ_OFFSET 16 |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2084 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2085 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2086 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2087 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2088 | \brief Set Priority Grouping |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2089 | \details Sets the priority grouping field using the required unlock sequence. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2090 | The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2091 | Only values from 0..7 are used. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2092 | In case of a conflict between priority grouping and available |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2093 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2094 | \param [in] PriorityGroup Priority grouping field. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2095 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2096 | __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2097 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2098 | uint32_t reg_value; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2099 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2100 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2101 | reg_value = SCB->AIRCR; /* read old register configuration */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2102 | reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2103 | reg_value = (reg_value | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2104 | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2105 | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2106 | SCB->AIRCR = reg_value; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2107 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2108 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2109 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2110 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2111 | \brief Get Priority Grouping |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2112 | \details Reads the priority grouping field from the NVIC Interrupt Controller. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2113 | \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2114 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2115 | __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2116 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2117 | return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2118 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2119 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2120 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2121 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2122 | \brief Enable Interrupt |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2123 | \details Enables a device specific interrupt in the NVIC interrupt controller. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2124 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2125 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2126 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2127 | __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2128 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2129 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2130 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2131 | NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2132 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2133 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2134 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2135 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2136 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2137 | \brief Get Interrupt Enable status |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2138 | \details Returns a device specific interrupt enable status from the NVIC interrupt controller. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2139 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2140 | \return 0 Interrupt is not enabled. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2141 | \return 1 Interrupt is enabled. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2142 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2143 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2144 | __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2145 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2146 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2147 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2148 | return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2149 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2150 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2151 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2152 | return(0U); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2153 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2154 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2155 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2156 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2157 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2158 | \brief Disable Interrupt |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2159 | \details Disables a device specific interrupt in the NVIC interrupt controller. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2160 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2161 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2162 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2163 | __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2164 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2165 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2166 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2167 | NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2168 | __DSB(); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2169 | __ISB(); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2170 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2171 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2172 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2173 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2174 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2175 | \brief Get Pending Interrupt |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2176 | \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2177 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2178 | \return 0 Interrupt status is not pending. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2179 | \return 1 Interrupt status is pending. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2180 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2181 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2182 | __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2183 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2184 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2185 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2186 | return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2187 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2188 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2189 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2190 | return(0U); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2191 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2192 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2193 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2194 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2195 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2196 | \brief Set Pending Interrupt |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2197 | \details Sets the pending bit of a device specific interrupt in the NVIC pending register. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2198 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2199 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2200 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2201 | __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2202 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2203 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2204 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2205 | NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2206 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2207 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2208 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2209 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2210 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2211 | \brief Clear Pending Interrupt |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2212 | \details Clears the pending bit of a device specific interrupt in the NVIC pending register. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2213 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2214 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2215 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2216 | __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2217 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2218 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2219 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2220 | NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2221 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2222 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2223 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2224 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2225 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2226 | \brief Get Active Interrupt |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2227 | \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2228 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2229 | \return 0 Interrupt status is not active. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2230 | \return 1 Interrupt status is active. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2231 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2232 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2233 | __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2234 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2235 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2236 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2237 | return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2238 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2239 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2240 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2241 | return(0U); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2242 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2243 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2244 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2245 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2246 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2247 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2248 | \brief Get Interrupt Target State |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2249 | \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2250 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2251 | \return 0 if interrupt is assigned to Secure |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2252 | \return 1 if interrupt is assigned to Non Secure |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2253 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2254 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2255 | __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2256 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2257 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2258 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2259 | return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2260 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2261 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2262 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2263 | return(0U); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2264 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2265 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2266 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2267 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2268 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2269 | \brief Set Interrupt Target State |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2270 | \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2271 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2272 | \return 0 if interrupt is assigned to Secure |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2273 | 1 if interrupt is assigned to Non Secure |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2274 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2275 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2276 | __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2277 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2278 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2279 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2280 | NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2281 | return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2282 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2283 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2284 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2285 | return(0U); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2286 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2287 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2288 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2289 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2290 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2291 | \brief Clear Interrupt Target State |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2292 | \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2293 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2294 | \return 0 if interrupt is assigned to Secure |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2295 | 1 if interrupt is assigned to Non Secure |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2296 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2297 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2298 | __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2299 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2300 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2301 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2302 | NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2303 | return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2304 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2305 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2306 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2307 | return(0U); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2308 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2309 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2310 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2311 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2312 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2313 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2314 | \brief Set Interrupt Priority |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2315 | \details Sets the priority of a device specific interrupt or a processor exception. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2316 | The interrupt number can be positive to specify a device specific interrupt, |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2317 | or negative to specify a processor exception. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2318 | \param [in] IRQn Interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2319 | \param [in] priority Priority to set. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2320 | \note The priority cannot be set for every processor exception. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2321 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2322 | __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2323 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2324 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2325 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2326 | NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2327 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2328 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2329 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2330 | SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2331 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2332 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2333 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2334 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2335 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2336 | \brief Get Interrupt Priority |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2337 | \details Reads the priority of a device specific interrupt or a processor exception. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2338 | The interrupt number can be positive to specify a device specific interrupt, |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2339 | or negative to specify a processor exception. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2340 | \param [in] IRQn Interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2341 | \return Interrupt Priority. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2342 | Value is aligned automatically to the implemented priority bits of the microcontroller. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2343 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2344 | __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2345 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2346 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2347 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2348 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2349 | return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2350 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2351 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2352 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2353 | return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2354 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2355 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2356 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2357 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2358 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2359 | \brief Encode Priority |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2360 | \details Encodes the priority for an interrupt with the given priority group, |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2361 | preemptive priority value, and subpriority value. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2362 | In case of a conflict between priority grouping and available |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2363 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2364 | \param [in] PriorityGroup Used priority group. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2365 | \param [in] PreemptPriority Preemptive priority value (starting from 0). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2366 | \param [in] SubPriority Subpriority value (starting from 0). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2367 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2368 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2369 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2370 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2371 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2372 | uint32_t PreemptPriorityBits; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2373 | uint32_t SubPriorityBits; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2374 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2375 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2376 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2377 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2378 | return ( |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2379 | ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2380 | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2381 | ); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2382 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2383 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2384 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2385 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2386 | \brief Decode Priority |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2387 | \details Decodes an interrupt priority value with a given priority group to |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2388 | preemptive priority value and subpriority value. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2389 | In case of a conflict between priority grouping and available |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2390 | priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2391 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2392 | \param [in] PriorityGroup Used priority group. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2393 | \param [out] pPreemptPriority Preemptive priority value (starting from 0). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2394 | \param [out] pSubPriority Subpriority value (starting from 0). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2395 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2396 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2397 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2398 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2399 | uint32_t PreemptPriorityBits; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2400 | uint32_t SubPriorityBits; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2401 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2402 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2403 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2404 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2405 | *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2406 | *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2407 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2408 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2409 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2410 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2411 | \brief Set Interrupt Vector |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2412 | \details Sets an interrupt vector in SRAM based interrupt vector table. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2413 | The interrupt number can be positive to specify a device specific interrupt, |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2414 | or negative to specify a processor exception. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2415 | VTOR must been relocated to SRAM before. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2416 | \param [in] IRQn Interrupt number |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2417 | \param [in] vector Address of interrupt handler function |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2418 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2419 | __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2420 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2421 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2422 | vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2423 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2424 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2425 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2426 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2427 | \brief Get Interrupt Vector |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2428 | \details Reads an interrupt vector from interrupt vector table. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2429 | The interrupt number can be positive to specify a device specific interrupt, |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2430 | or negative to specify a processor exception. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2431 | \param [in] IRQn Interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2432 | \return Address of interrupt handler function |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2433 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2434 | __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2435 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2436 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2437 | return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2438 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2439 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2440 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2441 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2442 | \brief System Reset |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2443 | \details Initiates a system reset request to reset the MCU. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2444 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2445 | __STATIC_INLINE void __NVIC_SystemReset(void) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2446 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2447 | __DSB(); /* Ensure all outstanding memory accesses included |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2448 | buffered write are completed before reset */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2449 | SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2450 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2451 | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2452 | __DSB(); /* Ensure completion of memory access */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2453 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2454 | for(;;) /* wait until reset */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2455 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2456 | __NOP(); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2457 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2458 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2459 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2460 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2461 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2462 | \brief Set Priority Grouping (non-secure) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2463 | \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2464 | The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2465 | Only values from 0..7 are used. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2466 | In case of a conflict between priority grouping and available |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2467 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2468 | \param [in] PriorityGroup Priority grouping field. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2469 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2470 | __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2471 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2472 | uint32_t reg_value; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2473 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2474 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2475 | reg_value = SCB_NS->AIRCR; /* read old register configuration */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2476 | reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2477 | reg_value = (reg_value | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2478 | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2479 | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2480 | SCB_NS->AIRCR = reg_value; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2481 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2482 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2483 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2484 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2485 | \brief Get Priority Grouping (non-secure) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2486 | \details Reads the priority grouping field from the non-secure NVIC when in secure state. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2487 | \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2488 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2489 | __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2490 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2491 | return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2492 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2493 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2494 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2495 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2496 | \brief Enable Interrupt (non-secure) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2497 | \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2498 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2499 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2500 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2501 | __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2502 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2503 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2504 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2505 | NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2506 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2507 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2508 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2509 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2510 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2511 | \brief Get Interrupt Enable status (non-secure) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2512 | \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2513 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2514 | \return 0 Interrupt is not enabled. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2515 | \return 1 Interrupt is enabled. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2516 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2517 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2518 | __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2519 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2520 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2521 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2522 | return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2523 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2524 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2525 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2526 | return(0U); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2527 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2528 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2529 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2530 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2531 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2532 | \brief Disable Interrupt (non-secure) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2533 | \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2534 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2535 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2536 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2537 | __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2538 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2539 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2540 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2541 | NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2542 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2543 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2544 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2545 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2546 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2547 | \brief Get Pending Interrupt (non-secure) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2548 | \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2549 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2550 | \return 0 Interrupt status is not pending. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2551 | \return 1 Interrupt status is pending. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2552 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2553 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2554 | __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2555 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2556 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2557 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2558 | return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2559 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2560 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2561 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2562 | return(0U); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2563 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2564 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2565 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2566 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2567 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2568 | \brief Set Pending Interrupt (non-secure) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2569 | \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2570 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2571 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2572 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2573 | __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2574 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2575 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2576 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2577 | NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2578 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2579 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2580 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2581 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2582 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2583 | \brief Clear Pending Interrupt (non-secure) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2584 | \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2585 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2586 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2587 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2588 | __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2589 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2590 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2591 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2592 | NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2593 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2594 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2595 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2596 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2597 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2598 | \brief Get Active Interrupt (non-secure) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2599 | \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2600 | \param [in] IRQn Device specific interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2601 | \return 0 Interrupt status is not active. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2602 | \return 1 Interrupt status is active. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2603 | \note IRQn must not be negative. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2604 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2605 | __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2606 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2607 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2608 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2609 | return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2610 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2611 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2612 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2613 | return(0U); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2614 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2615 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2616 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2617 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2618 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2619 | \brief Set Interrupt Priority (non-secure) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2620 | \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2621 | The interrupt number can be positive to specify a device specific interrupt, |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2622 | or negative to specify a processor exception. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2623 | \param [in] IRQn Interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2624 | \param [in] priority Priority to set. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2625 | \note The priority cannot be set for every non-secure processor exception. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2626 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2627 | __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2628 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2629 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2630 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2631 | NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2632 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2633 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2634 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2635 | SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2636 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2637 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2638 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2639 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2640 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2641 | \brief Get Interrupt Priority (non-secure) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2642 | \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2643 | The interrupt number can be positive to specify a device specific interrupt, |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2644 | or negative to specify a processor exception. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2645 | \param [in] IRQn Interrupt number. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2646 | \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2647 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2648 | __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2649 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2650 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2651 | if ((int32_t)(IRQn) >= 0) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2652 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2653 | return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2654 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2655 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2656 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2657 | return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2658 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2659 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2660 | #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2661 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2662 | /*@} end of CMSIS_Core_NVICFunctions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2663 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2664 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2665 | /* ########################## FPU functions #################################### */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2666 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2667 | \ingroup CMSIS_Core_FunctionInterface |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2668 | \defgroup CMSIS_Core_FpuFunctions FPU Functions |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2669 | \brief Function that provides FPU type. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2670 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2671 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2672 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2673 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2674 | \brief get FPU type |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2675 | \details returns the FPU type |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2676 | \returns |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2677 | - \b 0: No FPU |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2678 | - \b 1: Single precision FPU |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2679 | - \b 2: Double + Single precision FPU |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2680 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2681 | __STATIC_INLINE uint32_t SCB_GetFPUType(void) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2682 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2683 | uint32_t mvfr0; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2684 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2685 | mvfr0 = FPU->MVFR0; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2686 | if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2687 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2688 | return 2U; /* Double + Single precision FPU */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2689 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2690 | else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2691 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2692 | return 1U; /* Single precision FPU */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2693 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2694 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2695 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2696 | return 0U; /* No FPU */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2697 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2698 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2699 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2700 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2701 | /*@} end of CMSIS_Core_FpuFunctions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2702 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2703 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2704 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2705 | /* ########################## SAU functions #################################### */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2706 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2707 | \ingroup CMSIS_Core_FunctionInterface |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2708 | \defgroup CMSIS_Core_SAUFunctions SAU Functions |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2709 | \brief Functions that configure the SAU. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2710 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2711 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2712 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2713 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2714 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2715 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2716 | \brief Enable SAU |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2717 | \details Enables the Security Attribution Unit (SAU). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2718 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2719 | __STATIC_INLINE void TZ_SAU_Enable(void) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2720 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2721 | SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2722 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2723 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2724 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2725 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2726 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2727 | \brief Disable SAU |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2728 | \details Disables the Security Attribution Unit (SAU). |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2729 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2730 | __STATIC_INLINE void TZ_SAU_Disable(void) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2731 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2732 | SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2733 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2734 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2735 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2736 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2737 | /*@} end of CMSIS_Core_SAUFunctions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2738 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2739 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2740 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2741 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2742 | /* ################################## SysTick function ############################################ */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2743 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2744 | \ingroup CMSIS_Core_FunctionInterface |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2745 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2746 | \brief Functions that configure the System. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2747 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2748 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2749 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2750 | #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2751 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2752 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2753 | \brief System Tick Configuration |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2754 | \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2755 | Counter is in free running mode to generate periodic interrupts. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2756 | \param [in] ticks Number of ticks between two interrupts. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2757 | \return 0 Function succeeded. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2758 | \return 1 Function failed. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2759 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2760 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2761 | must contain a vendor-specific implementation of this function. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2762 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2763 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2764 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2765 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2766 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2767 | return (1UL); /* Reload value impossible */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2768 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2769 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2770 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2771 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2772 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2773 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2774 | SysTick_CTRL_TICKINT_Msk | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2775 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2776 | return (0UL); /* Function successful */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2777 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2778 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2779 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2780 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2781 | \brief System Tick Configuration (non-secure) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2782 | \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2783 | Counter is in free running mode to generate periodic interrupts. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2784 | \param [in] ticks Number of ticks between two interrupts. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2785 | \return 0 Function succeeded. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2786 | \return 1 Function failed. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2787 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2788 | function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2789 | must contain a vendor-specific implementation of this function. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2790 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2791 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2792 | __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2793 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2794 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2795 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2796 | return (1UL); /* Reload value impossible */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2797 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2798 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2799 | SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2800 | TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2801 | SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2802 | SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2803 | SysTick_CTRL_TICKINT_Msk | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2804 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2805 | return (0UL); /* Function successful */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2806 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2807 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2808 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2809 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2810 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2811 | /*@} end of CMSIS_Core_SysTickFunctions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2812 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2813 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2814 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2815 | /* ##################################### Debug In/Output function ########################################### */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2816 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2817 | \ingroup CMSIS_Core_FunctionInterface |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2818 | \defgroup CMSIS_core_DebugFunctions ITM Functions |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2819 | \brief Functions that access the ITM debug interface. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2820 | @{ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2821 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2822 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2823 | extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2824 | #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2825 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2826 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2827 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2828 | \brief ITM Send Character |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2829 | \details Transmits a character via the ITM channel 0, and |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2830 | \li Just returns when no debugger is connected that has booked the output. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2831 | \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2832 | \param [in] ch Character to transmit. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2833 | \returns Character to transmit. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2834 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2835 | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2836 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2837 | if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2838 | ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2839 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2840 | while (ITM->PORT[0U].u32 == 0UL) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2841 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2842 | __NOP(); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2843 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2844 | ITM->PORT[0U].u8 = (uint8_t)ch; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2845 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2846 | return (ch); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2847 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2848 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2849 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2850 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2851 | \brief ITM Receive Character |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2852 | \details Inputs a character via the external variable \ref ITM_RxBuffer. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2853 | \return Received character. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2854 | \return -1 No character pending. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2855 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2856 | __STATIC_INLINE int32_t ITM_ReceiveChar (void) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2857 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2858 | int32_t ch = -1; /* no character available */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2859 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2860 | if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2861 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2862 | ch = ITM_RxBuffer; |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2863 | ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2864 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2865 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2866 | return (ch); |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2867 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2868 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2869 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2870 | /** |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2871 | \brief ITM Check Character |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2872 | \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2873 | \return 0 No character available. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2874 | \return 1 Character available. |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2875 | */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2876 | __STATIC_INLINE int32_t ITM_CheckChar (void) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2877 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2878 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2879 | if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2880 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2881 | return (0); /* no character available */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2882 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2883 | else |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2884 | { |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2885 | return (1); /* character available */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2886 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2887 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2888 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2889 | /*@} end of CMSIS_core_DebugFunctions */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2890 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2891 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2892 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2893 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2894 | #ifdef __cplusplus |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2895 | } |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2896 | #endif |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2897 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2898 | #endif /* __CORE_ARMV8MML_H_DEPENDANT */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2899 | |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2900 | #endif /* __CMSIS_GENERIC */ |
| abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 | 0:bdf663c61a82 | 2901 |