zhang boie / mbed-dev-f30333

mbed-dev-f303

hal/spi_api.h@0:bdf663c61a82, 2022-06-14 (annotated)

Committer:
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4
Date:
Tue Jun 14 09:21:18 2022 +0000
Revision:
0:bdf663c61a82
lib

Who changed what in which revision?

UserRevisionLine numberNew contents of line
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 1
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 2 /** \addtogroup hal */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 3 /** @{*/
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 4 /* mbed Microcontroller Library
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 5 * Copyright (c) 2006-2013 ARM Limited
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 6 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 7 * Licensed under the Apache License, Version 2.0 (the "License");
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 8 * you may not use this file except in compliance with the License.
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 9 * You may obtain a copy of the License at
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 10 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 11 * http://www.apache.org/licenses/LICENSE-2.0
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 12 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 13 * Unless required by applicable law or agreed to in writing, software
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 14 * distributed under the License is distributed on an "AS IS" BASIS,
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 16 * See the License for the specific language governing permissions and
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 17 * limitations under the License.
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 18 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 19 #ifndef MBED_SPI_API_H
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 20 #define MBED_SPI_API_H
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 21
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 22 #include "device.h"
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 23 #include "hal/dma_api.h"
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 24 #include "hal/buffer.h"
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 25
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 26 #if DEVICE_SPI
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 27
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 28 #define SPI_EVENT_ERROR (1 << 1)
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 29 #define SPI_EVENT_COMPLETE (1 << 2)
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 30 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 31 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 32
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 33 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 34
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 35 #define SPI_FILL_WORD (0xFFFF)
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 36 #define SPI_FILL_CHAR (0xFF)
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 37
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 38 #if DEVICE_SPI_ASYNCH
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 39 /** Asynch SPI HAL structure
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 40 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 41 typedef struct {
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 42 struct spi_s spi; /**< Target specific SPI structure */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 43 struct buffer_s tx_buff; /**< Tx buffer */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 44 struct buffer_s rx_buff; /**< Rx buffer */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 45 } spi_t;
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 46
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 47 #else
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 48 /** Non-asynch SPI HAL structure
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 49 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 50 typedef struct spi_s spi_t;
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 51
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 52 #endif
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 53
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 54 #ifdef __cplusplus
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 55 extern "C" {
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 56 #endif
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 57
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 58 /**
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 59 * \defgroup hal_GeneralSPI SPI Configuration Functions
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 60 * @{
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 61 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 62
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 63 /** Initialize the SPI peripheral
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 64 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 65 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 66 * @param[out] obj The SPI object to initialize
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 67 * @param[in] mosi The pin to use for MOSI
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 68 * @param[in] miso The pin to use for MISO
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 69 * @param[in] sclk The pin to use for SCLK
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 70 * @param[in] ssel The pin to use for SSEL
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 71 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 72 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 73
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 74 /** Release a SPI object
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 75 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 76 * TODO: spi_free is currently unimplemented
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 77 * This will require reference counting at the C++ level to be safe
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 78 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 79 * Return the pins owned by the SPI object to their reset state
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 80 * Disable the SPI peripheral
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 81 * Disable the SPI clock
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 82 * @param[in] obj The SPI object to deinitialize
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 83 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 84 void spi_free(spi_t *obj);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 85
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 86 /** Configure the SPI format
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 87 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 88 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 89 * The default bit order is MSB.
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 90 * @param[in,out] obj The SPI object to configure
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 91 * @param[in] bits The number of bits per frame
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 92 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 93 * @param[in] slave Zero for master mode or non-zero for slave mode
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 94 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 95 void spi_format(spi_t *obj, int bits, int mode, int slave);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 96
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 97 /** Set the SPI baud rate
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 98 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 99 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 100 * Configures the SPI peripheral's baud rate
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 101 * @param[in,out] obj The SPI object to configure
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 102 * @param[in] hz The baud rate in Hz
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 103 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 104 void spi_frequency(spi_t *obj, int hz);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 105
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 106 /**@}*/
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 107 /**
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 108 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 109 * @{
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 110 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 111
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 112 /** Write a byte out in master mode and receive a value
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 113 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 114 * @param[in] obj The SPI peripheral to use for sending
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 115 * @param[in] value The value to send
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 116 * @return Returns the value received during send
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 117 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 118 int spi_master_write(spi_t *obj, int value);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 119
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 120 /** Write a block out in master mode and receive a value
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 121 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 122 * The total number of bytes sent and recieved will be the maximum of
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 123 * tx_length and rx_length. The bytes written will be padded with the
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 124 * value 0xff.
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 125 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 126 * @param[in] obj The SPI peripheral to use for sending
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 127 * @param[in] tx_buffer Pointer to the byte-array of data to write to the device
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 128 * @param[in] tx_length Number of bytes to write, may be zero
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 129 * @param[in] rx_buffer Pointer to the byte-array of data to read from the device
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 130 * @param[in] rx_length Number of bytes to read, may be zero
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 131 * @param[in] write_fill Default data transmitted while performing a read
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 132 * @returns
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 133 * The number of bytes written and read from the device. This is
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 134 * maximum of tx_length and rx_length.
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 135 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 136 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 137
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 138 /** Check if a value is available to read
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 139 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 140 * @param[in] obj The SPI peripheral to check
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 141 * @return non-zero if a value is available
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 142 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 143 int spi_slave_receive(spi_t *obj);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 144
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 145 /** Get a received value out of the SPI receive buffer in slave mode
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 146 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 147 * Blocks until a value is available
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 148 * @param[in] obj The SPI peripheral to read
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 149 * @return The value received
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 150 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 151 int spi_slave_read(spi_t *obj);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 152
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 153 /** Write a value to the SPI peripheral in slave mode
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 154 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 155 * Blocks until the SPI peripheral can be written to
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 156 * @param[in] obj The SPI peripheral to write
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 157 * @param[in] value The value to write
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 158 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 159 void spi_slave_write(spi_t *obj, int value);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 160
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 161 /** Checks if the specified SPI peripheral is in use
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 162 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 163 * @param[in] obj The SPI peripheral to check
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 164 * @return non-zero if the peripheral is currently transmitting
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 165 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 166 int spi_busy(spi_t *obj);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 167
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 168 /** Get the module number
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 169 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 170 * @param[in] obj The SPI peripheral to check
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 171 * @return The module number
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 172 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 173 uint8_t spi_get_module(spi_t *obj);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 174
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 175 /**@}*/
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 176
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 177 #if DEVICE_SPI_ASYNCH
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 178 /**
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 179 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 180 * @{
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 181 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 182
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 183 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 184 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 185 * @param[in] obj The SPI object that holds the transfer information
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 186 * @param[in] tx The transmit buffer
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 187 * @param[in] tx_length The number of bytes to transmit
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 188 * @param[in] rx The receive buffer
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 189 * @param[in] rx_length The number of bytes to receive
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 190 * @param[in] bit_width The bit width of buffer words
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 191 * @param[in] event The logical OR of events to be registered
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 192 * @param[in] handler SPI interrupt handler
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 193 * @param[in] hint A suggestion for how to use DMA with this transfer
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 194 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 195 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 196
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 197 /** The asynchronous IRQ handler
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 198 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 199 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 200 * conditions, such as buffer overflows or transfer complete.
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 201 * @param[in] obj The SPI object that holds the transfer information
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 202 * @return Event flags if a transfer termination condition was met; otherwise 0.
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 203 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 204 uint32_t spi_irq_handler_asynch(spi_t *obj);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 205
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 206 /** Attempts to determine if the SPI peripheral is already in use
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 207 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 208 * If a temporary DMA channel has been allocated, peripheral is in use.
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 209 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 210 * channel were allocated.
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 211 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 212 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 213 * there are any bytes in the FIFOs.
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 214 * @param[in] obj The SPI object to check for activity
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 215 * @return Non-zero if the SPI port is active or zero if it is not.
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 216 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 217 uint8_t spi_active(spi_t *obj);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 218
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 219 /** Abort an SPI transfer
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 220 *
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 221 * @param obj The SPI peripheral to stop
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 222 */
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 223 void spi_abort_asynch(spi_t *obj);
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 224
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 225
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 226 #endif
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 227
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 228 /**@}*/
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 229
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 230 #ifdef __cplusplus
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 231 }
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 232 #endif // __cplusplus
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 233
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 234 #endif // SPI_DEVICE
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 235
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 236 #endif // MBED_SPI_API_H
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 237
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 238 /** @}*/
abe5b02d-a2d4-4fe9-818e-c4e57c809ea4 0:bdf663c61a82 239