Mateusz Kowalik / Application_danix

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of Application by Daniel Sygut

mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_ebi.h@15:2a20c3d2616e, 2018-02-15 (annotated)

Committer:
Zaitsev
Date:
Thu Feb 15 14:29:23 2018 +0000
Revision:
15:2a20c3d2616e
Parent:
10:41552d038a69 
j

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zaitsev 10:41552d038a69 1 /**************************************************************************//**
Zaitsev 10:41552d038a69 2 * @file efm32wg_ebi.h
Zaitsev 10:41552d038a69 3 * @brief EFM32WG_EBI register and bit field definitions
Zaitsev 10:41552d038a69 4 * @version 5.0.0
Zaitsev 10:41552d038a69 5 ******************************************************************************
Zaitsev 10:41552d038a69 6 * @section License
Zaitsev 10:41552d038a69 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
Zaitsev 10:41552d038a69 8 ******************************************************************************
Zaitsev 10:41552d038a69 9 *
Zaitsev 10:41552d038a69 10 * Permission is granted to anyone to use this software for any purpose,
Zaitsev 10:41552d038a69 11 * including commercial applications, and to alter it and redistribute it
Zaitsev 10:41552d038a69 12 * freely, subject to the following restrictions:
Zaitsev 10:41552d038a69 13 *
Zaitsev 10:41552d038a69 14 * 1. The origin of this software must not be misrepresented; you must not
Zaitsev 10:41552d038a69 15 * claim that you wrote the original software.@n
Zaitsev 10:41552d038a69 16 * 2. Altered source versions must be plainly marked as such, and must not be
Zaitsev 10:41552d038a69 17 * misrepresented as being the original software.@n
Zaitsev 10:41552d038a69 18 * 3. This notice may not be removed or altered from any source distribution.
Zaitsev 10:41552d038a69 19 *
Zaitsev 10:41552d038a69 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
Zaitsev 10:41552d038a69 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
Zaitsev 10:41552d038a69 22 * providing the Software "AS IS", with no express or implied warranties of any
Zaitsev 10:41552d038a69 23 * kind, including, but not limited to, any implied warranties of
Zaitsev 10:41552d038a69 24 * merchantability or fitness for any particular purpose or warranties against
Zaitsev 10:41552d038a69 25 * infringement of any proprietary rights of a third party.
Zaitsev 10:41552d038a69 26 *
Zaitsev 10:41552d038a69 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
Zaitsev 10:41552d038a69 28 * incidental, or special damages, or any other relief, or for any claim by
Zaitsev 10:41552d038a69 29 * any third party, arising from your use of this Software.
Zaitsev 10:41552d038a69 30 *
Zaitsev 10:41552d038a69 31 *****************************************************************************/
Zaitsev 10:41552d038a69 32 /**************************************************************************//**
Zaitsev 10:41552d038a69 33 * @addtogroup Parts
Zaitsev 10:41552d038a69 34 * @{
Zaitsev 10:41552d038a69 35 ******************************************************************************/
Zaitsev 10:41552d038a69 36 /**************************************************************************//**
Zaitsev 10:41552d038a69 37 * @defgroup EFM32WG_EBI
Zaitsev 10:41552d038a69 38 * @{
Zaitsev 10:41552d038a69 39 * @brief EFM32WG_EBI Register Declaration
Zaitsev 10:41552d038a69 40 *****************************************************************************/
Zaitsev 10:41552d038a69 41 typedef struct
Zaitsev 10:41552d038a69 42 {
Zaitsev 10:41552d038a69 43 __IOM uint32_t CTRL; /**< Control Register */
Zaitsev 10:41552d038a69 44 __IOM uint32_t ADDRTIMING; /**< Address Timing Register */
Zaitsev 10:41552d038a69 45 __IOM uint32_t RDTIMING; /**< Read Timing Register */
Zaitsev 10:41552d038a69 46 __IOM uint32_t WRTIMING; /**< Write Timing Register */
Zaitsev 10:41552d038a69 47 __IOM uint32_t POLARITY; /**< Polarity Register */
Zaitsev 10:41552d038a69 48 __IOM uint32_t ROUTE; /**< I/O Routing Register */
Zaitsev 10:41552d038a69 49 __IOM uint32_t ADDRTIMING1; /**< Address Timing Register 1 */
Zaitsev 10:41552d038a69 50 __IOM uint32_t RDTIMING1; /**< Read Timing Register 1 */
Zaitsev 10:41552d038a69 51 __IOM uint32_t WRTIMING1; /**< Write Timing Register 1 */
Zaitsev 10:41552d038a69 52 __IOM uint32_t POLARITY1; /**< Polarity Register 1 */
Zaitsev 10:41552d038a69 53 __IOM uint32_t ADDRTIMING2; /**< Address Timing Register 2 */
Zaitsev 10:41552d038a69 54 __IOM uint32_t RDTIMING2; /**< Read Timing Register 2 */
Zaitsev 10:41552d038a69 55 __IOM uint32_t WRTIMING2; /**< Write Timing Register 2 */
Zaitsev 10:41552d038a69 56 __IOM uint32_t POLARITY2; /**< Polarity Register 2 */
Zaitsev 10:41552d038a69 57 __IOM uint32_t ADDRTIMING3; /**< Address Timing Register 3 */
Zaitsev 10:41552d038a69 58 __IOM uint32_t RDTIMING3; /**< Read Timing Register 3 */
Zaitsev 10:41552d038a69 59 __IOM uint32_t WRTIMING3; /**< Write Timing Register 3 */
Zaitsev 10:41552d038a69 60 __IOM uint32_t POLARITY3; /**< Polarity Register 3 */
Zaitsev 10:41552d038a69 61 __IOM uint32_t PAGECTRL; /**< Page Control Register */
Zaitsev 10:41552d038a69 62 __IOM uint32_t NANDCTRL; /**< NAND Control Register */
Zaitsev 10:41552d038a69 63 __IOM uint32_t CMD; /**< Command Register */
Zaitsev 10:41552d038a69 64 __IM uint32_t STATUS; /**< Status Register */
Zaitsev 10:41552d038a69 65 __IM uint32_t ECCPARITY; /**< ECC Parity register */
Zaitsev 10:41552d038a69 66 __IOM uint32_t TFTCTRL; /**< TFT Control Register */
Zaitsev 10:41552d038a69 67 __IM uint32_t TFTSTATUS; /**< TFT Status Register */
Zaitsev 10:41552d038a69 68 __IOM uint32_t TFTFRAMEBASE; /**< TFT Frame Base Register */
Zaitsev 10:41552d038a69 69 __IOM uint32_t TFTSTRIDE; /**< TFT Stride Register */
Zaitsev 10:41552d038a69 70 __IOM uint32_t TFTSIZE; /**< TFT Size Register */
Zaitsev 10:41552d038a69 71 __IOM uint32_t TFTHPORCH; /**< TFT Horizontal Porch Register */
Zaitsev 10:41552d038a69 72 __IOM uint32_t TFTVPORCH; /**< TFT Vertical Porch Register */
Zaitsev 10:41552d038a69 73 __IOM uint32_t TFTTIMING; /**< TFT Timing Register */
Zaitsev 10:41552d038a69 74 __IOM uint32_t TFTPOLARITY; /**< TFT Polarity Register */
Zaitsev 10:41552d038a69 75 __IOM uint32_t TFTDD; /**< TFT Direct Drive Data Register */
Zaitsev 10:41552d038a69 76 __IOM uint32_t TFTALPHA; /**< TFT Alpha Blending Register */
Zaitsev 10:41552d038a69 77 __IOM uint32_t TFTPIXEL0; /**< TFT Pixel 0 Register */
Zaitsev 10:41552d038a69 78 __IOM uint32_t TFTPIXEL1; /**< TFT Pixel 1 Register */
Zaitsev 10:41552d038a69 79 __IM uint32_t TFTPIXEL; /**< TFT Alpha Blending Result Pixel Register */
Zaitsev 10:41552d038a69 80 __IOM uint32_t TFTMASK; /**< TFT Masking Register */
Zaitsev 10:41552d038a69 81 __IM uint32_t IF; /**< Interrupt Flag Register */
Zaitsev 10:41552d038a69 82 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
Zaitsev 10:41552d038a69 83 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
Zaitsev 10:41552d038a69 84 __IOM uint32_t IEN; /**< Interrupt Enable Register */
Zaitsev 10:41552d038a69 85 } EBI_TypeDef; /** @} */
Zaitsev 10:41552d038a69 86
Zaitsev 10:41552d038a69 87 /**************************************************************************//**
Zaitsev 10:41552d038a69 88 * @defgroup EFM32WG_EBI_BitFields
Zaitsev 10:41552d038a69 89 * @{
Zaitsev 10:41552d038a69 90 *****************************************************************************/
Zaitsev 10:41552d038a69 91
Zaitsev 10:41552d038a69 92 /* Bit fields for EBI CTRL */
Zaitsev 10:41552d038a69 93 #define _EBI_CTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_CTRL */
Zaitsev 10:41552d038a69 94 #define _EBI_CTRL_MASK 0xCFFFFFFFUL /**< Mask for EBI_CTRL */
Zaitsev 10:41552d038a69 95 #define _EBI_CTRL_MODE_SHIFT 0 /**< Shift value for EBI_MODE */
Zaitsev 10:41552d038a69 96 #define _EBI_CTRL_MODE_MASK 0x3UL /**< Bit mask for EBI_MODE */
Zaitsev 10:41552d038a69 97 #define _EBI_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 98 #define _EBI_CTRL_MODE_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */
Zaitsev 10:41552d038a69 99 #define _EBI_CTRL_MODE_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 100 #define _EBI_CTRL_MODE_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 101 #define _EBI_CTRL_MODE_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */
Zaitsev 10:41552d038a69 102 #define EBI_CTRL_MODE_DEFAULT (_EBI_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 103 #define EBI_CTRL_MODE_D8A8 (_EBI_CTRL_MODE_D8A8 << 0) /**< Shifted mode D8A8 for EBI_CTRL */
Zaitsev 10:41552d038a69 104 #define EBI_CTRL_MODE_D16A16ALE (_EBI_CTRL_MODE_D16A16ALE << 0) /**< Shifted mode D16A16ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 105 #define EBI_CTRL_MODE_D8A24ALE (_EBI_CTRL_MODE_D8A24ALE << 0) /**< Shifted mode D8A24ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 106 #define EBI_CTRL_MODE_D16 (_EBI_CTRL_MODE_D16 << 0) /**< Shifted mode D16 for EBI_CTRL */
Zaitsev 10:41552d038a69 107 #define _EBI_CTRL_MODE1_SHIFT 2 /**< Shift value for EBI_MODE1 */
Zaitsev 10:41552d038a69 108 #define _EBI_CTRL_MODE1_MASK 0xCUL /**< Bit mask for EBI_MODE1 */
Zaitsev 10:41552d038a69 109 #define _EBI_CTRL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 110 #define _EBI_CTRL_MODE1_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */
Zaitsev 10:41552d038a69 111 #define _EBI_CTRL_MODE1_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 112 #define _EBI_CTRL_MODE1_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 113 #define _EBI_CTRL_MODE1_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */
Zaitsev 10:41552d038a69 114 #define EBI_CTRL_MODE1_DEFAULT (_EBI_CTRL_MODE1_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 115 #define EBI_CTRL_MODE1_D8A8 (_EBI_CTRL_MODE1_D8A8 << 2) /**< Shifted mode D8A8 for EBI_CTRL */
Zaitsev 10:41552d038a69 116 #define EBI_CTRL_MODE1_D16A16ALE (_EBI_CTRL_MODE1_D16A16ALE << 2) /**< Shifted mode D16A16ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 117 #define EBI_CTRL_MODE1_D8A24ALE (_EBI_CTRL_MODE1_D8A24ALE << 2) /**< Shifted mode D8A24ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 118 #define EBI_CTRL_MODE1_D16 (_EBI_CTRL_MODE1_D16 << 2) /**< Shifted mode D16 for EBI_CTRL */
Zaitsev 10:41552d038a69 119 #define _EBI_CTRL_MODE2_SHIFT 4 /**< Shift value for EBI_MODE2 */
Zaitsev 10:41552d038a69 120 #define _EBI_CTRL_MODE2_MASK 0x30UL /**< Bit mask for EBI_MODE2 */
Zaitsev 10:41552d038a69 121 #define _EBI_CTRL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 122 #define _EBI_CTRL_MODE2_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */
Zaitsev 10:41552d038a69 123 #define _EBI_CTRL_MODE2_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 124 #define _EBI_CTRL_MODE2_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 125 #define _EBI_CTRL_MODE2_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */
Zaitsev 10:41552d038a69 126 #define EBI_CTRL_MODE2_DEFAULT (_EBI_CTRL_MODE2_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 127 #define EBI_CTRL_MODE2_D8A8 (_EBI_CTRL_MODE2_D8A8 << 4) /**< Shifted mode D8A8 for EBI_CTRL */
Zaitsev 10:41552d038a69 128 #define EBI_CTRL_MODE2_D16A16ALE (_EBI_CTRL_MODE2_D16A16ALE << 4) /**< Shifted mode D16A16ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 129 #define EBI_CTRL_MODE2_D8A24ALE (_EBI_CTRL_MODE2_D8A24ALE << 4) /**< Shifted mode D8A24ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 130 #define EBI_CTRL_MODE2_D16 (_EBI_CTRL_MODE2_D16 << 4) /**< Shifted mode D16 for EBI_CTRL */
Zaitsev 10:41552d038a69 131 #define _EBI_CTRL_MODE3_SHIFT 6 /**< Shift value for EBI_MODE3 */
Zaitsev 10:41552d038a69 132 #define _EBI_CTRL_MODE3_MASK 0xC0UL /**< Bit mask for EBI_MODE3 */
Zaitsev 10:41552d038a69 133 #define _EBI_CTRL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 134 #define _EBI_CTRL_MODE3_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */
Zaitsev 10:41552d038a69 135 #define _EBI_CTRL_MODE3_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 136 #define _EBI_CTRL_MODE3_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 137 #define _EBI_CTRL_MODE3_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */
Zaitsev 10:41552d038a69 138 #define EBI_CTRL_MODE3_DEFAULT (_EBI_CTRL_MODE3_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 139 #define EBI_CTRL_MODE3_D8A8 (_EBI_CTRL_MODE3_D8A8 << 6) /**< Shifted mode D8A8 for EBI_CTRL */
Zaitsev 10:41552d038a69 140 #define EBI_CTRL_MODE3_D16A16ALE (_EBI_CTRL_MODE3_D16A16ALE << 6) /**< Shifted mode D16A16ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 141 #define EBI_CTRL_MODE3_D8A24ALE (_EBI_CTRL_MODE3_D8A24ALE << 6) /**< Shifted mode D8A24ALE for EBI_CTRL */
Zaitsev 10:41552d038a69 142 #define EBI_CTRL_MODE3_D16 (_EBI_CTRL_MODE3_D16 << 6) /**< Shifted mode D16 for EBI_CTRL */
Zaitsev 10:41552d038a69 143 #define EBI_CTRL_BANK0EN (0x1UL << 8) /**< Bank 0 Enable */
Zaitsev 10:41552d038a69 144 #define _EBI_CTRL_BANK0EN_SHIFT 8 /**< Shift value for EBI_BANK0EN */
Zaitsev 10:41552d038a69 145 #define _EBI_CTRL_BANK0EN_MASK 0x100UL /**< Bit mask for EBI_BANK0EN */
Zaitsev 10:41552d038a69 146 #define _EBI_CTRL_BANK0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 147 #define EBI_CTRL_BANK0EN_DEFAULT (_EBI_CTRL_BANK0EN_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 148 #define EBI_CTRL_BANK1EN (0x1UL << 9) /**< Bank 1 Enable */
Zaitsev 10:41552d038a69 149 #define _EBI_CTRL_BANK1EN_SHIFT 9 /**< Shift value for EBI_BANK1EN */
Zaitsev 10:41552d038a69 150 #define _EBI_CTRL_BANK1EN_MASK 0x200UL /**< Bit mask for EBI_BANK1EN */
Zaitsev 10:41552d038a69 151 #define _EBI_CTRL_BANK1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 152 #define EBI_CTRL_BANK1EN_DEFAULT (_EBI_CTRL_BANK1EN_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 153 #define EBI_CTRL_BANK2EN (0x1UL << 10) /**< Bank 2 Enable */
Zaitsev 10:41552d038a69 154 #define _EBI_CTRL_BANK2EN_SHIFT 10 /**< Shift value for EBI_BANK2EN */
Zaitsev 10:41552d038a69 155 #define _EBI_CTRL_BANK2EN_MASK 0x400UL /**< Bit mask for EBI_BANK2EN */
Zaitsev 10:41552d038a69 156 #define _EBI_CTRL_BANK2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 157 #define EBI_CTRL_BANK2EN_DEFAULT (_EBI_CTRL_BANK2EN_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 158 #define EBI_CTRL_BANK3EN (0x1UL << 11) /**< Bank 3 Enable */
Zaitsev 10:41552d038a69 159 #define _EBI_CTRL_BANK3EN_SHIFT 11 /**< Shift value for EBI_BANK3EN */
Zaitsev 10:41552d038a69 160 #define _EBI_CTRL_BANK3EN_MASK 0x800UL /**< Bit mask for EBI_BANK3EN */
Zaitsev 10:41552d038a69 161 #define _EBI_CTRL_BANK3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 162 #define EBI_CTRL_BANK3EN_DEFAULT (_EBI_CTRL_BANK3EN_DEFAULT << 11) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 163 #define EBI_CTRL_NOIDLE (0x1UL << 12) /**< No idle cycle insertion on bank 0. */
Zaitsev 10:41552d038a69 164 #define _EBI_CTRL_NOIDLE_SHIFT 12 /**< Shift value for EBI_NOIDLE */
Zaitsev 10:41552d038a69 165 #define _EBI_CTRL_NOIDLE_MASK 0x1000UL /**< Bit mask for EBI_NOIDLE */
Zaitsev 10:41552d038a69 166 #define _EBI_CTRL_NOIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 167 #define EBI_CTRL_NOIDLE_DEFAULT (_EBI_CTRL_NOIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 168 #define EBI_CTRL_NOIDLE1 (0x1UL << 13) /**< No idle cycle insertion on bank 1. */
Zaitsev 10:41552d038a69 169 #define _EBI_CTRL_NOIDLE1_SHIFT 13 /**< Shift value for EBI_NOIDLE1 */
Zaitsev 10:41552d038a69 170 #define _EBI_CTRL_NOIDLE1_MASK 0x2000UL /**< Bit mask for EBI_NOIDLE1 */
Zaitsev 10:41552d038a69 171 #define _EBI_CTRL_NOIDLE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 172 #define EBI_CTRL_NOIDLE1_DEFAULT (_EBI_CTRL_NOIDLE1_DEFAULT << 13) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 173 #define EBI_CTRL_NOIDLE2 (0x1UL << 14) /**< No idle cycle insertion on bank 2. */
Zaitsev 10:41552d038a69 174 #define _EBI_CTRL_NOIDLE2_SHIFT 14 /**< Shift value for EBI_NOIDLE2 */
Zaitsev 10:41552d038a69 175 #define _EBI_CTRL_NOIDLE2_MASK 0x4000UL /**< Bit mask for EBI_NOIDLE2 */
Zaitsev 10:41552d038a69 176 #define _EBI_CTRL_NOIDLE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 177 #define EBI_CTRL_NOIDLE2_DEFAULT (_EBI_CTRL_NOIDLE2_DEFAULT << 14) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 178 #define EBI_CTRL_NOIDLE3 (0x1UL << 15) /**< No idle cycle insertion on bank 3. */
Zaitsev 10:41552d038a69 179 #define _EBI_CTRL_NOIDLE3_SHIFT 15 /**< Shift value for EBI_NOIDLE3 */
Zaitsev 10:41552d038a69 180 #define _EBI_CTRL_NOIDLE3_MASK 0x8000UL /**< Bit mask for EBI_NOIDLE3 */
Zaitsev 10:41552d038a69 181 #define _EBI_CTRL_NOIDLE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 182 #define EBI_CTRL_NOIDLE3_DEFAULT (_EBI_CTRL_NOIDLE3_DEFAULT << 15) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 183 #define EBI_CTRL_ARDYEN (0x1UL << 16) /**< ARDY Enable */
Zaitsev 10:41552d038a69 184 #define _EBI_CTRL_ARDYEN_SHIFT 16 /**< Shift value for EBI_ARDYEN */
Zaitsev 10:41552d038a69 185 #define _EBI_CTRL_ARDYEN_MASK 0x10000UL /**< Bit mask for EBI_ARDYEN */
Zaitsev 10:41552d038a69 186 #define _EBI_CTRL_ARDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 187 #define EBI_CTRL_ARDYEN_DEFAULT (_EBI_CTRL_ARDYEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 188 #define EBI_CTRL_ARDYTODIS (0x1UL << 17) /**< ARDY Timeout Disable */
Zaitsev 10:41552d038a69 189 #define _EBI_CTRL_ARDYTODIS_SHIFT 17 /**< Shift value for EBI_ARDYTODIS */
Zaitsev 10:41552d038a69 190 #define _EBI_CTRL_ARDYTODIS_MASK 0x20000UL /**< Bit mask for EBI_ARDYTODIS */
Zaitsev 10:41552d038a69 191 #define _EBI_CTRL_ARDYTODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 192 #define EBI_CTRL_ARDYTODIS_DEFAULT (_EBI_CTRL_ARDYTODIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 193 #define EBI_CTRL_ARDY1EN (0x1UL << 18) /**< ARDY Enable for bank 1 */
Zaitsev 10:41552d038a69 194 #define _EBI_CTRL_ARDY1EN_SHIFT 18 /**< Shift value for EBI_ARDY1EN */
Zaitsev 10:41552d038a69 195 #define _EBI_CTRL_ARDY1EN_MASK 0x40000UL /**< Bit mask for EBI_ARDY1EN */
Zaitsev 10:41552d038a69 196 #define _EBI_CTRL_ARDY1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 197 #define EBI_CTRL_ARDY1EN_DEFAULT (_EBI_CTRL_ARDY1EN_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 198 #define EBI_CTRL_ARDYTO1DIS (0x1UL << 19) /**< ARDY Timeout Disable for bank 1 */
Zaitsev 10:41552d038a69 199 #define _EBI_CTRL_ARDYTO1DIS_SHIFT 19 /**< Shift value for EBI_ARDYTO1DIS */
Zaitsev 10:41552d038a69 200 #define _EBI_CTRL_ARDYTO1DIS_MASK 0x80000UL /**< Bit mask for EBI_ARDYTO1DIS */
Zaitsev 10:41552d038a69 201 #define _EBI_CTRL_ARDYTO1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 202 #define EBI_CTRL_ARDYTO1DIS_DEFAULT (_EBI_CTRL_ARDYTO1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 203 #define EBI_CTRL_ARDY2EN (0x1UL << 20) /**< ARDY Enable for bank 2 */
Zaitsev 10:41552d038a69 204 #define _EBI_CTRL_ARDY2EN_SHIFT 20 /**< Shift value for EBI_ARDY2EN */
Zaitsev 10:41552d038a69 205 #define _EBI_CTRL_ARDY2EN_MASK 0x100000UL /**< Bit mask for EBI_ARDY2EN */
Zaitsev 10:41552d038a69 206 #define _EBI_CTRL_ARDY2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 207 #define EBI_CTRL_ARDY2EN_DEFAULT (_EBI_CTRL_ARDY2EN_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 208 #define EBI_CTRL_ARDYTO2DIS (0x1UL << 21) /**< ARDY Timeout Disable for bank 2 */
Zaitsev 10:41552d038a69 209 #define _EBI_CTRL_ARDYTO2DIS_SHIFT 21 /**< Shift value for EBI_ARDYTO2DIS */
Zaitsev 10:41552d038a69 210 #define _EBI_CTRL_ARDYTO2DIS_MASK 0x200000UL /**< Bit mask for EBI_ARDYTO2DIS */
Zaitsev 10:41552d038a69 211 #define _EBI_CTRL_ARDYTO2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 212 #define EBI_CTRL_ARDYTO2DIS_DEFAULT (_EBI_CTRL_ARDYTO2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 213 #define EBI_CTRL_ARDY3EN (0x1UL << 22) /**< ARDY Enable for bank 3 */
Zaitsev 10:41552d038a69 214 #define _EBI_CTRL_ARDY3EN_SHIFT 22 /**< Shift value for EBI_ARDY3EN */
Zaitsev 10:41552d038a69 215 #define _EBI_CTRL_ARDY3EN_MASK 0x400000UL /**< Bit mask for EBI_ARDY3EN */
Zaitsev 10:41552d038a69 216 #define _EBI_CTRL_ARDY3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 217 #define EBI_CTRL_ARDY3EN_DEFAULT (_EBI_CTRL_ARDY3EN_DEFAULT << 22) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 218 #define EBI_CTRL_ARDYTO3DIS (0x1UL << 23) /**< ARDY Timeout Disable for bank 3 */
Zaitsev 10:41552d038a69 219 #define _EBI_CTRL_ARDYTO3DIS_SHIFT 23 /**< Shift value for EBI_ARDYTO3DIS */
Zaitsev 10:41552d038a69 220 #define _EBI_CTRL_ARDYTO3DIS_MASK 0x800000UL /**< Bit mask for EBI_ARDYTO3DIS */
Zaitsev 10:41552d038a69 221 #define _EBI_CTRL_ARDYTO3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 222 #define EBI_CTRL_ARDYTO3DIS_DEFAULT (_EBI_CTRL_ARDYTO3DIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 223 #define EBI_CTRL_BL (0x1UL << 24) /**< Byte Lane Enable for bank 0 */
Zaitsev 10:41552d038a69 224 #define _EBI_CTRL_BL_SHIFT 24 /**< Shift value for EBI_BL */
Zaitsev 10:41552d038a69 225 #define _EBI_CTRL_BL_MASK 0x1000000UL /**< Bit mask for EBI_BL */
Zaitsev 10:41552d038a69 226 #define _EBI_CTRL_BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 227 #define EBI_CTRL_BL_DEFAULT (_EBI_CTRL_BL_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 228 #define EBI_CTRL_BL1 (0x1UL << 25) /**< Byte Lane Enable for bank 1 */
Zaitsev 10:41552d038a69 229 #define _EBI_CTRL_BL1_SHIFT 25 /**< Shift value for EBI_BL1 */
Zaitsev 10:41552d038a69 230 #define _EBI_CTRL_BL1_MASK 0x2000000UL /**< Bit mask for EBI_BL1 */
Zaitsev 10:41552d038a69 231 #define _EBI_CTRL_BL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 232 #define EBI_CTRL_BL1_DEFAULT (_EBI_CTRL_BL1_DEFAULT << 25) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 233 #define EBI_CTRL_BL2 (0x1UL << 26) /**< Byte Lane Enable for bank 2 */
Zaitsev 10:41552d038a69 234 #define _EBI_CTRL_BL2_SHIFT 26 /**< Shift value for EBI_BL2 */
Zaitsev 10:41552d038a69 235 #define _EBI_CTRL_BL2_MASK 0x4000000UL /**< Bit mask for EBI_BL2 */
Zaitsev 10:41552d038a69 236 #define _EBI_CTRL_BL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 237 #define EBI_CTRL_BL2_DEFAULT (_EBI_CTRL_BL2_DEFAULT << 26) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 238 #define EBI_CTRL_BL3 (0x1UL << 27) /**< Byte Lane Enable for bank 3 */
Zaitsev 10:41552d038a69 239 #define _EBI_CTRL_BL3_SHIFT 27 /**< Shift value for EBI_BL3 */
Zaitsev 10:41552d038a69 240 #define _EBI_CTRL_BL3_MASK 0x8000000UL /**< Bit mask for EBI_BL3 */
Zaitsev 10:41552d038a69 241 #define _EBI_CTRL_BL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 242 #define EBI_CTRL_BL3_DEFAULT (_EBI_CTRL_BL3_DEFAULT << 27) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 243 #define EBI_CTRL_ITS (0x1UL << 30) /**< Individual Timing Set, Line Polarity and Mode Definition Enable */
Zaitsev 10:41552d038a69 244 #define _EBI_CTRL_ITS_SHIFT 30 /**< Shift value for EBI_ITS */
Zaitsev 10:41552d038a69 245 #define _EBI_CTRL_ITS_MASK 0x40000000UL /**< Bit mask for EBI_ITS */
Zaitsev 10:41552d038a69 246 #define _EBI_CTRL_ITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 247 #define EBI_CTRL_ITS_DEFAULT (_EBI_CTRL_ITS_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 248 #define EBI_CTRL_ALTMAP (0x1UL << 31) /**< Alternative Address Map Enable */
Zaitsev 10:41552d038a69 249 #define _EBI_CTRL_ALTMAP_SHIFT 31 /**< Shift value for EBI_ALTMAP */
Zaitsev 10:41552d038a69 250 #define _EBI_CTRL_ALTMAP_MASK 0x80000000UL /**< Bit mask for EBI_ALTMAP */
Zaitsev 10:41552d038a69 251 #define _EBI_CTRL_ALTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 252 #define EBI_CTRL_ALTMAP_DEFAULT (_EBI_CTRL_ALTMAP_DEFAULT << 31) /**< Shifted mode DEFAULT for EBI_CTRL */
Zaitsev 10:41552d038a69 253
Zaitsev 10:41552d038a69 254 /* Bit fields for EBI ADDRTIMING */
Zaitsev 10:41552d038a69 255 #define _EBI_ADDRTIMING_RESETVALUE 0x00000303UL /**< Default value for EBI_ADDRTIMING */
Zaitsev 10:41552d038a69 256 #define _EBI_ADDRTIMING_MASK 0x10000303UL /**< Mask for EBI_ADDRTIMING */
Zaitsev 10:41552d038a69 257 #define _EBI_ADDRTIMING_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */
Zaitsev 10:41552d038a69 258 #define _EBI_ADDRTIMING_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */
Zaitsev 10:41552d038a69 259 #define _EBI_ADDRTIMING_ADDRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING */
Zaitsev 10:41552d038a69 260 #define EBI_ADDRTIMING_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */
Zaitsev 10:41552d038a69 261 #define _EBI_ADDRTIMING_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */
Zaitsev 10:41552d038a69 262 #define _EBI_ADDRTIMING_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */
Zaitsev 10:41552d038a69 263 #define _EBI_ADDRTIMING_ADDRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING */
Zaitsev 10:41552d038a69 264 #define EBI_ADDRTIMING_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */
Zaitsev 10:41552d038a69 265 #define EBI_ADDRTIMING_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */
Zaitsev 10:41552d038a69 266 #define _EBI_ADDRTIMING_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */
Zaitsev 10:41552d038a69 267 #define _EBI_ADDRTIMING_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */
Zaitsev 10:41552d038a69 268 #define _EBI_ADDRTIMING_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING */
Zaitsev 10:41552d038a69 269 #define EBI_ADDRTIMING_HALFALE_DEFAULT (_EBI_ADDRTIMING_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */
Zaitsev 10:41552d038a69 270
Zaitsev 10:41552d038a69 271 /* Bit fields for EBI RDTIMING */
Zaitsev 10:41552d038a69 272 #define _EBI_RDTIMING_RESETVALUE 0x00033F03UL /**< Default value for EBI_RDTIMING */
Zaitsev 10:41552d038a69 273 #define _EBI_RDTIMING_MASK 0x70033F03UL /**< Mask for EBI_RDTIMING */
Zaitsev 10:41552d038a69 274 #define _EBI_RDTIMING_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */
Zaitsev 10:41552d038a69 275 #define _EBI_RDTIMING_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */
Zaitsev 10:41552d038a69 276 #define _EBI_RDTIMING_RDSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING */
Zaitsev 10:41552d038a69 277 #define EBI_RDTIMING_RDSETUP_DEFAULT (_EBI_RDTIMING_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING */
Zaitsev 10:41552d038a69 278 #define _EBI_RDTIMING_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */
Zaitsev 10:41552d038a69 279 #define _EBI_RDTIMING_RDSTRB_MASK 0x3F00UL /**< Bit mask for EBI_RDSTRB */
Zaitsev 10:41552d038a69 280 #define _EBI_RDTIMING_RDSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_RDTIMING */
Zaitsev 10:41552d038a69 281 #define EBI_RDTIMING_RDSTRB_DEFAULT (_EBI_RDTIMING_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING */
Zaitsev 10:41552d038a69 282 #define _EBI_RDTIMING_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */
Zaitsev 10:41552d038a69 283 #define _EBI_RDTIMING_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */
Zaitsev 10:41552d038a69 284 #define _EBI_RDTIMING_RDHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING */
Zaitsev 10:41552d038a69 285 #define EBI_RDTIMING_RDHOLD_DEFAULT (_EBI_RDTIMING_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING */
Zaitsev 10:41552d038a69 286 #define EBI_RDTIMING_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */
Zaitsev 10:41552d038a69 287 #define _EBI_RDTIMING_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */
Zaitsev 10:41552d038a69 288 #define _EBI_RDTIMING_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */
Zaitsev 10:41552d038a69 289 #define _EBI_RDTIMING_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */
Zaitsev 10:41552d038a69 290 #define EBI_RDTIMING_HALFRE_DEFAULT (_EBI_RDTIMING_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING */
Zaitsev 10:41552d038a69 291 #define EBI_RDTIMING_PREFETCH (0x1UL << 29) /**< Prefetch Enable */
Zaitsev 10:41552d038a69 292 #define _EBI_RDTIMING_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */
Zaitsev 10:41552d038a69 293 #define _EBI_RDTIMING_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */
Zaitsev 10:41552d038a69 294 #define _EBI_RDTIMING_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */
Zaitsev 10:41552d038a69 295 #define EBI_RDTIMING_PREFETCH_DEFAULT (_EBI_RDTIMING_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING */
Zaitsev 10:41552d038a69 296 #define EBI_RDTIMING_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */
Zaitsev 10:41552d038a69 297 #define _EBI_RDTIMING_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */
Zaitsev 10:41552d038a69 298 #define _EBI_RDTIMING_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */
Zaitsev 10:41552d038a69 299 #define _EBI_RDTIMING_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */
Zaitsev 10:41552d038a69 300 #define EBI_RDTIMING_PAGEMODE_DEFAULT (_EBI_RDTIMING_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING */
Zaitsev 10:41552d038a69 301
Zaitsev 10:41552d038a69 302 /* Bit fields for EBI WRTIMING */
Zaitsev 10:41552d038a69 303 #define _EBI_WRTIMING_RESETVALUE 0x00033F03UL /**< Default value for EBI_WRTIMING */
Zaitsev 10:41552d038a69 304 #define _EBI_WRTIMING_MASK 0x30033F03UL /**< Mask for EBI_WRTIMING */
Zaitsev 10:41552d038a69 305 #define _EBI_WRTIMING_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */
Zaitsev 10:41552d038a69 306 #define _EBI_WRTIMING_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */
Zaitsev 10:41552d038a69 307 #define _EBI_WRTIMING_WRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING */
Zaitsev 10:41552d038a69 308 #define EBI_WRTIMING_WRSETUP_DEFAULT (_EBI_WRTIMING_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING */
Zaitsev 10:41552d038a69 309 #define _EBI_WRTIMING_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */
Zaitsev 10:41552d038a69 310 #define _EBI_WRTIMING_WRSTRB_MASK 0x3F00UL /**< Bit mask for EBI_WRSTRB */
Zaitsev 10:41552d038a69 311 #define _EBI_WRTIMING_WRSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_WRTIMING */
Zaitsev 10:41552d038a69 312 #define EBI_WRTIMING_WRSTRB_DEFAULT (_EBI_WRTIMING_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING */
Zaitsev 10:41552d038a69 313 #define _EBI_WRTIMING_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */
Zaitsev 10:41552d038a69 314 #define _EBI_WRTIMING_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */
Zaitsev 10:41552d038a69 315 #define _EBI_WRTIMING_WRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING */
Zaitsev 10:41552d038a69 316 #define EBI_WRTIMING_WRHOLD_DEFAULT (_EBI_WRTIMING_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING */
Zaitsev 10:41552d038a69 317 #define EBI_WRTIMING_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */
Zaitsev 10:41552d038a69 318 #define _EBI_WRTIMING_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */
Zaitsev 10:41552d038a69 319 #define _EBI_WRTIMING_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */
Zaitsev 10:41552d038a69 320 #define _EBI_WRTIMING_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */
Zaitsev 10:41552d038a69 321 #define EBI_WRTIMING_HALFWE_DEFAULT (_EBI_WRTIMING_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING */
Zaitsev 10:41552d038a69 322 #define EBI_WRTIMING_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */
Zaitsev 10:41552d038a69 323 #define _EBI_WRTIMING_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */
Zaitsev 10:41552d038a69 324 #define _EBI_WRTIMING_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */
Zaitsev 10:41552d038a69 325 #define _EBI_WRTIMING_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */
Zaitsev 10:41552d038a69 326 #define EBI_WRTIMING_WBUFDIS_DEFAULT (_EBI_WRTIMING_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING */
Zaitsev 10:41552d038a69 327
Zaitsev 10:41552d038a69 328 /* Bit fields for EBI POLARITY */
Zaitsev 10:41552d038a69 329 #define _EBI_POLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY */
Zaitsev 10:41552d038a69 330 #define _EBI_POLARITY_MASK 0x0000003FUL /**< Mask for EBI_POLARITY */
Zaitsev 10:41552d038a69 331 #define EBI_POLARITY_CSPOL (0x1UL << 0) /**< Chip Select Polarity */
Zaitsev 10:41552d038a69 332 #define _EBI_POLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */
Zaitsev 10:41552d038a69 333 #define _EBI_POLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */
Zaitsev 10:41552d038a69 334 #define _EBI_POLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
Zaitsev 10:41552d038a69 335 #define _EBI_POLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
Zaitsev 10:41552d038a69 336 #define _EBI_POLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
Zaitsev 10:41552d038a69 337 #define EBI_POLARITY_CSPOL_DEFAULT (_EBI_POLARITY_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY */
Zaitsev 10:41552d038a69 338 #define EBI_POLARITY_CSPOL_ACTIVELOW (_EBI_POLARITY_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
Zaitsev 10:41552d038a69 339 #define EBI_POLARITY_CSPOL_ACTIVEHIGH (_EBI_POLARITY_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
Zaitsev 10:41552d038a69 340 #define EBI_POLARITY_REPOL (0x1UL << 1) /**< Read Enable Polarity */
Zaitsev 10:41552d038a69 341 #define _EBI_POLARITY_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */
Zaitsev 10:41552d038a69 342 #define _EBI_POLARITY_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */
Zaitsev 10:41552d038a69 343 #define _EBI_POLARITY_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
Zaitsev 10:41552d038a69 344 #define _EBI_POLARITY_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
Zaitsev 10:41552d038a69 345 #define _EBI_POLARITY_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
Zaitsev 10:41552d038a69 346 #define EBI_POLARITY_REPOL_DEFAULT (_EBI_POLARITY_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY */
Zaitsev 10:41552d038a69 347 #define EBI_POLARITY_REPOL_ACTIVELOW (_EBI_POLARITY_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
Zaitsev 10:41552d038a69 348 #define EBI_POLARITY_REPOL_ACTIVEHIGH (_EBI_POLARITY_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
Zaitsev 10:41552d038a69 349 #define EBI_POLARITY_WEPOL (0x1UL << 2) /**< Write Enable Polarity */
Zaitsev 10:41552d038a69 350 #define _EBI_POLARITY_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */
Zaitsev 10:41552d038a69 351 #define _EBI_POLARITY_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */
Zaitsev 10:41552d038a69 352 #define _EBI_POLARITY_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
Zaitsev 10:41552d038a69 353 #define _EBI_POLARITY_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
Zaitsev 10:41552d038a69 354 #define _EBI_POLARITY_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
Zaitsev 10:41552d038a69 355 #define EBI_POLARITY_WEPOL_DEFAULT (_EBI_POLARITY_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY */
Zaitsev 10:41552d038a69 356 #define EBI_POLARITY_WEPOL_ACTIVELOW (_EBI_POLARITY_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
Zaitsev 10:41552d038a69 357 #define EBI_POLARITY_WEPOL_ACTIVEHIGH (_EBI_POLARITY_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
Zaitsev 10:41552d038a69 358 #define EBI_POLARITY_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */
Zaitsev 10:41552d038a69 359 #define _EBI_POLARITY_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */
Zaitsev 10:41552d038a69 360 #define _EBI_POLARITY_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */
Zaitsev 10:41552d038a69 361 #define _EBI_POLARITY_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
Zaitsev 10:41552d038a69 362 #define _EBI_POLARITY_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
Zaitsev 10:41552d038a69 363 #define _EBI_POLARITY_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
Zaitsev 10:41552d038a69 364 #define EBI_POLARITY_ALEPOL_DEFAULT (_EBI_POLARITY_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY */
Zaitsev 10:41552d038a69 365 #define EBI_POLARITY_ALEPOL_ACTIVELOW (_EBI_POLARITY_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
Zaitsev 10:41552d038a69 366 #define EBI_POLARITY_ALEPOL_ACTIVEHIGH (_EBI_POLARITY_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
Zaitsev 10:41552d038a69 367 #define EBI_POLARITY_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */
Zaitsev 10:41552d038a69 368 #define _EBI_POLARITY_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */
Zaitsev 10:41552d038a69 369 #define _EBI_POLARITY_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */
Zaitsev 10:41552d038a69 370 #define _EBI_POLARITY_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
Zaitsev 10:41552d038a69 371 #define _EBI_POLARITY_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
Zaitsev 10:41552d038a69 372 #define _EBI_POLARITY_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
Zaitsev 10:41552d038a69 373 #define EBI_POLARITY_ARDYPOL_DEFAULT (_EBI_POLARITY_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY */
Zaitsev 10:41552d038a69 374 #define EBI_POLARITY_ARDYPOL_ACTIVELOW (_EBI_POLARITY_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
Zaitsev 10:41552d038a69 375 #define EBI_POLARITY_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
Zaitsev 10:41552d038a69 376 #define EBI_POLARITY_BLPOL (0x1UL << 5) /**< BL Polarity */
Zaitsev 10:41552d038a69 377 #define _EBI_POLARITY_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */
Zaitsev 10:41552d038a69 378 #define _EBI_POLARITY_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */
Zaitsev 10:41552d038a69 379 #define _EBI_POLARITY_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
Zaitsev 10:41552d038a69 380 #define _EBI_POLARITY_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
Zaitsev 10:41552d038a69 381 #define _EBI_POLARITY_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
Zaitsev 10:41552d038a69 382 #define EBI_POLARITY_BLPOL_DEFAULT (_EBI_POLARITY_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY */
Zaitsev 10:41552d038a69 383 #define EBI_POLARITY_BLPOL_ACTIVELOW (_EBI_POLARITY_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
Zaitsev 10:41552d038a69 384 #define EBI_POLARITY_BLPOL_ACTIVEHIGH (_EBI_POLARITY_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
Zaitsev 10:41552d038a69 385
Zaitsev 10:41552d038a69 386 /* Bit fields for EBI ROUTE */
Zaitsev 10:41552d038a69 387 #define _EBI_ROUTE_RESETVALUE 0x00000000UL /**< Default value for EBI_ROUTE */
Zaitsev 10:41552d038a69 388 #define _EBI_ROUTE_MASK 0x777F10FFUL /**< Mask for EBI_ROUTE */
Zaitsev 10:41552d038a69 389 #define EBI_ROUTE_EBIPEN (0x1UL << 0) /**< EBI Pin Enable */
Zaitsev 10:41552d038a69 390 #define _EBI_ROUTE_EBIPEN_SHIFT 0 /**< Shift value for EBI_EBIPEN */
Zaitsev 10:41552d038a69 391 #define _EBI_ROUTE_EBIPEN_MASK 0x1UL /**< Bit mask for EBI_EBIPEN */
Zaitsev 10:41552d038a69 392 #define _EBI_ROUTE_EBIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 393 #define EBI_ROUTE_EBIPEN_DEFAULT (_EBI_ROUTE_EBIPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 394 #define EBI_ROUTE_CS0PEN (0x1UL << 1) /**< EBI_CS0 Pin Enable */
Zaitsev 10:41552d038a69 395 #define _EBI_ROUTE_CS0PEN_SHIFT 1 /**< Shift value for EBI_CS0PEN */
Zaitsev 10:41552d038a69 396 #define _EBI_ROUTE_CS0PEN_MASK 0x2UL /**< Bit mask for EBI_CS0PEN */
Zaitsev 10:41552d038a69 397 #define _EBI_ROUTE_CS0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 398 #define EBI_ROUTE_CS0PEN_DEFAULT (_EBI_ROUTE_CS0PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 399 #define EBI_ROUTE_CS1PEN (0x1UL << 2) /**< EBI_CS1 Pin Enable */
Zaitsev 10:41552d038a69 400 #define _EBI_ROUTE_CS1PEN_SHIFT 2 /**< Shift value for EBI_CS1PEN */
Zaitsev 10:41552d038a69 401 #define _EBI_ROUTE_CS1PEN_MASK 0x4UL /**< Bit mask for EBI_CS1PEN */
Zaitsev 10:41552d038a69 402 #define _EBI_ROUTE_CS1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 403 #define EBI_ROUTE_CS1PEN_DEFAULT (_EBI_ROUTE_CS1PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 404 #define EBI_ROUTE_CS2PEN (0x1UL << 3) /**< EBI_CS2 Pin Enable */
Zaitsev 10:41552d038a69 405 #define _EBI_ROUTE_CS2PEN_SHIFT 3 /**< Shift value for EBI_CS2PEN */
Zaitsev 10:41552d038a69 406 #define _EBI_ROUTE_CS2PEN_MASK 0x8UL /**< Bit mask for EBI_CS2PEN */
Zaitsev 10:41552d038a69 407 #define _EBI_ROUTE_CS2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 408 #define EBI_ROUTE_CS2PEN_DEFAULT (_EBI_ROUTE_CS2PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 409 #define EBI_ROUTE_CS3PEN (0x1UL << 4) /**< EBI_CS3 Pin Enable */
Zaitsev 10:41552d038a69 410 #define _EBI_ROUTE_CS3PEN_SHIFT 4 /**< Shift value for EBI_CS3PEN */
Zaitsev 10:41552d038a69 411 #define _EBI_ROUTE_CS3PEN_MASK 0x10UL /**< Bit mask for EBI_CS3PEN */
Zaitsev 10:41552d038a69 412 #define _EBI_ROUTE_CS3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 413 #define EBI_ROUTE_CS3PEN_DEFAULT (_EBI_ROUTE_CS3PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 414 #define EBI_ROUTE_ALEPEN (0x1UL << 5) /**< EBI_ALE Pin Enable */
Zaitsev 10:41552d038a69 415 #define _EBI_ROUTE_ALEPEN_SHIFT 5 /**< Shift value for EBI_ALEPEN */
Zaitsev 10:41552d038a69 416 #define _EBI_ROUTE_ALEPEN_MASK 0x20UL /**< Bit mask for EBI_ALEPEN */
Zaitsev 10:41552d038a69 417 #define _EBI_ROUTE_ALEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 418 #define EBI_ROUTE_ALEPEN_DEFAULT (_EBI_ROUTE_ALEPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 419 #define EBI_ROUTE_ARDYPEN (0x1UL << 6) /**< EBI_ARDY Pin Enable */
Zaitsev 10:41552d038a69 420 #define _EBI_ROUTE_ARDYPEN_SHIFT 6 /**< Shift value for EBI_ARDYPEN */
Zaitsev 10:41552d038a69 421 #define _EBI_ROUTE_ARDYPEN_MASK 0x40UL /**< Bit mask for EBI_ARDYPEN */
Zaitsev 10:41552d038a69 422 #define _EBI_ROUTE_ARDYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 423 #define EBI_ROUTE_ARDYPEN_DEFAULT (_EBI_ROUTE_ARDYPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 424 #define EBI_ROUTE_BLPEN (0x1UL << 7) /**< EBI_BL[1:0] Pin Enable */
Zaitsev 10:41552d038a69 425 #define _EBI_ROUTE_BLPEN_SHIFT 7 /**< Shift value for EBI_BLPEN */
Zaitsev 10:41552d038a69 426 #define _EBI_ROUTE_BLPEN_MASK 0x80UL /**< Bit mask for EBI_BLPEN */
Zaitsev 10:41552d038a69 427 #define _EBI_ROUTE_BLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 428 #define EBI_ROUTE_BLPEN_DEFAULT (_EBI_ROUTE_BLPEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 429 #define EBI_ROUTE_NANDPEN (0x1UL << 12) /**< NANDRE and NANDWE Pin Enable */
Zaitsev 10:41552d038a69 430 #define _EBI_ROUTE_NANDPEN_SHIFT 12 /**< Shift value for EBI_NANDPEN */
Zaitsev 10:41552d038a69 431 #define _EBI_ROUTE_NANDPEN_MASK 0x1000UL /**< Bit mask for EBI_NANDPEN */
Zaitsev 10:41552d038a69 432 #define _EBI_ROUTE_NANDPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 433 #define EBI_ROUTE_NANDPEN_DEFAULT (_EBI_ROUTE_NANDPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 434 #define _EBI_ROUTE_ALB_SHIFT 16 /**< Shift value for EBI_ALB */
Zaitsev 10:41552d038a69 435 #define _EBI_ROUTE_ALB_MASK 0x30000UL /**< Bit mask for EBI_ALB */
Zaitsev 10:41552d038a69 436 #define _EBI_ROUTE_ALB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 437 #define _EBI_ROUTE_ALB_A0 0x00000000UL /**< Mode A0 for EBI_ROUTE */
Zaitsev 10:41552d038a69 438 #define _EBI_ROUTE_ALB_A8 0x00000001UL /**< Mode A8 for EBI_ROUTE */
Zaitsev 10:41552d038a69 439 #define _EBI_ROUTE_ALB_A16 0x00000002UL /**< Mode A16 for EBI_ROUTE */
Zaitsev 10:41552d038a69 440 #define _EBI_ROUTE_ALB_A24 0x00000003UL /**< Mode A24 for EBI_ROUTE */
Zaitsev 10:41552d038a69 441 #define EBI_ROUTE_ALB_DEFAULT (_EBI_ROUTE_ALB_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 442 #define EBI_ROUTE_ALB_A0 (_EBI_ROUTE_ALB_A0 << 16) /**< Shifted mode A0 for EBI_ROUTE */
Zaitsev 10:41552d038a69 443 #define EBI_ROUTE_ALB_A8 (_EBI_ROUTE_ALB_A8 << 16) /**< Shifted mode A8 for EBI_ROUTE */
Zaitsev 10:41552d038a69 444 #define EBI_ROUTE_ALB_A16 (_EBI_ROUTE_ALB_A16 << 16) /**< Shifted mode A16 for EBI_ROUTE */
Zaitsev 10:41552d038a69 445 #define EBI_ROUTE_ALB_A24 (_EBI_ROUTE_ALB_A24 << 16) /**< Shifted mode A24 for EBI_ROUTE */
Zaitsev 10:41552d038a69 446 #define _EBI_ROUTE_APEN_SHIFT 18 /**< Shift value for EBI_APEN */
Zaitsev 10:41552d038a69 447 #define _EBI_ROUTE_APEN_MASK 0x7C0000UL /**< Bit mask for EBI_APEN */
Zaitsev 10:41552d038a69 448 #define _EBI_ROUTE_APEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 449 #define _EBI_ROUTE_APEN_A0 0x00000000UL /**< Mode A0 for EBI_ROUTE */
Zaitsev 10:41552d038a69 450 #define _EBI_ROUTE_APEN_A5 0x00000005UL /**< Mode A5 for EBI_ROUTE */
Zaitsev 10:41552d038a69 451 #define _EBI_ROUTE_APEN_A6 0x00000006UL /**< Mode A6 for EBI_ROUTE */
Zaitsev 10:41552d038a69 452 #define _EBI_ROUTE_APEN_A7 0x00000007UL /**< Mode A7 for EBI_ROUTE */
Zaitsev 10:41552d038a69 453 #define _EBI_ROUTE_APEN_A8 0x00000008UL /**< Mode A8 for EBI_ROUTE */
Zaitsev 10:41552d038a69 454 #define _EBI_ROUTE_APEN_A9 0x00000009UL /**< Mode A9 for EBI_ROUTE */
Zaitsev 10:41552d038a69 455 #define _EBI_ROUTE_APEN_A10 0x0000000AUL /**< Mode A10 for EBI_ROUTE */
Zaitsev 10:41552d038a69 456 #define _EBI_ROUTE_APEN_A11 0x0000000BUL /**< Mode A11 for EBI_ROUTE */
Zaitsev 10:41552d038a69 457 #define _EBI_ROUTE_APEN_A12 0x0000000CUL /**< Mode A12 for EBI_ROUTE */
Zaitsev 10:41552d038a69 458 #define _EBI_ROUTE_APEN_A13 0x0000000DUL /**< Mode A13 for EBI_ROUTE */
Zaitsev 10:41552d038a69 459 #define _EBI_ROUTE_APEN_A14 0x0000000EUL /**< Mode A14 for EBI_ROUTE */
Zaitsev 10:41552d038a69 460 #define _EBI_ROUTE_APEN_A15 0x0000000FUL /**< Mode A15 for EBI_ROUTE */
Zaitsev 10:41552d038a69 461 #define _EBI_ROUTE_APEN_A16 0x00000010UL /**< Mode A16 for EBI_ROUTE */
Zaitsev 10:41552d038a69 462 #define _EBI_ROUTE_APEN_A17 0x00000011UL /**< Mode A17 for EBI_ROUTE */
Zaitsev 10:41552d038a69 463 #define _EBI_ROUTE_APEN_A18 0x00000012UL /**< Mode A18 for EBI_ROUTE */
Zaitsev 10:41552d038a69 464 #define _EBI_ROUTE_APEN_A19 0x00000013UL /**< Mode A19 for EBI_ROUTE */
Zaitsev 10:41552d038a69 465 #define _EBI_ROUTE_APEN_A20 0x00000014UL /**< Mode A20 for EBI_ROUTE */
Zaitsev 10:41552d038a69 466 #define _EBI_ROUTE_APEN_A21 0x00000015UL /**< Mode A21 for EBI_ROUTE */
Zaitsev 10:41552d038a69 467 #define _EBI_ROUTE_APEN_A22 0x00000016UL /**< Mode A22 for EBI_ROUTE */
Zaitsev 10:41552d038a69 468 #define _EBI_ROUTE_APEN_A23 0x00000017UL /**< Mode A23 for EBI_ROUTE */
Zaitsev 10:41552d038a69 469 #define _EBI_ROUTE_APEN_A24 0x00000018UL /**< Mode A24 for EBI_ROUTE */
Zaitsev 10:41552d038a69 470 #define _EBI_ROUTE_APEN_A25 0x00000019UL /**< Mode A25 for EBI_ROUTE */
Zaitsev 10:41552d038a69 471 #define _EBI_ROUTE_APEN_A26 0x0000001AUL /**< Mode A26 for EBI_ROUTE */
Zaitsev 10:41552d038a69 472 #define _EBI_ROUTE_APEN_A27 0x0000001BUL /**< Mode A27 for EBI_ROUTE */
Zaitsev 10:41552d038a69 473 #define _EBI_ROUTE_APEN_A28 0x0000001CUL /**< Mode A28 for EBI_ROUTE */
Zaitsev 10:41552d038a69 474 #define EBI_ROUTE_APEN_DEFAULT (_EBI_ROUTE_APEN_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 475 #define EBI_ROUTE_APEN_A0 (_EBI_ROUTE_APEN_A0 << 18) /**< Shifted mode A0 for EBI_ROUTE */
Zaitsev 10:41552d038a69 476 #define EBI_ROUTE_APEN_A5 (_EBI_ROUTE_APEN_A5 << 18) /**< Shifted mode A5 for EBI_ROUTE */
Zaitsev 10:41552d038a69 477 #define EBI_ROUTE_APEN_A6 (_EBI_ROUTE_APEN_A6 << 18) /**< Shifted mode A6 for EBI_ROUTE */
Zaitsev 10:41552d038a69 478 #define EBI_ROUTE_APEN_A7 (_EBI_ROUTE_APEN_A7 << 18) /**< Shifted mode A7 for EBI_ROUTE */
Zaitsev 10:41552d038a69 479 #define EBI_ROUTE_APEN_A8 (_EBI_ROUTE_APEN_A8 << 18) /**< Shifted mode A8 for EBI_ROUTE */
Zaitsev 10:41552d038a69 480 #define EBI_ROUTE_APEN_A9 (_EBI_ROUTE_APEN_A9 << 18) /**< Shifted mode A9 for EBI_ROUTE */
Zaitsev 10:41552d038a69 481 #define EBI_ROUTE_APEN_A10 (_EBI_ROUTE_APEN_A10 << 18) /**< Shifted mode A10 for EBI_ROUTE */
Zaitsev 10:41552d038a69 482 #define EBI_ROUTE_APEN_A11 (_EBI_ROUTE_APEN_A11 << 18) /**< Shifted mode A11 for EBI_ROUTE */
Zaitsev 10:41552d038a69 483 #define EBI_ROUTE_APEN_A12 (_EBI_ROUTE_APEN_A12 << 18) /**< Shifted mode A12 for EBI_ROUTE */
Zaitsev 10:41552d038a69 484 #define EBI_ROUTE_APEN_A13 (_EBI_ROUTE_APEN_A13 << 18) /**< Shifted mode A13 for EBI_ROUTE */
Zaitsev 10:41552d038a69 485 #define EBI_ROUTE_APEN_A14 (_EBI_ROUTE_APEN_A14 << 18) /**< Shifted mode A14 for EBI_ROUTE */
Zaitsev 10:41552d038a69 486 #define EBI_ROUTE_APEN_A15 (_EBI_ROUTE_APEN_A15 << 18) /**< Shifted mode A15 for EBI_ROUTE */
Zaitsev 10:41552d038a69 487 #define EBI_ROUTE_APEN_A16 (_EBI_ROUTE_APEN_A16 << 18) /**< Shifted mode A16 for EBI_ROUTE */
Zaitsev 10:41552d038a69 488 #define EBI_ROUTE_APEN_A17 (_EBI_ROUTE_APEN_A17 << 18) /**< Shifted mode A17 for EBI_ROUTE */
Zaitsev 10:41552d038a69 489 #define EBI_ROUTE_APEN_A18 (_EBI_ROUTE_APEN_A18 << 18) /**< Shifted mode A18 for EBI_ROUTE */
Zaitsev 10:41552d038a69 490 #define EBI_ROUTE_APEN_A19 (_EBI_ROUTE_APEN_A19 << 18) /**< Shifted mode A19 for EBI_ROUTE */
Zaitsev 10:41552d038a69 491 #define EBI_ROUTE_APEN_A20 (_EBI_ROUTE_APEN_A20 << 18) /**< Shifted mode A20 for EBI_ROUTE */
Zaitsev 10:41552d038a69 492 #define EBI_ROUTE_APEN_A21 (_EBI_ROUTE_APEN_A21 << 18) /**< Shifted mode A21 for EBI_ROUTE */
Zaitsev 10:41552d038a69 493 #define EBI_ROUTE_APEN_A22 (_EBI_ROUTE_APEN_A22 << 18) /**< Shifted mode A22 for EBI_ROUTE */
Zaitsev 10:41552d038a69 494 #define EBI_ROUTE_APEN_A23 (_EBI_ROUTE_APEN_A23 << 18) /**< Shifted mode A23 for EBI_ROUTE */
Zaitsev 10:41552d038a69 495 #define EBI_ROUTE_APEN_A24 (_EBI_ROUTE_APEN_A24 << 18) /**< Shifted mode A24 for EBI_ROUTE */
Zaitsev 10:41552d038a69 496 #define EBI_ROUTE_APEN_A25 (_EBI_ROUTE_APEN_A25 << 18) /**< Shifted mode A25 for EBI_ROUTE */
Zaitsev 10:41552d038a69 497 #define EBI_ROUTE_APEN_A26 (_EBI_ROUTE_APEN_A26 << 18) /**< Shifted mode A26 for EBI_ROUTE */
Zaitsev 10:41552d038a69 498 #define EBI_ROUTE_APEN_A27 (_EBI_ROUTE_APEN_A27 << 18) /**< Shifted mode A27 for EBI_ROUTE */
Zaitsev 10:41552d038a69 499 #define EBI_ROUTE_APEN_A28 (_EBI_ROUTE_APEN_A28 << 18) /**< Shifted mode A28 for EBI_ROUTE */
Zaitsev 10:41552d038a69 500 #define EBI_ROUTE_TFTPEN (0x1UL << 24) /**< EBI_TFT Pin Enable */
Zaitsev 10:41552d038a69 501 #define _EBI_ROUTE_TFTPEN_SHIFT 24 /**< Shift value for EBI_TFTPEN */
Zaitsev 10:41552d038a69 502 #define _EBI_ROUTE_TFTPEN_MASK 0x1000000UL /**< Bit mask for EBI_TFTPEN */
Zaitsev 10:41552d038a69 503 #define _EBI_ROUTE_TFTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 504 #define EBI_ROUTE_TFTPEN_DEFAULT (_EBI_ROUTE_TFTPEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 505 #define EBI_ROUTE_DATAENPEN (0x1UL << 25) /**< EBI_TFT Pin Enable */
Zaitsev 10:41552d038a69 506 #define _EBI_ROUTE_DATAENPEN_SHIFT 25 /**< Shift value for EBI_DATAENPEN */
Zaitsev 10:41552d038a69 507 #define _EBI_ROUTE_DATAENPEN_MASK 0x2000000UL /**< Bit mask for EBI_DATAENPEN */
Zaitsev 10:41552d038a69 508 #define _EBI_ROUTE_DATAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 509 #define EBI_ROUTE_DATAENPEN_DEFAULT (_EBI_ROUTE_DATAENPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 510 #define EBI_ROUTE_CSTFTPEN (0x1UL << 26) /**< EBI_CSTFT Pin Enable */
Zaitsev 10:41552d038a69 511 #define _EBI_ROUTE_CSTFTPEN_SHIFT 26 /**< Shift value for EBI_CSTFTPEN */
Zaitsev 10:41552d038a69 512 #define _EBI_ROUTE_CSTFTPEN_MASK 0x4000000UL /**< Bit mask for EBI_CSTFTPEN */
Zaitsev 10:41552d038a69 513 #define _EBI_ROUTE_CSTFTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 514 #define EBI_ROUTE_CSTFTPEN_DEFAULT (_EBI_ROUTE_CSTFTPEN_DEFAULT << 26) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 515 #define _EBI_ROUTE_LOCATION_SHIFT 28 /**< Shift value for EBI_LOCATION */
Zaitsev 10:41552d038a69 516 #define _EBI_ROUTE_LOCATION_MASK 0x70000000UL /**< Bit mask for EBI_LOCATION */
Zaitsev 10:41552d038a69 517 #define _EBI_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTE */
Zaitsev 10:41552d038a69 518 #define _EBI_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 519 #define _EBI_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTE */
Zaitsev 10:41552d038a69 520 #define _EBI_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTE */
Zaitsev 10:41552d038a69 521 #define EBI_ROUTE_LOCATION_LOC0 (_EBI_ROUTE_LOCATION_LOC0 << 28) /**< Shifted mode LOC0 for EBI_ROUTE */
Zaitsev 10:41552d038a69 522 #define EBI_ROUTE_LOCATION_DEFAULT (_EBI_ROUTE_LOCATION_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ROUTE */
Zaitsev 10:41552d038a69 523 #define EBI_ROUTE_LOCATION_LOC1 (_EBI_ROUTE_LOCATION_LOC1 << 28) /**< Shifted mode LOC1 for EBI_ROUTE */
Zaitsev 10:41552d038a69 524 #define EBI_ROUTE_LOCATION_LOC2 (_EBI_ROUTE_LOCATION_LOC2 << 28) /**< Shifted mode LOC2 for EBI_ROUTE */
Zaitsev 10:41552d038a69 525
Zaitsev 10:41552d038a69 526 /* Bit fields for EBI ADDRTIMING1 */
Zaitsev 10:41552d038a69 527 #define _EBI_ADDRTIMING1_RESETVALUE 0x00000303UL /**< Default value for EBI_ADDRTIMING1 */
Zaitsev 10:41552d038a69 528 #define _EBI_ADDRTIMING1_MASK 0x10000303UL /**< Mask for EBI_ADDRTIMING1 */
Zaitsev 10:41552d038a69 529 #define _EBI_ADDRTIMING1_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */
Zaitsev 10:41552d038a69 530 #define _EBI_ADDRTIMING1_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */
Zaitsev 10:41552d038a69 531 #define _EBI_ADDRTIMING1_ADDRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */
Zaitsev 10:41552d038a69 532 #define EBI_ADDRTIMING1_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING1_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */
Zaitsev 10:41552d038a69 533 #define _EBI_ADDRTIMING1_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */
Zaitsev 10:41552d038a69 534 #define _EBI_ADDRTIMING1_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */
Zaitsev 10:41552d038a69 535 #define _EBI_ADDRTIMING1_ADDRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */
Zaitsev 10:41552d038a69 536 #define EBI_ADDRTIMING1_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING1_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */
Zaitsev 10:41552d038a69 537 #define EBI_ADDRTIMING1_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */
Zaitsev 10:41552d038a69 538 #define _EBI_ADDRTIMING1_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */
Zaitsev 10:41552d038a69 539 #define _EBI_ADDRTIMING1_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */
Zaitsev 10:41552d038a69 540 #define _EBI_ADDRTIMING1_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */
Zaitsev 10:41552d038a69 541 #define EBI_ADDRTIMING1_HALFALE_DEFAULT (_EBI_ADDRTIMING1_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */
Zaitsev 10:41552d038a69 542
Zaitsev 10:41552d038a69 543 /* Bit fields for EBI RDTIMING1 */
Zaitsev 10:41552d038a69 544 #define _EBI_RDTIMING1_RESETVALUE 0x00033F03UL /**< Default value for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 545 #define _EBI_RDTIMING1_MASK 0x70033F03UL /**< Mask for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 546 #define _EBI_RDTIMING1_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */
Zaitsev 10:41552d038a69 547 #define _EBI_RDTIMING1_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */
Zaitsev 10:41552d038a69 548 #define _EBI_RDTIMING1_RDSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 549 #define EBI_RDTIMING1_RDSETUP_DEFAULT (_EBI_RDTIMING1_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 550 #define _EBI_RDTIMING1_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */
Zaitsev 10:41552d038a69 551 #define _EBI_RDTIMING1_RDSTRB_MASK 0x3F00UL /**< Bit mask for EBI_RDSTRB */
Zaitsev 10:41552d038a69 552 #define _EBI_RDTIMING1_RDSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 553 #define EBI_RDTIMING1_RDSTRB_DEFAULT (_EBI_RDTIMING1_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 554 #define _EBI_RDTIMING1_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */
Zaitsev 10:41552d038a69 555 #define _EBI_RDTIMING1_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */
Zaitsev 10:41552d038a69 556 #define _EBI_RDTIMING1_RDHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 557 #define EBI_RDTIMING1_RDHOLD_DEFAULT (_EBI_RDTIMING1_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 558 #define EBI_RDTIMING1_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */
Zaitsev 10:41552d038a69 559 #define _EBI_RDTIMING1_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */
Zaitsev 10:41552d038a69 560 #define _EBI_RDTIMING1_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */
Zaitsev 10:41552d038a69 561 #define _EBI_RDTIMING1_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 562 #define EBI_RDTIMING1_HALFRE_DEFAULT (_EBI_RDTIMING1_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 563 #define EBI_RDTIMING1_PREFETCH (0x1UL << 29) /**< Prefetch Enable */
Zaitsev 10:41552d038a69 564 #define _EBI_RDTIMING1_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */
Zaitsev 10:41552d038a69 565 #define _EBI_RDTIMING1_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */
Zaitsev 10:41552d038a69 566 #define _EBI_RDTIMING1_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 567 #define EBI_RDTIMING1_PREFETCH_DEFAULT (_EBI_RDTIMING1_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 568 #define EBI_RDTIMING1_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */
Zaitsev 10:41552d038a69 569 #define _EBI_RDTIMING1_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */
Zaitsev 10:41552d038a69 570 #define _EBI_RDTIMING1_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */
Zaitsev 10:41552d038a69 571 #define _EBI_RDTIMING1_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 572 #define EBI_RDTIMING1_PAGEMODE_DEFAULT (_EBI_RDTIMING1_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
Zaitsev 10:41552d038a69 573
Zaitsev 10:41552d038a69 574 /* Bit fields for EBI WRTIMING1 */
Zaitsev 10:41552d038a69 575 #define _EBI_WRTIMING1_RESETVALUE 0x00033F03UL /**< Default value for EBI_WRTIMING1 */
Zaitsev 10:41552d038a69 576 #define _EBI_WRTIMING1_MASK 0x30033F03UL /**< Mask for EBI_WRTIMING1 */
Zaitsev 10:41552d038a69 577 #define _EBI_WRTIMING1_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */
Zaitsev 10:41552d038a69 578 #define _EBI_WRTIMING1_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */
Zaitsev 10:41552d038a69 579 #define _EBI_WRTIMING1_WRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING1 */
Zaitsev 10:41552d038a69 580 #define EBI_WRTIMING1_WRSETUP_DEFAULT (_EBI_WRTIMING1_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
Zaitsev 10:41552d038a69 581 #define _EBI_WRTIMING1_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */
Zaitsev 10:41552d038a69 582 #define _EBI_WRTIMING1_WRSTRB_MASK 0x3F00UL /**< Bit mask for EBI_WRSTRB */
Zaitsev 10:41552d038a69 583 #define _EBI_WRTIMING1_WRSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_WRTIMING1 */
Zaitsev 10:41552d038a69 584 #define EBI_WRTIMING1_WRSTRB_DEFAULT (_EBI_WRTIMING1_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
Zaitsev 10:41552d038a69 585 #define _EBI_WRTIMING1_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */
Zaitsev 10:41552d038a69 586 #define _EBI_WRTIMING1_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */
Zaitsev 10:41552d038a69 587 #define _EBI_WRTIMING1_WRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING1 */
Zaitsev 10:41552d038a69 588 #define EBI_WRTIMING1_WRHOLD_DEFAULT (_EBI_WRTIMING1_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
Zaitsev 10:41552d038a69 589 #define EBI_WRTIMING1_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */
Zaitsev 10:41552d038a69 590 #define _EBI_WRTIMING1_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */
Zaitsev 10:41552d038a69 591 #define _EBI_WRTIMING1_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */
Zaitsev 10:41552d038a69 592 #define _EBI_WRTIMING1_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING1 */
Zaitsev 10:41552d038a69 593 #define EBI_WRTIMING1_HALFWE_DEFAULT (_EBI_WRTIMING1_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
Zaitsev 10:41552d038a69 594 #define EBI_WRTIMING1_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */
Zaitsev 10:41552d038a69 595 #define _EBI_WRTIMING1_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */
Zaitsev 10:41552d038a69 596 #define _EBI_WRTIMING1_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */
Zaitsev 10:41552d038a69 597 #define _EBI_WRTIMING1_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING1 */
Zaitsev 10:41552d038a69 598 #define EBI_WRTIMING1_WBUFDIS_DEFAULT (_EBI_WRTIMING1_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
Zaitsev 10:41552d038a69 599
Zaitsev 10:41552d038a69 600 /* Bit fields for EBI POLARITY1 */
Zaitsev 10:41552d038a69 601 #define _EBI_POLARITY1_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 602 #define _EBI_POLARITY1_MASK 0x0000003FUL /**< Mask for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 603 #define EBI_POLARITY1_CSPOL (0x1UL << 0) /**< Chip Select Polarity */
Zaitsev 10:41552d038a69 604 #define _EBI_POLARITY1_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */
Zaitsev 10:41552d038a69 605 #define _EBI_POLARITY1_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */
Zaitsev 10:41552d038a69 606 #define _EBI_POLARITY1_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 607 #define _EBI_POLARITY1_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 608 #define _EBI_POLARITY1_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 609 #define EBI_POLARITY1_CSPOL_DEFAULT (_EBI_POLARITY1_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 610 #define EBI_POLARITY1_CSPOL_ACTIVELOW (_EBI_POLARITY1_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 611 #define EBI_POLARITY1_CSPOL_ACTIVEHIGH (_EBI_POLARITY1_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 612 #define EBI_POLARITY1_REPOL (0x1UL << 1) /**< Read Enable Polarity */
Zaitsev 10:41552d038a69 613 #define _EBI_POLARITY1_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */
Zaitsev 10:41552d038a69 614 #define _EBI_POLARITY1_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */
Zaitsev 10:41552d038a69 615 #define _EBI_POLARITY1_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 616 #define _EBI_POLARITY1_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 617 #define _EBI_POLARITY1_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 618 #define EBI_POLARITY1_REPOL_DEFAULT (_EBI_POLARITY1_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 619 #define EBI_POLARITY1_REPOL_ACTIVELOW (_EBI_POLARITY1_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 620 #define EBI_POLARITY1_REPOL_ACTIVEHIGH (_EBI_POLARITY1_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 621 #define EBI_POLARITY1_WEPOL (0x1UL << 2) /**< Write Enable Polarity */
Zaitsev 10:41552d038a69 622 #define _EBI_POLARITY1_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */
Zaitsev 10:41552d038a69 623 #define _EBI_POLARITY1_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */
Zaitsev 10:41552d038a69 624 #define _EBI_POLARITY1_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 625 #define _EBI_POLARITY1_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 626 #define _EBI_POLARITY1_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 627 #define EBI_POLARITY1_WEPOL_DEFAULT (_EBI_POLARITY1_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 628 #define EBI_POLARITY1_WEPOL_ACTIVELOW (_EBI_POLARITY1_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 629 #define EBI_POLARITY1_WEPOL_ACTIVEHIGH (_EBI_POLARITY1_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 630 #define EBI_POLARITY1_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */
Zaitsev 10:41552d038a69 631 #define _EBI_POLARITY1_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */
Zaitsev 10:41552d038a69 632 #define _EBI_POLARITY1_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */
Zaitsev 10:41552d038a69 633 #define _EBI_POLARITY1_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 634 #define _EBI_POLARITY1_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 635 #define _EBI_POLARITY1_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 636 #define EBI_POLARITY1_ALEPOL_DEFAULT (_EBI_POLARITY1_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 637 #define EBI_POLARITY1_ALEPOL_ACTIVELOW (_EBI_POLARITY1_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 638 #define EBI_POLARITY1_ALEPOL_ACTIVEHIGH (_EBI_POLARITY1_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 639 #define EBI_POLARITY1_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */
Zaitsev 10:41552d038a69 640 #define _EBI_POLARITY1_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */
Zaitsev 10:41552d038a69 641 #define _EBI_POLARITY1_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */
Zaitsev 10:41552d038a69 642 #define _EBI_POLARITY1_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 643 #define _EBI_POLARITY1_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 644 #define _EBI_POLARITY1_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 645 #define EBI_POLARITY1_ARDYPOL_DEFAULT (_EBI_POLARITY1_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 646 #define EBI_POLARITY1_ARDYPOL_ACTIVELOW (_EBI_POLARITY1_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 647 #define EBI_POLARITY1_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY1_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 648 #define EBI_POLARITY1_BLPOL (0x1UL << 5) /**< BL Polarity */
Zaitsev 10:41552d038a69 649 #define _EBI_POLARITY1_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */
Zaitsev 10:41552d038a69 650 #define _EBI_POLARITY1_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */
Zaitsev 10:41552d038a69 651 #define _EBI_POLARITY1_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 652 #define _EBI_POLARITY1_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 653 #define _EBI_POLARITY1_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 654 #define EBI_POLARITY1_BLPOL_DEFAULT (_EBI_POLARITY1_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 655 #define EBI_POLARITY1_BLPOL_ACTIVELOW (_EBI_POLARITY1_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 656 #define EBI_POLARITY1_BLPOL_ACTIVEHIGH (_EBI_POLARITY1_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
Zaitsev 10:41552d038a69 657
Zaitsev 10:41552d038a69 658 /* Bit fields for EBI ADDRTIMING2 */
Zaitsev 10:41552d038a69 659 #define _EBI_ADDRTIMING2_RESETVALUE 0x00000303UL /**< Default value for EBI_ADDRTIMING2 */
Zaitsev 10:41552d038a69 660 #define _EBI_ADDRTIMING2_MASK 0x10000303UL /**< Mask for EBI_ADDRTIMING2 */
Zaitsev 10:41552d038a69 661 #define _EBI_ADDRTIMING2_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */
Zaitsev 10:41552d038a69 662 #define _EBI_ADDRTIMING2_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */
Zaitsev 10:41552d038a69 663 #define _EBI_ADDRTIMING2_ADDRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */
Zaitsev 10:41552d038a69 664 #define EBI_ADDRTIMING2_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING2_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */
Zaitsev 10:41552d038a69 665 #define _EBI_ADDRTIMING2_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */
Zaitsev 10:41552d038a69 666 #define _EBI_ADDRTIMING2_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */
Zaitsev 10:41552d038a69 667 #define _EBI_ADDRTIMING2_ADDRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */
Zaitsev 10:41552d038a69 668 #define EBI_ADDRTIMING2_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING2_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */
Zaitsev 10:41552d038a69 669 #define EBI_ADDRTIMING2_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */
Zaitsev 10:41552d038a69 670 #define _EBI_ADDRTIMING2_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */
Zaitsev 10:41552d038a69 671 #define _EBI_ADDRTIMING2_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */
Zaitsev 10:41552d038a69 672 #define _EBI_ADDRTIMING2_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */
Zaitsev 10:41552d038a69 673 #define EBI_ADDRTIMING2_HALFALE_DEFAULT (_EBI_ADDRTIMING2_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */
Zaitsev 10:41552d038a69 674
Zaitsev 10:41552d038a69 675 /* Bit fields for EBI RDTIMING2 */
Zaitsev 10:41552d038a69 676 #define _EBI_RDTIMING2_RESETVALUE 0x00033F03UL /**< Default value for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 677 #define _EBI_RDTIMING2_MASK 0x70033F03UL /**< Mask for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 678 #define _EBI_RDTIMING2_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */
Zaitsev 10:41552d038a69 679 #define _EBI_RDTIMING2_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */
Zaitsev 10:41552d038a69 680 #define _EBI_RDTIMING2_RDSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 681 #define EBI_RDTIMING2_RDSETUP_DEFAULT (_EBI_RDTIMING2_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 682 #define _EBI_RDTIMING2_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */
Zaitsev 10:41552d038a69 683 #define _EBI_RDTIMING2_RDSTRB_MASK 0x3F00UL /**< Bit mask for EBI_RDSTRB */
Zaitsev 10:41552d038a69 684 #define _EBI_RDTIMING2_RDSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 685 #define EBI_RDTIMING2_RDSTRB_DEFAULT (_EBI_RDTIMING2_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 686 #define _EBI_RDTIMING2_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */
Zaitsev 10:41552d038a69 687 #define _EBI_RDTIMING2_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */
Zaitsev 10:41552d038a69 688 #define _EBI_RDTIMING2_RDHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 689 #define EBI_RDTIMING2_RDHOLD_DEFAULT (_EBI_RDTIMING2_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 690 #define EBI_RDTIMING2_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */
Zaitsev 10:41552d038a69 691 #define _EBI_RDTIMING2_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */
Zaitsev 10:41552d038a69 692 #define _EBI_RDTIMING2_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */
Zaitsev 10:41552d038a69 693 #define _EBI_RDTIMING2_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 694 #define EBI_RDTIMING2_HALFRE_DEFAULT (_EBI_RDTIMING2_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 695 #define EBI_RDTIMING2_PREFETCH (0x1UL << 29) /**< Prefetch Enable */
Zaitsev 10:41552d038a69 696 #define _EBI_RDTIMING2_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */
Zaitsev 10:41552d038a69 697 #define _EBI_RDTIMING2_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */
Zaitsev 10:41552d038a69 698 #define _EBI_RDTIMING2_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 699 #define EBI_RDTIMING2_PREFETCH_DEFAULT (_EBI_RDTIMING2_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 700 #define EBI_RDTIMING2_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */
Zaitsev 10:41552d038a69 701 #define _EBI_RDTIMING2_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */
Zaitsev 10:41552d038a69 702 #define _EBI_RDTIMING2_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */
Zaitsev 10:41552d038a69 703 #define _EBI_RDTIMING2_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 704 #define EBI_RDTIMING2_PAGEMODE_DEFAULT (_EBI_RDTIMING2_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
Zaitsev 10:41552d038a69 705
Zaitsev 10:41552d038a69 706 /* Bit fields for EBI WRTIMING2 */
Zaitsev 10:41552d038a69 707 #define _EBI_WRTIMING2_RESETVALUE 0x00033F03UL /**< Default value for EBI_WRTIMING2 */
Zaitsev 10:41552d038a69 708 #define _EBI_WRTIMING2_MASK 0x30033F03UL /**< Mask for EBI_WRTIMING2 */
Zaitsev 10:41552d038a69 709 #define _EBI_WRTIMING2_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */
Zaitsev 10:41552d038a69 710 #define _EBI_WRTIMING2_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */
Zaitsev 10:41552d038a69 711 #define _EBI_WRTIMING2_WRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING2 */
Zaitsev 10:41552d038a69 712 #define EBI_WRTIMING2_WRSETUP_DEFAULT (_EBI_WRTIMING2_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
Zaitsev 10:41552d038a69 713 #define _EBI_WRTIMING2_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */
Zaitsev 10:41552d038a69 714 #define _EBI_WRTIMING2_WRSTRB_MASK 0x3F00UL /**< Bit mask for EBI_WRSTRB */
Zaitsev 10:41552d038a69 715 #define _EBI_WRTIMING2_WRSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_WRTIMING2 */
Zaitsev 10:41552d038a69 716 #define EBI_WRTIMING2_WRSTRB_DEFAULT (_EBI_WRTIMING2_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
Zaitsev 10:41552d038a69 717 #define _EBI_WRTIMING2_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */
Zaitsev 10:41552d038a69 718 #define _EBI_WRTIMING2_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */
Zaitsev 10:41552d038a69 719 #define _EBI_WRTIMING2_WRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING2 */
Zaitsev 10:41552d038a69 720 #define EBI_WRTIMING2_WRHOLD_DEFAULT (_EBI_WRTIMING2_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
Zaitsev 10:41552d038a69 721 #define EBI_WRTIMING2_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */
Zaitsev 10:41552d038a69 722 #define _EBI_WRTIMING2_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */
Zaitsev 10:41552d038a69 723 #define _EBI_WRTIMING2_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */
Zaitsev 10:41552d038a69 724 #define _EBI_WRTIMING2_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING2 */
Zaitsev 10:41552d038a69 725 #define EBI_WRTIMING2_HALFWE_DEFAULT (_EBI_WRTIMING2_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
Zaitsev 10:41552d038a69 726 #define EBI_WRTIMING2_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */
Zaitsev 10:41552d038a69 727 #define _EBI_WRTIMING2_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */
Zaitsev 10:41552d038a69 728 #define _EBI_WRTIMING2_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */
Zaitsev 10:41552d038a69 729 #define _EBI_WRTIMING2_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING2 */
Zaitsev 10:41552d038a69 730 #define EBI_WRTIMING2_WBUFDIS_DEFAULT (_EBI_WRTIMING2_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
Zaitsev 10:41552d038a69 731
Zaitsev 10:41552d038a69 732 /* Bit fields for EBI POLARITY2 */
Zaitsev 10:41552d038a69 733 #define _EBI_POLARITY2_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 734 #define _EBI_POLARITY2_MASK 0x0000003FUL /**< Mask for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 735 #define EBI_POLARITY2_CSPOL (0x1UL << 0) /**< Chip Select Polarity */
Zaitsev 10:41552d038a69 736 #define _EBI_POLARITY2_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */
Zaitsev 10:41552d038a69 737 #define _EBI_POLARITY2_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */
Zaitsev 10:41552d038a69 738 #define _EBI_POLARITY2_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 739 #define _EBI_POLARITY2_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 740 #define _EBI_POLARITY2_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 741 #define EBI_POLARITY2_CSPOL_DEFAULT (_EBI_POLARITY2_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 742 #define EBI_POLARITY2_CSPOL_ACTIVELOW (_EBI_POLARITY2_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 743 #define EBI_POLARITY2_CSPOL_ACTIVEHIGH (_EBI_POLARITY2_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 744 #define EBI_POLARITY2_REPOL (0x1UL << 1) /**< Read Enable Polarity */
Zaitsev 10:41552d038a69 745 #define _EBI_POLARITY2_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */
Zaitsev 10:41552d038a69 746 #define _EBI_POLARITY2_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */
Zaitsev 10:41552d038a69 747 #define _EBI_POLARITY2_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 748 #define _EBI_POLARITY2_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 749 #define _EBI_POLARITY2_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 750 #define EBI_POLARITY2_REPOL_DEFAULT (_EBI_POLARITY2_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 751 #define EBI_POLARITY2_REPOL_ACTIVELOW (_EBI_POLARITY2_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 752 #define EBI_POLARITY2_REPOL_ACTIVEHIGH (_EBI_POLARITY2_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 753 #define EBI_POLARITY2_WEPOL (0x1UL << 2) /**< Write Enable Polarity */
Zaitsev 10:41552d038a69 754 #define _EBI_POLARITY2_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */
Zaitsev 10:41552d038a69 755 #define _EBI_POLARITY2_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */
Zaitsev 10:41552d038a69 756 #define _EBI_POLARITY2_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 757 #define _EBI_POLARITY2_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 758 #define _EBI_POLARITY2_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 759 #define EBI_POLARITY2_WEPOL_DEFAULT (_EBI_POLARITY2_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 760 #define EBI_POLARITY2_WEPOL_ACTIVELOW (_EBI_POLARITY2_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 761 #define EBI_POLARITY2_WEPOL_ACTIVEHIGH (_EBI_POLARITY2_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 762 #define EBI_POLARITY2_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */
Zaitsev 10:41552d038a69 763 #define _EBI_POLARITY2_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */
Zaitsev 10:41552d038a69 764 #define _EBI_POLARITY2_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */
Zaitsev 10:41552d038a69 765 #define _EBI_POLARITY2_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 766 #define _EBI_POLARITY2_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 767 #define _EBI_POLARITY2_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 768 #define EBI_POLARITY2_ALEPOL_DEFAULT (_EBI_POLARITY2_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 769 #define EBI_POLARITY2_ALEPOL_ACTIVELOW (_EBI_POLARITY2_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 770 #define EBI_POLARITY2_ALEPOL_ACTIVEHIGH (_EBI_POLARITY2_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 771 #define EBI_POLARITY2_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */
Zaitsev 10:41552d038a69 772 #define _EBI_POLARITY2_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */
Zaitsev 10:41552d038a69 773 #define _EBI_POLARITY2_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */
Zaitsev 10:41552d038a69 774 #define _EBI_POLARITY2_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 775 #define _EBI_POLARITY2_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 776 #define _EBI_POLARITY2_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 777 #define EBI_POLARITY2_ARDYPOL_DEFAULT (_EBI_POLARITY2_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 778 #define EBI_POLARITY2_ARDYPOL_ACTIVELOW (_EBI_POLARITY2_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 779 #define EBI_POLARITY2_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY2_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 780 #define EBI_POLARITY2_BLPOL (0x1UL << 5) /**< BL Polarity */
Zaitsev 10:41552d038a69 781 #define _EBI_POLARITY2_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */
Zaitsev 10:41552d038a69 782 #define _EBI_POLARITY2_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */
Zaitsev 10:41552d038a69 783 #define _EBI_POLARITY2_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 784 #define _EBI_POLARITY2_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 785 #define _EBI_POLARITY2_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 786 #define EBI_POLARITY2_BLPOL_DEFAULT (_EBI_POLARITY2_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 787 #define EBI_POLARITY2_BLPOL_ACTIVELOW (_EBI_POLARITY2_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 788 #define EBI_POLARITY2_BLPOL_ACTIVEHIGH (_EBI_POLARITY2_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
Zaitsev 10:41552d038a69 789
Zaitsev 10:41552d038a69 790 /* Bit fields for EBI ADDRTIMING3 */
Zaitsev 10:41552d038a69 791 #define _EBI_ADDRTIMING3_RESETVALUE 0x00000303UL /**< Default value for EBI_ADDRTIMING3 */
Zaitsev 10:41552d038a69 792 #define _EBI_ADDRTIMING3_MASK 0x10000303UL /**< Mask for EBI_ADDRTIMING3 */
Zaitsev 10:41552d038a69 793 #define _EBI_ADDRTIMING3_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */
Zaitsev 10:41552d038a69 794 #define _EBI_ADDRTIMING3_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */
Zaitsev 10:41552d038a69 795 #define _EBI_ADDRTIMING3_ADDRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */
Zaitsev 10:41552d038a69 796 #define EBI_ADDRTIMING3_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING3_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */
Zaitsev 10:41552d038a69 797 #define _EBI_ADDRTIMING3_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */
Zaitsev 10:41552d038a69 798 #define _EBI_ADDRTIMING3_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */
Zaitsev 10:41552d038a69 799 #define _EBI_ADDRTIMING3_ADDRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */
Zaitsev 10:41552d038a69 800 #define EBI_ADDRTIMING3_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING3_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */
Zaitsev 10:41552d038a69 801 #define EBI_ADDRTIMING3_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */
Zaitsev 10:41552d038a69 802 #define _EBI_ADDRTIMING3_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */
Zaitsev 10:41552d038a69 803 #define _EBI_ADDRTIMING3_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */
Zaitsev 10:41552d038a69 804 #define _EBI_ADDRTIMING3_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */
Zaitsev 10:41552d038a69 805 #define EBI_ADDRTIMING3_HALFALE_DEFAULT (_EBI_ADDRTIMING3_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */
Zaitsev 10:41552d038a69 806
Zaitsev 10:41552d038a69 807 /* Bit fields for EBI RDTIMING3 */
Zaitsev 10:41552d038a69 808 #define _EBI_RDTIMING3_RESETVALUE 0x00033F03UL /**< Default value for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 809 #define _EBI_RDTIMING3_MASK 0x70033F03UL /**< Mask for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 810 #define _EBI_RDTIMING3_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */
Zaitsev 10:41552d038a69 811 #define _EBI_RDTIMING3_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */
Zaitsev 10:41552d038a69 812 #define _EBI_RDTIMING3_RDSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 813 #define EBI_RDTIMING3_RDSETUP_DEFAULT (_EBI_RDTIMING3_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 814 #define _EBI_RDTIMING3_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */
Zaitsev 10:41552d038a69 815 #define _EBI_RDTIMING3_RDSTRB_MASK 0x3F00UL /**< Bit mask for EBI_RDSTRB */
Zaitsev 10:41552d038a69 816 #define _EBI_RDTIMING3_RDSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 817 #define EBI_RDTIMING3_RDSTRB_DEFAULT (_EBI_RDTIMING3_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 818 #define _EBI_RDTIMING3_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */
Zaitsev 10:41552d038a69 819 #define _EBI_RDTIMING3_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */
Zaitsev 10:41552d038a69 820 #define _EBI_RDTIMING3_RDHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 821 #define EBI_RDTIMING3_RDHOLD_DEFAULT (_EBI_RDTIMING3_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 822 #define EBI_RDTIMING3_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */
Zaitsev 10:41552d038a69 823 #define _EBI_RDTIMING3_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */
Zaitsev 10:41552d038a69 824 #define _EBI_RDTIMING3_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */
Zaitsev 10:41552d038a69 825 #define _EBI_RDTIMING3_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 826 #define EBI_RDTIMING3_HALFRE_DEFAULT (_EBI_RDTIMING3_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 827 #define EBI_RDTIMING3_PREFETCH (0x1UL << 29) /**< Prefetch Enable */
Zaitsev 10:41552d038a69 828 #define _EBI_RDTIMING3_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */
Zaitsev 10:41552d038a69 829 #define _EBI_RDTIMING3_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */
Zaitsev 10:41552d038a69 830 #define _EBI_RDTIMING3_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 831 #define EBI_RDTIMING3_PREFETCH_DEFAULT (_EBI_RDTIMING3_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 832 #define EBI_RDTIMING3_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */
Zaitsev 10:41552d038a69 833 #define _EBI_RDTIMING3_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */
Zaitsev 10:41552d038a69 834 #define _EBI_RDTIMING3_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */
Zaitsev 10:41552d038a69 835 #define _EBI_RDTIMING3_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 836 #define EBI_RDTIMING3_PAGEMODE_DEFAULT (_EBI_RDTIMING3_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
Zaitsev 10:41552d038a69 837
Zaitsev 10:41552d038a69 838 /* Bit fields for EBI WRTIMING3 */
Zaitsev 10:41552d038a69 839 #define _EBI_WRTIMING3_RESETVALUE 0x00033F03UL /**< Default value for EBI_WRTIMING3 */
Zaitsev 10:41552d038a69 840 #define _EBI_WRTIMING3_MASK 0x30033F03UL /**< Mask for EBI_WRTIMING3 */
Zaitsev 10:41552d038a69 841 #define _EBI_WRTIMING3_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */
Zaitsev 10:41552d038a69 842 #define _EBI_WRTIMING3_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */
Zaitsev 10:41552d038a69 843 #define _EBI_WRTIMING3_WRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING3 */
Zaitsev 10:41552d038a69 844 #define EBI_WRTIMING3_WRSETUP_DEFAULT (_EBI_WRTIMING3_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
Zaitsev 10:41552d038a69 845 #define _EBI_WRTIMING3_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */
Zaitsev 10:41552d038a69 846 #define _EBI_WRTIMING3_WRSTRB_MASK 0x3F00UL /**< Bit mask for EBI_WRSTRB */
Zaitsev 10:41552d038a69 847 #define _EBI_WRTIMING3_WRSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_WRTIMING3 */
Zaitsev 10:41552d038a69 848 #define EBI_WRTIMING3_WRSTRB_DEFAULT (_EBI_WRTIMING3_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
Zaitsev 10:41552d038a69 849 #define _EBI_WRTIMING3_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */
Zaitsev 10:41552d038a69 850 #define _EBI_WRTIMING3_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */
Zaitsev 10:41552d038a69 851 #define _EBI_WRTIMING3_WRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING3 */
Zaitsev 10:41552d038a69 852 #define EBI_WRTIMING3_WRHOLD_DEFAULT (_EBI_WRTIMING3_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
Zaitsev 10:41552d038a69 853 #define EBI_WRTIMING3_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */
Zaitsev 10:41552d038a69 854 #define _EBI_WRTIMING3_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */
Zaitsev 10:41552d038a69 855 #define _EBI_WRTIMING3_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */
Zaitsev 10:41552d038a69 856 #define _EBI_WRTIMING3_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING3 */
Zaitsev 10:41552d038a69 857 #define EBI_WRTIMING3_HALFWE_DEFAULT (_EBI_WRTIMING3_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
Zaitsev 10:41552d038a69 858 #define EBI_WRTIMING3_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */
Zaitsev 10:41552d038a69 859 #define _EBI_WRTIMING3_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */
Zaitsev 10:41552d038a69 860 #define _EBI_WRTIMING3_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */
Zaitsev 10:41552d038a69 861 #define _EBI_WRTIMING3_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING3 */
Zaitsev 10:41552d038a69 862 #define EBI_WRTIMING3_WBUFDIS_DEFAULT (_EBI_WRTIMING3_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
Zaitsev 10:41552d038a69 863
Zaitsev 10:41552d038a69 864 /* Bit fields for EBI POLARITY3 */
Zaitsev 10:41552d038a69 865 #define _EBI_POLARITY3_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 866 #define _EBI_POLARITY3_MASK 0x0000003FUL /**< Mask for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 867 #define EBI_POLARITY3_CSPOL (0x1UL << 0) /**< Chip Select Polarity */
Zaitsev 10:41552d038a69 868 #define _EBI_POLARITY3_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */
Zaitsev 10:41552d038a69 869 #define _EBI_POLARITY3_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */
Zaitsev 10:41552d038a69 870 #define _EBI_POLARITY3_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 871 #define _EBI_POLARITY3_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 872 #define _EBI_POLARITY3_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 873 #define EBI_POLARITY3_CSPOL_DEFAULT (_EBI_POLARITY3_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 874 #define EBI_POLARITY3_CSPOL_ACTIVELOW (_EBI_POLARITY3_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 875 #define EBI_POLARITY3_CSPOL_ACTIVEHIGH (_EBI_POLARITY3_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 876 #define EBI_POLARITY3_REPOL (0x1UL << 1) /**< Read Enable Polarity */
Zaitsev 10:41552d038a69 877 #define _EBI_POLARITY3_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */
Zaitsev 10:41552d038a69 878 #define _EBI_POLARITY3_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */
Zaitsev 10:41552d038a69 879 #define _EBI_POLARITY3_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 880 #define _EBI_POLARITY3_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 881 #define _EBI_POLARITY3_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 882 #define EBI_POLARITY3_REPOL_DEFAULT (_EBI_POLARITY3_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 883 #define EBI_POLARITY3_REPOL_ACTIVELOW (_EBI_POLARITY3_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 884 #define EBI_POLARITY3_REPOL_ACTIVEHIGH (_EBI_POLARITY3_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 885 #define EBI_POLARITY3_WEPOL (0x1UL << 2) /**< Write Enable Polarity */
Zaitsev 10:41552d038a69 886 #define _EBI_POLARITY3_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */
Zaitsev 10:41552d038a69 887 #define _EBI_POLARITY3_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */
Zaitsev 10:41552d038a69 888 #define _EBI_POLARITY3_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 889 #define _EBI_POLARITY3_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 890 #define _EBI_POLARITY3_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 891 #define EBI_POLARITY3_WEPOL_DEFAULT (_EBI_POLARITY3_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 892 #define EBI_POLARITY3_WEPOL_ACTIVELOW (_EBI_POLARITY3_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 893 #define EBI_POLARITY3_WEPOL_ACTIVEHIGH (_EBI_POLARITY3_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 894 #define EBI_POLARITY3_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */
Zaitsev 10:41552d038a69 895 #define _EBI_POLARITY3_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */
Zaitsev 10:41552d038a69 896 #define _EBI_POLARITY3_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */
Zaitsev 10:41552d038a69 897 #define _EBI_POLARITY3_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 898 #define _EBI_POLARITY3_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 899 #define _EBI_POLARITY3_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 900 #define EBI_POLARITY3_ALEPOL_DEFAULT (_EBI_POLARITY3_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 901 #define EBI_POLARITY3_ALEPOL_ACTIVELOW (_EBI_POLARITY3_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 902 #define EBI_POLARITY3_ALEPOL_ACTIVEHIGH (_EBI_POLARITY3_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 903 #define EBI_POLARITY3_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */
Zaitsev 10:41552d038a69 904 #define _EBI_POLARITY3_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */
Zaitsev 10:41552d038a69 905 #define _EBI_POLARITY3_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */
Zaitsev 10:41552d038a69 906 #define _EBI_POLARITY3_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 907 #define _EBI_POLARITY3_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 908 #define _EBI_POLARITY3_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 909 #define EBI_POLARITY3_ARDYPOL_DEFAULT (_EBI_POLARITY3_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 910 #define EBI_POLARITY3_ARDYPOL_ACTIVELOW (_EBI_POLARITY3_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 911 #define EBI_POLARITY3_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY3_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 912 #define EBI_POLARITY3_BLPOL (0x1UL << 5) /**< BL Polarity */
Zaitsev 10:41552d038a69 913 #define _EBI_POLARITY3_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */
Zaitsev 10:41552d038a69 914 #define _EBI_POLARITY3_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */
Zaitsev 10:41552d038a69 915 #define _EBI_POLARITY3_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 916 #define _EBI_POLARITY3_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 917 #define _EBI_POLARITY3_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 918 #define EBI_POLARITY3_BLPOL_DEFAULT (_EBI_POLARITY3_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 919 #define EBI_POLARITY3_BLPOL_ACTIVELOW (_EBI_POLARITY3_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 920 #define EBI_POLARITY3_BLPOL_ACTIVEHIGH (_EBI_POLARITY3_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
Zaitsev 10:41552d038a69 921
Zaitsev 10:41552d038a69 922 /* Bit fields for EBI PAGECTRL */
Zaitsev 10:41552d038a69 923 #define _EBI_PAGECTRL_RESETVALUE 0x00000700UL /**< Default value for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 924 #define _EBI_PAGECTRL_MASK 0x07F00713UL /**< Mask for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 925 #define _EBI_PAGECTRL_PAGELEN_SHIFT 0 /**< Shift value for EBI_PAGELEN */
Zaitsev 10:41552d038a69 926 #define _EBI_PAGECTRL_PAGELEN_MASK 0x3UL /**< Bit mask for EBI_PAGELEN */
Zaitsev 10:41552d038a69 927 #define _EBI_PAGECTRL_PAGELEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 928 #define _EBI_PAGECTRL_PAGELEN_MEMBER4 0x00000000UL /**< Mode MEMBER4 for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 929 #define _EBI_PAGECTRL_PAGELEN_MEMBER8 0x00000001UL /**< Mode MEMBER8 for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 930 #define _EBI_PAGECTRL_PAGELEN_MEMBER16 0x00000002UL /**< Mode MEMBER16 for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 931 #define _EBI_PAGECTRL_PAGELEN_MEMBER32 0x00000003UL /**< Mode MEMBER32 for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 932 #define EBI_PAGECTRL_PAGELEN_DEFAULT (_EBI_PAGECTRL_PAGELEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 933 #define EBI_PAGECTRL_PAGELEN_MEMBER4 (_EBI_PAGECTRL_PAGELEN_MEMBER4 << 0) /**< Shifted mode MEMBER4 for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 934 #define EBI_PAGECTRL_PAGELEN_MEMBER8 (_EBI_PAGECTRL_PAGELEN_MEMBER8 << 0) /**< Shifted mode MEMBER8 for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 935 #define EBI_PAGECTRL_PAGELEN_MEMBER16 (_EBI_PAGECTRL_PAGELEN_MEMBER16 << 0) /**< Shifted mode MEMBER16 for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 936 #define EBI_PAGECTRL_PAGELEN_MEMBER32 (_EBI_PAGECTRL_PAGELEN_MEMBER32 << 0) /**< Shifted mode MEMBER32 for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 937 #define EBI_PAGECTRL_INCHIT (0x1UL << 4) /**< Intrapage hit only on incremental addresses */
Zaitsev 10:41552d038a69 938 #define _EBI_PAGECTRL_INCHIT_SHIFT 4 /**< Shift value for EBI_INCHIT */
Zaitsev 10:41552d038a69 939 #define _EBI_PAGECTRL_INCHIT_MASK 0x10UL /**< Bit mask for EBI_INCHIT */
Zaitsev 10:41552d038a69 940 #define _EBI_PAGECTRL_INCHIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 941 #define EBI_PAGECTRL_INCHIT_DEFAULT (_EBI_PAGECTRL_INCHIT_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 942 #define _EBI_PAGECTRL_RDPA_SHIFT 8 /**< Shift value for EBI_RDPA */
Zaitsev 10:41552d038a69 943 #define _EBI_PAGECTRL_RDPA_MASK 0x700UL /**< Bit mask for EBI_RDPA */
Zaitsev 10:41552d038a69 944 #define _EBI_PAGECTRL_RDPA_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 945 #define EBI_PAGECTRL_RDPA_DEFAULT (_EBI_PAGECTRL_RDPA_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 946 #define _EBI_PAGECTRL_KEEPOPEN_SHIFT 20 /**< Shift value for EBI_KEEPOPEN */
Zaitsev 10:41552d038a69 947 #define _EBI_PAGECTRL_KEEPOPEN_MASK 0x7F00000UL /**< Bit mask for EBI_KEEPOPEN */
Zaitsev 10:41552d038a69 948 #define _EBI_PAGECTRL_KEEPOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 949 #define EBI_PAGECTRL_KEEPOPEN_DEFAULT (_EBI_PAGECTRL_KEEPOPEN_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_PAGECTRL */
Zaitsev 10:41552d038a69 950
Zaitsev 10:41552d038a69 951 /* Bit fields for EBI NANDCTRL */
Zaitsev 10:41552d038a69 952 #define _EBI_NANDCTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 953 #define _EBI_NANDCTRL_MASK 0x00000031UL /**< Mask for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 954 #define EBI_NANDCTRL_EN (0x1UL << 0) /**< NAND Flash control enable */
Zaitsev 10:41552d038a69 955 #define _EBI_NANDCTRL_EN_SHIFT 0 /**< Shift value for EBI_EN */
Zaitsev 10:41552d038a69 956 #define _EBI_NANDCTRL_EN_MASK 0x1UL /**< Bit mask for EBI_EN */
Zaitsev 10:41552d038a69 957 #define _EBI_NANDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 958 #define EBI_NANDCTRL_EN_DEFAULT (_EBI_NANDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 959 #define _EBI_NANDCTRL_BANKSEL_SHIFT 4 /**< Shift value for EBI_BANKSEL */
Zaitsev 10:41552d038a69 960 #define _EBI_NANDCTRL_BANKSEL_MASK 0x30UL /**< Bit mask for EBI_BANKSEL */
Zaitsev 10:41552d038a69 961 #define _EBI_NANDCTRL_BANKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 962 #define _EBI_NANDCTRL_BANKSEL_BANK0 0x00000000UL /**< Mode BANK0 for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 963 #define _EBI_NANDCTRL_BANKSEL_BANK1 0x00000001UL /**< Mode BANK1 for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 964 #define _EBI_NANDCTRL_BANKSEL_BANK2 0x00000002UL /**< Mode BANK2 for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 965 #define _EBI_NANDCTRL_BANKSEL_BANK3 0x00000003UL /**< Mode BANK3 for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 966 #define EBI_NANDCTRL_BANKSEL_DEFAULT (_EBI_NANDCTRL_BANKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 967 #define EBI_NANDCTRL_BANKSEL_BANK0 (_EBI_NANDCTRL_BANKSEL_BANK0 << 4) /**< Shifted mode BANK0 for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 968 #define EBI_NANDCTRL_BANKSEL_BANK1 (_EBI_NANDCTRL_BANKSEL_BANK1 << 4) /**< Shifted mode BANK1 for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 969 #define EBI_NANDCTRL_BANKSEL_BANK2 (_EBI_NANDCTRL_BANKSEL_BANK2 << 4) /**< Shifted mode BANK2 for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 970 #define EBI_NANDCTRL_BANKSEL_BANK3 (_EBI_NANDCTRL_BANKSEL_BANK3 << 4) /**< Shifted mode BANK3 for EBI_NANDCTRL */
Zaitsev 10:41552d038a69 971
Zaitsev 10:41552d038a69 972 /* Bit fields for EBI CMD */
Zaitsev 10:41552d038a69 973 #define _EBI_CMD_RESETVALUE 0x00000000UL /**< Default value for EBI_CMD */
Zaitsev 10:41552d038a69 974 #define _EBI_CMD_MASK 0x00000007UL /**< Mask for EBI_CMD */
Zaitsev 10:41552d038a69 975 #define EBI_CMD_ECCSTART (0x1UL << 0) /**< Error Correction Code Generation Start */
Zaitsev 10:41552d038a69 976 #define _EBI_CMD_ECCSTART_SHIFT 0 /**< Shift value for EBI_ECCSTART */
Zaitsev 10:41552d038a69 977 #define _EBI_CMD_ECCSTART_MASK 0x1UL /**< Bit mask for EBI_ECCSTART */
Zaitsev 10:41552d038a69 978 #define _EBI_CMD_ECCSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */
Zaitsev 10:41552d038a69 979 #define EBI_CMD_ECCSTART_DEFAULT (_EBI_CMD_ECCSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_CMD */
Zaitsev 10:41552d038a69 980 #define EBI_CMD_ECCSTOP (0x1UL << 1) /**< Error Correction Code Generation Stop */
Zaitsev 10:41552d038a69 981 #define _EBI_CMD_ECCSTOP_SHIFT 1 /**< Shift value for EBI_ECCSTOP */
Zaitsev 10:41552d038a69 982 #define _EBI_CMD_ECCSTOP_MASK 0x2UL /**< Bit mask for EBI_ECCSTOP */
Zaitsev 10:41552d038a69 983 #define _EBI_CMD_ECCSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */
Zaitsev 10:41552d038a69 984 #define EBI_CMD_ECCSTOP_DEFAULT (_EBI_CMD_ECCSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_CMD */
Zaitsev 10:41552d038a69 985 #define EBI_CMD_ECCCLEAR (0x1UL << 2) /**< Error Correction Code Clear */
Zaitsev 10:41552d038a69 986 #define _EBI_CMD_ECCCLEAR_SHIFT 2 /**< Shift value for EBI_ECCCLEAR */
Zaitsev 10:41552d038a69 987 #define _EBI_CMD_ECCCLEAR_MASK 0x4UL /**< Bit mask for EBI_ECCCLEAR */
Zaitsev 10:41552d038a69 988 #define _EBI_CMD_ECCCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */
Zaitsev 10:41552d038a69 989 #define EBI_CMD_ECCCLEAR_DEFAULT (_EBI_CMD_ECCCLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_CMD */
Zaitsev 10:41552d038a69 990
Zaitsev 10:41552d038a69 991 /* Bit fields for EBI STATUS */
Zaitsev 10:41552d038a69 992 #define _EBI_STATUS_RESETVALUE 0x00000000UL /**< Default value for EBI_STATUS */
Zaitsev 10:41552d038a69 993 #define _EBI_STATUS_MASK 0x00003711UL /**< Mask for EBI_STATUS */
Zaitsev 10:41552d038a69 994 #define EBI_STATUS_AHBACT (0x1UL << 0) /**< EBI Busy with AHB Transaction. */
Zaitsev 10:41552d038a69 995 #define _EBI_STATUS_AHBACT_SHIFT 0 /**< Shift value for EBI_AHBACT */
Zaitsev 10:41552d038a69 996 #define _EBI_STATUS_AHBACT_MASK 0x1UL /**< Bit mask for EBI_AHBACT */
Zaitsev 10:41552d038a69 997 #define _EBI_STATUS_AHBACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 998 #define EBI_STATUS_AHBACT_DEFAULT (_EBI_STATUS_AHBACT_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 999 #define EBI_STATUS_ECCACT (0x1UL << 4) /**< EBI ECC Generation Active. */
Zaitsev 10:41552d038a69 1000 #define _EBI_STATUS_ECCACT_SHIFT 4 /**< Shift value for EBI_ECCACT */
Zaitsev 10:41552d038a69 1001 #define _EBI_STATUS_ECCACT_MASK 0x10UL /**< Bit mask for EBI_ECCACT */
Zaitsev 10:41552d038a69 1002 #define _EBI_STATUS_ECCACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 1003 #define EBI_STATUS_ECCACT_DEFAULT (_EBI_STATUS_ECCACT_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 1004 #define EBI_STATUS_TFTPIXEL0EMPTY (0x1UL << 8) /**< EBI_TFTPIXEL0 is empty. */
Zaitsev 10:41552d038a69 1005 #define _EBI_STATUS_TFTPIXEL0EMPTY_SHIFT 8 /**< Shift value for EBI_TFTPIXEL0EMPTY */
Zaitsev 10:41552d038a69 1006 #define _EBI_STATUS_TFTPIXEL0EMPTY_MASK 0x100UL /**< Bit mask for EBI_TFTPIXEL0EMPTY */
Zaitsev 10:41552d038a69 1007 #define _EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 1008 #define EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT (_EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 1009 #define EBI_STATUS_TFTPIXEL1EMPTY (0x1UL << 9) /**< EBI_TFTPIXEL1 is empty. */
Zaitsev 10:41552d038a69 1010 #define _EBI_STATUS_TFTPIXEL1EMPTY_SHIFT 9 /**< Shift value for EBI_TFTPIXEL1EMPTY */
Zaitsev 10:41552d038a69 1011 #define _EBI_STATUS_TFTPIXEL1EMPTY_MASK 0x200UL /**< Bit mask for EBI_TFTPIXEL1EMPTY */
Zaitsev 10:41552d038a69 1012 #define _EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 1013 #define EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT (_EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 1014 #define EBI_STATUS_TFTPIXELFULL (0x1UL << 10) /**< EBI_TFTPIXEL0 is full. */
Zaitsev 10:41552d038a69 1015 #define _EBI_STATUS_TFTPIXELFULL_SHIFT 10 /**< Shift value for EBI_TFTPIXELFULL */
Zaitsev 10:41552d038a69 1016 #define _EBI_STATUS_TFTPIXELFULL_MASK 0x400UL /**< Bit mask for EBI_TFTPIXELFULL */
Zaitsev 10:41552d038a69 1017 #define _EBI_STATUS_TFTPIXELFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 1018 #define EBI_STATUS_TFTPIXELFULL_DEFAULT (_EBI_STATUS_TFTPIXELFULL_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 1019 #define EBI_STATUS_DDACT (0x1UL << 12) /**< EBI Busy with Direct Drive Transactions. */
Zaitsev 10:41552d038a69 1020 #define _EBI_STATUS_DDACT_SHIFT 12 /**< Shift value for EBI_DDACT */
Zaitsev 10:41552d038a69 1021 #define _EBI_STATUS_DDACT_MASK 0x1000UL /**< Bit mask for EBI_DDACT */
Zaitsev 10:41552d038a69 1022 #define _EBI_STATUS_DDACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 1023 #define EBI_STATUS_DDACT_DEFAULT (_EBI_STATUS_DDACT_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 1024 #define EBI_STATUS_TFTDDEMPTY (0x1UL << 13) /**< EBI_TFTDD register is empty. */
Zaitsev 10:41552d038a69 1025 #define _EBI_STATUS_TFTDDEMPTY_SHIFT 13 /**< Shift value for EBI_TFTDDEMPTY */
Zaitsev 10:41552d038a69 1026 #define _EBI_STATUS_TFTDDEMPTY_MASK 0x2000UL /**< Bit mask for EBI_TFTDDEMPTY */
Zaitsev 10:41552d038a69 1027 #define _EBI_STATUS_TFTDDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 1028 #define EBI_STATUS_TFTDDEMPTY_DEFAULT (_EBI_STATUS_TFTDDEMPTY_DEFAULT << 13) /**< Shifted mode DEFAULT for EBI_STATUS */
Zaitsev 10:41552d038a69 1029
Zaitsev 10:41552d038a69 1030 /* Bit fields for EBI ECCPARITY */
Zaitsev 10:41552d038a69 1031 #define _EBI_ECCPARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_ECCPARITY */
Zaitsev 10:41552d038a69 1032 #define _EBI_ECCPARITY_MASK 0xFFFFFFFFUL /**< Mask for EBI_ECCPARITY */
Zaitsev 10:41552d038a69 1033 #define _EBI_ECCPARITY_ECCPARITY_SHIFT 0 /**< Shift value for EBI_ECCPARITY */
Zaitsev 10:41552d038a69 1034 #define _EBI_ECCPARITY_ECCPARITY_MASK 0xFFFFFFFFUL /**< Bit mask for EBI_ECCPARITY */
Zaitsev 10:41552d038a69 1035 #define _EBI_ECCPARITY_ECCPARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ECCPARITY */
Zaitsev 10:41552d038a69 1036 #define EBI_ECCPARITY_ECCPARITY_DEFAULT (_EBI_ECCPARITY_ECCPARITY_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ECCPARITY */
Zaitsev 10:41552d038a69 1037
Zaitsev 10:41552d038a69 1038 /* Bit fields for EBI TFTCTRL */
Zaitsev 10:41552d038a69 1039 #define _EBI_TFTCTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1040 #define _EBI_TFTCTRL_MASK 0x01311F1FUL /**< Mask for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1041 #define _EBI_TFTCTRL_DD_SHIFT 0 /**< Shift value for EBI_DD */
Zaitsev 10:41552d038a69 1042 #define _EBI_TFTCTRL_DD_MASK 0x3UL /**< Bit mask for EBI_DD */
Zaitsev 10:41552d038a69 1043 #define _EBI_TFTCTRL_DD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1044 #define _EBI_TFTCTRL_DD_DISABLED 0x00000000UL /**< Mode DISABLED for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1045 #define _EBI_TFTCTRL_DD_INTERNAL 0x00000001UL /**< Mode INTERNAL for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1046 #define _EBI_TFTCTRL_DD_EXTERNAL 0x00000002UL /**< Mode EXTERNAL for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1047 #define EBI_TFTCTRL_DD_DEFAULT (_EBI_TFTCTRL_DD_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1048 #define EBI_TFTCTRL_DD_DISABLED (_EBI_TFTCTRL_DD_DISABLED << 0) /**< Shifted mode DISABLED for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1049 #define EBI_TFTCTRL_DD_INTERNAL (_EBI_TFTCTRL_DD_INTERNAL << 0) /**< Shifted mode INTERNAL for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1050 #define EBI_TFTCTRL_DD_EXTERNAL (_EBI_TFTCTRL_DD_EXTERNAL << 0) /**< Shifted mode EXTERNAL for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1051 #define _EBI_TFTCTRL_MASKBLEND_SHIFT 2 /**< Shift value for EBI_MASKBLEND */
Zaitsev 10:41552d038a69 1052 #define _EBI_TFTCTRL_MASKBLEND_MASK 0x1CUL /**< Bit mask for EBI_MASKBLEND */
Zaitsev 10:41552d038a69 1053 #define _EBI_TFTCTRL_MASKBLEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1054 #define _EBI_TFTCTRL_MASKBLEND_DISABLED 0x00000000UL /**< Mode DISABLED for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1055 #define _EBI_TFTCTRL_MASKBLEND_IMASK 0x00000001UL /**< Mode IMASK for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1056 #define _EBI_TFTCTRL_MASKBLEND_IALPHA 0x00000002UL /**< Mode IALPHA for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1057 #define _EBI_TFTCTRL_MASKBLEND_IMASKIALPHA 0x00000003UL /**< Mode IMASKIALPHA for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1058 #define _EBI_TFTCTRL_MASKBLEND_EMASK 0x00000005UL /**< Mode EMASK for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1059 #define _EBI_TFTCTRL_MASKBLEND_EALPHA 0x00000006UL /**< Mode EALPHA for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1060 #define _EBI_TFTCTRL_MASKBLEND_EMASKEALPHA 0x00000007UL /**< Mode EMASKEALPHA for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1061 #define EBI_TFTCTRL_MASKBLEND_DEFAULT (_EBI_TFTCTRL_MASKBLEND_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1062 #define EBI_TFTCTRL_MASKBLEND_DISABLED (_EBI_TFTCTRL_MASKBLEND_DISABLED << 2) /**< Shifted mode DISABLED for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1063 #define EBI_TFTCTRL_MASKBLEND_IMASK (_EBI_TFTCTRL_MASKBLEND_IMASK << 2) /**< Shifted mode IMASK for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1064 #define EBI_TFTCTRL_MASKBLEND_IALPHA (_EBI_TFTCTRL_MASKBLEND_IALPHA << 2) /**< Shifted mode IALPHA for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1065 #define EBI_TFTCTRL_MASKBLEND_IMASKIALPHA (_EBI_TFTCTRL_MASKBLEND_IMASKIALPHA << 2) /**< Shifted mode IMASKIALPHA for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1066 #define EBI_TFTCTRL_MASKBLEND_EMASK (_EBI_TFTCTRL_MASKBLEND_EMASK << 2) /**< Shifted mode EMASK for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1067 #define EBI_TFTCTRL_MASKBLEND_EALPHA (_EBI_TFTCTRL_MASKBLEND_EALPHA << 2) /**< Shifted mode EALPHA for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1068 #define EBI_TFTCTRL_MASKBLEND_EMASKEALPHA (_EBI_TFTCTRL_MASKBLEND_EMASKEALPHA << 2) /**< Shifted mode EMASKEALPHA for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1069 #define EBI_TFTCTRL_SHIFTDCLKEN (0x1UL << 8) /**< TFT EBI_DCLK Shift Enable */
Zaitsev 10:41552d038a69 1070 #define _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT 8 /**< Shift value for EBI_SHIFTDCLKEN */
Zaitsev 10:41552d038a69 1071 #define _EBI_TFTCTRL_SHIFTDCLKEN_MASK 0x100UL /**< Bit mask for EBI_SHIFTDCLKEN */
Zaitsev 10:41552d038a69 1072 #define _EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1073 #define EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT (_EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1074 #define EBI_TFTCTRL_FBCTRIG (0x1UL << 9) /**< TFT Frame Base Copy Trigger */
Zaitsev 10:41552d038a69 1075 #define _EBI_TFTCTRL_FBCTRIG_SHIFT 9 /**< Shift value for EBI_FBCTRIG */
Zaitsev 10:41552d038a69 1076 #define _EBI_TFTCTRL_FBCTRIG_MASK 0x200UL /**< Bit mask for EBI_FBCTRIG */
Zaitsev 10:41552d038a69 1077 #define _EBI_TFTCTRL_FBCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1078 #define _EBI_TFTCTRL_FBCTRIG_VSYNC 0x00000000UL /**< Mode VSYNC for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1079 #define _EBI_TFTCTRL_FBCTRIG_HSYNC 0x00000001UL /**< Mode HSYNC for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1080 #define EBI_TFTCTRL_FBCTRIG_DEFAULT (_EBI_TFTCTRL_FBCTRIG_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1081 #define EBI_TFTCTRL_FBCTRIG_VSYNC (_EBI_TFTCTRL_FBCTRIG_VSYNC << 9) /**< Shifted mode VSYNC for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1082 #define EBI_TFTCTRL_FBCTRIG_HSYNC (_EBI_TFTCTRL_FBCTRIG_HSYNC << 9) /**< Shifted mode HSYNC for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1083 #define _EBI_TFTCTRL_INTERLEAVE_SHIFT 10 /**< Shift value for EBI_INTERLEAVE */
Zaitsev 10:41552d038a69 1084 #define _EBI_TFTCTRL_INTERLEAVE_MASK 0xC00UL /**< Bit mask for EBI_INTERLEAVE */
Zaitsev 10:41552d038a69 1085 #define _EBI_TFTCTRL_INTERLEAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1086 #define _EBI_TFTCTRL_INTERLEAVE_UNLIMITED 0x00000000UL /**< Mode UNLIMITED for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1087 #define _EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK 0x00000001UL /**< Mode ONEPERDCLK for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1088 #define _EBI_TFTCTRL_INTERLEAVE_PORCH 0x00000002UL /**< Mode PORCH for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1089 #define EBI_TFTCTRL_INTERLEAVE_DEFAULT (_EBI_TFTCTRL_INTERLEAVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1090 #define EBI_TFTCTRL_INTERLEAVE_UNLIMITED (_EBI_TFTCTRL_INTERLEAVE_UNLIMITED << 10) /**< Shifted mode UNLIMITED for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1091 #define EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK (_EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK << 10) /**< Shifted mode ONEPERDCLK for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1092 #define EBI_TFTCTRL_INTERLEAVE_PORCH (_EBI_TFTCTRL_INTERLEAVE_PORCH << 10) /**< Shifted mode PORCH for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1093 #define EBI_TFTCTRL_COLOR1SRC (0x1UL << 12) /**< Masking/Alpha Blending Color1 Source */
Zaitsev 10:41552d038a69 1094 #define _EBI_TFTCTRL_COLOR1SRC_SHIFT 12 /**< Shift value for EBI_COLOR1SRC */
Zaitsev 10:41552d038a69 1095 #define _EBI_TFTCTRL_COLOR1SRC_MASK 0x1000UL /**< Bit mask for EBI_COLOR1SRC */
Zaitsev 10:41552d038a69 1096 #define _EBI_TFTCTRL_COLOR1SRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1097 #define _EBI_TFTCTRL_COLOR1SRC_MEM 0x00000000UL /**< Mode MEM for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1098 #define _EBI_TFTCTRL_COLOR1SRC_PIXEL1 0x00000001UL /**< Mode PIXEL1 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1099 #define EBI_TFTCTRL_COLOR1SRC_DEFAULT (_EBI_TFTCTRL_COLOR1SRC_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1100 #define EBI_TFTCTRL_COLOR1SRC_MEM (_EBI_TFTCTRL_COLOR1SRC_MEM << 12) /**< Shifted mode MEM for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1101 #define EBI_TFTCTRL_COLOR1SRC_PIXEL1 (_EBI_TFTCTRL_COLOR1SRC_PIXEL1 << 12) /**< Shifted mode PIXEL1 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1102 #define EBI_TFTCTRL_WIDTH (0x1UL << 16) /**< TFT Transaction Width */
Zaitsev 10:41552d038a69 1103 #define _EBI_TFTCTRL_WIDTH_SHIFT 16 /**< Shift value for EBI_WIDTH */
Zaitsev 10:41552d038a69 1104 #define _EBI_TFTCTRL_WIDTH_MASK 0x10000UL /**< Bit mask for EBI_WIDTH */
Zaitsev 10:41552d038a69 1105 #define _EBI_TFTCTRL_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1106 #define _EBI_TFTCTRL_WIDTH_BYTE 0x00000000UL /**< Mode BYTE for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1107 #define _EBI_TFTCTRL_WIDTH_HALFWORD 0x00000001UL /**< Mode HALFWORD for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1108 #define EBI_TFTCTRL_WIDTH_DEFAULT (_EBI_TFTCTRL_WIDTH_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1109 #define EBI_TFTCTRL_WIDTH_BYTE (_EBI_TFTCTRL_WIDTH_BYTE << 16) /**< Shifted mode BYTE for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1110 #define EBI_TFTCTRL_WIDTH_HALFWORD (_EBI_TFTCTRL_WIDTH_HALFWORD << 16) /**< Shifted mode HALFWORD for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1111 #define _EBI_TFTCTRL_BANKSEL_SHIFT 20 /**< Shift value for EBI_BANKSEL */
Zaitsev 10:41552d038a69 1112 #define _EBI_TFTCTRL_BANKSEL_MASK 0x300000UL /**< Bit mask for EBI_BANKSEL */
Zaitsev 10:41552d038a69 1113 #define _EBI_TFTCTRL_BANKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1114 #define _EBI_TFTCTRL_BANKSEL_BANK0 0x00000000UL /**< Mode BANK0 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1115 #define _EBI_TFTCTRL_BANKSEL_BANK1 0x00000001UL /**< Mode BANK1 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1116 #define _EBI_TFTCTRL_BANKSEL_BANK2 0x00000002UL /**< Mode BANK2 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1117 #define _EBI_TFTCTRL_BANKSEL_BANK3 0x00000003UL /**< Mode BANK3 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1118 #define EBI_TFTCTRL_BANKSEL_DEFAULT (_EBI_TFTCTRL_BANKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1119 #define EBI_TFTCTRL_BANKSEL_BANK0 (_EBI_TFTCTRL_BANKSEL_BANK0 << 20) /**< Shifted mode BANK0 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1120 #define EBI_TFTCTRL_BANKSEL_BANK1 (_EBI_TFTCTRL_BANKSEL_BANK1 << 20) /**< Shifted mode BANK1 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1121 #define EBI_TFTCTRL_BANKSEL_BANK2 (_EBI_TFTCTRL_BANKSEL_BANK2 << 20) /**< Shifted mode BANK2 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1122 #define EBI_TFTCTRL_BANKSEL_BANK3 (_EBI_TFTCTRL_BANKSEL_BANK3 << 20) /**< Shifted mode BANK3 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1123 #define EBI_TFTCTRL_RGBMODE (0x1UL << 24) /**< TFT RGB Mode */
Zaitsev 10:41552d038a69 1124 #define _EBI_TFTCTRL_RGBMODE_SHIFT 24 /**< Shift value for EBI_RGBMODE */
Zaitsev 10:41552d038a69 1125 #define _EBI_TFTCTRL_RGBMODE_MASK 0x1000000UL /**< Bit mask for EBI_RGBMODE */
Zaitsev 10:41552d038a69 1126 #define _EBI_TFTCTRL_RGBMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1127 #define _EBI_TFTCTRL_RGBMODE_RGB565 0x00000000UL /**< Mode RGB565 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1128 #define _EBI_TFTCTRL_RGBMODE_RGB555 0x00000001UL /**< Mode RGB555 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1129 #define EBI_TFTCTRL_RGBMODE_DEFAULT (_EBI_TFTCTRL_RGBMODE_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1130 #define EBI_TFTCTRL_RGBMODE_RGB565 (_EBI_TFTCTRL_RGBMODE_RGB565 << 24) /**< Shifted mode RGB565 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1131 #define EBI_TFTCTRL_RGBMODE_RGB555 (_EBI_TFTCTRL_RGBMODE_RGB555 << 24) /**< Shifted mode RGB555 for EBI_TFTCTRL */
Zaitsev 10:41552d038a69 1132
Zaitsev 10:41552d038a69 1133 /* Bit fields for EBI TFTSTATUS */
Zaitsev 10:41552d038a69 1134 #define _EBI_TFTSTATUS_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSTATUS */
Zaitsev 10:41552d038a69 1135 #define _EBI_TFTSTATUS_MASK 0x07FF07FFUL /**< Mask for EBI_TFTSTATUS */
Zaitsev 10:41552d038a69 1136 #define _EBI_TFTSTATUS_HCNT_SHIFT 0 /**< Shift value for EBI_HCNT */
Zaitsev 10:41552d038a69 1137 #define _EBI_TFTSTATUS_HCNT_MASK 0x7FFUL /**< Bit mask for EBI_HCNT */
Zaitsev 10:41552d038a69 1138 #define _EBI_TFTSTATUS_HCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTATUS */
Zaitsev 10:41552d038a69 1139 #define EBI_TFTSTATUS_HCNT_DEFAULT (_EBI_TFTSTATUS_HCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSTATUS */
Zaitsev 10:41552d038a69 1140 #define _EBI_TFTSTATUS_VCNT_SHIFT 16 /**< Shift value for EBI_VCNT */
Zaitsev 10:41552d038a69 1141 #define _EBI_TFTSTATUS_VCNT_MASK 0x7FF0000UL /**< Bit mask for EBI_VCNT */
Zaitsev 10:41552d038a69 1142 #define _EBI_TFTSTATUS_VCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTATUS */
Zaitsev 10:41552d038a69 1143 #define EBI_TFTSTATUS_VCNT_DEFAULT (_EBI_TFTSTATUS_VCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTSTATUS */
Zaitsev 10:41552d038a69 1144
Zaitsev 10:41552d038a69 1145 /* Bit fields for EBI TFTFRAMEBASE */
Zaitsev 10:41552d038a69 1146 #define _EBI_TFTFRAMEBASE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTFRAMEBASE */
Zaitsev 10:41552d038a69 1147 #define _EBI_TFTFRAMEBASE_MASK 0x0FFFFFFFUL /**< Mask for EBI_TFTFRAMEBASE */
Zaitsev 10:41552d038a69 1148 #define _EBI_TFTFRAMEBASE_FRAMEBASE_SHIFT 0 /**< Shift value for EBI_FRAMEBASE */
Zaitsev 10:41552d038a69 1149 #define _EBI_TFTFRAMEBASE_FRAMEBASE_MASK 0xFFFFFFFUL /**< Bit mask for EBI_FRAMEBASE */
Zaitsev 10:41552d038a69 1150 #define _EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTFRAMEBASE */
Zaitsev 10:41552d038a69 1151 #define EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT (_EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTFRAMEBASE */
Zaitsev 10:41552d038a69 1152
Zaitsev 10:41552d038a69 1153 /* Bit fields for EBI TFTSTRIDE */
Zaitsev 10:41552d038a69 1154 #define _EBI_TFTSTRIDE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSTRIDE */
Zaitsev 10:41552d038a69 1155 #define _EBI_TFTSTRIDE_MASK 0x00000FFFUL /**< Mask for EBI_TFTSTRIDE */
Zaitsev 10:41552d038a69 1156 #define _EBI_TFTSTRIDE_HSTRIDE_SHIFT 0 /**< Shift value for EBI_HSTRIDE */
Zaitsev 10:41552d038a69 1157 #define _EBI_TFTSTRIDE_HSTRIDE_MASK 0xFFFUL /**< Bit mask for EBI_HSTRIDE */
Zaitsev 10:41552d038a69 1158 #define _EBI_TFTSTRIDE_HSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTRIDE */
Zaitsev 10:41552d038a69 1159 #define EBI_TFTSTRIDE_HSTRIDE_DEFAULT (_EBI_TFTSTRIDE_HSTRIDE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSTRIDE */
Zaitsev 10:41552d038a69 1160
Zaitsev 10:41552d038a69 1161 /* Bit fields for EBI TFTSIZE */
Zaitsev 10:41552d038a69 1162 #define _EBI_TFTSIZE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSIZE */
Zaitsev 10:41552d038a69 1163 #define _EBI_TFTSIZE_MASK 0x03FF03FFUL /**< Mask for EBI_TFTSIZE */
Zaitsev 10:41552d038a69 1164 #define _EBI_TFTSIZE_HSZ_SHIFT 0 /**< Shift value for EBI_HSZ */
Zaitsev 10:41552d038a69 1165 #define _EBI_TFTSIZE_HSZ_MASK 0x3FFUL /**< Bit mask for EBI_HSZ */
Zaitsev 10:41552d038a69 1166 #define _EBI_TFTSIZE_HSZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSIZE */
Zaitsev 10:41552d038a69 1167 #define EBI_TFTSIZE_HSZ_DEFAULT (_EBI_TFTSIZE_HSZ_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSIZE */
Zaitsev 10:41552d038a69 1168 #define _EBI_TFTSIZE_VSZ_SHIFT 16 /**< Shift value for EBI_VSZ */
Zaitsev 10:41552d038a69 1169 #define _EBI_TFTSIZE_VSZ_MASK 0x3FF0000UL /**< Bit mask for EBI_VSZ */
Zaitsev 10:41552d038a69 1170 #define _EBI_TFTSIZE_VSZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSIZE */
Zaitsev 10:41552d038a69 1171 #define EBI_TFTSIZE_VSZ_DEFAULT (_EBI_TFTSIZE_VSZ_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTSIZE */
Zaitsev 10:41552d038a69 1172
Zaitsev 10:41552d038a69 1173 /* Bit fields for EBI TFTHPORCH */
Zaitsev 10:41552d038a69 1174 #define _EBI_TFTHPORCH_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTHPORCH */
Zaitsev 10:41552d038a69 1175 #define _EBI_TFTHPORCH_MASK 0x33FCFF7FUL /**< Mask for EBI_TFTHPORCH */
Zaitsev 10:41552d038a69 1176 #define _EBI_TFTHPORCH_HSYNC_SHIFT 0 /**< Shift value for EBI_HSYNC */
Zaitsev 10:41552d038a69 1177 #define _EBI_TFTHPORCH_HSYNC_MASK 0x7FUL /**< Bit mask for EBI_HSYNC */
Zaitsev 10:41552d038a69 1178 #define _EBI_TFTHPORCH_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */
Zaitsev 10:41552d038a69 1179 #define EBI_TFTHPORCH_HSYNC_DEFAULT (_EBI_TFTHPORCH_HSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */
Zaitsev 10:41552d038a69 1180 #define _EBI_TFTHPORCH_HFPORCH_SHIFT 8 /**< Shift value for EBI_HFPORCH */
Zaitsev 10:41552d038a69 1181 #define _EBI_TFTHPORCH_HFPORCH_MASK 0xFF00UL /**< Bit mask for EBI_HFPORCH */
Zaitsev 10:41552d038a69 1182 #define _EBI_TFTHPORCH_HFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */
Zaitsev 10:41552d038a69 1183 #define EBI_TFTHPORCH_HFPORCH_DEFAULT (_EBI_TFTHPORCH_HFPORCH_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */
Zaitsev 10:41552d038a69 1184 #define _EBI_TFTHPORCH_HBPORCH_SHIFT 18 /**< Shift value for EBI_HBPORCH */
Zaitsev 10:41552d038a69 1185 #define _EBI_TFTHPORCH_HBPORCH_MASK 0x3FC0000UL /**< Bit mask for EBI_HBPORCH */
Zaitsev 10:41552d038a69 1186 #define _EBI_TFTHPORCH_HBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */
Zaitsev 10:41552d038a69 1187 #define EBI_TFTHPORCH_HBPORCH_DEFAULT (_EBI_TFTHPORCH_HBPORCH_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */
Zaitsev 10:41552d038a69 1188 #define _EBI_TFTHPORCH_HSYNCSTART_SHIFT 28 /**< Shift value for EBI_HSYNCSTART */
Zaitsev 10:41552d038a69 1189 #define _EBI_TFTHPORCH_HSYNCSTART_MASK 0x30000000UL /**< Bit mask for EBI_HSYNCSTART */
Zaitsev 10:41552d038a69 1190 #define _EBI_TFTHPORCH_HSYNCSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */
Zaitsev 10:41552d038a69 1191 #define EBI_TFTHPORCH_HSYNCSTART_DEFAULT (_EBI_TFTHPORCH_HSYNCSTART_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */
Zaitsev 10:41552d038a69 1192
Zaitsev 10:41552d038a69 1193 /* Bit fields for EBI TFTVPORCH */
Zaitsev 10:41552d038a69 1194 #define _EBI_TFTVPORCH_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTVPORCH */
Zaitsev 10:41552d038a69 1195 #define _EBI_TFTVPORCH_MASK 0x03FCFF7FUL /**< Mask for EBI_TFTVPORCH */
Zaitsev 10:41552d038a69 1196 #define _EBI_TFTVPORCH_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */
Zaitsev 10:41552d038a69 1197 #define _EBI_TFTVPORCH_VSYNC_MASK 0x7FUL /**< Bit mask for EBI_VSYNC */
Zaitsev 10:41552d038a69 1198 #define _EBI_TFTVPORCH_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */
Zaitsev 10:41552d038a69 1199 #define EBI_TFTVPORCH_VSYNC_DEFAULT (_EBI_TFTVPORCH_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */
Zaitsev 10:41552d038a69 1200 #define _EBI_TFTVPORCH_VFPORCH_SHIFT 8 /**< Shift value for EBI_VFPORCH */
Zaitsev 10:41552d038a69 1201 #define _EBI_TFTVPORCH_VFPORCH_MASK 0xFF00UL /**< Bit mask for EBI_VFPORCH */
Zaitsev 10:41552d038a69 1202 #define _EBI_TFTVPORCH_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */
Zaitsev 10:41552d038a69 1203 #define EBI_TFTVPORCH_VFPORCH_DEFAULT (_EBI_TFTVPORCH_VFPORCH_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */
Zaitsev 10:41552d038a69 1204 #define _EBI_TFTVPORCH_VBPORCH_SHIFT 18 /**< Shift value for EBI_VBPORCH */
Zaitsev 10:41552d038a69 1205 #define _EBI_TFTVPORCH_VBPORCH_MASK 0x3FC0000UL /**< Bit mask for EBI_VBPORCH */
Zaitsev 10:41552d038a69 1206 #define _EBI_TFTVPORCH_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */
Zaitsev 10:41552d038a69 1207 #define EBI_TFTVPORCH_VBPORCH_DEFAULT (_EBI_TFTVPORCH_VBPORCH_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */
Zaitsev 10:41552d038a69 1208
Zaitsev 10:41552d038a69 1209 /* Bit fields for EBI TFTTIMING */
Zaitsev 10:41552d038a69 1210 #define _EBI_TFTTIMING_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTTIMING */
Zaitsev 10:41552d038a69 1211 #define _EBI_TFTTIMING_MASK 0x337FF7FFUL /**< Mask for EBI_TFTTIMING */
Zaitsev 10:41552d038a69 1212 #define _EBI_TFTTIMING_DCLKPERIOD_SHIFT 0 /**< Shift value for EBI_DCLKPERIOD */
Zaitsev 10:41552d038a69 1213 #define _EBI_TFTTIMING_DCLKPERIOD_MASK 0x7FFUL /**< Bit mask for EBI_DCLKPERIOD */
Zaitsev 10:41552d038a69 1214 #define _EBI_TFTTIMING_DCLKPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */
Zaitsev 10:41552d038a69 1215 #define EBI_TFTTIMING_DCLKPERIOD_DEFAULT (_EBI_TFTTIMING_DCLKPERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTTIMING */
Zaitsev 10:41552d038a69 1216 #define _EBI_TFTTIMING_TFTSTART_SHIFT 12 /**< Shift value for EBI_TFTSTART */
Zaitsev 10:41552d038a69 1217 #define _EBI_TFTTIMING_TFTSTART_MASK 0x7FF000UL /**< Bit mask for EBI_TFTSTART */
Zaitsev 10:41552d038a69 1218 #define _EBI_TFTTIMING_TFTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */
Zaitsev 10:41552d038a69 1219 #define EBI_TFTTIMING_TFTSTART_DEFAULT (_EBI_TFTTIMING_TFTSTART_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_TFTTIMING */
Zaitsev 10:41552d038a69 1220 #define _EBI_TFTTIMING_TFTSETUP_SHIFT 24 /**< Shift value for EBI_TFTSETUP */
Zaitsev 10:41552d038a69 1221 #define _EBI_TFTTIMING_TFTSETUP_MASK 0x3000000UL /**< Bit mask for EBI_TFTSETUP */
Zaitsev 10:41552d038a69 1222 #define _EBI_TFTTIMING_TFTSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */
Zaitsev 10:41552d038a69 1223 #define EBI_TFTTIMING_TFTSETUP_DEFAULT (_EBI_TFTTIMING_TFTSETUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_TFTTIMING */
Zaitsev 10:41552d038a69 1224 #define _EBI_TFTTIMING_TFTHOLD_SHIFT 28 /**< Shift value for EBI_TFTHOLD */
Zaitsev 10:41552d038a69 1225 #define _EBI_TFTTIMING_TFTHOLD_MASK 0x30000000UL /**< Bit mask for EBI_TFTHOLD */
Zaitsev 10:41552d038a69 1226 #define _EBI_TFTTIMING_TFTHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */
Zaitsev 10:41552d038a69 1227 #define EBI_TFTTIMING_TFTHOLD_DEFAULT (_EBI_TFTTIMING_TFTHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_TFTTIMING */
Zaitsev 10:41552d038a69 1228
Zaitsev 10:41552d038a69 1229 /* Bit fields for EBI TFTPOLARITY */
Zaitsev 10:41552d038a69 1230 #define _EBI_TFTPOLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1231 #define _EBI_TFTPOLARITY_MASK 0x0000001FUL /**< Mask for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1232 #define EBI_TFTPOLARITY_CSPOL (0x1UL << 0) /**< TFT Chip Select Polarity */
Zaitsev 10:41552d038a69 1233 #define _EBI_TFTPOLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */
Zaitsev 10:41552d038a69 1234 #define _EBI_TFTPOLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */
Zaitsev 10:41552d038a69 1235 #define _EBI_TFTPOLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1236 #define _EBI_TFTPOLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1237 #define _EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1238 #define EBI_TFTPOLARITY_CSPOL_DEFAULT (_EBI_TFTPOLARITY_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1239 #define EBI_TFTPOLARITY_CSPOL_ACTIVELOW (_EBI_TFTPOLARITY_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1240 #define EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1241 #define EBI_TFTPOLARITY_DCLKPOL (0x1UL << 1) /**< TFT DCLK Polarity */
Zaitsev 10:41552d038a69 1242 #define _EBI_TFTPOLARITY_DCLKPOL_SHIFT 1 /**< Shift value for EBI_DCLKPOL */
Zaitsev 10:41552d038a69 1243 #define _EBI_TFTPOLARITY_DCLKPOL_MASK 0x2UL /**< Bit mask for EBI_DCLKPOL */
Zaitsev 10:41552d038a69 1244 #define _EBI_TFTPOLARITY_DCLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1245 #define _EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING 0x00000000UL /**< Mode ACTIVEFALLING for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1246 #define _EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING 0x00000001UL /**< Mode ACTIVERISING for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1247 #define EBI_TFTPOLARITY_DCLKPOL_DEFAULT (_EBI_TFTPOLARITY_DCLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1248 #define EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING (_EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING << 1) /**< Shifted mode ACTIVEFALLING for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1249 #define EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING (_EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING << 1) /**< Shifted mode ACTIVERISING for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1250 #define EBI_TFTPOLARITY_DATAENPOL (0x1UL << 2) /**< TFT DATAEN Polarity */
Zaitsev 10:41552d038a69 1251 #define _EBI_TFTPOLARITY_DATAENPOL_SHIFT 2 /**< Shift value for EBI_DATAENPOL */
Zaitsev 10:41552d038a69 1252 #define _EBI_TFTPOLARITY_DATAENPOL_MASK 0x4UL /**< Bit mask for EBI_DATAENPOL */
Zaitsev 10:41552d038a69 1253 #define _EBI_TFTPOLARITY_DATAENPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1254 #define _EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1255 #define _EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1256 #define EBI_TFTPOLARITY_DATAENPOL_DEFAULT (_EBI_TFTPOLARITY_DATAENPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1257 #define EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW (_EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1258 #define EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1259 #define EBI_TFTPOLARITY_HSYNCPOL (0x1UL << 3) /**< Address Latch Polarity */
Zaitsev 10:41552d038a69 1260 #define _EBI_TFTPOLARITY_HSYNCPOL_SHIFT 3 /**< Shift value for EBI_HSYNCPOL */
Zaitsev 10:41552d038a69 1261 #define _EBI_TFTPOLARITY_HSYNCPOL_MASK 0x8UL /**< Bit mask for EBI_HSYNCPOL */
Zaitsev 10:41552d038a69 1262 #define _EBI_TFTPOLARITY_HSYNCPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1263 #define _EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1264 #define _EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1265 #define EBI_TFTPOLARITY_HSYNCPOL_DEFAULT (_EBI_TFTPOLARITY_HSYNCPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1266 #define EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1267 #define EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1268 #define EBI_TFTPOLARITY_VSYNCPOL (0x1UL << 4) /**< VSYNC Polarity */
Zaitsev 10:41552d038a69 1269 #define _EBI_TFTPOLARITY_VSYNCPOL_SHIFT 4 /**< Shift value for EBI_VSYNCPOL */
Zaitsev 10:41552d038a69 1270 #define _EBI_TFTPOLARITY_VSYNCPOL_MASK 0x10UL /**< Bit mask for EBI_VSYNCPOL */
Zaitsev 10:41552d038a69 1271 #define _EBI_TFTPOLARITY_VSYNCPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1272 #define _EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1273 #define _EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1274 #define EBI_TFTPOLARITY_VSYNCPOL_DEFAULT (_EBI_TFTPOLARITY_VSYNCPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1275 #define EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1276 #define EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */
Zaitsev 10:41552d038a69 1277
Zaitsev 10:41552d038a69 1278 /* Bit fields for EBI TFTDD */
Zaitsev 10:41552d038a69 1279 #define _EBI_TFTDD_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTDD */
Zaitsev 10:41552d038a69 1280 #define _EBI_TFTDD_MASK 0x0000FFFFUL /**< Mask for EBI_TFTDD */
Zaitsev 10:41552d038a69 1281 #define _EBI_TFTDD_DATA_SHIFT 0 /**< Shift value for EBI_DATA */
Zaitsev 10:41552d038a69 1282 #define _EBI_TFTDD_DATA_MASK 0xFFFFUL /**< Bit mask for EBI_DATA */
Zaitsev 10:41552d038a69 1283 #define _EBI_TFTDD_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTDD */
Zaitsev 10:41552d038a69 1284 #define EBI_TFTDD_DATA_DEFAULT (_EBI_TFTDD_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTDD */
Zaitsev 10:41552d038a69 1285
Zaitsev 10:41552d038a69 1286 /* Bit fields for EBI TFTALPHA */
Zaitsev 10:41552d038a69 1287 #define _EBI_TFTALPHA_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTALPHA */
Zaitsev 10:41552d038a69 1288 #define _EBI_TFTALPHA_MASK 0x000001FFUL /**< Mask for EBI_TFTALPHA */
Zaitsev 10:41552d038a69 1289 #define _EBI_TFTALPHA_ALPHA_SHIFT 0 /**< Shift value for EBI_ALPHA */
Zaitsev 10:41552d038a69 1290 #define _EBI_TFTALPHA_ALPHA_MASK 0x1FFUL /**< Bit mask for EBI_ALPHA */
Zaitsev 10:41552d038a69 1291 #define _EBI_TFTALPHA_ALPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTALPHA */
Zaitsev 10:41552d038a69 1292 #define EBI_TFTALPHA_ALPHA_DEFAULT (_EBI_TFTALPHA_ALPHA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTALPHA */
Zaitsev 10:41552d038a69 1293
Zaitsev 10:41552d038a69 1294 /* Bit fields for EBI TFTPIXEL0 */
Zaitsev 10:41552d038a69 1295 #define _EBI_TFTPIXEL0_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL0 */
Zaitsev 10:41552d038a69 1296 #define _EBI_TFTPIXEL0_MASK 0x0000FFFFUL /**< Mask for EBI_TFTPIXEL0 */
Zaitsev 10:41552d038a69 1297 #define _EBI_TFTPIXEL0_DATA_SHIFT 0 /**< Shift value for EBI_DATA */
Zaitsev 10:41552d038a69 1298 #define _EBI_TFTPIXEL0_DATA_MASK 0xFFFFUL /**< Bit mask for EBI_DATA */
Zaitsev 10:41552d038a69 1299 #define _EBI_TFTPIXEL0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL0 */
Zaitsev 10:41552d038a69 1300 #define EBI_TFTPIXEL0_DATA_DEFAULT (_EBI_TFTPIXEL0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL0 */
Zaitsev 10:41552d038a69 1301
Zaitsev 10:41552d038a69 1302 /* Bit fields for EBI TFTPIXEL1 */
Zaitsev 10:41552d038a69 1303 #define _EBI_TFTPIXEL1_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL1 */
Zaitsev 10:41552d038a69 1304 #define _EBI_TFTPIXEL1_MASK 0x0000FFFFUL /**< Mask for EBI_TFTPIXEL1 */
Zaitsev 10:41552d038a69 1305 #define _EBI_TFTPIXEL1_DATA_SHIFT 0 /**< Shift value for EBI_DATA */
Zaitsev 10:41552d038a69 1306 #define _EBI_TFTPIXEL1_DATA_MASK 0xFFFFUL /**< Bit mask for EBI_DATA */
Zaitsev 10:41552d038a69 1307 #define _EBI_TFTPIXEL1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL1 */
Zaitsev 10:41552d038a69 1308 #define EBI_TFTPIXEL1_DATA_DEFAULT (_EBI_TFTPIXEL1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL1 */
Zaitsev 10:41552d038a69 1309
Zaitsev 10:41552d038a69 1310 /* Bit fields for EBI TFTPIXEL */
Zaitsev 10:41552d038a69 1311 #define _EBI_TFTPIXEL_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL */
Zaitsev 10:41552d038a69 1312 #define _EBI_TFTPIXEL_MASK 0x0000FFFFUL /**< Mask for EBI_TFTPIXEL */
Zaitsev 10:41552d038a69 1313 #define _EBI_TFTPIXEL_DATA_SHIFT 0 /**< Shift value for EBI_DATA */
Zaitsev 10:41552d038a69 1314 #define _EBI_TFTPIXEL_DATA_MASK 0xFFFFUL /**< Bit mask for EBI_DATA */
Zaitsev 10:41552d038a69 1315 #define _EBI_TFTPIXEL_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL */
Zaitsev 10:41552d038a69 1316 #define EBI_TFTPIXEL_DATA_DEFAULT (_EBI_TFTPIXEL_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL */
Zaitsev 10:41552d038a69 1317
Zaitsev 10:41552d038a69 1318 /* Bit fields for EBI TFTMASK */
Zaitsev 10:41552d038a69 1319 #define _EBI_TFTMASK_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTMASK */
Zaitsev 10:41552d038a69 1320 #define _EBI_TFTMASK_MASK 0x0000FFFFUL /**< Mask for EBI_TFTMASK */
Zaitsev 10:41552d038a69 1321 #define _EBI_TFTMASK_TFTMASK_SHIFT 0 /**< Shift value for EBI_TFTMASK */
Zaitsev 10:41552d038a69 1322 #define _EBI_TFTMASK_TFTMASK_MASK 0xFFFFUL /**< Bit mask for EBI_TFTMASK */
Zaitsev 10:41552d038a69 1323 #define _EBI_TFTMASK_TFTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTMASK */
Zaitsev 10:41552d038a69 1324 #define EBI_TFTMASK_TFTMASK_DEFAULT (_EBI_TFTMASK_TFTMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTMASK */
Zaitsev 10:41552d038a69 1325
Zaitsev 10:41552d038a69 1326 /* Bit fields for EBI IF */
Zaitsev 10:41552d038a69 1327 #define _EBI_IF_RESETVALUE 0x00000000UL /**< Default value for EBI_IF */
Zaitsev 10:41552d038a69 1328 #define _EBI_IF_MASK 0x0000003FUL /**< Mask for EBI_IF */
Zaitsev 10:41552d038a69 1329 #define EBI_IF_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag */
Zaitsev 10:41552d038a69 1330 #define _EBI_IF_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */
Zaitsev 10:41552d038a69 1331 #define _EBI_IF_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */
Zaitsev 10:41552d038a69 1332 #define _EBI_IF_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */
Zaitsev 10:41552d038a69 1333 #define EBI_IF_VSYNC_DEFAULT (_EBI_IF_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IF */
Zaitsev 10:41552d038a69 1334 #define EBI_IF_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag */
Zaitsev 10:41552d038a69 1335 #define _EBI_IF_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */
Zaitsev 10:41552d038a69 1336 #define _EBI_IF_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */
Zaitsev 10:41552d038a69 1337 #define _EBI_IF_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */
Zaitsev 10:41552d038a69 1338 #define EBI_IF_HSYNC_DEFAULT (_EBI_IF_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IF */
Zaitsev 10:41552d038a69 1339 #define EBI_IF_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag */
Zaitsev 10:41552d038a69 1340 #define _EBI_IF_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */
Zaitsev 10:41552d038a69 1341 #define _EBI_IF_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */
Zaitsev 10:41552d038a69 1342 #define _EBI_IF_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */
Zaitsev 10:41552d038a69 1343 #define EBI_IF_VBPORCH_DEFAULT (_EBI_IF_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IF */
Zaitsev 10:41552d038a69 1344 #define EBI_IF_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag */
Zaitsev 10:41552d038a69 1345 #define _EBI_IF_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */
Zaitsev 10:41552d038a69 1346 #define _EBI_IF_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */
Zaitsev 10:41552d038a69 1347 #define _EBI_IF_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */
Zaitsev 10:41552d038a69 1348 #define EBI_IF_VFPORCH_DEFAULT (_EBI_IF_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IF */
Zaitsev 10:41552d038a69 1349 #define EBI_IF_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag */
Zaitsev 10:41552d038a69 1350 #define _EBI_IF_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */
Zaitsev 10:41552d038a69 1351 #define _EBI_IF_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */
Zaitsev 10:41552d038a69 1352 #define _EBI_IF_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */
Zaitsev 10:41552d038a69 1353 #define EBI_IF_DDEMPTY_DEFAULT (_EBI_IF_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IF */
Zaitsev 10:41552d038a69 1354 #define EBI_IF_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag */
Zaitsev 10:41552d038a69 1355 #define _EBI_IF_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */
Zaitsev 10:41552d038a69 1356 #define _EBI_IF_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */
Zaitsev 10:41552d038a69 1357 #define _EBI_IF_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */
Zaitsev 10:41552d038a69 1358 #define EBI_IF_DDJIT_DEFAULT (_EBI_IF_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IF */
Zaitsev 10:41552d038a69 1359
Zaitsev 10:41552d038a69 1360 /* Bit fields for EBI IFS */
Zaitsev 10:41552d038a69 1361 #define _EBI_IFS_RESETVALUE 0x00000000UL /**< Default value for EBI_IFS */
Zaitsev 10:41552d038a69 1362 #define _EBI_IFS_MASK 0x0000003FUL /**< Mask for EBI_IFS */
Zaitsev 10:41552d038a69 1363 #define EBI_IFS_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag Set */
Zaitsev 10:41552d038a69 1364 #define _EBI_IFS_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */
Zaitsev 10:41552d038a69 1365 #define _EBI_IFS_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */
Zaitsev 10:41552d038a69 1366 #define _EBI_IFS_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */
Zaitsev 10:41552d038a69 1367 #define EBI_IFS_VSYNC_DEFAULT (_EBI_IFS_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IFS */
Zaitsev 10:41552d038a69 1368 #define EBI_IFS_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag Set */
Zaitsev 10:41552d038a69 1369 #define _EBI_IFS_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */
Zaitsev 10:41552d038a69 1370 #define _EBI_IFS_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */
Zaitsev 10:41552d038a69 1371 #define _EBI_IFS_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */
Zaitsev 10:41552d038a69 1372 #define EBI_IFS_HSYNC_DEFAULT (_EBI_IFS_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IFS */
Zaitsev 10:41552d038a69 1373 #define EBI_IFS_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag Set */
Zaitsev 10:41552d038a69 1374 #define _EBI_IFS_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */
Zaitsev 10:41552d038a69 1375 #define _EBI_IFS_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */
Zaitsev 10:41552d038a69 1376 #define _EBI_IFS_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */
Zaitsev 10:41552d038a69 1377 #define EBI_IFS_VBPORCH_DEFAULT (_EBI_IFS_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IFS */
Zaitsev 10:41552d038a69 1378 #define EBI_IFS_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag Set */
Zaitsev 10:41552d038a69 1379 #define _EBI_IFS_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */
Zaitsev 10:41552d038a69 1380 #define _EBI_IFS_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */
Zaitsev 10:41552d038a69 1381 #define _EBI_IFS_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */
Zaitsev 10:41552d038a69 1382 #define EBI_IFS_VFPORCH_DEFAULT (_EBI_IFS_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IFS */
Zaitsev 10:41552d038a69 1383 #define EBI_IFS_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag Set */
Zaitsev 10:41552d038a69 1384 #define _EBI_IFS_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */
Zaitsev 10:41552d038a69 1385 #define _EBI_IFS_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */
Zaitsev 10:41552d038a69 1386 #define _EBI_IFS_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */
Zaitsev 10:41552d038a69 1387 #define EBI_IFS_DDEMPTY_DEFAULT (_EBI_IFS_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IFS */
Zaitsev 10:41552d038a69 1388 #define EBI_IFS_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag Set */
Zaitsev 10:41552d038a69 1389 #define _EBI_IFS_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */
Zaitsev 10:41552d038a69 1390 #define _EBI_IFS_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */
Zaitsev 10:41552d038a69 1391 #define _EBI_IFS_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */
Zaitsev 10:41552d038a69 1392 #define EBI_IFS_DDJIT_DEFAULT (_EBI_IFS_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IFS */
Zaitsev 10:41552d038a69 1393
Zaitsev 10:41552d038a69 1394 /* Bit fields for EBI IFC */
Zaitsev 10:41552d038a69 1395 #define _EBI_IFC_RESETVALUE 0x00000000UL /**< Default value for EBI_IFC */
Zaitsev 10:41552d038a69 1396 #define _EBI_IFC_MASK 0x0000003FUL /**< Mask for EBI_IFC */
Zaitsev 10:41552d038a69 1397 #define EBI_IFC_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag Clear */
Zaitsev 10:41552d038a69 1398 #define _EBI_IFC_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */
Zaitsev 10:41552d038a69 1399 #define _EBI_IFC_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */
Zaitsev 10:41552d038a69 1400 #define _EBI_IFC_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */
Zaitsev 10:41552d038a69 1401 #define EBI_IFC_VSYNC_DEFAULT (_EBI_IFC_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IFC */
Zaitsev 10:41552d038a69 1402 #define EBI_IFC_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag Clear */
Zaitsev 10:41552d038a69 1403 #define _EBI_IFC_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */
Zaitsev 10:41552d038a69 1404 #define _EBI_IFC_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */
Zaitsev 10:41552d038a69 1405 #define _EBI_IFC_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */
Zaitsev 10:41552d038a69 1406 #define EBI_IFC_HSYNC_DEFAULT (_EBI_IFC_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IFC */
Zaitsev 10:41552d038a69 1407 #define EBI_IFC_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag Clear */
Zaitsev 10:41552d038a69 1408 #define _EBI_IFC_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */
Zaitsev 10:41552d038a69 1409 #define _EBI_IFC_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */
Zaitsev 10:41552d038a69 1410 #define _EBI_IFC_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */
Zaitsev 10:41552d038a69 1411 #define EBI_IFC_VBPORCH_DEFAULT (_EBI_IFC_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IFC */
Zaitsev 10:41552d038a69 1412 #define EBI_IFC_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag Clear */
Zaitsev 10:41552d038a69 1413 #define _EBI_IFC_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */
Zaitsev 10:41552d038a69 1414 #define _EBI_IFC_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */
Zaitsev 10:41552d038a69 1415 #define _EBI_IFC_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */
Zaitsev 10:41552d038a69 1416 #define EBI_IFC_VFPORCH_DEFAULT (_EBI_IFC_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IFC */
Zaitsev 10:41552d038a69 1417 #define EBI_IFC_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag Clear */
Zaitsev 10:41552d038a69 1418 #define _EBI_IFC_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */
Zaitsev 10:41552d038a69 1419 #define _EBI_IFC_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */
Zaitsev 10:41552d038a69 1420 #define _EBI_IFC_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */
Zaitsev 10:41552d038a69 1421 #define EBI_IFC_DDEMPTY_DEFAULT (_EBI_IFC_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IFC */
Zaitsev 10:41552d038a69 1422 #define EBI_IFC_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag Clear */
Zaitsev 10:41552d038a69 1423 #define _EBI_IFC_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */
Zaitsev 10:41552d038a69 1424 #define _EBI_IFC_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */
Zaitsev 10:41552d038a69 1425 #define _EBI_IFC_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */
Zaitsev 10:41552d038a69 1426 #define EBI_IFC_DDJIT_DEFAULT (_EBI_IFC_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IFC */
Zaitsev 10:41552d038a69 1427
Zaitsev 10:41552d038a69 1428 /* Bit fields for EBI IEN */
Zaitsev 10:41552d038a69 1429 #define _EBI_IEN_RESETVALUE 0x00000000UL /**< Default value for EBI_IEN */
Zaitsev 10:41552d038a69 1430 #define _EBI_IEN_MASK 0x0000003FUL /**< Mask for EBI_IEN */
Zaitsev 10:41552d038a69 1431 #define EBI_IEN_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Enable */
Zaitsev 10:41552d038a69 1432 #define _EBI_IEN_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */
Zaitsev 10:41552d038a69 1433 #define _EBI_IEN_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */
Zaitsev 10:41552d038a69 1434 #define _EBI_IEN_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */
Zaitsev 10:41552d038a69 1435 #define EBI_IEN_VSYNC_DEFAULT (_EBI_IEN_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IEN */
Zaitsev 10:41552d038a69 1436 #define EBI_IEN_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Enable */
Zaitsev 10:41552d038a69 1437 #define _EBI_IEN_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */
Zaitsev 10:41552d038a69 1438 #define _EBI_IEN_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */
Zaitsev 10:41552d038a69 1439 #define _EBI_IEN_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */
Zaitsev 10:41552d038a69 1440 #define EBI_IEN_HSYNC_DEFAULT (_EBI_IEN_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IEN */
Zaitsev 10:41552d038a69 1441 #define EBI_IEN_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Enable */
Zaitsev 10:41552d038a69 1442 #define _EBI_IEN_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */
Zaitsev 10:41552d038a69 1443 #define _EBI_IEN_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */
Zaitsev 10:41552d038a69 1444 #define _EBI_IEN_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */
Zaitsev 10:41552d038a69 1445 #define EBI_IEN_VBPORCH_DEFAULT (_EBI_IEN_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IEN */
Zaitsev 10:41552d038a69 1446 #define EBI_IEN_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Enable */
Zaitsev 10:41552d038a69 1447 #define _EBI_IEN_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */
Zaitsev 10:41552d038a69 1448 #define _EBI_IEN_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */
Zaitsev 10:41552d038a69 1449 #define _EBI_IEN_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */
Zaitsev 10:41552d038a69 1450 #define EBI_IEN_VFPORCH_DEFAULT (_EBI_IEN_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IEN */
Zaitsev 10:41552d038a69 1451 #define EBI_IEN_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Enable */
Zaitsev 10:41552d038a69 1452 #define _EBI_IEN_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */
Zaitsev 10:41552d038a69 1453 #define _EBI_IEN_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */
Zaitsev 10:41552d038a69 1454 #define _EBI_IEN_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */
Zaitsev 10:41552d038a69 1455 #define EBI_IEN_DDEMPTY_DEFAULT (_EBI_IEN_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IEN */
Zaitsev 10:41552d038a69 1456 #define EBI_IEN_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Enable */
Zaitsev 10:41552d038a69 1457 #define _EBI_IEN_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */
Zaitsev 10:41552d038a69 1458 #define _EBI_IEN_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */
Zaitsev 10:41552d038a69 1459 #define _EBI_IEN_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */
Zaitsev 10:41552d038a69 1460 #define EBI_IEN_DDJIT_DEFAULT (_EBI_IEN_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IEN */
Zaitsev 10:41552d038a69 1461
Zaitsev 10:41552d038a69 1462 /** @} End of group EFM32WG_EBI */
Zaitsev 10:41552d038a69 1463 /** @} End of group Parts */
Zaitsev 10:41552d038a69 1464