Mateusz Kowalik / Application_danix

Fork of Application by Daniel Sygut

Committer:
Zaitsev
Date:
Tue Jan 10 20:42:26 2017 +0000
Revision:
10:41552d038a69
USB Serial bi-directional bridge

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zaitsev 10:41552d038a69 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
Zaitsev 10:41552d038a69 2 *
Zaitsev 10:41552d038a69 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
Zaitsev 10:41552d038a69 4 * and associated documentation files (the "Software"), to deal in the Software without
Zaitsev 10:41552d038a69 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
Zaitsev 10:41552d038a69 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
Zaitsev 10:41552d038a69 7 * Software is furnished to do so, subject to the following conditions:
Zaitsev 10:41552d038a69 8 *
Zaitsev 10:41552d038a69 9 * The above copyright notice and this permission notice shall be included in all copies or
Zaitsev 10:41552d038a69 10 * substantial portions of the Software.
Zaitsev 10:41552d038a69 11 *
Zaitsev 10:41552d038a69 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
Zaitsev 10:41552d038a69 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
Zaitsev 10:41552d038a69 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
Zaitsev 10:41552d038a69 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Zaitsev 10:41552d038a69 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Zaitsev 10:41552d038a69 17 */
Zaitsev 10:41552d038a69 18
Zaitsev 10:41552d038a69 19 #if defined(TARGET_LPC11UXX) || defined(TARGET_LPC11U6X) || defined(TARGET_LPC1347) || defined(TARGET_LPC1549)
Zaitsev 10:41552d038a69 20
Zaitsev 10:41552d038a69 21 #if defined(TARGET_LPC1347) || defined(TARGET_LPC1549)
Zaitsev 10:41552d038a69 22 #define USB_IRQ USB_IRQ_IRQn
Zaitsev 10:41552d038a69 23 #else
Zaitsev 10:41552d038a69 24 #define USB_IRQ USB_IRQn
Zaitsev 10:41552d038a69 25 #endif
Zaitsev 10:41552d038a69 26
Zaitsev 10:41552d038a69 27 #include "USBHAL.h"
Zaitsev 10:41552d038a69 28
Zaitsev 10:41552d038a69 29 USBHAL * USBHAL::instance;
Zaitsev 10:41552d038a69 30 #if defined(TARGET_LPC1549)
Zaitsev 10:41552d038a69 31 static uint8_t usbmem[2048] __attribute__((aligned(2048)));
Zaitsev 10:41552d038a69 32 #endif
Zaitsev 10:41552d038a69 33
Zaitsev 10:41552d038a69 34 // Valid physical endpoint numbers are 0 to (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
Zaitsev 10:41552d038a69 35 #define LAST_PHYSICAL_ENDPOINT (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
Zaitsev 10:41552d038a69 36
Zaitsev 10:41552d038a69 37 // Convert physical endpoint number to register bit
Zaitsev 10:41552d038a69 38 #define EP(endpoint) (1UL<<endpoint)
Zaitsev 10:41552d038a69 39
Zaitsev 10:41552d038a69 40 // Convert physical to logical
Zaitsev 10:41552d038a69 41 #define PHY_TO_LOG(endpoint) ((endpoint)>>1)
Zaitsev 10:41552d038a69 42
Zaitsev 10:41552d038a69 43 // Get endpoint direction
Zaitsev 10:41552d038a69 44 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
Zaitsev 10:41552d038a69 45 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
Zaitsev 10:41552d038a69 46
Zaitsev 10:41552d038a69 47 // USB RAM
Zaitsev 10:41552d038a69 48 #if defined(TARGET_LPC1549)
Zaitsev 10:41552d038a69 49 #define USB_RAM_START ((uint32_t)usbmem)
Zaitsev 10:41552d038a69 50 #define USB_RAM_SIZE sizeof(usbmem)
Zaitsev 10:41552d038a69 51 #else
Zaitsev 10:41552d038a69 52 #define USB_RAM_START (0x20004000)
Zaitsev 10:41552d038a69 53 #define USB_RAM_SIZE (0x00000800)
Zaitsev 10:41552d038a69 54 #endif
Zaitsev 10:41552d038a69 55
Zaitsev 10:41552d038a69 56 // SYSAHBCLKCTRL
Zaitsev 10:41552d038a69 57 #if defined(TARGET_LPC1549)
Zaitsev 10:41552d038a69 58 #define CLK_USB (1UL<<23)
Zaitsev 10:41552d038a69 59 #else
Zaitsev 10:41552d038a69 60 #define CLK_USB (1UL<<14)
Zaitsev 10:41552d038a69 61 #define CLK_USBRAM (1UL<<27)
Zaitsev 10:41552d038a69 62 #endif
Zaitsev 10:41552d038a69 63
Zaitsev 10:41552d038a69 64 // USB Information register
Zaitsev 10:41552d038a69 65 #define FRAME_NR(a) ((a) & 0x7ff) // Frame number
Zaitsev 10:41552d038a69 66
Zaitsev 10:41552d038a69 67 // USB Device Command/Status register
Zaitsev 10:41552d038a69 68 #define DEV_ADDR_MASK (0x7f) // Device address
Zaitsev 10:41552d038a69 69 #define DEV_ADDR(a) ((a) & DEV_ADDR_MASK)
Zaitsev 10:41552d038a69 70 #define DEV_EN (1UL<<7) // Device enable
Zaitsev 10:41552d038a69 71 #define SETUP (1UL<<8) // SETUP token received
Zaitsev 10:41552d038a69 72 #define PLL_ON (1UL<<9) // PLL enabled in suspend
Zaitsev 10:41552d038a69 73 #define DCON (1UL<<16) // Device status - connect
Zaitsev 10:41552d038a69 74 #define DSUS (1UL<<17) // Device status - suspend
Zaitsev 10:41552d038a69 75 #define DCON_C (1UL<<24) // Connect change
Zaitsev 10:41552d038a69 76 #define DSUS_C (1UL<<25) // Suspend change
Zaitsev 10:41552d038a69 77 #define DRES_C (1UL<<26) // Reset change
Zaitsev 10:41552d038a69 78 #define VBUSDEBOUNCED (1UL<<28) // Vbus detected
Zaitsev 10:41552d038a69 79
Zaitsev 10:41552d038a69 80 // Endpoint Command/Status list
Zaitsev 10:41552d038a69 81 #define CMDSTS_A (1UL<<31) // Active
Zaitsev 10:41552d038a69 82 #define CMDSTS_D (1UL<<30) // Disable
Zaitsev 10:41552d038a69 83 #define CMDSTS_S (1UL<<29) // Stall
Zaitsev 10:41552d038a69 84 #define CMDSTS_TR (1UL<<28) // Toggle Reset
Zaitsev 10:41552d038a69 85 #define CMDSTS_RF (1UL<<27) // Rate Feedback mode
Zaitsev 10:41552d038a69 86 #define CMDSTS_TV (1UL<<27) // Toggle Value
Zaitsev 10:41552d038a69 87 #define CMDSTS_T (1UL<<26) // Endpoint Type
Zaitsev 10:41552d038a69 88 #define CMDSTS_NBYTES(n) (((n)&0x3ff)<<16) // Number of bytes
Zaitsev 10:41552d038a69 89 #define CMDSTS_ADDRESS_OFFSET(a) (((a)>>6)&0xffff) // Buffer start address
Zaitsev 10:41552d038a69 90
Zaitsev 10:41552d038a69 91 #define BYTES_REMAINING(s) (((s)>>16)&0x3ff) // Bytes remaining after transfer
Zaitsev 10:41552d038a69 92
Zaitsev 10:41552d038a69 93 // USB Non-endpoint interrupt sources
Zaitsev 10:41552d038a69 94 #define FRAME_INT (1UL<<30)
Zaitsev 10:41552d038a69 95 #define DEV_INT (1UL<<31)
Zaitsev 10:41552d038a69 96
Zaitsev 10:41552d038a69 97 static volatile int epComplete = 0;
Zaitsev 10:41552d038a69 98
Zaitsev 10:41552d038a69 99 // One entry for a double-buffered logical endpoint in the endpoint
Zaitsev 10:41552d038a69 100 // command/status list. Endpoint 0 is single buffered, out[1] is used
Zaitsev 10:41552d038a69 101 // for the SETUP packet and in[1] is not used
Zaitsev 10:41552d038a69 102 typedef struct {
Zaitsev 10:41552d038a69 103 uint32_t out[2];
Zaitsev 10:41552d038a69 104 uint32_t in[2];
Zaitsev 10:41552d038a69 105 } PACKED EP_COMMAND_STATUS;
Zaitsev 10:41552d038a69 106
Zaitsev 10:41552d038a69 107 typedef struct {
Zaitsev 10:41552d038a69 108 uint8_t out[MAX_PACKET_SIZE_EP0];
Zaitsev 10:41552d038a69 109 uint8_t in[MAX_PACKET_SIZE_EP0];
Zaitsev 10:41552d038a69 110 uint8_t setup[SETUP_PACKET_SIZE];
Zaitsev 10:41552d038a69 111 } PACKED CONTROL_TRANSFER;
Zaitsev 10:41552d038a69 112
Zaitsev 10:41552d038a69 113 typedef struct {
Zaitsev 10:41552d038a69 114 uint32_t maxPacket;
Zaitsev 10:41552d038a69 115 uint32_t buffer[2];
Zaitsev 10:41552d038a69 116 uint32_t options;
Zaitsev 10:41552d038a69 117 } PACKED EP_STATE;
Zaitsev 10:41552d038a69 118
Zaitsev 10:41552d038a69 119 static volatile EP_STATE endpointState[NUMBER_OF_PHYSICAL_ENDPOINTS];
Zaitsev 10:41552d038a69 120
Zaitsev 10:41552d038a69 121 // Pointer to the endpoint command/status list
Zaitsev 10:41552d038a69 122 static EP_COMMAND_STATUS *ep = NULL;
Zaitsev 10:41552d038a69 123
Zaitsev 10:41552d038a69 124 // Pointer to endpoint 0 data (IN/OUT and SETUP)
Zaitsev 10:41552d038a69 125 static CONTROL_TRANSFER *ct = NULL;
Zaitsev 10:41552d038a69 126
Zaitsev 10:41552d038a69 127 // Shadow DEVCMDSTAT register to avoid accidentally clearing flags or
Zaitsev 10:41552d038a69 128 // initiating a remote wakeup event.
Zaitsev 10:41552d038a69 129 static volatile uint32_t devCmdStat;
Zaitsev 10:41552d038a69 130
Zaitsev 10:41552d038a69 131 // Pointers used to allocate USB RAM
Zaitsev 10:41552d038a69 132 static uint32_t usbRamPtr = USB_RAM_START;
Zaitsev 10:41552d038a69 133 static uint32_t epRamPtr = 0; // Buffers for endpoints > 0 start here
Zaitsev 10:41552d038a69 134
Zaitsev 10:41552d038a69 135 #define ROUND_UP_TO_MULTIPLE(x, m) ((((x)+((m)-1))/(m))*(m))
Zaitsev 10:41552d038a69 136
Zaitsev 10:41552d038a69 137 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size);
Zaitsev 10:41552d038a69 138 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size) {
Zaitsev 10:41552d038a69 139 if (size > 0) {
Zaitsev 10:41552d038a69 140 do {
Zaitsev 10:41552d038a69 141 *dst++ = *src++;
Zaitsev 10:41552d038a69 142 } while (--size > 0);
Zaitsev 10:41552d038a69 143 }
Zaitsev 10:41552d038a69 144 }
Zaitsev 10:41552d038a69 145
Zaitsev 10:41552d038a69 146
Zaitsev 10:41552d038a69 147 USBHAL::USBHAL(void) {
Zaitsev 10:41552d038a69 148 NVIC_DisableIRQ(USB_IRQ);
Zaitsev 10:41552d038a69 149
Zaitsev 10:41552d038a69 150 // fill in callback array
Zaitsev 10:41552d038a69 151 epCallback[0] = &USBHAL::EP1_OUT_callback;
Zaitsev 10:41552d038a69 152 epCallback[1] = &USBHAL::EP1_IN_callback;
Zaitsev 10:41552d038a69 153 epCallback[2] = &USBHAL::EP2_OUT_callback;
Zaitsev 10:41552d038a69 154 epCallback[3] = &USBHAL::EP2_IN_callback;
Zaitsev 10:41552d038a69 155 epCallback[4] = &USBHAL::EP3_OUT_callback;
Zaitsev 10:41552d038a69 156 epCallback[5] = &USBHAL::EP3_IN_callback;
Zaitsev 10:41552d038a69 157 epCallback[6] = &USBHAL::EP4_OUT_callback;
Zaitsev 10:41552d038a69 158 epCallback[7] = &USBHAL::EP4_IN_callback;
Zaitsev 10:41552d038a69 159
Zaitsev 10:41552d038a69 160 #if defined(TARGET_LPC1549)
Zaitsev 10:41552d038a69 161 /* Set USB PLL input to system oscillator */
Zaitsev 10:41552d038a69 162 LPC_SYSCON->USBPLLCLKSEL = 0x01;
Zaitsev 10:41552d038a69 163
Zaitsev 10:41552d038a69 164 /* Setup USB PLL (FCLKIN = 12MHz) * 4 = 48MHz
Zaitsev 10:41552d038a69 165 MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
Zaitsev 10:41552d038a69 166 FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
Zaitsev 10:41552d038a69 167 FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Zaitsev 10:41552d038a69 168 LPC_SYSCON->USBPLLCTRL = (0x3 | (1UL << 6));
Zaitsev 10:41552d038a69 169
Zaitsev 10:41552d038a69 170 /* Powerup USB PLL */
Zaitsev 10:41552d038a69 171 LPC_SYSCON->PDRUNCFG &= ~(CLK_USB);
Zaitsev 10:41552d038a69 172
Zaitsev 10:41552d038a69 173 /* Wait for PLL to lock */
Zaitsev 10:41552d038a69 174 while(!(LPC_SYSCON->USBPLLSTAT & 0x01));
Zaitsev 10:41552d038a69 175
Zaitsev 10:41552d038a69 176 /* enable USB main clock */
Zaitsev 10:41552d038a69 177 LPC_SYSCON->USBCLKSEL = 0x02;
Zaitsev 10:41552d038a69 178 LPC_SYSCON->USBCLKDIV = 1;
Zaitsev 10:41552d038a69 179
Zaitsev 10:41552d038a69 180 /* Enable AHB clock to the USB block. */
Zaitsev 10:41552d038a69 181 LPC_SYSCON->SYSAHBCLKCTRL1 |= CLK_USB;
Zaitsev 10:41552d038a69 182
Zaitsev 10:41552d038a69 183 /* power UP USB Phy */
Zaitsev 10:41552d038a69 184 LPC_SYSCON->PDRUNCFG &= ~(1UL << 9);
Zaitsev 10:41552d038a69 185
Zaitsev 10:41552d038a69 186 /* Reset USB block */
Zaitsev 10:41552d038a69 187 LPC_SYSCON->PRESETCTRL1 |= (CLK_USB);
Zaitsev 10:41552d038a69 188 LPC_SYSCON->PRESETCTRL1 &= ~(CLK_USB);
Zaitsev 10:41552d038a69 189
Zaitsev 10:41552d038a69 190 #else
Zaitsev 10:41552d038a69 191 #if defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501)
Zaitsev 10:41552d038a69 192 // USB_VBUS input with pull-down
Zaitsev 10:41552d038a69 193 LPC_IOCON->PIO0_3 = 0x00000009;
Zaitsev 10:41552d038a69 194 #endif
Zaitsev 10:41552d038a69 195
Zaitsev 10:41552d038a69 196 // nUSB_CONNECT output
Zaitsev 10:41552d038a69 197 LPC_IOCON->PIO0_6 = 0x00000001;
Zaitsev 10:41552d038a69 198
Zaitsev 10:41552d038a69 199 // Enable clocks (USB registers, USB RAM)
Zaitsev 10:41552d038a69 200 LPC_SYSCON->SYSAHBCLKCTRL |= CLK_USB | CLK_USBRAM;
Zaitsev 10:41552d038a69 201
Zaitsev 10:41552d038a69 202 // Ensure device disconnected (DCON not set)
Zaitsev 10:41552d038a69 203 LPC_USB->DEVCMDSTAT = 0;
Zaitsev 10:41552d038a69 204 #endif
Zaitsev 10:41552d038a69 205 // to ensure that the USB host sees the device as
Zaitsev 10:41552d038a69 206 // disconnected if the target CPU is reset.
Zaitsev 10:41552d038a69 207 wait(0.3);
Zaitsev 10:41552d038a69 208
Zaitsev 10:41552d038a69 209 // Reserve space in USB RAM for endpoint command/status list
Zaitsev 10:41552d038a69 210 // Must be 256 byte aligned
Zaitsev 10:41552d038a69 211 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 256);
Zaitsev 10:41552d038a69 212 ep = (EP_COMMAND_STATUS *)usbRamPtr;
Zaitsev 10:41552d038a69 213 usbRamPtr += (sizeof(EP_COMMAND_STATUS) * NUMBER_OF_LOGICAL_ENDPOINTS);
Zaitsev 10:41552d038a69 214 LPC_USB->EPLISTSTART = (uint32_t)(ep) & 0xffffff00;
Zaitsev 10:41552d038a69 215
Zaitsev 10:41552d038a69 216 // Reserve space in USB RAM for Endpoint 0
Zaitsev 10:41552d038a69 217 // Must be 64 byte aligned
Zaitsev 10:41552d038a69 218 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 64);
Zaitsev 10:41552d038a69 219 ct = (CONTROL_TRANSFER *)usbRamPtr;
Zaitsev 10:41552d038a69 220 usbRamPtr += sizeof(CONTROL_TRANSFER);
Zaitsev 10:41552d038a69 221 LPC_USB->DATABUFSTART =(uint32_t)(ct) & 0xffc00000;
Zaitsev 10:41552d038a69 222
Zaitsev 10:41552d038a69 223 // Setup command/status list for EP0
Zaitsev 10:41552d038a69 224 ep[0].out[0] = 0;
Zaitsev 10:41552d038a69 225 ep[0].in[0] = 0;
Zaitsev 10:41552d038a69 226 ep[0].out[1] = CMDSTS_ADDRESS_OFFSET((uint32_t)ct->setup);
Zaitsev 10:41552d038a69 227
Zaitsev 10:41552d038a69 228 // Route all interrupts to IRQ, some can be routed to
Zaitsev 10:41552d038a69 229 // USB_FIQ if you wish.
Zaitsev 10:41552d038a69 230 LPC_USB->INTROUTING = 0;
Zaitsev 10:41552d038a69 231
Zaitsev 10:41552d038a69 232 // Set device address 0, enable USB device, no remote wakeup
Zaitsev 10:41552d038a69 233 devCmdStat = DEV_ADDR(0) | DEV_EN | DSUS;
Zaitsev 10:41552d038a69 234 LPC_USB->DEVCMDSTAT = devCmdStat;
Zaitsev 10:41552d038a69 235
Zaitsev 10:41552d038a69 236 // Enable interrupts for device events and EP0
Zaitsev 10:41552d038a69 237 LPC_USB->INTEN = DEV_INT | EP(EP0IN) | EP(EP0OUT) | FRAME_INT;
Zaitsev 10:41552d038a69 238 instance = this;
Zaitsev 10:41552d038a69 239
Zaitsev 10:41552d038a69 240 //attach IRQ handler and enable interrupts
Zaitsev 10:41552d038a69 241 NVIC_SetVector(USB_IRQ, (uint32_t)&_usbisr);
Zaitsev 10:41552d038a69 242 }
Zaitsev 10:41552d038a69 243
Zaitsev 10:41552d038a69 244 USBHAL::~USBHAL(void) {
Zaitsev 10:41552d038a69 245 // Ensure device disconnected (DCON not set)
Zaitsev 10:41552d038a69 246 LPC_USB->DEVCMDSTAT = 0;
Zaitsev 10:41552d038a69 247 // Disable USB interrupts
Zaitsev 10:41552d038a69 248 NVIC_DisableIRQ(USB_IRQ);
Zaitsev 10:41552d038a69 249 }
Zaitsev 10:41552d038a69 250
Zaitsev 10:41552d038a69 251 void USBHAL::connect(void) {
Zaitsev 10:41552d038a69 252 NVIC_EnableIRQ(USB_IRQ);
Zaitsev 10:41552d038a69 253 devCmdStat |= DCON;
Zaitsev 10:41552d038a69 254 LPC_USB->DEVCMDSTAT = devCmdStat;
Zaitsev 10:41552d038a69 255 }
Zaitsev 10:41552d038a69 256
Zaitsev 10:41552d038a69 257 void USBHAL::disconnect(void) {
Zaitsev 10:41552d038a69 258 NVIC_DisableIRQ(USB_IRQ);
Zaitsev 10:41552d038a69 259 devCmdStat &= ~DCON;
Zaitsev 10:41552d038a69 260 LPC_USB->DEVCMDSTAT = devCmdStat;
Zaitsev 10:41552d038a69 261 }
Zaitsev 10:41552d038a69 262
Zaitsev 10:41552d038a69 263 void USBHAL::configureDevice(void) {
Zaitsev 10:41552d038a69 264 // Not required
Zaitsev 10:41552d038a69 265 }
Zaitsev 10:41552d038a69 266
Zaitsev 10:41552d038a69 267 void USBHAL::unconfigureDevice(void) {
Zaitsev 10:41552d038a69 268 // Not required
Zaitsev 10:41552d038a69 269 }
Zaitsev 10:41552d038a69 270
Zaitsev 10:41552d038a69 271 void USBHAL::EP0setup(uint8_t *buffer) {
Zaitsev 10:41552d038a69 272 // Copy setup packet data
Zaitsev 10:41552d038a69 273 USBMemCopy(buffer, ct->setup, SETUP_PACKET_SIZE);
Zaitsev 10:41552d038a69 274 }
Zaitsev 10:41552d038a69 275
Zaitsev 10:41552d038a69 276 void USBHAL::EP0read(void) {
Zaitsev 10:41552d038a69 277 // Start an endpoint 0 read
Zaitsev 10:41552d038a69 278
Zaitsev 10:41552d038a69 279 // The USB ISR will call USBDevice_EP0out() when a packet has been read,
Zaitsev 10:41552d038a69 280 // the USBDevice layer then calls USBBusInterface_EP0getReadResult() to
Zaitsev 10:41552d038a69 281 // read the data.
Zaitsev 10:41552d038a69 282
Zaitsev 10:41552d038a69 283 ep[0].out[0] = CMDSTS_A |CMDSTS_NBYTES(MAX_PACKET_SIZE_EP0) \
Zaitsev 10:41552d038a69 284 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out);
Zaitsev 10:41552d038a69 285 }
Zaitsev 10:41552d038a69 286
Zaitsev 10:41552d038a69 287 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
Zaitsev 10:41552d038a69 288 // Complete an endpoint 0 read
Zaitsev 10:41552d038a69 289 uint32_t bytesRead;
Zaitsev 10:41552d038a69 290
Zaitsev 10:41552d038a69 291 // Find how many bytes were read
Zaitsev 10:41552d038a69 292 bytesRead = MAX_PACKET_SIZE_EP0 - BYTES_REMAINING(ep[0].out[0]);
Zaitsev 10:41552d038a69 293
Zaitsev 10:41552d038a69 294 // Copy data
Zaitsev 10:41552d038a69 295 USBMemCopy(buffer, ct->out, bytesRead);
Zaitsev 10:41552d038a69 296 return bytesRead;
Zaitsev 10:41552d038a69 297 }
Zaitsev 10:41552d038a69 298
Zaitsev 10:41552d038a69 299
Zaitsev 10:41552d038a69 300 void USBHAL::EP0readStage(void) {
Zaitsev 10:41552d038a69 301 // Not required
Zaitsev 10:41552d038a69 302 }
Zaitsev 10:41552d038a69 303
Zaitsev 10:41552d038a69 304 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
Zaitsev 10:41552d038a69 305 // Start and endpoint 0 write
Zaitsev 10:41552d038a69 306
Zaitsev 10:41552d038a69 307 // The USB ISR will call USBDevice_EP0in() when the data has
Zaitsev 10:41552d038a69 308 // been written, the USBDevice layer then calls
Zaitsev 10:41552d038a69 309 // USBBusInterface_EP0getWriteResult() to complete the transaction.
Zaitsev 10:41552d038a69 310
Zaitsev 10:41552d038a69 311 // Copy data
Zaitsev 10:41552d038a69 312 USBMemCopy(ct->in, buffer, size);
Zaitsev 10:41552d038a69 313
Zaitsev 10:41552d038a69 314 // Start transfer
Zaitsev 10:41552d038a69 315 ep[0].in[0] = CMDSTS_A | CMDSTS_NBYTES(size) \
Zaitsev 10:41552d038a69 316 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->in);
Zaitsev 10:41552d038a69 317 }
Zaitsev 10:41552d038a69 318
Zaitsev 10:41552d038a69 319
Zaitsev 10:41552d038a69 320 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
Zaitsev 10:41552d038a69 321 uint8_t bf = 0;
Zaitsev 10:41552d038a69 322 uint32_t flags = 0;
Zaitsev 10:41552d038a69 323
Zaitsev 10:41552d038a69 324 //check which buffer must be filled
Zaitsev 10:41552d038a69 325 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Zaitsev 10:41552d038a69 326 // Double buffered
Zaitsev 10:41552d038a69 327 if (LPC_USB->EPINUSE & EP(endpoint)) {
Zaitsev 10:41552d038a69 328 bf = 1;
Zaitsev 10:41552d038a69 329 } else {
Zaitsev 10:41552d038a69 330 bf = 0;
Zaitsev 10:41552d038a69 331 }
Zaitsev 10:41552d038a69 332 }
Zaitsev 10:41552d038a69 333
Zaitsev 10:41552d038a69 334 // if isochronous endpoint, T = 1
Zaitsev 10:41552d038a69 335 if(endpointState[endpoint].options & ISOCHRONOUS)
Zaitsev 10:41552d038a69 336 {
Zaitsev 10:41552d038a69 337 flags |= CMDSTS_T;
Zaitsev 10:41552d038a69 338 }
Zaitsev 10:41552d038a69 339
Zaitsev 10:41552d038a69 340 //Active the endpoint for reading
Zaitsev 10:41552d038a69 341 ep[PHY_TO_LOG(endpoint)].out[bf] = CMDSTS_A | CMDSTS_NBYTES(maximumSize) \
Zaitsev 10:41552d038a69 342 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out) | flags;
Zaitsev 10:41552d038a69 343 return EP_PENDING;
Zaitsev 10:41552d038a69 344 }
Zaitsev 10:41552d038a69 345
Zaitsev 10:41552d038a69 346 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead) {
Zaitsev 10:41552d038a69 347
Zaitsev 10:41552d038a69 348 uint8_t bf = 0;
Zaitsev 10:41552d038a69 349
Zaitsev 10:41552d038a69 350 if (!(epComplete & EP(endpoint)))
Zaitsev 10:41552d038a69 351 return EP_PENDING;
Zaitsev 10:41552d038a69 352 else {
Zaitsev 10:41552d038a69 353 epComplete &= ~EP(endpoint);
Zaitsev 10:41552d038a69 354
Zaitsev 10:41552d038a69 355 //check which buffer has been filled
Zaitsev 10:41552d038a69 356 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Zaitsev 10:41552d038a69 357 // Double buffered (here we read the previous buffer which was used)
Zaitsev 10:41552d038a69 358 if (LPC_USB->EPINUSE & EP(endpoint)) {
Zaitsev 10:41552d038a69 359 bf = 0;
Zaitsev 10:41552d038a69 360 } else {
Zaitsev 10:41552d038a69 361 bf = 1;
Zaitsev 10:41552d038a69 362 }
Zaitsev 10:41552d038a69 363 }
Zaitsev 10:41552d038a69 364
Zaitsev 10:41552d038a69 365 // Find how many bytes were read
Zaitsev 10:41552d038a69 366 *bytesRead = (uint32_t) (endpointState[endpoint].maxPacket - BYTES_REMAINING(ep[PHY_TO_LOG(endpoint)].out[bf]));
Zaitsev 10:41552d038a69 367
Zaitsev 10:41552d038a69 368 // Copy data
Zaitsev 10:41552d038a69 369 USBMemCopy(data, ct->out, *bytesRead);
Zaitsev 10:41552d038a69 370 return EP_COMPLETED;
Zaitsev 10:41552d038a69 371 }
Zaitsev 10:41552d038a69 372 }
Zaitsev 10:41552d038a69 373
Zaitsev 10:41552d038a69 374 void USBHAL::EP0getWriteResult(void) {
Zaitsev 10:41552d038a69 375 // Not required
Zaitsev 10:41552d038a69 376 }
Zaitsev 10:41552d038a69 377
Zaitsev 10:41552d038a69 378 void USBHAL::EP0stall(void) {
Zaitsev 10:41552d038a69 379 ep[0].in[0] = CMDSTS_S;
Zaitsev 10:41552d038a69 380 ep[0].out[0] = CMDSTS_S;
Zaitsev 10:41552d038a69 381 }
Zaitsev 10:41552d038a69 382
Zaitsev 10:41552d038a69 383 void USBHAL::setAddress(uint8_t address) {
Zaitsev 10:41552d038a69 384 devCmdStat &= ~DEV_ADDR_MASK;
Zaitsev 10:41552d038a69 385 devCmdStat |= DEV_ADDR(address);
Zaitsev 10:41552d038a69 386 LPC_USB->DEVCMDSTAT = devCmdStat;
Zaitsev 10:41552d038a69 387 }
Zaitsev 10:41552d038a69 388
Zaitsev 10:41552d038a69 389 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
Zaitsev 10:41552d038a69 390 uint32_t flags = 0;
Zaitsev 10:41552d038a69 391 uint32_t bf;
Zaitsev 10:41552d038a69 392
Zaitsev 10:41552d038a69 393 // Validate parameters
Zaitsev 10:41552d038a69 394 if (data == NULL) {
Zaitsev 10:41552d038a69 395 return EP_INVALID;
Zaitsev 10:41552d038a69 396 }
Zaitsev 10:41552d038a69 397
Zaitsev 10:41552d038a69 398 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
Zaitsev 10:41552d038a69 399 return EP_INVALID;
Zaitsev 10:41552d038a69 400 }
Zaitsev 10:41552d038a69 401
Zaitsev 10:41552d038a69 402 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
Zaitsev 10:41552d038a69 403 return EP_INVALID;
Zaitsev 10:41552d038a69 404 }
Zaitsev 10:41552d038a69 405
Zaitsev 10:41552d038a69 406 if (size > endpointState[endpoint].maxPacket) {
Zaitsev 10:41552d038a69 407 return EP_INVALID;
Zaitsev 10:41552d038a69 408 }
Zaitsev 10:41552d038a69 409
Zaitsev 10:41552d038a69 410 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Zaitsev 10:41552d038a69 411 // Double buffered
Zaitsev 10:41552d038a69 412 if (LPC_USB->EPINUSE & EP(endpoint)) {
Zaitsev 10:41552d038a69 413 bf = 1;
Zaitsev 10:41552d038a69 414 } else {
Zaitsev 10:41552d038a69 415 bf = 0;
Zaitsev 10:41552d038a69 416 }
Zaitsev 10:41552d038a69 417 } else {
Zaitsev 10:41552d038a69 418 // Single buffered
Zaitsev 10:41552d038a69 419 bf = 0;
Zaitsev 10:41552d038a69 420 }
Zaitsev 10:41552d038a69 421
Zaitsev 10:41552d038a69 422 // Check if already active
Zaitsev 10:41552d038a69 423 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
Zaitsev 10:41552d038a69 424 return EP_INVALID;
Zaitsev 10:41552d038a69 425 }
Zaitsev 10:41552d038a69 426
Zaitsev 10:41552d038a69 427 // Check if stalled
Zaitsev 10:41552d038a69 428 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
Zaitsev 10:41552d038a69 429 return EP_STALLED;
Zaitsev 10:41552d038a69 430 }
Zaitsev 10:41552d038a69 431
Zaitsev 10:41552d038a69 432 // Copy data to USB RAM
Zaitsev 10:41552d038a69 433 USBMemCopy((uint8_t *)endpointState[endpoint].buffer[bf], data, size);
Zaitsev 10:41552d038a69 434
Zaitsev 10:41552d038a69 435 // Add options
Zaitsev 10:41552d038a69 436 if (endpointState[endpoint].options & RATE_FEEDBACK_MODE) {
Zaitsev 10:41552d038a69 437 flags |= CMDSTS_RF;
Zaitsev 10:41552d038a69 438 }
Zaitsev 10:41552d038a69 439
Zaitsev 10:41552d038a69 440 if (endpointState[endpoint].options & ISOCHRONOUS) {
Zaitsev 10:41552d038a69 441 flags |= CMDSTS_T;
Zaitsev 10:41552d038a69 442 }
Zaitsev 10:41552d038a69 443
Zaitsev 10:41552d038a69 444 // Add transfer
Zaitsev 10:41552d038a69 445 ep[PHY_TO_LOG(endpoint)].in[bf] = CMDSTS_ADDRESS_OFFSET( \
Zaitsev 10:41552d038a69 446 endpointState[endpoint].buffer[bf]) \
Zaitsev 10:41552d038a69 447 | CMDSTS_NBYTES(size) | CMDSTS_A | flags;
Zaitsev 10:41552d038a69 448
Zaitsev 10:41552d038a69 449 return EP_PENDING;
Zaitsev 10:41552d038a69 450 }
Zaitsev 10:41552d038a69 451
Zaitsev 10:41552d038a69 452 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
Zaitsev 10:41552d038a69 453 uint32_t bf;
Zaitsev 10:41552d038a69 454
Zaitsev 10:41552d038a69 455 // Validate parameters
Zaitsev 10:41552d038a69 456 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
Zaitsev 10:41552d038a69 457 return EP_INVALID;
Zaitsev 10:41552d038a69 458 }
Zaitsev 10:41552d038a69 459
Zaitsev 10:41552d038a69 460 if (OUT_EP(endpoint)) {
Zaitsev 10:41552d038a69 461 return EP_INVALID;
Zaitsev 10:41552d038a69 462 }
Zaitsev 10:41552d038a69 463
Zaitsev 10:41552d038a69 464 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Zaitsev 10:41552d038a69 465 // Double buffered // TODO: FIX THIS
Zaitsev 10:41552d038a69 466 if (LPC_USB->EPINUSE & EP(endpoint)) {
Zaitsev 10:41552d038a69 467 bf = 1;
Zaitsev 10:41552d038a69 468 } else {
Zaitsev 10:41552d038a69 469 bf = 0;
Zaitsev 10:41552d038a69 470 }
Zaitsev 10:41552d038a69 471 } else {
Zaitsev 10:41552d038a69 472 // Single buffered
Zaitsev 10:41552d038a69 473 bf = 0;
Zaitsev 10:41552d038a69 474 }
Zaitsev 10:41552d038a69 475
Zaitsev 10:41552d038a69 476 // Check if endpoint still active
Zaitsev 10:41552d038a69 477 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
Zaitsev 10:41552d038a69 478 return EP_PENDING;
Zaitsev 10:41552d038a69 479 }
Zaitsev 10:41552d038a69 480
Zaitsev 10:41552d038a69 481 // Check if stalled
Zaitsev 10:41552d038a69 482 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
Zaitsev 10:41552d038a69 483 return EP_STALLED;
Zaitsev 10:41552d038a69 484 }
Zaitsev 10:41552d038a69 485
Zaitsev 10:41552d038a69 486 return EP_COMPLETED;
Zaitsev 10:41552d038a69 487 }
Zaitsev 10:41552d038a69 488
Zaitsev 10:41552d038a69 489 void USBHAL::stallEndpoint(uint8_t endpoint) {
Zaitsev 10:41552d038a69 490
Zaitsev 10:41552d038a69 491 // FIX: should this clear active bit?
Zaitsev 10:41552d038a69 492 if (IN_EP(endpoint)) {
Zaitsev 10:41552d038a69 493 ep[PHY_TO_LOG(endpoint)].in[0] |= CMDSTS_S;
Zaitsev 10:41552d038a69 494 ep[PHY_TO_LOG(endpoint)].in[1] |= CMDSTS_S;
Zaitsev 10:41552d038a69 495 } else {
Zaitsev 10:41552d038a69 496 ep[PHY_TO_LOG(endpoint)].out[0] |= CMDSTS_S;
Zaitsev 10:41552d038a69 497 ep[PHY_TO_LOG(endpoint)].out[1] |= CMDSTS_S;
Zaitsev 10:41552d038a69 498 }
Zaitsev 10:41552d038a69 499 }
Zaitsev 10:41552d038a69 500
Zaitsev 10:41552d038a69 501 void USBHAL::unstallEndpoint(uint8_t endpoint) {
Zaitsev 10:41552d038a69 502 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Zaitsev 10:41552d038a69 503 // Double buffered
Zaitsev 10:41552d038a69 504 if (IN_EP(endpoint)) {
Zaitsev 10:41552d038a69 505 ep[PHY_TO_LOG(endpoint)].in[0] = 0; // S = 0
Zaitsev 10:41552d038a69 506 ep[PHY_TO_LOG(endpoint)].in[1] = 0; // S = 0
Zaitsev 10:41552d038a69 507
Zaitsev 10:41552d038a69 508 if (LPC_USB->EPINUSE & EP(endpoint)) {
Zaitsev 10:41552d038a69 509 ep[PHY_TO_LOG(endpoint)].in[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Zaitsev 10:41552d038a69 510 } else {
Zaitsev 10:41552d038a69 511 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Zaitsev 10:41552d038a69 512 }
Zaitsev 10:41552d038a69 513 } else {
Zaitsev 10:41552d038a69 514 ep[PHY_TO_LOG(endpoint)].out[0] = 0; // S = 0
Zaitsev 10:41552d038a69 515 ep[PHY_TO_LOG(endpoint)].out[1] = 0; // S = 0
Zaitsev 10:41552d038a69 516
Zaitsev 10:41552d038a69 517 if (LPC_USB->EPINUSE & EP(endpoint)) {
Zaitsev 10:41552d038a69 518 ep[PHY_TO_LOG(endpoint)].out[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Zaitsev 10:41552d038a69 519 } else {
Zaitsev 10:41552d038a69 520 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Zaitsev 10:41552d038a69 521 }
Zaitsev 10:41552d038a69 522 }
Zaitsev 10:41552d038a69 523 } else {
Zaitsev 10:41552d038a69 524 // Single buffered
Zaitsev 10:41552d038a69 525 if (IN_EP(endpoint)) {
Zaitsev 10:41552d038a69 526 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Zaitsev 10:41552d038a69 527 } else {
Zaitsev 10:41552d038a69 528 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Zaitsev 10:41552d038a69 529 }
Zaitsev 10:41552d038a69 530 }
Zaitsev 10:41552d038a69 531 }
Zaitsev 10:41552d038a69 532
Zaitsev 10:41552d038a69 533 bool USBHAL::getEndpointStallState(unsigned char endpoint) {
Zaitsev 10:41552d038a69 534 if (IN_EP(endpoint)) {
Zaitsev 10:41552d038a69 535 if (LPC_USB->EPINUSE & EP(endpoint)) {
Zaitsev 10:41552d038a69 536 if (ep[PHY_TO_LOG(endpoint)].in[1] & CMDSTS_S) {
Zaitsev 10:41552d038a69 537 return true;
Zaitsev 10:41552d038a69 538 }
Zaitsev 10:41552d038a69 539 } else {
Zaitsev 10:41552d038a69 540 if (ep[PHY_TO_LOG(endpoint)].in[0] & CMDSTS_S) {
Zaitsev 10:41552d038a69 541 return true;
Zaitsev 10:41552d038a69 542 }
Zaitsev 10:41552d038a69 543 }
Zaitsev 10:41552d038a69 544 } else {
Zaitsev 10:41552d038a69 545 if (LPC_USB->EPINUSE & EP(endpoint)) {
Zaitsev 10:41552d038a69 546 if (ep[PHY_TO_LOG(endpoint)].out[1] & CMDSTS_S) {
Zaitsev 10:41552d038a69 547 return true;
Zaitsev 10:41552d038a69 548 }
Zaitsev 10:41552d038a69 549 } else {
Zaitsev 10:41552d038a69 550 if (ep[PHY_TO_LOG(endpoint)].out[0] & CMDSTS_S) {
Zaitsev 10:41552d038a69 551 return true;
Zaitsev 10:41552d038a69 552 }
Zaitsev 10:41552d038a69 553 }
Zaitsev 10:41552d038a69 554 }
Zaitsev 10:41552d038a69 555
Zaitsev 10:41552d038a69 556 return false;
Zaitsev 10:41552d038a69 557 }
Zaitsev 10:41552d038a69 558
Zaitsev 10:41552d038a69 559 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options) {
Zaitsev 10:41552d038a69 560 uint32_t tmpEpRamPtr;
Zaitsev 10:41552d038a69 561
Zaitsev 10:41552d038a69 562 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
Zaitsev 10:41552d038a69 563 return false;
Zaitsev 10:41552d038a69 564 }
Zaitsev 10:41552d038a69 565
Zaitsev 10:41552d038a69 566 // Not applicable to the control endpoints
Zaitsev 10:41552d038a69 567 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
Zaitsev 10:41552d038a69 568 return false;
Zaitsev 10:41552d038a69 569 }
Zaitsev 10:41552d038a69 570
Zaitsev 10:41552d038a69 571 // Allocate buffers in USB RAM
Zaitsev 10:41552d038a69 572 tmpEpRamPtr = epRamPtr;
Zaitsev 10:41552d038a69 573
Zaitsev 10:41552d038a69 574 // Must be 64 byte aligned
Zaitsev 10:41552d038a69 575 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
Zaitsev 10:41552d038a69 576
Zaitsev 10:41552d038a69 577 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
Zaitsev 10:41552d038a69 578 // Out of memory
Zaitsev 10:41552d038a69 579 return false;
Zaitsev 10:41552d038a69 580 }
Zaitsev 10:41552d038a69 581
Zaitsev 10:41552d038a69 582 // Allocate first buffer
Zaitsev 10:41552d038a69 583 endpointState[endpoint].buffer[0] = tmpEpRamPtr;
Zaitsev 10:41552d038a69 584 tmpEpRamPtr += maxPacket;
Zaitsev 10:41552d038a69 585
Zaitsev 10:41552d038a69 586 if (!(options & SINGLE_BUFFERED)) {
Zaitsev 10:41552d038a69 587 // Must be 64 byte aligned
Zaitsev 10:41552d038a69 588 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
Zaitsev 10:41552d038a69 589
Zaitsev 10:41552d038a69 590 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
Zaitsev 10:41552d038a69 591 // Out of memory
Zaitsev 10:41552d038a69 592 return false;
Zaitsev 10:41552d038a69 593 }
Zaitsev 10:41552d038a69 594
Zaitsev 10:41552d038a69 595 // Allocate second buffer
Zaitsev 10:41552d038a69 596 endpointState[endpoint].buffer[1] = tmpEpRamPtr;
Zaitsev 10:41552d038a69 597 tmpEpRamPtr += maxPacket;
Zaitsev 10:41552d038a69 598 }
Zaitsev 10:41552d038a69 599
Zaitsev 10:41552d038a69 600 // Commit to this USB RAM allocation
Zaitsev 10:41552d038a69 601 epRamPtr = tmpEpRamPtr;
Zaitsev 10:41552d038a69 602
Zaitsev 10:41552d038a69 603 // Remaining endpoint state values
Zaitsev 10:41552d038a69 604 endpointState[endpoint].maxPacket = maxPacket;
Zaitsev 10:41552d038a69 605 endpointState[endpoint].options = options;
Zaitsev 10:41552d038a69 606
Zaitsev 10:41552d038a69 607 // Enable double buffering if required
Zaitsev 10:41552d038a69 608 if (options & SINGLE_BUFFERED) {
Zaitsev 10:41552d038a69 609 LPC_USB->EPBUFCFG &= ~EP(endpoint);
Zaitsev 10:41552d038a69 610 } else {
Zaitsev 10:41552d038a69 611 // Double buffered
Zaitsev 10:41552d038a69 612 LPC_USB->EPBUFCFG |= EP(endpoint);
Zaitsev 10:41552d038a69 613 }
Zaitsev 10:41552d038a69 614
Zaitsev 10:41552d038a69 615 // Enable interrupt
Zaitsev 10:41552d038a69 616 LPC_USB->INTEN |= EP(endpoint);
Zaitsev 10:41552d038a69 617
Zaitsev 10:41552d038a69 618 // Enable endpoint
Zaitsev 10:41552d038a69 619 unstallEndpoint(endpoint);
Zaitsev 10:41552d038a69 620 return true;
Zaitsev 10:41552d038a69 621 }
Zaitsev 10:41552d038a69 622
Zaitsev 10:41552d038a69 623 void USBHAL::remoteWakeup(void) {
Zaitsev 10:41552d038a69 624 // Clearing DSUS bit initiates a remote wakeup if the
Zaitsev 10:41552d038a69 625 // device is currently enabled and suspended - otherwise
Zaitsev 10:41552d038a69 626 // it has no effect.
Zaitsev 10:41552d038a69 627 LPC_USB->DEVCMDSTAT = devCmdStat & ~DSUS;
Zaitsev 10:41552d038a69 628 }
Zaitsev 10:41552d038a69 629
Zaitsev 10:41552d038a69 630
Zaitsev 10:41552d038a69 631 static void disableEndpoints(void) {
Zaitsev 10:41552d038a69 632 uint32_t logEp;
Zaitsev 10:41552d038a69 633
Zaitsev 10:41552d038a69 634 // Ref. Table 158 "When a bus reset is received, software
Zaitsev 10:41552d038a69 635 // must set the disable bit of all endpoints to 1".
Zaitsev 10:41552d038a69 636
Zaitsev 10:41552d038a69 637 for (logEp = 1; logEp < NUMBER_OF_LOGICAL_ENDPOINTS; logEp++) {
Zaitsev 10:41552d038a69 638 ep[logEp].out[0] = CMDSTS_D;
Zaitsev 10:41552d038a69 639 ep[logEp].out[1] = CMDSTS_D;
Zaitsev 10:41552d038a69 640 ep[logEp].in[0] = CMDSTS_D;
Zaitsev 10:41552d038a69 641 ep[logEp].in[1] = CMDSTS_D;
Zaitsev 10:41552d038a69 642 }
Zaitsev 10:41552d038a69 643
Zaitsev 10:41552d038a69 644 // Start of USB RAM for endpoints > 0
Zaitsev 10:41552d038a69 645 epRamPtr = usbRamPtr;
Zaitsev 10:41552d038a69 646 }
Zaitsev 10:41552d038a69 647
Zaitsev 10:41552d038a69 648
Zaitsev 10:41552d038a69 649
Zaitsev 10:41552d038a69 650 void USBHAL::_usbisr(void) {
Zaitsev 10:41552d038a69 651 instance->usbisr();
Zaitsev 10:41552d038a69 652 }
Zaitsev 10:41552d038a69 653
Zaitsev 10:41552d038a69 654 void USBHAL::usbisr(void) {
Zaitsev 10:41552d038a69 655 // Start of frame
Zaitsev 10:41552d038a69 656 if (LPC_USB->INTSTAT & FRAME_INT) {
Zaitsev 10:41552d038a69 657 // Clear SOF interrupt
Zaitsev 10:41552d038a69 658 LPC_USB->INTSTAT = FRAME_INT;
Zaitsev 10:41552d038a69 659
Zaitsev 10:41552d038a69 660 // SOF event, read frame number
Zaitsev 10:41552d038a69 661 SOF(FRAME_NR(LPC_USB->INFO));
Zaitsev 10:41552d038a69 662 }
Zaitsev 10:41552d038a69 663
Zaitsev 10:41552d038a69 664 // Device state
Zaitsev 10:41552d038a69 665 if (LPC_USB->INTSTAT & DEV_INT) {
Zaitsev 10:41552d038a69 666 LPC_USB->INTSTAT = DEV_INT;
Zaitsev 10:41552d038a69 667
Zaitsev 10:41552d038a69 668 if (LPC_USB->DEVCMDSTAT & DSUS_C) {
Zaitsev 10:41552d038a69 669 // Suspend status changed
Zaitsev 10:41552d038a69 670 LPC_USB->DEVCMDSTAT = devCmdStat | DSUS_C;
Zaitsev 10:41552d038a69 671 if (LPC_USB->DEVCMDSTAT & DSUS) {
Zaitsev 10:41552d038a69 672 suspendStateChanged(1);
Zaitsev 10:41552d038a69 673 } else {
Zaitsev 10:41552d038a69 674 suspendStateChanged(0);
Zaitsev 10:41552d038a69 675 }
Zaitsev 10:41552d038a69 676 }
Zaitsev 10:41552d038a69 677
Zaitsev 10:41552d038a69 678 if (LPC_USB->DEVCMDSTAT & DRES_C) {
Zaitsev 10:41552d038a69 679 // Bus reset
Zaitsev 10:41552d038a69 680 LPC_USB->DEVCMDSTAT = devCmdStat | DRES_C;
Zaitsev 10:41552d038a69 681
Zaitsev 10:41552d038a69 682 // Disable endpoints > 0
Zaitsev 10:41552d038a69 683 disableEndpoints();
Zaitsev 10:41552d038a69 684
Zaitsev 10:41552d038a69 685 // Bus reset event
Zaitsev 10:41552d038a69 686 busReset();
Zaitsev 10:41552d038a69 687 }
Zaitsev 10:41552d038a69 688 }
Zaitsev 10:41552d038a69 689
Zaitsev 10:41552d038a69 690 // Endpoint 0
Zaitsev 10:41552d038a69 691 if (LPC_USB->INTSTAT & EP(EP0OUT)) {
Zaitsev 10:41552d038a69 692 // Clear EP0OUT/SETUP interrupt
Zaitsev 10:41552d038a69 693 LPC_USB->INTSTAT = EP(EP0OUT);
Zaitsev 10:41552d038a69 694
Zaitsev 10:41552d038a69 695 // Check if SETUP
Zaitsev 10:41552d038a69 696 if (LPC_USB->DEVCMDSTAT & SETUP) {
Zaitsev 10:41552d038a69 697 // Clear Active and Stall bits for EP0
Zaitsev 10:41552d038a69 698 // Documentation does not make it clear if we must use the
Zaitsev 10:41552d038a69 699 // EPSKIP register to achieve this, Fig. 16 and NXP reference
Zaitsev 10:41552d038a69 700 // code suggests we can just clear the Active bits - check with
Zaitsev 10:41552d038a69 701 // NXP to be sure.
Zaitsev 10:41552d038a69 702 ep[0].in[0] = 0;
Zaitsev 10:41552d038a69 703 ep[0].out[0] = 0;
Zaitsev 10:41552d038a69 704
Zaitsev 10:41552d038a69 705 // Clear EP0IN interrupt
Zaitsev 10:41552d038a69 706 LPC_USB->INTSTAT = EP(EP0IN);
Zaitsev 10:41552d038a69 707
Zaitsev 10:41552d038a69 708 // Clear SETUP (and INTONNAK_CI/O) in device status register
Zaitsev 10:41552d038a69 709 LPC_USB->DEVCMDSTAT = devCmdStat | SETUP;
Zaitsev 10:41552d038a69 710
Zaitsev 10:41552d038a69 711 // EP0 SETUP event (SETUP data received)
Zaitsev 10:41552d038a69 712 EP0setupCallback();
Zaitsev 10:41552d038a69 713 } else {
Zaitsev 10:41552d038a69 714 // EP0OUT ACK event (OUT data received)
Zaitsev 10:41552d038a69 715 EP0out();
Zaitsev 10:41552d038a69 716 }
Zaitsev 10:41552d038a69 717 }
Zaitsev 10:41552d038a69 718
Zaitsev 10:41552d038a69 719 if (LPC_USB->INTSTAT & EP(EP0IN)) {
Zaitsev 10:41552d038a69 720 // Clear EP0IN interrupt
Zaitsev 10:41552d038a69 721 LPC_USB->INTSTAT = EP(EP0IN);
Zaitsev 10:41552d038a69 722
Zaitsev 10:41552d038a69 723 // EP0IN ACK event (IN data sent)
Zaitsev 10:41552d038a69 724 EP0in();
Zaitsev 10:41552d038a69 725 }
Zaitsev 10:41552d038a69 726
Zaitsev 10:41552d038a69 727 for (uint8_t num = 2; num < 5*2; num++) {
Zaitsev 10:41552d038a69 728 if (LPC_USB->INTSTAT & EP(num)) {
Zaitsev 10:41552d038a69 729 LPC_USB->INTSTAT = EP(num);
Zaitsev 10:41552d038a69 730 epComplete |= EP(num);
Zaitsev 10:41552d038a69 731 if ((instance->*(epCallback[num - 2]))()) {
Zaitsev 10:41552d038a69 732 epComplete &= ~EP(num);
Zaitsev 10:41552d038a69 733 }
Zaitsev 10:41552d038a69 734 }
Zaitsev 10:41552d038a69 735 }
Zaitsev 10:41552d038a69 736 }
Zaitsev 10:41552d038a69 737
Zaitsev 10:41552d038a69 738 #endif