Mateusz Kowalik / Application

USB Serial application

Fork of USBSerial_HelloWorld by Samuel Mokrani

mbed-dev/cmsis/core_caFunc.h@10:41552d038a69, 2017-01-10 (annotated)

Committer:
Zaitsev
Date:
Tue Jan 10 20:42:26 2017 +0000
Revision:
10:41552d038a69
USB Serial bi-directional bridge

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zaitsev 10:41552d038a69 1 /**************************************************************************//**
Zaitsev 10:41552d038a69 2 * @file core_caFunc.h
Zaitsev 10:41552d038a69 3 * @brief CMSIS Cortex-A Core Function Access Header File
Zaitsev 10:41552d038a69 4 * @version V3.10
Zaitsev 10:41552d038a69 5 * @date 30 Oct 2013
Zaitsev 10:41552d038a69 6 *
Zaitsev 10:41552d038a69 7 * @note
Zaitsev 10:41552d038a69 8 *
Zaitsev 10:41552d038a69 9 ******************************************************************************/
Zaitsev 10:41552d038a69 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Zaitsev 10:41552d038a69 11
Zaitsev 10:41552d038a69 12 All rights reserved.
Zaitsev 10:41552d038a69 13 Redistribution and use in source and binary forms, with or without
Zaitsev 10:41552d038a69 14 modification, are permitted provided that the following conditions are met:
Zaitsev 10:41552d038a69 15 - Redistributions of source code must retain the above copyright
Zaitsev 10:41552d038a69 16 notice, this list of conditions and the following disclaimer.
Zaitsev 10:41552d038a69 17 - Redistributions in binary form must reproduce the above copyright
Zaitsev 10:41552d038a69 18 notice, this list of conditions and the following disclaimer in the
Zaitsev 10:41552d038a69 19 documentation and/or other materials provided with the distribution.
Zaitsev 10:41552d038a69 20 - Neither the name of ARM nor the names of its contributors may be used
Zaitsev 10:41552d038a69 21 to endorse or promote products derived from this software without
Zaitsev 10:41552d038a69 22 specific prior written permission.
Zaitsev 10:41552d038a69 23 *
Zaitsev 10:41552d038a69 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Zaitsev 10:41552d038a69 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Zaitsev 10:41552d038a69 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Zaitsev 10:41552d038a69 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Zaitsev 10:41552d038a69 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Zaitsev 10:41552d038a69 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Zaitsev 10:41552d038a69 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Zaitsev 10:41552d038a69 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Zaitsev 10:41552d038a69 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Zaitsev 10:41552d038a69 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Zaitsev 10:41552d038a69 34 POSSIBILITY OF SUCH DAMAGE.
Zaitsev 10:41552d038a69 35 ---------------------------------------------------------------------------*/
Zaitsev 10:41552d038a69 36
Zaitsev 10:41552d038a69 37
Zaitsev 10:41552d038a69 38 #ifndef __CORE_CAFUNC_H__
Zaitsev 10:41552d038a69 39 #define __CORE_CAFUNC_H__
Zaitsev 10:41552d038a69 40
Zaitsev 10:41552d038a69 41
Zaitsev 10:41552d038a69 42 /* ########################### Core Function Access ########################### */
Zaitsev 10:41552d038a69 43 /** \ingroup CMSIS_Core_FunctionInterface
Zaitsev 10:41552d038a69 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Zaitsev 10:41552d038a69 45 @{
Zaitsev 10:41552d038a69 46 */
Zaitsev 10:41552d038a69 47
Zaitsev 10:41552d038a69 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Zaitsev 10:41552d038a69 49 /* ARM armcc specific functions */
Zaitsev 10:41552d038a69 50
Zaitsev 10:41552d038a69 51 #if (__ARMCC_VERSION < 400677)
Zaitsev 10:41552d038a69 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Zaitsev 10:41552d038a69 53 #endif
Zaitsev 10:41552d038a69 54
Zaitsev 10:41552d038a69 55 #define MODE_USR 0x10
Zaitsev 10:41552d038a69 56 #define MODE_FIQ 0x11
Zaitsev 10:41552d038a69 57 #define MODE_IRQ 0x12
Zaitsev 10:41552d038a69 58 #define MODE_SVC 0x13
Zaitsev 10:41552d038a69 59 #define MODE_MON 0x16
Zaitsev 10:41552d038a69 60 #define MODE_ABT 0x17
Zaitsev 10:41552d038a69 61 #define MODE_HYP 0x1A
Zaitsev 10:41552d038a69 62 #define MODE_UND 0x1B
Zaitsev 10:41552d038a69 63 #define MODE_SYS 0x1F
Zaitsev 10:41552d038a69 64
Zaitsev 10:41552d038a69 65 /** \brief Get APSR Register
Zaitsev 10:41552d038a69 66
Zaitsev 10:41552d038a69 67 This function returns the content of the APSR Register.
Zaitsev 10:41552d038a69 68
Zaitsev 10:41552d038a69 69 \return APSR Register value
Zaitsev 10:41552d038a69 70 */
Zaitsev 10:41552d038a69 71 __STATIC_INLINE uint32_t __get_APSR(void)
Zaitsev 10:41552d038a69 72 {
Zaitsev 10:41552d038a69 73 register uint32_t __regAPSR __ASM("apsr");
Zaitsev 10:41552d038a69 74 return(__regAPSR);
Zaitsev 10:41552d038a69 75 }
Zaitsev 10:41552d038a69 76
Zaitsev 10:41552d038a69 77
Zaitsev 10:41552d038a69 78 /** \brief Get CPSR Register
Zaitsev 10:41552d038a69 79
Zaitsev 10:41552d038a69 80 This function returns the content of the CPSR Register.
Zaitsev 10:41552d038a69 81
Zaitsev 10:41552d038a69 82 \return CPSR Register value
Zaitsev 10:41552d038a69 83 */
Zaitsev 10:41552d038a69 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Zaitsev 10:41552d038a69 85 {
Zaitsev 10:41552d038a69 86 register uint32_t __regCPSR __ASM("cpsr");
Zaitsev 10:41552d038a69 87 return(__regCPSR);
Zaitsev 10:41552d038a69 88 }
Zaitsev 10:41552d038a69 89
Zaitsev 10:41552d038a69 90 /** \brief Set Stack Pointer
Zaitsev 10:41552d038a69 91
Zaitsev 10:41552d038a69 92 This function assigns the given value to the current stack pointer.
Zaitsev 10:41552d038a69 93
Zaitsev 10:41552d038a69 94 \param [in] topOfStack Stack Pointer value to set
Zaitsev 10:41552d038a69 95 */
Zaitsev 10:41552d038a69 96 register uint32_t __regSP __ASM("sp");
Zaitsev 10:41552d038a69 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Zaitsev 10:41552d038a69 98 {
Zaitsev 10:41552d038a69 99 __regSP = topOfStack;
Zaitsev 10:41552d038a69 100 }
Zaitsev 10:41552d038a69 101
Zaitsev 10:41552d038a69 102
Zaitsev 10:41552d038a69 103 /** \brief Get link register
Zaitsev 10:41552d038a69 104
Zaitsev 10:41552d038a69 105 This function returns the value of the link register
Zaitsev 10:41552d038a69 106
Zaitsev 10:41552d038a69 107 \return Value of link register
Zaitsev 10:41552d038a69 108 */
Zaitsev 10:41552d038a69 109 register uint32_t __reglr __ASM("lr");
Zaitsev 10:41552d038a69 110 __STATIC_INLINE uint32_t __get_LR(void)
Zaitsev 10:41552d038a69 111 {
Zaitsev 10:41552d038a69 112 return(__reglr);
Zaitsev 10:41552d038a69 113 }
Zaitsev 10:41552d038a69 114
Zaitsev 10:41552d038a69 115 /** \brief Set link register
Zaitsev 10:41552d038a69 116
Zaitsev 10:41552d038a69 117 This function sets the value of the link register
Zaitsev 10:41552d038a69 118
Zaitsev 10:41552d038a69 119 \param [in] lr LR value to set
Zaitsev 10:41552d038a69 120 */
Zaitsev 10:41552d038a69 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Zaitsev 10:41552d038a69 122 {
Zaitsev 10:41552d038a69 123 __reglr = lr;
Zaitsev 10:41552d038a69 124 }
Zaitsev 10:41552d038a69 125
Zaitsev 10:41552d038a69 126 /** \brief Set Process Stack Pointer
Zaitsev 10:41552d038a69 127
Zaitsev 10:41552d038a69 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Zaitsev 10:41552d038a69 129
Zaitsev 10:41552d038a69 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Zaitsev 10:41552d038a69 131 */
Zaitsev 10:41552d038a69 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Zaitsev 10:41552d038a69 133 {
Zaitsev 10:41552d038a69 134 ARM
Zaitsev 10:41552d038a69 135 PRESERVE8
Zaitsev 10:41552d038a69 136
Zaitsev 10:41552d038a69 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Zaitsev 10:41552d038a69 138 MRS R1, CPSR
Zaitsev 10:41552d038a69 139 CPS #MODE_SYS ;no effect in USR mode
Zaitsev 10:41552d038a69 140 MOV SP, R0
Zaitsev 10:41552d038a69 141 MSR CPSR_c, R1 ;no effect in USR mode
Zaitsev 10:41552d038a69 142 ISB
Zaitsev 10:41552d038a69 143 BX LR
Zaitsev 10:41552d038a69 144
Zaitsev 10:41552d038a69 145 }
Zaitsev 10:41552d038a69 146
Zaitsev 10:41552d038a69 147 /** \brief Set User Mode
Zaitsev 10:41552d038a69 148
Zaitsev 10:41552d038a69 149 This function changes the processor state to User Mode
Zaitsev 10:41552d038a69 150 */
Zaitsev 10:41552d038a69 151 __STATIC_ASM void __set_CPS_USR(void)
Zaitsev 10:41552d038a69 152 {
Zaitsev 10:41552d038a69 153 ARM
Zaitsev 10:41552d038a69 154
Zaitsev 10:41552d038a69 155 CPS #MODE_USR
Zaitsev 10:41552d038a69 156 BX LR
Zaitsev 10:41552d038a69 157 }
Zaitsev 10:41552d038a69 158
Zaitsev 10:41552d038a69 159
Zaitsev 10:41552d038a69 160 /** \brief Enable FIQ
Zaitsev 10:41552d038a69 161
Zaitsev 10:41552d038a69 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Zaitsev 10:41552d038a69 163 Can only be executed in Privileged modes.
Zaitsev 10:41552d038a69 164 */
Zaitsev 10:41552d038a69 165 #define __enable_fault_irq __enable_fiq
Zaitsev 10:41552d038a69 166
Zaitsev 10:41552d038a69 167
Zaitsev 10:41552d038a69 168 /** \brief Disable FIQ
Zaitsev 10:41552d038a69 169
Zaitsev 10:41552d038a69 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Zaitsev 10:41552d038a69 171 Can only be executed in Privileged modes.
Zaitsev 10:41552d038a69 172 */
Zaitsev 10:41552d038a69 173 #define __disable_fault_irq __disable_fiq
Zaitsev 10:41552d038a69 174
Zaitsev 10:41552d038a69 175
Zaitsev 10:41552d038a69 176 /** \brief Get FPSCR
Zaitsev 10:41552d038a69 177
Zaitsev 10:41552d038a69 178 This function returns the current value of the Floating Point Status/Control register.
Zaitsev 10:41552d038a69 179
Zaitsev 10:41552d038a69 180 \return Floating Point Status/Control register value
Zaitsev 10:41552d038a69 181 */
Zaitsev 10:41552d038a69 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Zaitsev 10:41552d038a69 183 {
Zaitsev 10:41552d038a69 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Zaitsev 10:41552d038a69 185 register uint32_t __regfpscr __ASM("fpscr");
Zaitsev 10:41552d038a69 186 return(__regfpscr);
Zaitsev 10:41552d038a69 187 #else
Zaitsev 10:41552d038a69 188 return(0);
Zaitsev 10:41552d038a69 189 #endif
Zaitsev 10:41552d038a69 190 }
Zaitsev 10:41552d038a69 191
Zaitsev 10:41552d038a69 192
Zaitsev 10:41552d038a69 193 /** \brief Set FPSCR
Zaitsev 10:41552d038a69 194
Zaitsev 10:41552d038a69 195 This function assigns the given value to the Floating Point Status/Control register.
Zaitsev 10:41552d038a69 196
Zaitsev 10:41552d038a69 197 \param [in] fpscr Floating Point Status/Control value to set
Zaitsev 10:41552d038a69 198 */
Zaitsev 10:41552d038a69 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Zaitsev 10:41552d038a69 200 {
Zaitsev 10:41552d038a69 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Zaitsev 10:41552d038a69 202 register uint32_t __regfpscr __ASM("fpscr");
Zaitsev 10:41552d038a69 203 __regfpscr = (fpscr);
Zaitsev 10:41552d038a69 204 #endif
Zaitsev 10:41552d038a69 205 }
Zaitsev 10:41552d038a69 206
Zaitsev 10:41552d038a69 207 /** \brief Get FPEXC
Zaitsev 10:41552d038a69 208
Zaitsev 10:41552d038a69 209 This function returns the current value of the Floating Point Exception Control register.
Zaitsev 10:41552d038a69 210
Zaitsev 10:41552d038a69 211 \return Floating Point Exception Control register value
Zaitsev 10:41552d038a69 212 */
Zaitsev 10:41552d038a69 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Zaitsev 10:41552d038a69 214 {
Zaitsev 10:41552d038a69 215 #if (__FPU_PRESENT == 1)
Zaitsev 10:41552d038a69 216 register uint32_t __regfpexc __ASM("fpexc");
Zaitsev 10:41552d038a69 217 return(__regfpexc);
Zaitsev 10:41552d038a69 218 #else
Zaitsev 10:41552d038a69 219 return(0);
Zaitsev 10:41552d038a69 220 #endif
Zaitsev 10:41552d038a69 221 }
Zaitsev 10:41552d038a69 222
Zaitsev 10:41552d038a69 223
Zaitsev 10:41552d038a69 224 /** \brief Set FPEXC
Zaitsev 10:41552d038a69 225
Zaitsev 10:41552d038a69 226 This function assigns the given value to the Floating Point Exception Control register.
Zaitsev 10:41552d038a69 227
Zaitsev 10:41552d038a69 228 \param [in] fpscr Floating Point Exception Control value to set
Zaitsev 10:41552d038a69 229 */
Zaitsev 10:41552d038a69 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Zaitsev 10:41552d038a69 231 {
Zaitsev 10:41552d038a69 232 #if (__FPU_PRESENT == 1)
Zaitsev 10:41552d038a69 233 register uint32_t __regfpexc __ASM("fpexc");
Zaitsev 10:41552d038a69 234 __regfpexc = (fpexc);
Zaitsev 10:41552d038a69 235 #endif
Zaitsev 10:41552d038a69 236 }
Zaitsev 10:41552d038a69 237
Zaitsev 10:41552d038a69 238 /** \brief Get CPACR
Zaitsev 10:41552d038a69 239
Zaitsev 10:41552d038a69 240 This function returns the current value of the Coprocessor Access Control register.
Zaitsev 10:41552d038a69 241
Zaitsev 10:41552d038a69 242 \return Coprocessor Access Control register value
Zaitsev 10:41552d038a69 243 */
Zaitsev 10:41552d038a69 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Zaitsev 10:41552d038a69 245 {
Zaitsev 10:41552d038a69 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Zaitsev 10:41552d038a69 247 return __regCPACR;
Zaitsev 10:41552d038a69 248 }
Zaitsev 10:41552d038a69 249
Zaitsev 10:41552d038a69 250 /** \brief Set CPACR
Zaitsev 10:41552d038a69 251
Zaitsev 10:41552d038a69 252 This function assigns the given value to the Coprocessor Access Control register.
Zaitsev 10:41552d038a69 253
Zaitsev 10:41552d038a69 254 \param [in] cpacr Coprocessor Acccess Control value to set
Zaitsev 10:41552d038a69 255 */
Zaitsev 10:41552d038a69 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Zaitsev 10:41552d038a69 257 {
Zaitsev 10:41552d038a69 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Zaitsev 10:41552d038a69 259 __regCPACR = cpacr;
Zaitsev 10:41552d038a69 260 __ISB();
Zaitsev 10:41552d038a69 261 }
Zaitsev 10:41552d038a69 262
Zaitsev 10:41552d038a69 263 /** \brief Get CBAR
Zaitsev 10:41552d038a69 264
Zaitsev 10:41552d038a69 265 This function returns the value of the Configuration Base Address register.
Zaitsev 10:41552d038a69 266
Zaitsev 10:41552d038a69 267 \return Configuration Base Address register value
Zaitsev 10:41552d038a69 268 */
Zaitsev 10:41552d038a69 269 __STATIC_INLINE uint32_t __get_CBAR() {
Zaitsev 10:41552d038a69 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Zaitsev 10:41552d038a69 271 return(__regCBAR);
Zaitsev 10:41552d038a69 272 }
Zaitsev 10:41552d038a69 273
Zaitsev 10:41552d038a69 274 /** \brief Get TTBR0
Zaitsev 10:41552d038a69 275
Zaitsev 10:41552d038a69 276 This function returns the value of the Translation Table Base Register 0.
Zaitsev 10:41552d038a69 277
Zaitsev 10:41552d038a69 278 \return Translation Table Base Register 0 value
Zaitsev 10:41552d038a69 279 */
Zaitsev 10:41552d038a69 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Zaitsev 10:41552d038a69 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Zaitsev 10:41552d038a69 282 return(__regTTBR0);
Zaitsev 10:41552d038a69 283 }
Zaitsev 10:41552d038a69 284
Zaitsev 10:41552d038a69 285 /** \brief Set TTBR0
Zaitsev 10:41552d038a69 286
Zaitsev 10:41552d038a69 287 This function assigns the given value to the Translation Table Base Register 0.
Zaitsev 10:41552d038a69 288
Zaitsev 10:41552d038a69 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Zaitsev 10:41552d038a69 290 */
Zaitsev 10:41552d038a69 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Zaitsev 10:41552d038a69 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Zaitsev 10:41552d038a69 293 __regTTBR0 = ttbr0;
Zaitsev 10:41552d038a69 294 __ISB();
Zaitsev 10:41552d038a69 295 }
Zaitsev 10:41552d038a69 296
Zaitsev 10:41552d038a69 297 /** \brief Get DACR
Zaitsev 10:41552d038a69 298
Zaitsev 10:41552d038a69 299 This function returns the value of the Domain Access Control Register.
Zaitsev 10:41552d038a69 300
Zaitsev 10:41552d038a69 301 \return Domain Access Control Register value
Zaitsev 10:41552d038a69 302 */
Zaitsev 10:41552d038a69 303 __STATIC_INLINE uint32_t __get_DACR() {
Zaitsev 10:41552d038a69 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Zaitsev 10:41552d038a69 305 return(__regDACR);
Zaitsev 10:41552d038a69 306 }
Zaitsev 10:41552d038a69 307
Zaitsev 10:41552d038a69 308 /** \brief Set DACR
Zaitsev 10:41552d038a69 309
Zaitsev 10:41552d038a69 310 This function assigns the given value to the Domain Access Control Register.
Zaitsev 10:41552d038a69 311
Zaitsev 10:41552d038a69 312 \param [in] dacr Domain Access Control Register value to set
Zaitsev 10:41552d038a69 313 */
Zaitsev 10:41552d038a69 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Zaitsev 10:41552d038a69 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Zaitsev 10:41552d038a69 316 __regDACR = dacr;
Zaitsev 10:41552d038a69 317 __ISB();
Zaitsev 10:41552d038a69 318 }
Zaitsev 10:41552d038a69 319
Zaitsev 10:41552d038a69 320 /******************************** Cache and BTAC enable ****************************************************/
Zaitsev 10:41552d038a69 321
Zaitsev 10:41552d038a69 322 /** \brief Set SCTLR
Zaitsev 10:41552d038a69 323
Zaitsev 10:41552d038a69 324 This function assigns the given value to the System Control Register.
Zaitsev 10:41552d038a69 325
Zaitsev 10:41552d038a69 326 \param [in] sctlr System Control Register value to set
Zaitsev 10:41552d038a69 327 */
Zaitsev 10:41552d038a69 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Zaitsev 10:41552d038a69 329 {
Zaitsev 10:41552d038a69 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Zaitsev 10:41552d038a69 331 __regSCTLR = sctlr;
Zaitsev 10:41552d038a69 332 }
Zaitsev 10:41552d038a69 333
Zaitsev 10:41552d038a69 334 /** \brief Get SCTLR
Zaitsev 10:41552d038a69 335
Zaitsev 10:41552d038a69 336 This function returns the value of the System Control Register.
Zaitsev 10:41552d038a69 337
Zaitsev 10:41552d038a69 338 \return System Control Register value
Zaitsev 10:41552d038a69 339 */
Zaitsev 10:41552d038a69 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Zaitsev 10:41552d038a69 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Zaitsev 10:41552d038a69 342 return(__regSCTLR);
Zaitsev 10:41552d038a69 343 }
Zaitsev 10:41552d038a69 344
Zaitsev 10:41552d038a69 345 /** \brief Enable Caches
Zaitsev 10:41552d038a69 346
Zaitsev 10:41552d038a69 347 Enable Caches
Zaitsev 10:41552d038a69 348 */
Zaitsev 10:41552d038a69 349 __STATIC_INLINE void __enable_caches(void) {
Zaitsev 10:41552d038a69 350 // Set I bit 12 to enable I Cache
Zaitsev 10:41552d038a69 351 // Set C bit 2 to enable D Cache
Zaitsev 10:41552d038a69 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Zaitsev 10:41552d038a69 353 }
Zaitsev 10:41552d038a69 354
Zaitsev 10:41552d038a69 355 /** \brief Disable Caches
Zaitsev 10:41552d038a69 356
Zaitsev 10:41552d038a69 357 Disable Caches
Zaitsev 10:41552d038a69 358 */
Zaitsev 10:41552d038a69 359 __STATIC_INLINE void __disable_caches(void) {
Zaitsev 10:41552d038a69 360 // Clear I bit 12 to disable I Cache
Zaitsev 10:41552d038a69 361 // Clear C bit 2 to disable D Cache
Zaitsev 10:41552d038a69 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Zaitsev 10:41552d038a69 363 __ISB();
Zaitsev 10:41552d038a69 364 }
Zaitsev 10:41552d038a69 365
Zaitsev 10:41552d038a69 366 /** \brief Enable BTAC
Zaitsev 10:41552d038a69 367
Zaitsev 10:41552d038a69 368 Enable BTAC
Zaitsev 10:41552d038a69 369 */
Zaitsev 10:41552d038a69 370 __STATIC_INLINE void __enable_btac(void) {
Zaitsev 10:41552d038a69 371 // Set Z bit 11 to enable branch prediction
Zaitsev 10:41552d038a69 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Zaitsev 10:41552d038a69 373 __ISB();
Zaitsev 10:41552d038a69 374 }
Zaitsev 10:41552d038a69 375
Zaitsev 10:41552d038a69 376 /** \brief Disable BTAC
Zaitsev 10:41552d038a69 377
Zaitsev 10:41552d038a69 378 Disable BTAC
Zaitsev 10:41552d038a69 379 */
Zaitsev 10:41552d038a69 380 __STATIC_INLINE void __disable_btac(void) {
Zaitsev 10:41552d038a69 381 // Clear Z bit 11 to disable branch prediction
Zaitsev 10:41552d038a69 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Zaitsev 10:41552d038a69 383 }
Zaitsev 10:41552d038a69 384
Zaitsev 10:41552d038a69 385
Zaitsev 10:41552d038a69 386 /** \brief Enable MMU
Zaitsev 10:41552d038a69 387
Zaitsev 10:41552d038a69 388 Enable MMU
Zaitsev 10:41552d038a69 389 */
Zaitsev 10:41552d038a69 390 __STATIC_INLINE void __enable_mmu(void) {
Zaitsev 10:41552d038a69 391 // Set M bit 0 to enable the MMU
Zaitsev 10:41552d038a69 392 // Set AFE bit to enable simplified access permissions model
Zaitsev 10:41552d038a69 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Zaitsev 10:41552d038a69 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Zaitsev 10:41552d038a69 395 __ISB();
Zaitsev 10:41552d038a69 396 }
Zaitsev 10:41552d038a69 397
Zaitsev 10:41552d038a69 398 /** \brief Disable MMU
Zaitsev 10:41552d038a69 399
Zaitsev 10:41552d038a69 400 Disable MMU
Zaitsev 10:41552d038a69 401 */
Zaitsev 10:41552d038a69 402 __STATIC_INLINE void __disable_mmu(void) {
Zaitsev 10:41552d038a69 403 // Clear M bit 0 to disable the MMU
Zaitsev 10:41552d038a69 404 __set_SCTLR( __get_SCTLR() & ~1);
Zaitsev 10:41552d038a69 405 __ISB();
Zaitsev 10:41552d038a69 406 }
Zaitsev 10:41552d038a69 407
Zaitsev 10:41552d038a69 408 /******************************** TLB maintenance operations ************************************************/
Zaitsev 10:41552d038a69 409 /** \brief Invalidate the whole tlb
Zaitsev 10:41552d038a69 410
Zaitsev 10:41552d038a69 411 TLBIALL. Invalidate the whole tlb
Zaitsev 10:41552d038a69 412 */
Zaitsev 10:41552d038a69 413
Zaitsev 10:41552d038a69 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Zaitsev 10:41552d038a69 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Zaitsev 10:41552d038a69 416 __TLBIALL = 0;
Zaitsev 10:41552d038a69 417 __DSB();
Zaitsev 10:41552d038a69 418 __ISB();
Zaitsev 10:41552d038a69 419 }
Zaitsev 10:41552d038a69 420
Zaitsev 10:41552d038a69 421 /******************************** BTB maintenance operations ************************************************/
Zaitsev 10:41552d038a69 422 /** \brief Invalidate entire branch predictor array
Zaitsev 10:41552d038a69 423
Zaitsev 10:41552d038a69 424 BPIALL. Branch Predictor Invalidate All.
Zaitsev 10:41552d038a69 425 */
Zaitsev 10:41552d038a69 426
Zaitsev 10:41552d038a69 427 __STATIC_INLINE void __v7_inv_btac(void) {
Zaitsev 10:41552d038a69 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Zaitsev 10:41552d038a69 429 __BPIALL = 0;
Zaitsev 10:41552d038a69 430 __DSB(); //ensure completion of the invalidation
Zaitsev 10:41552d038a69 431 __ISB(); //ensure instruction fetch path sees new state
Zaitsev 10:41552d038a69 432 }
Zaitsev 10:41552d038a69 433
Zaitsev 10:41552d038a69 434
Zaitsev 10:41552d038a69 435 /******************************** L1 cache operations ******************************************************/
Zaitsev 10:41552d038a69 436
Zaitsev 10:41552d038a69 437 /** \brief Invalidate the whole I$
Zaitsev 10:41552d038a69 438
Zaitsev 10:41552d038a69 439 ICIALLU. Instruction Cache Invalidate All to PoU
Zaitsev 10:41552d038a69 440 */
Zaitsev 10:41552d038a69 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Zaitsev 10:41552d038a69 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Zaitsev 10:41552d038a69 443 __ICIALLU = 0;
Zaitsev 10:41552d038a69 444 __DSB(); //ensure completion of the invalidation
Zaitsev 10:41552d038a69 445 __ISB(); //ensure instruction fetch path sees new I cache state
Zaitsev 10:41552d038a69 446 }
Zaitsev 10:41552d038a69 447
Zaitsev 10:41552d038a69 448 /** \brief Clean D$ by MVA
Zaitsev 10:41552d038a69 449
Zaitsev 10:41552d038a69 450 DCCMVAC. Data cache clean by MVA to PoC
Zaitsev 10:41552d038a69 451 */
Zaitsev 10:41552d038a69 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Zaitsev 10:41552d038a69 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Zaitsev 10:41552d038a69 454 __DCCMVAC = (uint32_t)va;
Zaitsev 10:41552d038a69 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Zaitsev 10:41552d038a69 456 }
Zaitsev 10:41552d038a69 457
Zaitsev 10:41552d038a69 458 /** \brief Invalidate D$ by MVA
Zaitsev 10:41552d038a69 459
Zaitsev 10:41552d038a69 460 DCIMVAC. Data cache invalidate by MVA to PoC
Zaitsev 10:41552d038a69 461 */
Zaitsev 10:41552d038a69 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Zaitsev 10:41552d038a69 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Zaitsev 10:41552d038a69 464 __DCIMVAC = (uint32_t)va;
Zaitsev 10:41552d038a69 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Zaitsev 10:41552d038a69 466 }
Zaitsev 10:41552d038a69 467
Zaitsev 10:41552d038a69 468 /** \brief Clean and Invalidate D$ by MVA
Zaitsev 10:41552d038a69 469
Zaitsev 10:41552d038a69 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Zaitsev 10:41552d038a69 471 */
Zaitsev 10:41552d038a69 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Zaitsev 10:41552d038a69 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Zaitsev 10:41552d038a69 474 __DCCIMVAC = (uint32_t)va;
Zaitsev 10:41552d038a69 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Zaitsev 10:41552d038a69 476 }
Zaitsev 10:41552d038a69 477
Zaitsev 10:41552d038a69 478 /** \brief Clean and Invalidate the entire data or unified cache
Zaitsev 10:41552d038a69 479
Zaitsev 10:41552d038a69 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Zaitsev 10:41552d038a69 481 */
Zaitsev 10:41552d038a69 482 #pragma push
Zaitsev 10:41552d038a69 483 #pragma arm
Zaitsev 10:41552d038a69 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Zaitsev 10:41552d038a69 485 ARM
Zaitsev 10:41552d038a69 486
Zaitsev 10:41552d038a69 487 PUSH {R4-R11}
Zaitsev 10:41552d038a69 488
Zaitsev 10:41552d038a69 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Zaitsev 10:41552d038a69 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Zaitsev 10:41552d038a69 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Zaitsev 10:41552d038a69 492 BEQ Finished // If 0, no need to clean
Zaitsev 10:41552d038a69 493
Zaitsev 10:41552d038a69 494 MOV R10, #0 // R10 holds current cache level << 1
Zaitsev 10:41552d038a69 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Zaitsev 10:41552d038a69 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Zaitsev 10:41552d038a69 497 AND R1, R1, #7 // Isolate those lower 3 bits
Zaitsev 10:41552d038a69 498 CMP R1, #2
Zaitsev 10:41552d038a69 499 BLT Skip // No cache or only instruction cache at this level
Zaitsev 10:41552d038a69 500
Zaitsev 10:41552d038a69 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Zaitsev 10:41552d038a69 502 ISB // ISB to sync the change to the CacheSizeID reg
Zaitsev 10:41552d038a69 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Zaitsev 10:41552d038a69 504 AND R2, R1, #7 // Extract the line length field
Zaitsev 10:41552d038a69 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Zaitsev 10:41552d038a69 506 LDR R4, =0x3FF
Zaitsev 10:41552d038a69 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Zaitsev 10:41552d038a69 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Zaitsev 10:41552d038a69 509 LDR R7, =0x7FFF
Zaitsev 10:41552d038a69 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Zaitsev 10:41552d038a69 511
Zaitsev 10:41552d038a69 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Zaitsev 10:41552d038a69 513
Zaitsev 10:41552d038a69 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Zaitsev 10:41552d038a69 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Zaitsev 10:41552d038a69 516 CMP R0, #0
Zaitsev 10:41552d038a69 517 BNE Dccsw
Zaitsev 10:41552d038a69 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Zaitsev 10:41552d038a69 519 B cont
Zaitsev 10:41552d038a69 520 Dccsw CMP R0, #1
Zaitsev 10:41552d038a69 521 BNE Dccisw
Zaitsev 10:41552d038a69 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Zaitsev 10:41552d038a69 523 B cont
Zaitsev 10:41552d038a69 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Zaitsev 10:41552d038a69 525 cont SUBS R9, R9, #1 // Decrement the Way number
Zaitsev 10:41552d038a69 526 BGE Loop3
Zaitsev 10:41552d038a69 527 SUBS R7, R7, #1 // Decrement the Set number
Zaitsev 10:41552d038a69 528 BGE Loop2
Zaitsev 10:41552d038a69 529 Skip ADD R10, R10, #2 // Increment the cache number
Zaitsev 10:41552d038a69 530 CMP R3, R10
Zaitsev 10:41552d038a69 531 BGT Loop1
Zaitsev 10:41552d038a69 532
Zaitsev 10:41552d038a69 533 Finished
Zaitsev 10:41552d038a69 534 DSB
Zaitsev 10:41552d038a69 535 POP {R4-R11}
Zaitsev 10:41552d038a69 536 BX lr
Zaitsev 10:41552d038a69 537
Zaitsev 10:41552d038a69 538 }
Zaitsev 10:41552d038a69 539 #pragma pop
Zaitsev 10:41552d038a69 540
Zaitsev 10:41552d038a69 541
Zaitsev 10:41552d038a69 542 /** \brief Invalidate the whole D$
Zaitsev 10:41552d038a69 543
Zaitsev 10:41552d038a69 544 DCISW. Invalidate by Set/Way
Zaitsev 10:41552d038a69 545 */
Zaitsev 10:41552d038a69 546
Zaitsev 10:41552d038a69 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Zaitsev 10:41552d038a69 548 __v7_all_cache(0);
Zaitsev 10:41552d038a69 549 }
Zaitsev 10:41552d038a69 550
Zaitsev 10:41552d038a69 551 /** \brief Clean the whole D$
Zaitsev 10:41552d038a69 552
Zaitsev 10:41552d038a69 553 DCCSW. Clean by Set/Way
Zaitsev 10:41552d038a69 554 */
Zaitsev 10:41552d038a69 555
Zaitsev 10:41552d038a69 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Zaitsev 10:41552d038a69 557 __v7_all_cache(1);
Zaitsev 10:41552d038a69 558 }
Zaitsev 10:41552d038a69 559
Zaitsev 10:41552d038a69 560 /** \brief Clean and invalidate the whole D$
Zaitsev 10:41552d038a69 561
Zaitsev 10:41552d038a69 562 DCCISW. Clean and Invalidate by Set/Way
Zaitsev 10:41552d038a69 563 */
Zaitsev 10:41552d038a69 564
Zaitsev 10:41552d038a69 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Zaitsev 10:41552d038a69 566 __v7_all_cache(2);
Zaitsev 10:41552d038a69 567 }
Zaitsev 10:41552d038a69 568
Zaitsev 10:41552d038a69 569 #include "core_ca_mmu.h"
Zaitsev 10:41552d038a69 570
Zaitsev 10:41552d038a69 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Zaitsev 10:41552d038a69 572
Zaitsev 10:41552d038a69 573 #define __inline inline
Zaitsev 10:41552d038a69 574
Zaitsev 10:41552d038a69 575 inline static uint32_t __disable_irq_iar() {
Zaitsev 10:41552d038a69 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Zaitsev 10:41552d038a69 577 __disable_irq();
Zaitsev 10:41552d038a69 578 return irq_dis;
Zaitsev 10:41552d038a69 579 }
Zaitsev 10:41552d038a69 580
Zaitsev 10:41552d038a69 581 #define MODE_USR 0x10
Zaitsev 10:41552d038a69 582 #define MODE_FIQ 0x11
Zaitsev 10:41552d038a69 583 #define MODE_IRQ 0x12
Zaitsev 10:41552d038a69 584 #define MODE_SVC 0x13
Zaitsev 10:41552d038a69 585 #define MODE_MON 0x16
Zaitsev 10:41552d038a69 586 #define MODE_ABT 0x17
Zaitsev 10:41552d038a69 587 #define MODE_HYP 0x1A
Zaitsev 10:41552d038a69 588 #define MODE_UND 0x1B
Zaitsev 10:41552d038a69 589 #define MODE_SYS 0x1F
Zaitsev 10:41552d038a69 590
Zaitsev 10:41552d038a69 591 /** \brief Set Process Stack Pointer
Zaitsev 10:41552d038a69 592
Zaitsev 10:41552d038a69 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Zaitsev 10:41552d038a69 594
Zaitsev 10:41552d038a69 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Zaitsev 10:41552d038a69 596 */
Zaitsev 10:41552d038a69 597 // from rt_CMSIS.c
Zaitsev 10:41552d038a69 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Zaitsev 10:41552d038a69 599 __asm(
Zaitsev 10:41552d038a69 600 " ARM\n"
Zaitsev 10:41552d038a69 601 // " PRESERVE8\n"
Zaitsev 10:41552d038a69 602
Zaitsev 10:41552d038a69 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Zaitsev 10:41552d038a69 604 " MRS R1, CPSR \n"
Zaitsev 10:41552d038a69 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Zaitsev 10:41552d038a69 606 " MOV SP, R0 \n"
Zaitsev 10:41552d038a69 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Zaitsev 10:41552d038a69 608 " ISB \n"
Zaitsev 10:41552d038a69 609 " BX LR \n");
Zaitsev 10:41552d038a69 610 }
Zaitsev 10:41552d038a69 611
Zaitsev 10:41552d038a69 612 /** \brief Set User Mode
Zaitsev 10:41552d038a69 613
Zaitsev 10:41552d038a69 614 This function changes the processor state to User Mode
Zaitsev 10:41552d038a69 615 */
Zaitsev 10:41552d038a69 616 // from rt_CMSIS.c
Zaitsev 10:41552d038a69 617 __arm static inline void __set_CPS_USR(void) {
Zaitsev 10:41552d038a69 618 __asm(
Zaitsev 10:41552d038a69 619 " ARM \n"
Zaitsev 10:41552d038a69 620
Zaitsev 10:41552d038a69 621 " CPS #0x10 \n" // MODE_USR
Zaitsev 10:41552d038a69 622 " BX LR\n");
Zaitsev 10:41552d038a69 623 }
Zaitsev 10:41552d038a69 624
Zaitsev 10:41552d038a69 625 /** \brief Set TTBR0
Zaitsev 10:41552d038a69 626
Zaitsev 10:41552d038a69 627 This function assigns the given value to the Translation Table Base Register 0.
Zaitsev 10:41552d038a69 628
Zaitsev 10:41552d038a69 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Zaitsev 10:41552d038a69 630 */
Zaitsev 10:41552d038a69 631 // from mmu_Renesas_RZ_A1.c
Zaitsev 10:41552d038a69 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Zaitsev 10:41552d038a69 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Zaitsev 10:41552d038a69 634 __ISB();
Zaitsev 10:41552d038a69 635 }
Zaitsev 10:41552d038a69 636
Zaitsev 10:41552d038a69 637 /** \brief Set DACR
Zaitsev 10:41552d038a69 638
Zaitsev 10:41552d038a69 639 This function assigns the given value to the Domain Access Control Register.
Zaitsev 10:41552d038a69 640
Zaitsev 10:41552d038a69 641 \param [in] dacr Domain Access Control Register value to set
Zaitsev 10:41552d038a69 642 */
Zaitsev 10:41552d038a69 643 // from mmu_Renesas_RZ_A1.c
Zaitsev 10:41552d038a69 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Zaitsev 10:41552d038a69 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Zaitsev 10:41552d038a69 646 __ISB();
Zaitsev 10:41552d038a69 647 }
Zaitsev 10:41552d038a69 648
Zaitsev 10:41552d038a69 649
Zaitsev 10:41552d038a69 650 /******************************** Cache and BTAC enable ****************************************************/
Zaitsev 10:41552d038a69 651 /** \brief Set SCTLR
Zaitsev 10:41552d038a69 652
Zaitsev 10:41552d038a69 653 This function assigns the given value to the System Control Register.
Zaitsev 10:41552d038a69 654
Zaitsev 10:41552d038a69 655 \param [in] sctlr System Control Register value to set
Zaitsev 10:41552d038a69 656 */
Zaitsev 10:41552d038a69 657 // from __enable_mmu()
Zaitsev 10:41552d038a69 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Zaitsev 10:41552d038a69 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Zaitsev 10:41552d038a69 660 }
Zaitsev 10:41552d038a69 661
Zaitsev 10:41552d038a69 662 /** \brief Get SCTLR
Zaitsev 10:41552d038a69 663
Zaitsev 10:41552d038a69 664 This function returns the value of the System Control Register.
Zaitsev 10:41552d038a69 665
Zaitsev 10:41552d038a69 666 \return System Control Register value
Zaitsev 10:41552d038a69 667 */
Zaitsev 10:41552d038a69 668 // from __enable_mmu()
Zaitsev 10:41552d038a69 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Zaitsev 10:41552d038a69 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Zaitsev 10:41552d038a69 671 return __regSCTLR;
Zaitsev 10:41552d038a69 672 }
Zaitsev 10:41552d038a69 673
Zaitsev 10:41552d038a69 674 /** \brief Enable Caches
Zaitsev 10:41552d038a69 675
Zaitsev 10:41552d038a69 676 Enable Caches
Zaitsev 10:41552d038a69 677 */
Zaitsev 10:41552d038a69 678 // from system_Renesas_RZ_A1.c
Zaitsev 10:41552d038a69 679 __STATIC_INLINE void __enable_caches(void) {
Zaitsev 10:41552d038a69 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Zaitsev 10:41552d038a69 681 }
Zaitsev 10:41552d038a69 682
Zaitsev 10:41552d038a69 683 /** \brief Enable BTAC
Zaitsev 10:41552d038a69 684
Zaitsev 10:41552d038a69 685 Enable BTAC
Zaitsev 10:41552d038a69 686 */
Zaitsev 10:41552d038a69 687 // from system_Renesas_RZ_A1.c
Zaitsev 10:41552d038a69 688 __STATIC_INLINE void __enable_btac(void) {
Zaitsev 10:41552d038a69 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Zaitsev 10:41552d038a69 690 __ISB();
Zaitsev 10:41552d038a69 691 }
Zaitsev 10:41552d038a69 692
Zaitsev 10:41552d038a69 693 /** \brief Enable MMU
Zaitsev 10:41552d038a69 694
Zaitsev 10:41552d038a69 695 Enable MMU
Zaitsev 10:41552d038a69 696 */
Zaitsev 10:41552d038a69 697 // from system_Renesas_RZ_A1.c
Zaitsev 10:41552d038a69 698 __STATIC_INLINE void __enable_mmu(void) {
Zaitsev 10:41552d038a69 699 // Set M bit 0 to enable the MMU
Zaitsev 10:41552d038a69 700 // Set AFE bit to enable simplified access permissions model
Zaitsev 10:41552d038a69 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Zaitsev 10:41552d038a69 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Zaitsev 10:41552d038a69 703 __ISB();
Zaitsev 10:41552d038a69 704 }
Zaitsev 10:41552d038a69 705
Zaitsev 10:41552d038a69 706 /******************************** TLB maintenance operations ************************************************/
Zaitsev 10:41552d038a69 707 /** \brief Invalidate the whole tlb
Zaitsev 10:41552d038a69 708
Zaitsev 10:41552d038a69 709 TLBIALL. Invalidate the whole tlb
Zaitsev 10:41552d038a69 710 */
Zaitsev 10:41552d038a69 711 // from system_Renesas_RZ_A1.c
Zaitsev 10:41552d038a69 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Zaitsev 10:41552d038a69 713 uint32_t val = 0;
Zaitsev 10:41552d038a69 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Zaitsev 10:41552d038a69 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Zaitsev 10:41552d038a69 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Zaitsev 10:41552d038a69 717 __DSB();
Zaitsev 10:41552d038a69 718 __ISB();
Zaitsev 10:41552d038a69 719 }
Zaitsev 10:41552d038a69 720
Zaitsev 10:41552d038a69 721 /******************************** BTB maintenance operations ************************************************/
Zaitsev 10:41552d038a69 722 /** \brief Invalidate entire branch predictor array
Zaitsev 10:41552d038a69 723
Zaitsev 10:41552d038a69 724 BPIALL. Branch Predictor Invalidate All.
Zaitsev 10:41552d038a69 725 */
Zaitsev 10:41552d038a69 726 // from system_Renesas_RZ_A1.c
Zaitsev 10:41552d038a69 727 __STATIC_INLINE void __v7_inv_btac(void) {
Zaitsev 10:41552d038a69 728 uint32_t val = 0;
Zaitsev 10:41552d038a69 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Zaitsev 10:41552d038a69 730 __DSB(); //ensure completion of the invalidation
Zaitsev 10:41552d038a69 731 __ISB(); //ensure instruction fetch path sees new state
Zaitsev 10:41552d038a69 732 }
Zaitsev 10:41552d038a69 733
Zaitsev 10:41552d038a69 734
Zaitsev 10:41552d038a69 735 /******************************** L1 cache operations ******************************************************/
Zaitsev 10:41552d038a69 736
Zaitsev 10:41552d038a69 737 /** \brief Invalidate the whole I$
Zaitsev 10:41552d038a69 738
Zaitsev 10:41552d038a69 739 ICIALLU. Instruction Cache Invalidate All to PoU
Zaitsev 10:41552d038a69 740 */
Zaitsev 10:41552d038a69 741 // from system_Renesas_RZ_A1.c
Zaitsev 10:41552d038a69 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Zaitsev 10:41552d038a69 743 uint32_t val = 0;
Zaitsev 10:41552d038a69 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Zaitsev 10:41552d038a69 745 __DSB(); //ensure completion of the invalidation
Zaitsev 10:41552d038a69 746 __ISB(); //ensure instruction fetch path sees new I cache state
Zaitsev 10:41552d038a69 747 }
Zaitsev 10:41552d038a69 748
Zaitsev 10:41552d038a69 749 // from __v7_inv_dcache_all()
Zaitsev 10:41552d038a69 750 __arm static inline void __v7_all_cache(uint32_t op) {
Zaitsev 10:41552d038a69 751 __asm(
Zaitsev 10:41552d038a69 752 " ARM \n"
Zaitsev 10:41552d038a69 753
Zaitsev 10:41552d038a69 754 " PUSH {R4-R11} \n"
Zaitsev 10:41552d038a69 755
Zaitsev 10:41552d038a69 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Zaitsev 10:41552d038a69 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Zaitsev 10:41552d038a69 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Zaitsev 10:41552d038a69 759 " BEQ Finished\n" // If 0, no need to clean
Zaitsev 10:41552d038a69 760
Zaitsev 10:41552d038a69 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Zaitsev 10:41552d038a69 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Zaitsev 10:41552d038a69 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Zaitsev 10:41552d038a69 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Zaitsev 10:41552d038a69 765 " CMP R1, #2 \n"
Zaitsev 10:41552d038a69 766 " BLT Skip \n" // No cache or only instruction cache at this level
Zaitsev 10:41552d038a69 767
Zaitsev 10:41552d038a69 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Zaitsev 10:41552d038a69 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Zaitsev 10:41552d038a69 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Zaitsev 10:41552d038a69 771 " AND R2, R1, #7 \n" // Extract the line length field
Zaitsev 10:41552d038a69 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Zaitsev 10:41552d038a69 773 " movw R4, #0x3FF \n"
Zaitsev 10:41552d038a69 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Zaitsev 10:41552d038a69 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Zaitsev 10:41552d038a69 776 " movw R7, #0x7FFF \n"
Zaitsev 10:41552d038a69 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Zaitsev 10:41552d038a69 778
Zaitsev 10:41552d038a69 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Zaitsev 10:41552d038a69 780
Zaitsev 10:41552d038a69 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Zaitsev 10:41552d038a69 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Zaitsev 10:41552d038a69 783 " CMP R0, #0 \n"
Zaitsev 10:41552d038a69 784 " BNE Dccsw \n"
Zaitsev 10:41552d038a69 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Zaitsev 10:41552d038a69 786 " B cont \n"
Zaitsev 10:41552d038a69 787 "Dccsw: CMP R0, #1 \n"
Zaitsev 10:41552d038a69 788 " BNE Dccisw \n"
Zaitsev 10:41552d038a69 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Zaitsev 10:41552d038a69 790 " B cont \n"
Zaitsev 10:41552d038a69 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Zaitsev 10:41552d038a69 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Zaitsev 10:41552d038a69 793 " BGE Loop3 \n"
Zaitsev 10:41552d038a69 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Zaitsev 10:41552d038a69 795 " BGE Loop2 \n"
Zaitsev 10:41552d038a69 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Zaitsev 10:41552d038a69 797 " CMP R3, R10 \n"
Zaitsev 10:41552d038a69 798 " BGT Loop1 \n"
Zaitsev 10:41552d038a69 799
Zaitsev 10:41552d038a69 800 "Finished: \n"
Zaitsev 10:41552d038a69 801 " DSB \n"
Zaitsev 10:41552d038a69 802 " POP {R4-R11} \n"
Zaitsev 10:41552d038a69 803 " BX lr \n" );
Zaitsev 10:41552d038a69 804 }
Zaitsev 10:41552d038a69 805
Zaitsev 10:41552d038a69 806 /** \brief Invalidate the whole D$
Zaitsev 10:41552d038a69 807
Zaitsev 10:41552d038a69 808 DCISW. Invalidate by Set/Way
Zaitsev 10:41552d038a69 809 */
Zaitsev 10:41552d038a69 810 // from system_Renesas_RZ_A1.c
Zaitsev 10:41552d038a69 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Zaitsev 10:41552d038a69 812 __v7_all_cache(0);
Zaitsev 10:41552d038a69 813 }
Zaitsev 10:41552d038a69 814 /** \brief Clean the whole D$
Zaitsev 10:41552d038a69 815
Zaitsev 10:41552d038a69 816 DCCSW. Clean by Set/Way
Zaitsev 10:41552d038a69 817 */
Zaitsev 10:41552d038a69 818
Zaitsev 10:41552d038a69 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Zaitsev 10:41552d038a69 820 __v7_all_cache(1);
Zaitsev 10:41552d038a69 821 }
Zaitsev 10:41552d038a69 822
Zaitsev 10:41552d038a69 823 /** \brief Clean and invalidate the whole D$
Zaitsev 10:41552d038a69 824
Zaitsev 10:41552d038a69 825 DCCISW. Clean and Invalidate by Set/Way
Zaitsev 10:41552d038a69 826 */
Zaitsev 10:41552d038a69 827
Zaitsev 10:41552d038a69 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Zaitsev 10:41552d038a69 829 __v7_all_cache(2);
Zaitsev 10:41552d038a69 830 }
Zaitsev 10:41552d038a69 831 /** \brief Clean and Invalidate D$ by MVA
Zaitsev 10:41552d038a69 832
Zaitsev 10:41552d038a69 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Zaitsev 10:41552d038a69 834 */
Zaitsev 10:41552d038a69 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Zaitsev 10:41552d038a69 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
Zaitsev 10:41552d038a69 837 __DMB();
Zaitsev 10:41552d038a69 838 }
Zaitsev 10:41552d038a69 839
Zaitsev 10:41552d038a69 840 #include "core_ca_mmu.h"
Zaitsev 10:41552d038a69 841
Zaitsev 10:41552d038a69 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Zaitsev 10:41552d038a69 843 /* GNU gcc specific functions */
Zaitsev 10:41552d038a69 844
Zaitsev 10:41552d038a69 845 #define MODE_USR 0x10
Zaitsev 10:41552d038a69 846 #define MODE_FIQ 0x11
Zaitsev 10:41552d038a69 847 #define MODE_IRQ 0x12
Zaitsev 10:41552d038a69 848 #define MODE_SVC 0x13
Zaitsev 10:41552d038a69 849 #define MODE_MON 0x16
Zaitsev 10:41552d038a69 850 #define MODE_ABT 0x17
Zaitsev 10:41552d038a69 851 #define MODE_HYP 0x1A
Zaitsev 10:41552d038a69 852 #define MODE_UND 0x1B
Zaitsev 10:41552d038a69 853 #define MODE_SYS 0x1F
Zaitsev 10:41552d038a69 854
Zaitsev 10:41552d038a69 855
Zaitsev 10:41552d038a69 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Zaitsev 10:41552d038a69 857 {
Zaitsev 10:41552d038a69 858 __ASM volatile ("cpsie i");
Zaitsev 10:41552d038a69 859 }
Zaitsev 10:41552d038a69 860
Zaitsev 10:41552d038a69 861 /** \brief Disable IRQ Interrupts
Zaitsev 10:41552d038a69 862
Zaitsev 10:41552d038a69 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Zaitsev 10:41552d038a69 864 Can only be executed in Privileged modes.
Zaitsev 10:41552d038a69 865 */
Zaitsev 10:41552d038a69 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Zaitsev 10:41552d038a69 867 {
Zaitsev 10:41552d038a69 868 uint32_t result;
Zaitsev 10:41552d038a69 869
Zaitsev 10:41552d038a69 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Zaitsev 10:41552d038a69 871 __ASM volatile ("cpsid i");
Zaitsev 10:41552d038a69 872 return(result & 0x80);
Zaitsev 10:41552d038a69 873 }
Zaitsev 10:41552d038a69 874
Zaitsev 10:41552d038a69 875
Zaitsev 10:41552d038a69 876 /** \brief Get APSR Register
Zaitsev 10:41552d038a69 877
Zaitsev 10:41552d038a69 878 This function returns the content of the APSR Register.
Zaitsev 10:41552d038a69 879
Zaitsev 10:41552d038a69 880 \return APSR Register value
Zaitsev 10:41552d038a69 881 */
Zaitsev 10:41552d038a69 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Zaitsev 10:41552d038a69 883 {
Zaitsev 10:41552d038a69 884 #if 1
Zaitsev 10:41552d038a69 885 register uint32_t __regAPSR;
Zaitsev 10:41552d038a69 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Zaitsev 10:41552d038a69 887 #else
Zaitsev 10:41552d038a69 888 register uint32_t __regAPSR __ASM("apsr");
Zaitsev 10:41552d038a69 889 #endif
Zaitsev 10:41552d038a69 890 return(__regAPSR);
Zaitsev 10:41552d038a69 891 }
Zaitsev 10:41552d038a69 892
Zaitsev 10:41552d038a69 893
Zaitsev 10:41552d038a69 894 /** \brief Get CPSR Register
Zaitsev 10:41552d038a69 895
Zaitsev 10:41552d038a69 896 This function returns the content of the CPSR Register.
Zaitsev 10:41552d038a69 897
Zaitsev 10:41552d038a69 898 \return CPSR Register value
Zaitsev 10:41552d038a69 899 */
Zaitsev 10:41552d038a69 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Zaitsev 10:41552d038a69 901 {
Zaitsev 10:41552d038a69 902 #if 1
Zaitsev 10:41552d038a69 903 register uint32_t __regCPSR;
Zaitsev 10:41552d038a69 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Zaitsev 10:41552d038a69 905 #else
Zaitsev 10:41552d038a69 906 register uint32_t __regCPSR __ASM("cpsr");
Zaitsev 10:41552d038a69 907 #endif
Zaitsev 10:41552d038a69 908 return(__regCPSR);
Zaitsev 10:41552d038a69 909 }
Zaitsev 10:41552d038a69 910
Zaitsev 10:41552d038a69 911 #if 0
Zaitsev 10:41552d038a69 912 /** \brief Set Stack Pointer
Zaitsev 10:41552d038a69 913
Zaitsev 10:41552d038a69 914 This function assigns the given value to the current stack pointer.
Zaitsev 10:41552d038a69 915
Zaitsev 10:41552d038a69 916 \param [in] topOfStack Stack Pointer value to set
Zaitsev 10:41552d038a69 917 */
Zaitsev 10:41552d038a69 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Zaitsev 10:41552d038a69 919 {
Zaitsev 10:41552d038a69 920 register uint32_t __regSP __ASM("sp");
Zaitsev 10:41552d038a69 921 __regSP = topOfStack;
Zaitsev 10:41552d038a69 922 }
Zaitsev 10:41552d038a69 923 #endif
Zaitsev 10:41552d038a69 924
Zaitsev 10:41552d038a69 925 /** \brief Get link register
Zaitsev 10:41552d038a69 926
Zaitsev 10:41552d038a69 927 This function returns the value of the link register
Zaitsev 10:41552d038a69 928
Zaitsev 10:41552d038a69 929 \return Value of link register
Zaitsev 10:41552d038a69 930 */
Zaitsev 10:41552d038a69 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Zaitsev 10:41552d038a69 932 {
Zaitsev 10:41552d038a69 933 register uint32_t __reglr __ASM("lr");
Zaitsev 10:41552d038a69 934 return(__reglr);
Zaitsev 10:41552d038a69 935 }
Zaitsev 10:41552d038a69 936
Zaitsev 10:41552d038a69 937 #if 0
Zaitsev 10:41552d038a69 938 /** \brief Set link register
Zaitsev 10:41552d038a69 939
Zaitsev 10:41552d038a69 940 This function sets the value of the link register
Zaitsev 10:41552d038a69 941
Zaitsev 10:41552d038a69 942 \param [in] lr LR value to set
Zaitsev 10:41552d038a69 943 */
Zaitsev 10:41552d038a69 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Zaitsev 10:41552d038a69 945 {
Zaitsev 10:41552d038a69 946 register uint32_t __reglr __ASM("lr");
Zaitsev 10:41552d038a69 947 __reglr = lr;
Zaitsev 10:41552d038a69 948 }
Zaitsev 10:41552d038a69 949 #endif
Zaitsev 10:41552d038a69 950
Zaitsev 10:41552d038a69 951 /** \brief Set Process Stack Pointer
Zaitsev 10:41552d038a69 952
Zaitsev 10:41552d038a69 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Zaitsev 10:41552d038a69 954
Zaitsev 10:41552d038a69 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Zaitsev 10:41552d038a69 956 */
Zaitsev 10:41552d038a69 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Zaitsev 10:41552d038a69 958 {
Zaitsev 10:41552d038a69 959 __asm__ volatile (
Zaitsev 10:41552d038a69 960 ".ARM;"
Zaitsev 10:41552d038a69 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Zaitsev 10:41552d038a69 962
Zaitsev 10:41552d038a69 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Zaitsev 10:41552d038a69 964 "MRS R1, CPSR;"
Zaitsev 10:41552d038a69 965 "CPS %0;" /* ;no effect in USR mode */
Zaitsev 10:41552d038a69 966 "MOV SP, R0;"
Zaitsev 10:41552d038a69 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Zaitsev 10:41552d038a69 968 "ISB;"
Zaitsev 10:41552d038a69 969 //"BX LR;"
Zaitsev 10:41552d038a69 970 :
Zaitsev 10:41552d038a69 971 : "i"(MODE_SYS)
Zaitsev 10:41552d038a69 972 : "r0", "r1");
Zaitsev 10:41552d038a69 973 return;
Zaitsev 10:41552d038a69 974 }
Zaitsev 10:41552d038a69 975
Zaitsev 10:41552d038a69 976 /** \brief Set User Mode
Zaitsev 10:41552d038a69 977
Zaitsev 10:41552d038a69 978 This function changes the processor state to User Mode
Zaitsev 10:41552d038a69 979 */
Zaitsev 10:41552d038a69 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Zaitsev 10:41552d038a69 981 {
Zaitsev 10:41552d038a69 982 __asm__ volatile (
Zaitsev 10:41552d038a69 983 ".ARM;"
Zaitsev 10:41552d038a69 984
Zaitsev 10:41552d038a69 985 "CPS %0;"
Zaitsev 10:41552d038a69 986 //"BX LR;"
Zaitsev 10:41552d038a69 987 :
Zaitsev 10:41552d038a69 988 : "i"(MODE_USR)
Zaitsev 10:41552d038a69 989 : );
Zaitsev 10:41552d038a69 990 return;
Zaitsev 10:41552d038a69 991 }
Zaitsev 10:41552d038a69 992
Zaitsev 10:41552d038a69 993
Zaitsev 10:41552d038a69 994 /** \brief Enable FIQ
Zaitsev 10:41552d038a69 995
Zaitsev 10:41552d038a69 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Zaitsev 10:41552d038a69 997 Can only be executed in Privileged modes.
Zaitsev 10:41552d038a69 998 */
Zaitsev 10:41552d038a69 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Zaitsev 10:41552d038a69 1000
Zaitsev 10:41552d038a69 1001
Zaitsev 10:41552d038a69 1002 /** \brief Disable FIQ
Zaitsev 10:41552d038a69 1003
Zaitsev 10:41552d038a69 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Zaitsev 10:41552d038a69 1005 Can only be executed in Privileged modes.
Zaitsev 10:41552d038a69 1006 */
Zaitsev 10:41552d038a69 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Zaitsev 10:41552d038a69 1008
Zaitsev 10:41552d038a69 1009
Zaitsev 10:41552d038a69 1010 /** \brief Get FPSCR
Zaitsev 10:41552d038a69 1011
Zaitsev 10:41552d038a69 1012 This function returns the current value of the Floating Point Status/Control register.
Zaitsev 10:41552d038a69 1013
Zaitsev 10:41552d038a69 1014 \return Floating Point Status/Control register value
Zaitsev 10:41552d038a69 1015 */
Zaitsev 10:41552d038a69 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Zaitsev 10:41552d038a69 1017 {
Zaitsev 10:41552d038a69 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Zaitsev 10:41552d038a69 1019 #if 1
Zaitsev 10:41552d038a69 1020 uint32_t result;
Zaitsev 10:41552d038a69 1021
Zaitsev 10:41552d038a69 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Zaitsev 10:41552d038a69 1023 return (result);
Zaitsev 10:41552d038a69 1024 #else
Zaitsev 10:41552d038a69 1025 register uint32_t __regfpscr __ASM("fpscr");
Zaitsev 10:41552d038a69 1026 return(__regfpscr);
Zaitsev 10:41552d038a69 1027 #endif
Zaitsev 10:41552d038a69 1028 #else
Zaitsev 10:41552d038a69 1029 return(0);
Zaitsev 10:41552d038a69 1030 #endif
Zaitsev 10:41552d038a69 1031 }
Zaitsev 10:41552d038a69 1032
Zaitsev 10:41552d038a69 1033
Zaitsev 10:41552d038a69 1034 /** \brief Set FPSCR
Zaitsev 10:41552d038a69 1035
Zaitsev 10:41552d038a69 1036 This function assigns the given value to the Floating Point Status/Control register.
Zaitsev 10:41552d038a69 1037
Zaitsev 10:41552d038a69 1038 \param [in] fpscr Floating Point Status/Control value to set
Zaitsev 10:41552d038a69 1039 */
Zaitsev 10:41552d038a69 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Zaitsev 10:41552d038a69 1041 {
Zaitsev 10:41552d038a69 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Zaitsev 10:41552d038a69 1043 #if 1
Zaitsev 10:41552d038a69 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Zaitsev 10:41552d038a69 1045 #else
Zaitsev 10:41552d038a69 1046 register uint32_t __regfpscr __ASM("fpscr");
Zaitsev 10:41552d038a69 1047 __regfpscr = (fpscr);
Zaitsev 10:41552d038a69 1048 #endif
Zaitsev 10:41552d038a69 1049 #endif
Zaitsev 10:41552d038a69 1050 }
Zaitsev 10:41552d038a69 1051
Zaitsev 10:41552d038a69 1052 /** \brief Get FPEXC
Zaitsev 10:41552d038a69 1053
Zaitsev 10:41552d038a69 1054 This function returns the current value of the Floating Point Exception Control register.
Zaitsev 10:41552d038a69 1055
Zaitsev 10:41552d038a69 1056 \return Floating Point Exception Control register value
Zaitsev 10:41552d038a69 1057 */
Zaitsev 10:41552d038a69 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Zaitsev 10:41552d038a69 1059 {
Zaitsev 10:41552d038a69 1060 #if (__FPU_PRESENT == 1)
Zaitsev 10:41552d038a69 1061 #if 1
Zaitsev 10:41552d038a69 1062 uint32_t result;
Zaitsev 10:41552d038a69 1063
Zaitsev 10:41552d038a69 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Zaitsev 10:41552d038a69 1065 return (result);
Zaitsev 10:41552d038a69 1066 #else
Zaitsev 10:41552d038a69 1067 register uint32_t __regfpexc __ASM("fpexc");
Zaitsev 10:41552d038a69 1068 return(__regfpexc);
Zaitsev 10:41552d038a69 1069 #endif
Zaitsev 10:41552d038a69 1070 #else
Zaitsev 10:41552d038a69 1071 return(0);
Zaitsev 10:41552d038a69 1072 #endif
Zaitsev 10:41552d038a69 1073 }
Zaitsev 10:41552d038a69 1074
Zaitsev 10:41552d038a69 1075
Zaitsev 10:41552d038a69 1076 /** \brief Set FPEXC
Zaitsev 10:41552d038a69 1077
Zaitsev 10:41552d038a69 1078 This function assigns the given value to the Floating Point Exception Control register.
Zaitsev 10:41552d038a69 1079
Zaitsev 10:41552d038a69 1080 \param [in] fpscr Floating Point Exception Control value to set
Zaitsev 10:41552d038a69 1081 */
Zaitsev 10:41552d038a69 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Zaitsev 10:41552d038a69 1083 {
Zaitsev 10:41552d038a69 1084 #if (__FPU_PRESENT == 1)
Zaitsev 10:41552d038a69 1085 #if 1
Zaitsev 10:41552d038a69 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Zaitsev 10:41552d038a69 1087 #else
Zaitsev 10:41552d038a69 1088 register uint32_t __regfpexc __ASM("fpexc");
Zaitsev 10:41552d038a69 1089 __regfpexc = (fpexc);
Zaitsev 10:41552d038a69 1090 #endif
Zaitsev 10:41552d038a69 1091 #endif
Zaitsev 10:41552d038a69 1092 }
Zaitsev 10:41552d038a69 1093
Zaitsev 10:41552d038a69 1094 /** \brief Get CPACR
Zaitsev 10:41552d038a69 1095
Zaitsev 10:41552d038a69 1096 This function returns the current value of the Coprocessor Access Control register.
Zaitsev 10:41552d038a69 1097
Zaitsev 10:41552d038a69 1098 \return Coprocessor Access Control register value
Zaitsev 10:41552d038a69 1099 */
Zaitsev 10:41552d038a69 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Zaitsev 10:41552d038a69 1101 {
Zaitsev 10:41552d038a69 1102 #if 1
Zaitsev 10:41552d038a69 1103 register uint32_t __regCPACR;
Zaitsev 10:41552d038a69 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Zaitsev 10:41552d038a69 1105 #else
Zaitsev 10:41552d038a69 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Zaitsev 10:41552d038a69 1107 #endif
Zaitsev 10:41552d038a69 1108 return __regCPACR;
Zaitsev 10:41552d038a69 1109 }
Zaitsev 10:41552d038a69 1110
Zaitsev 10:41552d038a69 1111 /** \brief Set CPACR
Zaitsev 10:41552d038a69 1112
Zaitsev 10:41552d038a69 1113 This function assigns the given value to the Coprocessor Access Control register.
Zaitsev 10:41552d038a69 1114
Zaitsev 10:41552d038a69 1115 \param [in] cpacr Coprocessor Acccess Control value to set
Zaitsev 10:41552d038a69 1116 */
Zaitsev 10:41552d038a69 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Zaitsev 10:41552d038a69 1118 {
Zaitsev 10:41552d038a69 1119 #if 1
Zaitsev 10:41552d038a69 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Zaitsev 10:41552d038a69 1121 #else
Zaitsev 10:41552d038a69 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Zaitsev 10:41552d038a69 1123 __regCPACR = cpacr;
Zaitsev 10:41552d038a69 1124 #endif
Zaitsev 10:41552d038a69 1125 __ISB();
Zaitsev 10:41552d038a69 1126 }
Zaitsev 10:41552d038a69 1127
Zaitsev 10:41552d038a69 1128 /** \brief Get CBAR
Zaitsev 10:41552d038a69 1129
Zaitsev 10:41552d038a69 1130 This function returns the value of the Configuration Base Address register.
Zaitsev 10:41552d038a69 1131
Zaitsev 10:41552d038a69 1132 \return Configuration Base Address register value
Zaitsev 10:41552d038a69 1133 */
Zaitsev 10:41552d038a69 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Zaitsev 10:41552d038a69 1135 #if 1
Zaitsev 10:41552d038a69 1136 register uint32_t __regCBAR;
Zaitsev 10:41552d038a69 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Zaitsev 10:41552d038a69 1138 #else
Zaitsev 10:41552d038a69 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Zaitsev 10:41552d038a69 1140 #endif
Zaitsev 10:41552d038a69 1141 return(__regCBAR);
Zaitsev 10:41552d038a69 1142 }
Zaitsev 10:41552d038a69 1143
Zaitsev 10:41552d038a69 1144 /** \brief Get TTBR0
Zaitsev 10:41552d038a69 1145
Zaitsev 10:41552d038a69 1146 This function returns the value of the Translation Table Base Register 0.
Zaitsev 10:41552d038a69 1147
Zaitsev 10:41552d038a69 1148 \return Translation Table Base Register 0 value
Zaitsev 10:41552d038a69 1149 */
Zaitsev 10:41552d038a69 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Zaitsev 10:41552d038a69 1151 #if 1
Zaitsev 10:41552d038a69 1152 register uint32_t __regTTBR0;
Zaitsev 10:41552d038a69 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Zaitsev 10:41552d038a69 1154 #else
Zaitsev 10:41552d038a69 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Zaitsev 10:41552d038a69 1156 #endif
Zaitsev 10:41552d038a69 1157 return(__regTTBR0);
Zaitsev 10:41552d038a69 1158 }
Zaitsev 10:41552d038a69 1159
Zaitsev 10:41552d038a69 1160 /** \brief Set TTBR0
Zaitsev 10:41552d038a69 1161
Zaitsev 10:41552d038a69 1162 This function assigns the given value to the Translation Table Base Register 0.
Zaitsev 10:41552d038a69 1163
Zaitsev 10:41552d038a69 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
Zaitsev 10:41552d038a69 1165 */
Zaitsev 10:41552d038a69 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Zaitsev 10:41552d038a69 1167 #if 1
Zaitsev 10:41552d038a69 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Zaitsev 10:41552d038a69 1169 #else
Zaitsev 10:41552d038a69 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Zaitsev 10:41552d038a69 1171 __regTTBR0 = ttbr0;
Zaitsev 10:41552d038a69 1172 #endif
Zaitsev 10:41552d038a69 1173 __ISB();
Zaitsev 10:41552d038a69 1174 }
Zaitsev 10:41552d038a69 1175
Zaitsev 10:41552d038a69 1176 /** \brief Get DACR
Zaitsev 10:41552d038a69 1177
Zaitsev 10:41552d038a69 1178 This function returns the value of the Domain Access Control Register.
Zaitsev 10:41552d038a69 1179
Zaitsev 10:41552d038a69 1180 \return Domain Access Control Register value
Zaitsev 10:41552d038a69 1181 */
Zaitsev 10:41552d038a69 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Zaitsev 10:41552d038a69 1183 #if 1
Zaitsev 10:41552d038a69 1184 register uint32_t __regDACR;
Zaitsev 10:41552d038a69 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Zaitsev 10:41552d038a69 1186 #else
Zaitsev 10:41552d038a69 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Zaitsev 10:41552d038a69 1188 #endif
Zaitsev 10:41552d038a69 1189 return(__regDACR);
Zaitsev 10:41552d038a69 1190 }
Zaitsev 10:41552d038a69 1191
Zaitsev 10:41552d038a69 1192 /** \brief Set DACR
Zaitsev 10:41552d038a69 1193
Zaitsev 10:41552d038a69 1194 This function assigns the given value to the Domain Access Control Register.
Zaitsev 10:41552d038a69 1195
Zaitsev 10:41552d038a69 1196 \param [in] dacr Domain Access Control Register value to set
Zaitsev 10:41552d038a69 1197 */
Zaitsev 10:41552d038a69 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Zaitsev 10:41552d038a69 1199 #if 1
Zaitsev 10:41552d038a69 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Zaitsev 10:41552d038a69 1201 #else
Zaitsev 10:41552d038a69 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Zaitsev 10:41552d038a69 1203 __regDACR = dacr;
Zaitsev 10:41552d038a69 1204 #endif
Zaitsev 10:41552d038a69 1205 __ISB();
Zaitsev 10:41552d038a69 1206 }
Zaitsev 10:41552d038a69 1207
Zaitsev 10:41552d038a69 1208 /******************************** Cache and BTAC enable ****************************************************/
Zaitsev 10:41552d038a69 1209
Zaitsev 10:41552d038a69 1210 /** \brief Set SCTLR
Zaitsev 10:41552d038a69 1211
Zaitsev 10:41552d038a69 1212 This function assigns the given value to the System Control Register.
Zaitsev 10:41552d038a69 1213
Zaitsev 10:41552d038a69 1214 \param [in] sctlr System Control Register value to set
Zaitsev 10:41552d038a69 1215 */
Zaitsev 10:41552d038a69 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Zaitsev 10:41552d038a69 1217 {
Zaitsev 10:41552d038a69 1218 #if 1
Zaitsev 10:41552d038a69 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Zaitsev 10:41552d038a69 1220 #else
Zaitsev 10:41552d038a69 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Zaitsev 10:41552d038a69 1222 __regSCTLR = sctlr;
Zaitsev 10:41552d038a69 1223 #endif
Zaitsev 10:41552d038a69 1224 }
Zaitsev 10:41552d038a69 1225
Zaitsev 10:41552d038a69 1226 /** \brief Get SCTLR
Zaitsev 10:41552d038a69 1227
Zaitsev 10:41552d038a69 1228 This function returns the value of the System Control Register.
Zaitsev 10:41552d038a69 1229
Zaitsev 10:41552d038a69 1230 \return System Control Register value
Zaitsev 10:41552d038a69 1231 */
Zaitsev 10:41552d038a69 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Zaitsev 10:41552d038a69 1233 #if 1
Zaitsev 10:41552d038a69 1234 register uint32_t __regSCTLR;
Zaitsev 10:41552d038a69 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Zaitsev 10:41552d038a69 1236 #else
Zaitsev 10:41552d038a69 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Zaitsev 10:41552d038a69 1238 #endif
Zaitsev 10:41552d038a69 1239 return(__regSCTLR);
Zaitsev 10:41552d038a69 1240 }
Zaitsev 10:41552d038a69 1241
Zaitsev 10:41552d038a69 1242 /** \brief Enable Caches
Zaitsev 10:41552d038a69 1243
Zaitsev 10:41552d038a69 1244 Enable Caches
Zaitsev 10:41552d038a69 1245 */
Zaitsev 10:41552d038a69 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Zaitsev 10:41552d038a69 1247 // Set I bit 12 to enable I Cache
Zaitsev 10:41552d038a69 1248 // Set C bit 2 to enable D Cache
Zaitsev 10:41552d038a69 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Zaitsev 10:41552d038a69 1250 }
Zaitsev 10:41552d038a69 1251
Zaitsev 10:41552d038a69 1252 /** \brief Disable Caches
Zaitsev 10:41552d038a69 1253
Zaitsev 10:41552d038a69 1254 Disable Caches
Zaitsev 10:41552d038a69 1255 */
Zaitsev 10:41552d038a69 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Zaitsev 10:41552d038a69 1257 // Clear I bit 12 to disable I Cache
Zaitsev 10:41552d038a69 1258 // Clear C bit 2 to disable D Cache
Zaitsev 10:41552d038a69 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Zaitsev 10:41552d038a69 1260 __ISB();
Zaitsev 10:41552d038a69 1261 }
Zaitsev 10:41552d038a69 1262
Zaitsev 10:41552d038a69 1263 /** \brief Enable BTAC
Zaitsev 10:41552d038a69 1264
Zaitsev 10:41552d038a69 1265 Enable BTAC
Zaitsev 10:41552d038a69 1266 */
Zaitsev 10:41552d038a69 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Zaitsev 10:41552d038a69 1268 // Set Z bit 11 to enable branch prediction
Zaitsev 10:41552d038a69 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
Zaitsev 10:41552d038a69 1270 __ISB();
Zaitsev 10:41552d038a69 1271 }
Zaitsev 10:41552d038a69 1272
Zaitsev 10:41552d038a69 1273 /** \brief Disable BTAC
Zaitsev 10:41552d038a69 1274
Zaitsev 10:41552d038a69 1275 Disable BTAC
Zaitsev 10:41552d038a69 1276 */
Zaitsev 10:41552d038a69 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Zaitsev 10:41552d038a69 1278 // Clear Z bit 11 to disable branch prediction
Zaitsev 10:41552d038a69 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Zaitsev 10:41552d038a69 1280 }
Zaitsev 10:41552d038a69 1281
Zaitsev 10:41552d038a69 1282
Zaitsev 10:41552d038a69 1283 /** \brief Enable MMU
Zaitsev 10:41552d038a69 1284
Zaitsev 10:41552d038a69 1285 Enable MMU
Zaitsev 10:41552d038a69 1286 */
Zaitsev 10:41552d038a69 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Zaitsev 10:41552d038a69 1288 // Set M bit 0 to enable the MMU
Zaitsev 10:41552d038a69 1289 // Set AFE bit to enable simplified access permissions model
Zaitsev 10:41552d038a69 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Zaitsev 10:41552d038a69 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Zaitsev 10:41552d038a69 1292 __ISB();
Zaitsev 10:41552d038a69 1293 }
Zaitsev 10:41552d038a69 1294
Zaitsev 10:41552d038a69 1295 /** \brief Disable MMU
Zaitsev 10:41552d038a69 1296
Zaitsev 10:41552d038a69 1297 Disable MMU
Zaitsev 10:41552d038a69 1298 */
Zaitsev 10:41552d038a69 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Zaitsev 10:41552d038a69 1300 // Clear M bit 0 to disable the MMU
Zaitsev 10:41552d038a69 1301 __set_SCTLR( __get_SCTLR() & ~1);
Zaitsev 10:41552d038a69 1302 __ISB();
Zaitsev 10:41552d038a69 1303 }
Zaitsev 10:41552d038a69 1304
Zaitsev 10:41552d038a69 1305 /******************************** TLB maintenance operations ************************************************/
Zaitsev 10:41552d038a69 1306 /** \brief Invalidate the whole tlb
Zaitsev 10:41552d038a69 1307
Zaitsev 10:41552d038a69 1308 TLBIALL. Invalidate the whole tlb
Zaitsev 10:41552d038a69 1309 */
Zaitsev 10:41552d038a69 1310
Zaitsev 10:41552d038a69 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Zaitsev 10:41552d038a69 1312 #if 1
Zaitsev 10:41552d038a69 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Zaitsev 10:41552d038a69 1314 #else
Zaitsev 10:41552d038a69 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Zaitsev 10:41552d038a69 1316 __TLBIALL = 0;
Zaitsev 10:41552d038a69 1317 #endif
Zaitsev 10:41552d038a69 1318 __DSB();
Zaitsev 10:41552d038a69 1319 __ISB();
Zaitsev 10:41552d038a69 1320 }
Zaitsev 10:41552d038a69 1321
Zaitsev 10:41552d038a69 1322 /******************************** BTB maintenance operations ************************************************/
Zaitsev 10:41552d038a69 1323 /** \brief Invalidate entire branch predictor array
Zaitsev 10:41552d038a69 1324
Zaitsev 10:41552d038a69 1325 BPIALL. Branch Predictor Invalidate All.
Zaitsev 10:41552d038a69 1326 */
Zaitsev 10:41552d038a69 1327
Zaitsev 10:41552d038a69 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Zaitsev 10:41552d038a69 1329 #if 1
Zaitsev 10:41552d038a69 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Zaitsev 10:41552d038a69 1331 #else
Zaitsev 10:41552d038a69 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Zaitsev 10:41552d038a69 1333 __BPIALL = 0;
Zaitsev 10:41552d038a69 1334 #endif
Zaitsev 10:41552d038a69 1335 __DSB(); //ensure completion of the invalidation
Zaitsev 10:41552d038a69 1336 __ISB(); //ensure instruction fetch path sees new state
Zaitsev 10:41552d038a69 1337 }
Zaitsev 10:41552d038a69 1338
Zaitsev 10:41552d038a69 1339
Zaitsev 10:41552d038a69 1340 /******************************** L1 cache operations ******************************************************/
Zaitsev 10:41552d038a69 1341
Zaitsev 10:41552d038a69 1342 /** \brief Invalidate the whole I$
Zaitsev 10:41552d038a69 1343
Zaitsev 10:41552d038a69 1344 ICIALLU. Instruction Cache Invalidate All to PoU
Zaitsev 10:41552d038a69 1345 */
Zaitsev 10:41552d038a69 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Zaitsev 10:41552d038a69 1347 #if 1
Zaitsev 10:41552d038a69 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Zaitsev 10:41552d038a69 1349 #else
Zaitsev 10:41552d038a69 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Zaitsev 10:41552d038a69 1351 __ICIALLU = 0;
Zaitsev 10:41552d038a69 1352 #endif
Zaitsev 10:41552d038a69 1353 __DSB(); //ensure completion of the invalidation
Zaitsev 10:41552d038a69 1354 __ISB(); //ensure instruction fetch path sees new I cache state
Zaitsev 10:41552d038a69 1355 }
Zaitsev 10:41552d038a69 1356
Zaitsev 10:41552d038a69 1357 /** \brief Clean D$ by MVA
Zaitsev 10:41552d038a69 1358
Zaitsev 10:41552d038a69 1359 DCCMVAC. Data cache clean by MVA to PoC
Zaitsev 10:41552d038a69 1360 */
Zaitsev 10:41552d038a69 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Zaitsev 10:41552d038a69 1362 #if 1
Zaitsev 10:41552d038a69 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Zaitsev 10:41552d038a69 1364 #else
Zaitsev 10:41552d038a69 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Zaitsev 10:41552d038a69 1366 __DCCMVAC = (uint32_t)va;
Zaitsev 10:41552d038a69 1367 #endif
Zaitsev 10:41552d038a69 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Zaitsev 10:41552d038a69 1369 }
Zaitsev 10:41552d038a69 1370
Zaitsev 10:41552d038a69 1371 /** \brief Invalidate D$ by MVA
Zaitsev 10:41552d038a69 1372
Zaitsev 10:41552d038a69 1373 DCIMVAC. Data cache invalidate by MVA to PoC
Zaitsev 10:41552d038a69 1374 */
Zaitsev 10:41552d038a69 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Zaitsev 10:41552d038a69 1376 #if 1
Zaitsev 10:41552d038a69 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Zaitsev 10:41552d038a69 1378 #else
Zaitsev 10:41552d038a69 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Zaitsev 10:41552d038a69 1380 __DCIMVAC = (uint32_t)va;
Zaitsev 10:41552d038a69 1381 #endif
Zaitsev 10:41552d038a69 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Zaitsev 10:41552d038a69 1383 }
Zaitsev 10:41552d038a69 1384
Zaitsev 10:41552d038a69 1385 /** \brief Clean and Invalidate D$ by MVA
Zaitsev 10:41552d038a69 1386
Zaitsev 10:41552d038a69 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Zaitsev 10:41552d038a69 1388 */
Zaitsev 10:41552d038a69 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Zaitsev 10:41552d038a69 1390 #if 1
Zaitsev 10:41552d038a69 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Zaitsev 10:41552d038a69 1392 #else
Zaitsev 10:41552d038a69 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Zaitsev 10:41552d038a69 1394 __DCCIMVAC = (uint32_t)va;
Zaitsev 10:41552d038a69 1395 #endif
Zaitsev 10:41552d038a69 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Zaitsev 10:41552d038a69 1397 }
Zaitsev 10:41552d038a69 1398
Zaitsev 10:41552d038a69 1399 /** \brief Clean and Invalidate the entire data or unified cache
Zaitsev 10:41552d038a69 1400
Zaitsev 10:41552d038a69 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Zaitsev 10:41552d038a69 1402 */
Zaitsev 10:41552d038a69 1403 extern void __v7_all_cache(uint32_t op);
Zaitsev 10:41552d038a69 1404
Zaitsev 10:41552d038a69 1405
Zaitsev 10:41552d038a69 1406 /** \brief Invalidate the whole D$
Zaitsev 10:41552d038a69 1407
Zaitsev 10:41552d038a69 1408 DCISW. Invalidate by Set/Way
Zaitsev 10:41552d038a69 1409 */
Zaitsev 10:41552d038a69 1410
Zaitsev 10:41552d038a69 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Zaitsev 10:41552d038a69 1412 __v7_all_cache(0);
Zaitsev 10:41552d038a69 1413 }
Zaitsev 10:41552d038a69 1414
Zaitsev 10:41552d038a69 1415 /** \brief Clean the whole D$
Zaitsev 10:41552d038a69 1416
Zaitsev 10:41552d038a69 1417 DCCSW. Clean by Set/Way
Zaitsev 10:41552d038a69 1418 */
Zaitsev 10:41552d038a69 1419
Zaitsev 10:41552d038a69 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Zaitsev 10:41552d038a69 1421 __v7_all_cache(1);
Zaitsev 10:41552d038a69 1422 }
Zaitsev 10:41552d038a69 1423
Zaitsev 10:41552d038a69 1424 /** \brief Clean and invalidate the whole D$
Zaitsev 10:41552d038a69 1425
Zaitsev 10:41552d038a69 1426 DCCISW. Clean and Invalidate by Set/Way
Zaitsev 10:41552d038a69 1427 */
Zaitsev 10:41552d038a69 1428
Zaitsev 10:41552d038a69 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Zaitsev 10:41552d038a69 1430 __v7_all_cache(2);
Zaitsev 10:41552d038a69 1431 }
Zaitsev 10:41552d038a69 1432
Zaitsev 10:41552d038a69 1433 #include "core_ca_mmu.h"
Zaitsev 10:41552d038a69 1434
Zaitsev 10:41552d038a69 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Zaitsev 10:41552d038a69 1436
Zaitsev 10:41552d038a69 1437 #error TASKING Compiler support not implemented for Cortex-A
Zaitsev 10:41552d038a69 1438
Zaitsev 10:41552d038a69 1439 #endif
Zaitsev 10:41552d038a69 1440
Zaitsev 10:41552d038a69 1441 /*@} end of CMSIS_Core_RegAccFunctions */
Zaitsev 10:41552d038a69 1442
Zaitsev 10:41552d038a69 1443
Zaitsev 10:41552d038a69 1444 #endif /* __CORE_CAFUNC_H__ */