Mateusz Kowalik / Application

USB Serial application

Fork of USBSerial_HelloWorld by Samuel Mokrani

mbed-dev/cmsis/core_cmSimd.h@11:b3f2a8bdac4d, 2017-12-16 (annotated)

Committer:
Zaitsev
Date:
Sat Dec 16 10:26:48 2017 +0000
Revision:
11:b3f2a8bdac4d
Parent:
10:41552d038a69 
A copy for D.S;

Who changed what in which revision?

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Zaitsev 10:41552d038a69 1 /**************************************************************************//**
Zaitsev 10:41552d038a69 2 * @file core_cmSimd.h
Zaitsev 10:41552d038a69 3 * @brief CMSIS Cortex-M SIMD Header File
Zaitsev 10:41552d038a69 4 * @version V4.10
Zaitsev 10:41552d038a69 5 * @date 18. March 2015
Zaitsev 10:41552d038a69 6 *
Zaitsev 10:41552d038a69 7 * @note
Zaitsev 10:41552d038a69 8 *
Zaitsev 10:41552d038a69 9 ******************************************************************************/
Zaitsev 10:41552d038a69 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
Zaitsev 10:41552d038a69 11
Zaitsev 10:41552d038a69 12 All rights reserved.
Zaitsev 10:41552d038a69 13 Redistribution and use in source and binary forms, with or without
Zaitsev 10:41552d038a69 14 modification, are permitted provided that the following conditions are met:
Zaitsev 10:41552d038a69 15 - Redistributions of source code must retain the above copyright
Zaitsev 10:41552d038a69 16 notice, this list of conditions and the following disclaimer.
Zaitsev 10:41552d038a69 17 - Redistributions in binary form must reproduce the above copyright
Zaitsev 10:41552d038a69 18 notice, this list of conditions and the following disclaimer in the
Zaitsev 10:41552d038a69 19 documentation and/or other materials provided with the distribution.
Zaitsev 10:41552d038a69 20 - Neither the name of ARM nor the names of its contributors may be used
Zaitsev 10:41552d038a69 21 to endorse or promote products derived from this software without
Zaitsev 10:41552d038a69 22 specific prior written permission.
Zaitsev 10:41552d038a69 23 *
Zaitsev 10:41552d038a69 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Zaitsev 10:41552d038a69 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Zaitsev 10:41552d038a69 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Zaitsev 10:41552d038a69 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Zaitsev 10:41552d038a69 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Zaitsev 10:41552d038a69 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Zaitsev 10:41552d038a69 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Zaitsev 10:41552d038a69 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Zaitsev 10:41552d038a69 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Zaitsev 10:41552d038a69 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Zaitsev 10:41552d038a69 34 POSSIBILITY OF SUCH DAMAGE.
Zaitsev 10:41552d038a69 35 ---------------------------------------------------------------------------*/
Zaitsev 10:41552d038a69 36
Zaitsev 10:41552d038a69 37
Zaitsev 10:41552d038a69 38 #if defined ( __ICCARM__ )
Zaitsev 10:41552d038a69 39 #pragma system_include /* treat file as system include file for MISRA check */
Zaitsev 10:41552d038a69 40 #endif
Zaitsev 10:41552d038a69 41
Zaitsev 10:41552d038a69 42 #ifndef __CORE_CMSIMD_H
Zaitsev 10:41552d038a69 43 #define __CORE_CMSIMD_H
Zaitsev 10:41552d038a69 44
Zaitsev 10:41552d038a69 45 #ifdef __cplusplus
Zaitsev 10:41552d038a69 46 extern "C" {
Zaitsev 10:41552d038a69 47 #endif
Zaitsev 10:41552d038a69 48
Zaitsev 10:41552d038a69 49
Zaitsev 10:41552d038a69 50 /*******************************************************************************
Zaitsev 10:41552d038a69 51 * Hardware Abstraction Layer
Zaitsev 10:41552d038a69 52 ******************************************************************************/
Zaitsev 10:41552d038a69 53
Zaitsev 10:41552d038a69 54
Zaitsev 10:41552d038a69 55 /* ################### Compiler specific Intrinsics ########################### */
Zaitsev 10:41552d038a69 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Zaitsev 10:41552d038a69 57 Access to dedicated SIMD instructions
Zaitsev 10:41552d038a69 58 @{
Zaitsev 10:41552d038a69 59 */
Zaitsev 10:41552d038a69 60
Zaitsev 10:41552d038a69 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Zaitsev 10:41552d038a69 62 /* ARM armcc specific functions */
Zaitsev 10:41552d038a69 63 #define __SADD8 __sadd8
Zaitsev 10:41552d038a69 64 #define __QADD8 __qadd8
Zaitsev 10:41552d038a69 65 #define __SHADD8 __shadd8
Zaitsev 10:41552d038a69 66 #define __UADD8 __uadd8
Zaitsev 10:41552d038a69 67 #define __UQADD8 __uqadd8
Zaitsev 10:41552d038a69 68 #define __UHADD8 __uhadd8
Zaitsev 10:41552d038a69 69 #define __SSUB8 __ssub8
Zaitsev 10:41552d038a69 70 #define __QSUB8 __qsub8
Zaitsev 10:41552d038a69 71 #define __SHSUB8 __shsub8
Zaitsev 10:41552d038a69 72 #define __USUB8 __usub8
Zaitsev 10:41552d038a69 73 #define __UQSUB8 __uqsub8
Zaitsev 10:41552d038a69 74 #define __UHSUB8 __uhsub8
Zaitsev 10:41552d038a69 75 #define __SADD16 __sadd16
Zaitsev 10:41552d038a69 76 #define __QADD16 __qadd16
Zaitsev 10:41552d038a69 77 #define __SHADD16 __shadd16
Zaitsev 10:41552d038a69 78 #define __UADD16 __uadd16
Zaitsev 10:41552d038a69 79 #define __UQADD16 __uqadd16
Zaitsev 10:41552d038a69 80 #define __UHADD16 __uhadd16
Zaitsev 10:41552d038a69 81 #define __SSUB16 __ssub16
Zaitsev 10:41552d038a69 82 #define __QSUB16 __qsub16
Zaitsev 10:41552d038a69 83 #define __SHSUB16 __shsub16
Zaitsev 10:41552d038a69 84 #define __USUB16 __usub16
Zaitsev 10:41552d038a69 85 #define __UQSUB16 __uqsub16
Zaitsev 10:41552d038a69 86 #define __UHSUB16 __uhsub16
Zaitsev 10:41552d038a69 87 #define __SASX __sasx
Zaitsev 10:41552d038a69 88 #define __QASX __qasx
Zaitsev 10:41552d038a69 89 #define __SHASX __shasx
Zaitsev 10:41552d038a69 90 #define __UASX __uasx
Zaitsev 10:41552d038a69 91 #define __UQASX __uqasx
Zaitsev 10:41552d038a69 92 #define __UHASX __uhasx
Zaitsev 10:41552d038a69 93 #define __SSAX __ssax
Zaitsev 10:41552d038a69 94 #define __QSAX __qsax
Zaitsev 10:41552d038a69 95 #define __SHSAX __shsax
Zaitsev 10:41552d038a69 96 #define __USAX __usax
Zaitsev 10:41552d038a69 97 #define __UQSAX __uqsax
Zaitsev 10:41552d038a69 98 #define __UHSAX __uhsax
Zaitsev 10:41552d038a69 99 #define __USAD8 __usad8
Zaitsev 10:41552d038a69 100 #define __USADA8 __usada8
Zaitsev 10:41552d038a69 101 #define __SSAT16 __ssat16
Zaitsev 10:41552d038a69 102 #define __USAT16 __usat16
Zaitsev 10:41552d038a69 103 #define __UXTB16 __uxtb16
Zaitsev 10:41552d038a69 104 #define __UXTAB16 __uxtab16
Zaitsev 10:41552d038a69 105 #define __SXTB16 __sxtb16
Zaitsev 10:41552d038a69 106 #define __SXTAB16 __sxtab16
Zaitsev 10:41552d038a69 107 #define __SMUAD __smuad
Zaitsev 10:41552d038a69 108 #define __SMUADX __smuadx
Zaitsev 10:41552d038a69 109 #define __SMLAD __smlad
Zaitsev 10:41552d038a69 110 #define __SMLADX __smladx
Zaitsev 10:41552d038a69 111 #define __SMLALD __smlald
Zaitsev 10:41552d038a69 112 #define __SMLALDX __smlaldx
Zaitsev 10:41552d038a69 113 #define __SMUSD __smusd
Zaitsev 10:41552d038a69 114 #define __SMUSDX __smusdx
Zaitsev 10:41552d038a69 115 #define __SMLSD __smlsd
Zaitsev 10:41552d038a69 116 #define __SMLSDX __smlsdx
Zaitsev 10:41552d038a69 117 #define __SMLSLD __smlsld
Zaitsev 10:41552d038a69 118 #define __SMLSLDX __smlsldx
Zaitsev 10:41552d038a69 119 #define __SEL __sel
Zaitsev 10:41552d038a69 120 #define __QADD __qadd
Zaitsev 10:41552d038a69 121 #define __QSUB __qsub
Zaitsev 10:41552d038a69 122
Zaitsev 10:41552d038a69 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
Zaitsev 10:41552d038a69 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
Zaitsev 10:41552d038a69 125
Zaitsev 10:41552d038a69 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
Zaitsev 10:41552d038a69 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
Zaitsev 10:41552d038a69 128
Zaitsev 10:41552d038a69 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
Zaitsev 10:41552d038a69 130 ((int64_t)(ARG3) << 32) ) >> 32))
Zaitsev 10:41552d038a69 131
Zaitsev 10:41552d038a69 132
Zaitsev 10:41552d038a69 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
Zaitsev 10:41552d038a69 134 /* GNU gcc specific functions */
Zaitsev 10:41552d038a69 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 136 {
Zaitsev 10:41552d038a69 137 uint32_t result;
Zaitsev 10:41552d038a69 138
Zaitsev 10:41552d038a69 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 140 return(result);
Zaitsev 10:41552d038a69 141 }
Zaitsev 10:41552d038a69 142
Zaitsev 10:41552d038a69 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 144 {
Zaitsev 10:41552d038a69 145 uint32_t result;
Zaitsev 10:41552d038a69 146
Zaitsev 10:41552d038a69 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 148 return(result);
Zaitsev 10:41552d038a69 149 }
Zaitsev 10:41552d038a69 150
Zaitsev 10:41552d038a69 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 152 {
Zaitsev 10:41552d038a69 153 uint32_t result;
Zaitsev 10:41552d038a69 154
Zaitsev 10:41552d038a69 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 156 return(result);
Zaitsev 10:41552d038a69 157 }
Zaitsev 10:41552d038a69 158
Zaitsev 10:41552d038a69 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 160 {
Zaitsev 10:41552d038a69 161 uint32_t result;
Zaitsev 10:41552d038a69 162
Zaitsev 10:41552d038a69 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 164 return(result);
Zaitsev 10:41552d038a69 165 }
Zaitsev 10:41552d038a69 166
Zaitsev 10:41552d038a69 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 168 {
Zaitsev 10:41552d038a69 169 uint32_t result;
Zaitsev 10:41552d038a69 170
Zaitsev 10:41552d038a69 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 172 return(result);
Zaitsev 10:41552d038a69 173 }
Zaitsev 10:41552d038a69 174
Zaitsev 10:41552d038a69 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 176 {
Zaitsev 10:41552d038a69 177 uint32_t result;
Zaitsev 10:41552d038a69 178
Zaitsev 10:41552d038a69 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 180 return(result);
Zaitsev 10:41552d038a69 181 }
Zaitsev 10:41552d038a69 182
Zaitsev 10:41552d038a69 183
Zaitsev 10:41552d038a69 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 185 {
Zaitsev 10:41552d038a69 186 uint32_t result;
Zaitsev 10:41552d038a69 187
Zaitsev 10:41552d038a69 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 189 return(result);
Zaitsev 10:41552d038a69 190 }
Zaitsev 10:41552d038a69 191
Zaitsev 10:41552d038a69 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 193 {
Zaitsev 10:41552d038a69 194 uint32_t result;
Zaitsev 10:41552d038a69 195
Zaitsev 10:41552d038a69 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 197 return(result);
Zaitsev 10:41552d038a69 198 }
Zaitsev 10:41552d038a69 199
Zaitsev 10:41552d038a69 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 201 {
Zaitsev 10:41552d038a69 202 uint32_t result;
Zaitsev 10:41552d038a69 203
Zaitsev 10:41552d038a69 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 205 return(result);
Zaitsev 10:41552d038a69 206 }
Zaitsev 10:41552d038a69 207
Zaitsev 10:41552d038a69 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 209 {
Zaitsev 10:41552d038a69 210 uint32_t result;
Zaitsev 10:41552d038a69 211
Zaitsev 10:41552d038a69 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 213 return(result);
Zaitsev 10:41552d038a69 214 }
Zaitsev 10:41552d038a69 215
Zaitsev 10:41552d038a69 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 217 {
Zaitsev 10:41552d038a69 218 uint32_t result;
Zaitsev 10:41552d038a69 219
Zaitsev 10:41552d038a69 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 221 return(result);
Zaitsev 10:41552d038a69 222 }
Zaitsev 10:41552d038a69 223
Zaitsev 10:41552d038a69 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 225 {
Zaitsev 10:41552d038a69 226 uint32_t result;
Zaitsev 10:41552d038a69 227
Zaitsev 10:41552d038a69 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 229 return(result);
Zaitsev 10:41552d038a69 230 }
Zaitsev 10:41552d038a69 231
Zaitsev 10:41552d038a69 232
Zaitsev 10:41552d038a69 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 234 {
Zaitsev 10:41552d038a69 235 uint32_t result;
Zaitsev 10:41552d038a69 236
Zaitsev 10:41552d038a69 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 238 return(result);
Zaitsev 10:41552d038a69 239 }
Zaitsev 10:41552d038a69 240
Zaitsev 10:41552d038a69 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 242 {
Zaitsev 10:41552d038a69 243 uint32_t result;
Zaitsev 10:41552d038a69 244
Zaitsev 10:41552d038a69 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 246 return(result);
Zaitsev 10:41552d038a69 247 }
Zaitsev 10:41552d038a69 248
Zaitsev 10:41552d038a69 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 250 {
Zaitsev 10:41552d038a69 251 uint32_t result;
Zaitsev 10:41552d038a69 252
Zaitsev 10:41552d038a69 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 254 return(result);
Zaitsev 10:41552d038a69 255 }
Zaitsev 10:41552d038a69 256
Zaitsev 10:41552d038a69 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 258 {
Zaitsev 10:41552d038a69 259 uint32_t result;
Zaitsev 10:41552d038a69 260
Zaitsev 10:41552d038a69 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 262 return(result);
Zaitsev 10:41552d038a69 263 }
Zaitsev 10:41552d038a69 264
Zaitsev 10:41552d038a69 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 266 {
Zaitsev 10:41552d038a69 267 uint32_t result;
Zaitsev 10:41552d038a69 268
Zaitsev 10:41552d038a69 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 270 return(result);
Zaitsev 10:41552d038a69 271 }
Zaitsev 10:41552d038a69 272
Zaitsev 10:41552d038a69 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 274 {
Zaitsev 10:41552d038a69 275 uint32_t result;
Zaitsev 10:41552d038a69 276
Zaitsev 10:41552d038a69 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 278 return(result);
Zaitsev 10:41552d038a69 279 }
Zaitsev 10:41552d038a69 280
Zaitsev 10:41552d038a69 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 282 {
Zaitsev 10:41552d038a69 283 uint32_t result;
Zaitsev 10:41552d038a69 284
Zaitsev 10:41552d038a69 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 286 return(result);
Zaitsev 10:41552d038a69 287 }
Zaitsev 10:41552d038a69 288
Zaitsev 10:41552d038a69 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 290 {
Zaitsev 10:41552d038a69 291 uint32_t result;
Zaitsev 10:41552d038a69 292
Zaitsev 10:41552d038a69 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 294 return(result);
Zaitsev 10:41552d038a69 295 }
Zaitsev 10:41552d038a69 296
Zaitsev 10:41552d038a69 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 298 {
Zaitsev 10:41552d038a69 299 uint32_t result;
Zaitsev 10:41552d038a69 300
Zaitsev 10:41552d038a69 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 302 return(result);
Zaitsev 10:41552d038a69 303 }
Zaitsev 10:41552d038a69 304
Zaitsev 10:41552d038a69 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 306 {
Zaitsev 10:41552d038a69 307 uint32_t result;
Zaitsev 10:41552d038a69 308
Zaitsev 10:41552d038a69 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 310 return(result);
Zaitsev 10:41552d038a69 311 }
Zaitsev 10:41552d038a69 312
Zaitsev 10:41552d038a69 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 314 {
Zaitsev 10:41552d038a69 315 uint32_t result;
Zaitsev 10:41552d038a69 316
Zaitsev 10:41552d038a69 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 318 return(result);
Zaitsev 10:41552d038a69 319 }
Zaitsev 10:41552d038a69 320
Zaitsev 10:41552d038a69 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 322 {
Zaitsev 10:41552d038a69 323 uint32_t result;
Zaitsev 10:41552d038a69 324
Zaitsev 10:41552d038a69 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 326 return(result);
Zaitsev 10:41552d038a69 327 }
Zaitsev 10:41552d038a69 328
Zaitsev 10:41552d038a69 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 330 {
Zaitsev 10:41552d038a69 331 uint32_t result;
Zaitsev 10:41552d038a69 332
Zaitsev 10:41552d038a69 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 334 return(result);
Zaitsev 10:41552d038a69 335 }
Zaitsev 10:41552d038a69 336
Zaitsev 10:41552d038a69 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 338 {
Zaitsev 10:41552d038a69 339 uint32_t result;
Zaitsev 10:41552d038a69 340
Zaitsev 10:41552d038a69 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 342 return(result);
Zaitsev 10:41552d038a69 343 }
Zaitsev 10:41552d038a69 344
Zaitsev 10:41552d038a69 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 346 {
Zaitsev 10:41552d038a69 347 uint32_t result;
Zaitsev 10:41552d038a69 348
Zaitsev 10:41552d038a69 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 350 return(result);
Zaitsev 10:41552d038a69 351 }
Zaitsev 10:41552d038a69 352
Zaitsev 10:41552d038a69 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 354 {
Zaitsev 10:41552d038a69 355 uint32_t result;
Zaitsev 10:41552d038a69 356
Zaitsev 10:41552d038a69 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 358 return(result);
Zaitsev 10:41552d038a69 359 }
Zaitsev 10:41552d038a69 360
Zaitsev 10:41552d038a69 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 362 {
Zaitsev 10:41552d038a69 363 uint32_t result;
Zaitsev 10:41552d038a69 364
Zaitsev 10:41552d038a69 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 366 return(result);
Zaitsev 10:41552d038a69 367 }
Zaitsev 10:41552d038a69 368
Zaitsev 10:41552d038a69 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 370 {
Zaitsev 10:41552d038a69 371 uint32_t result;
Zaitsev 10:41552d038a69 372
Zaitsev 10:41552d038a69 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 374 return(result);
Zaitsev 10:41552d038a69 375 }
Zaitsev 10:41552d038a69 376
Zaitsev 10:41552d038a69 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 378 {
Zaitsev 10:41552d038a69 379 uint32_t result;
Zaitsev 10:41552d038a69 380
Zaitsev 10:41552d038a69 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 382 return(result);
Zaitsev 10:41552d038a69 383 }
Zaitsev 10:41552d038a69 384
Zaitsev 10:41552d038a69 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 386 {
Zaitsev 10:41552d038a69 387 uint32_t result;
Zaitsev 10:41552d038a69 388
Zaitsev 10:41552d038a69 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 390 return(result);
Zaitsev 10:41552d038a69 391 }
Zaitsev 10:41552d038a69 392
Zaitsev 10:41552d038a69 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 394 {
Zaitsev 10:41552d038a69 395 uint32_t result;
Zaitsev 10:41552d038a69 396
Zaitsev 10:41552d038a69 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 398 return(result);
Zaitsev 10:41552d038a69 399 }
Zaitsev 10:41552d038a69 400
Zaitsev 10:41552d038a69 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 402 {
Zaitsev 10:41552d038a69 403 uint32_t result;
Zaitsev 10:41552d038a69 404
Zaitsev 10:41552d038a69 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 406 return(result);
Zaitsev 10:41552d038a69 407 }
Zaitsev 10:41552d038a69 408
Zaitsev 10:41552d038a69 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 410 {
Zaitsev 10:41552d038a69 411 uint32_t result;
Zaitsev 10:41552d038a69 412
Zaitsev 10:41552d038a69 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 414 return(result);
Zaitsev 10:41552d038a69 415 }
Zaitsev 10:41552d038a69 416
Zaitsev 10:41552d038a69 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 418 {
Zaitsev 10:41552d038a69 419 uint32_t result;
Zaitsev 10:41552d038a69 420
Zaitsev 10:41552d038a69 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 422 return(result);
Zaitsev 10:41552d038a69 423 }
Zaitsev 10:41552d038a69 424
Zaitsev 10:41552d038a69 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 426 {
Zaitsev 10:41552d038a69 427 uint32_t result;
Zaitsev 10:41552d038a69 428
Zaitsev 10:41552d038a69 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 430 return(result);
Zaitsev 10:41552d038a69 431 }
Zaitsev 10:41552d038a69 432
Zaitsev 10:41552d038a69 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
Zaitsev 10:41552d038a69 434 {
Zaitsev 10:41552d038a69 435 uint32_t result;
Zaitsev 10:41552d038a69 436
Zaitsev 10:41552d038a69 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
Zaitsev 10:41552d038a69 438 return(result);
Zaitsev 10:41552d038a69 439 }
Zaitsev 10:41552d038a69 440
Zaitsev 10:41552d038a69 441 #define __SSAT16(ARG1,ARG2) \
Zaitsev 10:41552d038a69 442 ({ \
Zaitsev 10:41552d038a69 443 uint32_t __RES, __ARG1 = (ARG1); \
Zaitsev 10:41552d038a69 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
Zaitsev 10:41552d038a69 445 __RES; \
Zaitsev 10:41552d038a69 446 })
Zaitsev 10:41552d038a69 447
Zaitsev 10:41552d038a69 448 #define __USAT16(ARG1,ARG2) \
Zaitsev 10:41552d038a69 449 ({ \
Zaitsev 10:41552d038a69 450 uint32_t __RES, __ARG1 = (ARG1); \
Zaitsev 10:41552d038a69 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
Zaitsev 10:41552d038a69 452 __RES; \
Zaitsev 10:41552d038a69 453 })
Zaitsev 10:41552d038a69 454
Zaitsev 10:41552d038a69 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
Zaitsev 10:41552d038a69 456 {
Zaitsev 10:41552d038a69 457 uint32_t result;
Zaitsev 10:41552d038a69 458
Zaitsev 10:41552d038a69 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
Zaitsev 10:41552d038a69 460 return(result);
Zaitsev 10:41552d038a69 461 }
Zaitsev 10:41552d038a69 462
Zaitsev 10:41552d038a69 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 464 {
Zaitsev 10:41552d038a69 465 uint32_t result;
Zaitsev 10:41552d038a69 466
Zaitsev 10:41552d038a69 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 468 return(result);
Zaitsev 10:41552d038a69 469 }
Zaitsev 10:41552d038a69 470
Zaitsev 10:41552d038a69 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
Zaitsev 10:41552d038a69 472 {
Zaitsev 10:41552d038a69 473 uint32_t result;
Zaitsev 10:41552d038a69 474
Zaitsev 10:41552d038a69 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
Zaitsev 10:41552d038a69 476 return(result);
Zaitsev 10:41552d038a69 477 }
Zaitsev 10:41552d038a69 478
Zaitsev 10:41552d038a69 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 480 {
Zaitsev 10:41552d038a69 481 uint32_t result;
Zaitsev 10:41552d038a69 482
Zaitsev 10:41552d038a69 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 484 return(result);
Zaitsev 10:41552d038a69 485 }
Zaitsev 10:41552d038a69 486
Zaitsev 10:41552d038a69 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 488 {
Zaitsev 10:41552d038a69 489 uint32_t result;
Zaitsev 10:41552d038a69 490
Zaitsev 10:41552d038a69 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 492 return(result);
Zaitsev 10:41552d038a69 493 }
Zaitsev 10:41552d038a69 494
Zaitsev 10:41552d038a69 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 496 {
Zaitsev 10:41552d038a69 497 uint32_t result;
Zaitsev 10:41552d038a69 498
Zaitsev 10:41552d038a69 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 500 return(result);
Zaitsev 10:41552d038a69 501 }
Zaitsev 10:41552d038a69 502
Zaitsev 10:41552d038a69 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
Zaitsev 10:41552d038a69 504 {
Zaitsev 10:41552d038a69 505 uint32_t result;
Zaitsev 10:41552d038a69 506
Zaitsev 10:41552d038a69 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
Zaitsev 10:41552d038a69 508 return(result);
Zaitsev 10:41552d038a69 509 }
Zaitsev 10:41552d038a69 510
Zaitsev 10:41552d038a69 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
Zaitsev 10:41552d038a69 512 {
Zaitsev 10:41552d038a69 513 uint32_t result;
Zaitsev 10:41552d038a69 514
Zaitsev 10:41552d038a69 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
Zaitsev 10:41552d038a69 516 return(result);
Zaitsev 10:41552d038a69 517 }
Zaitsev 10:41552d038a69 518
Zaitsev 10:41552d038a69 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
Zaitsev 10:41552d038a69 520 {
Zaitsev 10:41552d038a69 521 union llreg_u{
Zaitsev 10:41552d038a69 522 uint32_t w32[2];
Zaitsev 10:41552d038a69 523 uint64_t w64;
Zaitsev 10:41552d038a69 524 } llr;
Zaitsev 10:41552d038a69 525 llr.w64 = acc;
Zaitsev 10:41552d038a69 526
Zaitsev 10:41552d038a69 527 #ifndef __ARMEB__ // Little endian
Zaitsev 10:41552d038a69 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
Zaitsev 10:41552d038a69 529 #else // Big endian
Zaitsev 10:41552d038a69 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
Zaitsev 10:41552d038a69 531 #endif
Zaitsev 10:41552d038a69 532
Zaitsev 10:41552d038a69 533 return(llr.w64);
Zaitsev 10:41552d038a69 534 }
Zaitsev 10:41552d038a69 535
Zaitsev 10:41552d038a69 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
Zaitsev 10:41552d038a69 537 {
Zaitsev 10:41552d038a69 538 union llreg_u{
Zaitsev 10:41552d038a69 539 uint32_t w32[2];
Zaitsev 10:41552d038a69 540 uint64_t w64;
Zaitsev 10:41552d038a69 541 } llr;
Zaitsev 10:41552d038a69 542 llr.w64 = acc;
Zaitsev 10:41552d038a69 543
Zaitsev 10:41552d038a69 544 #ifndef __ARMEB__ // Little endian
Zaitsev 10:41552d038a69 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
Zaitsev 10:41552d038a69 546 #else // Big endian
Zaitsev 10:41552d038a69 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
Zaitsev 10:41552d038a69 548 #endif
Zaitsev 10:41552d038a69 549
Zaitsev 10:41552d038a69 550 return(llr.w64);
Zaitsev 10:41552d038a69 551 }
Zaitsev 10:41552d038a69 552
Zaitsev 10:41552d038a69 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 554 {
Zaitsev 10:41552d038a69 555 uint32_t result;
Zaitsev 10:41552d038a69 556
Zaitsev 10:41552d038a69 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 558 return(result);
Zaitsev 10:41552d038a69 559 }
Zaitsev 10:41552d038a69 560
Zaitsev 10:41552d038a69 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 562 {
Zaitsev 10:41552d038a69 563 uint32_t result;
Zaitsev 10:41552d038a69 564
Zaitsev 10:41552d038a69 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 566 return(result);
Zaitsev 10:41552d038a69 567 }
Zaitsev 10:41552d038a69 568
Zaitsev 10:41552d038a69 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
Zaitsev 10:41552d038a69 570 {
Zaitsev 10:41552d038a69 571 uint32_t result;
Zaitsev 10:41552d038a69 572
Zaitsev 10:41552d038a69 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
Zaitsev 10:41552d038a69 574 return(result);
Zaitsev 10:41552d038a69 575 }
Zaitsev 10:41552d038a69 576
Zaitsev 10:41552d038a69 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
Zaitsev 10:41552d038a69 578 {
Zaitsev 10:41552d038a69 579 uint32_t result;
Zaitsev 10:41552d038a69 580
Zaitsev 10:41552d038a69 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
Zaitsev 10:41552d038a69 582 return(result);
Zaitsev 10:41552d038a69 583 }
Zaitsev 10:41552d038a69 584
Zaitsev 10:41552d038a69 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
Zaitsev 10:41552d038a69 586 {
Zaitsev 10:41552d038a69 587 union llreg_u{
Zaitsev 10:41552d038a69 588 uint32_t w32[2];
Zaitsev 10:41552d038a69 589 uint64_t w64;
Zaitsev 10:41552d038a69 590 } llr;
Zaitsev 10:41552d038a69 591 llr.w64 = acc;
Zaitsev 10:41552d038a69 592
Zaitsev 10:41552d038a69 593 #ifndef __ARMEB__ // Little endian
Zaitsev 10:41552d038a69 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
Zaitsev 10:41552d038a69 595 #else // Big endian
Zaitsev 10:41552d038a69 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
Zaitsev 10:41552d038a69 597 #endif
Zaitsev 10:41552d038a69 598
Zaitsev 10:41552d038a69 599 return(llr.w64);
Zaitsev 10:41552d038a69 600 }
Zaitsev 10:41552d038a69 601
Zaitsev 10:41552d038a69 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
Zaitsev 10:41552d038a69 603 {
Zaitsev 10:41552d038a69 604 union llreg_u{
Zaitsev 10:41552d038a69 605 uint32_t w32[2];
Zaitsev 10:41552d038a69 606 uint64_t w64;
Zaitsev 10:41552d038a69 607 } llr;
Zaitsev 10:41552d038a69 608 llr.w64 = acc;
Zaitsev 10:41552d038a69 609
Zaitsev 10:41552d038a69 610 #ifndef __ARMEB__ // Little endian
Zaitsev 10:41552d038a69 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
Zaitsev 10:41552d038a69 612 #else // Big endian
Zaitsev 10:41552d038a69 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
Zaitsev 10:41552d038a69 614 #endif
Zaitsev 10:41552d038a69 615
Zaitsev 10:41552d038a69 616 return(llr.w64);
Zaitsev 10:41552d038a69 617 }
Zaitsev 10:41552d038a69 618
Zaitsev 10:41552d038a69 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 620 {
Zaitsev 10:41552d038a69 621 uint32_t result;
Zaitsev 10:41552d038a69 622
Zaitsev 10:41552d038a69 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 624 return(result);
Zaitsev 10:41552d038a69 625 }
Zaitsev 10:41552d038a69 626
Zaitsev 10:41552d038a69 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 628 {
Zaitsev 10:41552d038a69 629 uint32_t result;
Zaitsev 10:41552d038a69 630
Zaitsev 10:41552d038a69 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 632 return(result);
Zaitsev 10:41552d038a69 633 }
Zaitsev 10:41552d038a69 634
Zaitsev 10:41552d038a69 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 636 {
Zaitsev 10:41552d038a69 637 uint32_t result;
Zaitsev 10:41552d038a69 638
Zaitsev 10:41552d038a69 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
Zaitsev 10:41552d038a69 640 return(result);
Zaitsev 10:41552d038a69 641 }
Zaitsev 10:41552d038a69 642
Zaitsev 10:41552d038a69 643 #define __PKHBT(ARG1,ARG2,ARG3) \
Zaitsev 10:41552d038a69 644 ({ \
Zaitsev 10:41552d038a69 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
Zaitsev 10:41552d038a69 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
Zaitsev 10:41552d038a69 647 __RES; \
Zaitsev 10:41552d038a69 648 })
Zaitsev 10:41552d038a69 649
Zaitsev 10:41552d038a69 650 #define __PKHTB(ARG1,ARG2,ARG3) \
Zaitsev 10:41552d038a69 651 ({ \
Zaitsev 10:41552d038a69 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
Zaitsev 10:41552d038a69 653 if (ARG3 == 0) \
Zaitsev 10:41552d038a69 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
Zaitsev 10:41552d038a69 655 else \
Zaitsev 10:41552d038a69 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
Zaitsev 10:41552d038a69 657 __RES; \
Zaitsev 10:41552d038a69 658 })
Zaitsev 10:41552d038a69 659
Zaitsev 10:41552d038a69 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
Zaitsev 10:41552d038a69 661 {
Zaitsev 10:41552d038a69 662 int32_t result;
Zaitsev 10:41552d038a69 663
Zaitsev 10:41552d038a69 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
Zaitsev 10:41552d038a69 665 return(result);
Zaitsev 10:41552d038a69 666 }
Zaitsev 10:41552d038a69 667
Zaitsev 10:41552d038a69 668
Zaitsev 10:41552d038a69 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
Zaitsev 10:41552d038a69 670 /* IAR iccarm specific functions */
Zaitsev 10:41552d038a69 671 #include <cmsis_iar.h>
Zaitsev 10:41552d038a69 672
Zaitsev 10:41552d038a69 673
Zaitsev 10:41552d038a69 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
Zaitsev 10:41552d038a69 675 /* TI CCS specific functions */
Zaitsev 10:41552d038a69 676 #include <cmsis_ccs.h>
Zaitsev 10:41552d038a69 677
Zaitsev 10:41552d038a69 678
Zaitsev 10:41552d038a69 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
Zaitsev 10:41552d038a69 680 /* TASKING carm specific functions */
Zaitsev 10:41552d038a69 681 /* not yet supported */
Zaitsev 10:41552d038a69 682
Zaitsev 10:41552d038a69 683
Zaitsev 10:41552d038a69 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
Zaitsev 10:41552d038a69 685 /* Cosmic specific functions */
Zaitsev 10:41552d038a69 686 #include <cmsis_csm.h>
Zaitsev 10:41552d038a69 687
Zaitsev 10:41552d038a69 688 #endif
Zaitsev 10:41552d038a69 689
Zaitsev 10:41552d038a69 690 /*@} end of group CMSIS_SIMD_intrinsics */
Zaitsev 10:41552d038a69 691
Zaitsev 10:41552d038a69 692
Zaitsev 10:41552d038a69 693 #ifdef __cplusplus
Zaitsev 10:41552d038a69 694 }
Zaitsev 10:41552d038a69 695 #endif
Zaitsev 10:41552d038a69 696
Zaitsev 10:41552d038a69 697 #endif /* __CORE_CMSIMD_H */