Mateusz Kowalik / Application

USB Serial application

Fork of USBSerial_HelloWorld by Samuel Mokrani

mbed-dev/cmsis/core_cmInstr.h@11:b3f2a8bdac4d, 2017-12-16 (annotated)

Committer:
Zaitsev
Date:
Sat Dec 16 10:26:48 2017 +0000
Revision:
11:b3f2a8bdac4d
Parent:
10:41552d038a69 
A copy for D.S;

Who changed what in which revision?

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Zaitsev 10:41552d038a69 1 /**************************************************************************//**
Zaitsev 10:41552d038a69 2 * @file core_cmInstr.h
Zaitsev 10:41552d038a69 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
Zaitsev 10:41552d038a69 4 * @version V4.10
Zaitsev 10:41552d038a69 5 * @date 18. March 2015
Zaitsev 10:41552d038a69 6 *
Zaitsev 10:41552d038a69 7 * @note
Zaitsev 10:41552d038a69 8 *
Zaitsev 10:41552d038a69 9 ******************************************************************************/
Zaitsev 10:41552d038a69 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
Zaitsev 10:41552d038a69 11
Zaitsev 10:41552d038a69 12 All rights reserved.
Zaitsev 10:41552d038a69 13 Redistribution and use in source and binary forms, with or without
Zaitsev 10:41552d038a69 14 modification, are permitted provided that the following conditions are met:
Zaitsev 10:41552d038a69 15 - Redistributions of source code must retain the above copyright
Zaitsev 10:41552d038a69 16 notice, this list of conditions and the following disclaimer.
Zaitsev 10:41552d038a69 17 - Redistributions in binary form must reproduce the above copyright
Zaitsev 10:41552d038a69 18 notice, this list of conditions and the following disclaimer in the
Zaitsev 10:41552d038a69 19 documentation and/or other materials provided with the distribution.
Zaitsev 10:41552d038a69 20 - Neither the name of ARM nor the names of its contributors may be used
Zaitsev 10:41552d038a69 21 to endorse or promote products derived from this software without
Zaitsev 10:41552d038a69 22 specific prior written permission.
Zaitsev 10:41552d038a69 23 *
Zaitsev 10:41552d038a69 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Zaitsev 10:41552d038a69 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Zaitsev 10:41552d038a69 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Zaitsev 10:41552d038a69 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Zaitsev 10:41552d038a69 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Zaitsev 10:41552d038a69 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Zaitsev 10:41552d038a69 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Zaitsev 10:41552d038a69 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Zaitsev 10:41552d038a69 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Zaitsev 10:41552d038a69 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Zaitsev 10:41552d038a69 34 POSSIBILITY OF SUCH DAMAGE.
Zaitsev 10:41552d038a69 35 ---------------------------------------------------------------------------*/
Zaitsev 10:41552d038a69 36
Zaitsev 10:41552d038a69 37
Zaitsev 10:41552d038a69 38 #ifndef __CORE_CMINSTR_H
Zaitsev 10:41552d038a69 39 #define __CORE_CMINSTR_H
Zaitsev 10:41552d038a69 40
Zaitsev 10:41552d038a69 41
Zaitsev 10:41552d038a69 42 /* ########################## Core Instruction Access ######################### */
Zaitsev 10:41552d038a69 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Zaitsev 10:41552d038a69 44 Access to dedicated instructions
Zaitsev 10:41552d038a69 45 @{
Zaitsev 10:41552d038a69 46 */
Zaitsev 10:41552d038a69 47
Zaitsev 10:41552d038a69 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Zaitsev 10:41552d038a69 49 /* ARM armcc specific functions */
Zaitsev 10:41552d038a69 50
Zaitsev 10:41552d038a69 51 #if (__ARMCC_VERSION < 400677)
Zaitsev 10:41552d038a69 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Zaitsev 10:41552d038a69 53 #endif
Zaitsev 10:41552d038a69 54
Zaitsev 10:41552d038a69 55
Zaitsev 10:41552d038a69 56 /** \brief No Operation
Zaitsev 10:41552d038a69 57
Zaitsev 10:41552d038a69 58 No Operation does nothing. This instruction can be used for code alignment purposes.
Zaitsev 10:41552d038a69 59 */
Zaitsev 10:41552d038a69 60 #define __NOP __nop
Zaitsev 10:41552d038a69 61
Zaitsev 10:41552d038a69 62
Zaitsev 10:41552d038a69 63 /** \brief Wait For Interrupt
Zaitsev 10:41552d038a69 64
Zaitsev 10:41552d038a69 65 Wait For Interrupt is a hint instruction that suspends execution
Zaitsev 10:41552d038a69 66 until one of a number of events occurs.
Zaitsev 10:41552d038a69 67 */
Zaitsev 10:41552d038a69 68 #define __WFI __wfi
Zaitsev 10:41552d038a69 69
Zaitsev 10:41552d038a69 70
Zaitsev 10:41552d038a69 71 /** \brief Wait For Event
Zaitsev 10:41552d038a69 72
Zaitsev 10:41552d038a69 73 Wait For Event is a hint instruction that permits the processor to enter
Zaitsev 10:41552d038a69 74 a low-power state until one of a number of events occurs.
Zaitsev 10:41552d038a69 75 */
Zaitsev 10:41552d038a69 76 #define __WFE __wfe
Zaitsev 10:41552d038a69 77
Zaitsev 10:41552d038a69 78
Zaitsev 10:41552d038a69 79 /** \brief Send Event
Zaitsev 10:41552d038a69 80
Zaitsev 10:41552d038a69 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
Zaitsev 10:41552d038a69 82 */
Zaitsev 10:41552d038a69 83 #define __SEV __sev
Zaitsev 10:41552d038a69 84
Zaitsev 10:41552d038a69 85
Zaitsev 10:41552d038a69 86 /** \brief Instruction Synchronization Barrier
Zaitsev 10:41552d038a69 87
Zaitsev 10:41552d038a69 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
Zaitsev 10:41552d038a69 89 so that all instructions following the ISB are fetched from cache or
Zaitsev 10:41552d038a69 90 memory, after the instruction has been completed.
Zaitsev 10:41552d038a69 91 */
Zaitsev 10:41552d038a69 92 #define __ISB() do {\
Zaitsev 10:41552d038a69 93 __schedule_barrier();\
Zaitsev 10:41552d038a69 94 __isb(0xF);\
Zaitsev 10:41552d038a69 95 __schedule_barrier();\
Zaitsev 10:41552d038a69 96 } while (0)
Zaitsev 10:41552d038a69 97
Zaitsev 10:41552d038a69 98 /** \brief Data Synchronization Barrier
Zaitsev 10:41552d038a69 99
Zaitsev 10:41552d038a69 100 This function acts as a special kind of Data Memory Barrier.
Zaitsev 10:41552d038a69 101 It completes when all explicit memory accesses before this instruction complete.
Zaitsev 10:41552d038a69 102 */
Zaitsev 10:41552d038a69 103 #define __DSB() do {\
Zaitsev 10:41552d038a69 104 __schedule_barrier();\
Zaitsev 10:41552d038a69 105 __dsb(0xF);\
Zaitsev 10:41552d038a69 106 __schedule_barrier();\
Zaitsev 10:41552d038a69 107 } while (0)
Zaitsev 10:41552d038a69 108
Zaitsev 10:41552d038a69 109 /** \brief Data Memory Barrier
Zaitsev 10:41552d038a69 110
Zaitsev 10:41552d038a69 111 This function ensures the apparent order of the explicit memory operations before
Zaitsev 10:41552d038a69 112 and after the instruction, without ensuring their completion.
Zaitsev 10:41552d038a69 113 */
Zaitsev 10:41552d038a69 114 #define __DMB() do {\
Zaitsev 10:41552d038a69 115 __schedule_barrier();\
Zaitsev 10:41552d038a69 116 __dmb(0xF);\
Zaitsev 10:41552d038a69 117 __schedule_barrier();\
Zaitsev 10:41552d038a69 118 } while (0)
Zaitsev 10:41552d038a69 119
Zaitsev 10:41552d038a69 120 /** \brief Reverse byte order (32 bit)
Zaitsev 10:41552d038a69 121
Zaitsev 10:41552d038a69 122 This function reverses the byte order in integer value.
Zaitsev 10:41552d038a69 123
Zaitsev 10:41552d038a69 124 \param [in] value Value to reverse
Zaitsev 10:41552d038a69 125 \return Reversed value
Zaitsev 10:41552d038a69 126 */
Zaitsev 10:41552d038a69 127 #define __REV __rev
Zaitsev 10:41552d038a69 128
Zaitsev 10:41552d038a69 129
Zaitsev 10:41552d038a69 130 /** \brief Reverse byte order (16 bit)
Zaitsev 10:41552d038a69 131
Zaitsev 10:41552d038a69 132 This function reverses the byte order in two unsigned short values.
Zaitsev 10:41552d038a69 133
Zaitsev 10:41552d038a69 134 \param [in] value Value to reverse
Zaitsev 10:41552d038a69 135 \return Reversed value
Zaitsev 10:41552d038a69 136 */
Zaitsev 10:41552d038a69 137 #ifndef __NO_EMBEDDED_ASM
Zaitsev 10:41552d038a69 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
Zaitsev 10:41552d038a69 139 {
Zaitsev 10:41552d038a69 140 rev16 r0, r0
Zaitsev 10:41552d038a69 141 bx lr
Zaitsev 10:41552d038a69 142 }
Zaitsev 10:41552d038a69 143 #endif
Zaitsev 10:41552d038a69 144
Zaitsev 10:41552d038a69 145 /** \brief Reverse byte order in signed short value
Zaitsev 10:41552d038a69 146
Zaitsev 10:41552d038a69 147 This function reverses the byte order in a signed short value with sign extension to integer.
Zaitsev 10:41552d038a69 148
Zaitsev 10:41552d038a69 149 \param [in] value Value to reverse
Zaitsev 10:41552d038a69 150 \return Reversed value
Zaitsev 10:41552d038a69 151 */
Zaitsev 10:41552d038a69 152 #ifndef __NO_EMBEDDED_ASM
Zaitsev 10:41552d038a69 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
Zaitsev 10:41552d038a69 154 {
Zaitsev 10:41552d038a69 155 revsh r0, r0
Zaitsev 10:41552d038a69 156 bx lr
Zaitsev 10:41552d038a69 157 }
Zaitsev 10:41552d038a69 158 #endif
Zaitsev 10:41552d038a69 159
Zaitsev 10:41552d038a69 160
Zaitsev 10:41552d038a69 161 /** \brief Rotate Right in unsigned value (32 bit)
Zaitsev 10:41552d038a69 162
Zaitsev 10:41552d038a69 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
Zaitsev 10:41552d038a69 164
Zaitsev 10:41552d038a69 165 \param [in] value Value to rotate
Zaitsev 10:41552d038a69 166 \param [in] value Number of Bits to rotate
Zaitsev 10:41552d038a69 167 \return Rotated value
Zaitsev 10:41552d038a69 168 */
Zaitsev 10:41552d038a69 169 #define __ROR __ror
Zaitsev 10:41552d038a69 170
Zaitsev 10:41552d038a69 171
Zaitsev 10:41552d038a69 172 /** \brief Breakpoint
Zaitsev 10:41552d038a69 173
Zaitsev 10:41552d038a69 174 This function causes the processor to enter Debug state.
Zaitsev 10:41552d038a69 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
Zaitsev 10:41552d038a69 176
Zaitsev 10:41552d038a69 177 \param [in] value is ignored by the processor.
Zaitsev 10:41552d038a69 178 If required, a debugger can use it to store additional information about the breakpoint.
Zaitsev 10:41552d038a69 179 */
Zaitsev 10:41552d038a69 180 #define __BKPT(value) __breakpoint(value)
Zaitsev 10:41552d038a69 181
Zaitsev 10:41552d038a69 182
Zaitsev 10:41552d038a69 183 /** \brief Reverse bit order of value
Zaitsev 10:41552d038a69 184
Zaitsev 10:41552d038a69 185 This function reverses the bit order of the given value.
Zaitsev 10:41552d038a69 186
Zaitsev 10:41552d038a69 187 \param [in] value Value to reverse
Zaitsev 10:41552d038a69 188 \return Reversed value
Zaitsev 10:41552d038a69 189 */
Zaitsev 10:41552d038a69 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
Zaitsev 10:41552d038a69 191 #define __RBIT __rbit
Zaitsev 10:41552d038a69 192 #else
Zaitsev 10:41552d038a69 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
Zaitsev 10:41552d038a69 194 {
Zaitsev 10:41552d038a69 195 uint32_t result;
Zaitsev 10:41552d038a69 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
Zaitsev 10:41552d038a69 197
Zaitsev 10:41552d038a69 198 result = value; // r will be reversed bits of v; first get LSB of v
Zaitsev 10:41552d038a69 199 for (value >>= 1; value; value >>= 1)
Zaitsev 10:41552d038a69 200 {
Zaitsev 10:41552d038a69 201 result <<= 1;
Zaitsev 10:41552d038a69 202 result |= value & 1;
Zaitsev 10:41552d038a69 203 s--;
Zaitsev 10:41552d038a69 204 }
Zaitsev 10:41552d038a69 205 result <<= s; // shift when v's highest bits are zero
Zaitsev 10:41552d038a69 206 return(result);
Zaitsev 10:41552d038a69 207 }
Zaitsev 10:41552d038a69 208 #endif
Zaitsev 10:41552d038a69 209
Zaitsev 10:41552d038a69 210
Zaitsev 10:41552d038a69 211 /** \brief Count leading zeros
Zaitsev 10:41552d038a69 212
Zaitsev 10:41552d038a69 213 This function counts the number of leading zeros of a data value.
Zaitsev 10:41552d038a69 214
Zaitsev 10:41552d038a69 215 \param [in] value Value to count the leading zeros
Zaitsev 10:41552d038a69 216 \return number of leading zeros in value
Zaitsev 10:41552d038a69 217 */
Zaitsev 10:41552d038a69 218 #define __CLZ __clz
Zaitsev 10:41552d038a69 219
Zaitsev 10:41552d038a69 220
Zaitsev 10:41552d038a69 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
Zaitsev 10:41552d038a69 222
Zaitsev 10:41552d038a69 223 /** \brief LDR Exclusive (8 bit)
Zaitsev 10:41552d038a69 224
Zaitsev 10:41552d038a69 225 This function executes a exclusive LDR instruction for 8 bit value.
Zaitsev 10:41552d038a69 226
Zaitsev 10:41552d038a69 227 \param [in] ptr Pointer to data
Zaitsev 10:41552d038a69 228 \return value of type uint8_t at (*ptr)
Zaitsev 10:41552d038a69 229 */
Zaitsev 10:41552d038a69 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
Zaitsev 10:41552d038a69 231
Zaitsev 10:41552d038a69 232
Zaitsev 10:41552d038a69 233 /** \brief LDR Exclusive (16 bit)
Zaitsev 10:41552d038a69 234
Zaitsev 10:41552d038a69 235 This function executes a exclusive LDR instruction for 16 bit values.
Zaitsev 10:41552d038a69 236
Zaitsev 10:41552d038a69 237 \param [in] ptr Pointer to data
Zaitsev 10:41552d038a69 238 \return value of type uint16_t at (*ptr)
Zaitsev 10:41552d038a69 239 */
Zaitsev 10:41552d038a69 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
Zaitsev 10:41552d038a69 241
Zaitsev 10:41552d038a69 242
Zaitsev 10:41552d038a69 243 /** \brief LDR Exclusive (32 bit)
Zaitsev 10:41552d038a69 244
Zaitsev 10:41552d038a69 245 This function executes a exclusive LDR instruction for 32 bit values.
Zaitsev 10:41552d038a69 246
Zaitsev 10:41552d038a69 247 \param [in] ptr Pointer to data
Zaitsev 10:41552d038a69 248 \return value of type uint32_t at (*ptr)
Zaitsev 10:41552d038a69 249 */
Zaitsev 10:41552d038a69 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
Zaitsev 10:41552d038a69 251
Zaitsev 10:41552d038a69 252
Zaitsev 10:41552d038a69 253 /** \brief STR Exclusive (8 bit)
Zaitsev 10:41552d038a69 254
Zaitsev 10:41552d038a69 255 This function executes a exclusive STR instruction for 8 bit values.
Zaitsev 10:41552d038a69 256
Zaitsev 10:41552d038a69 257 \param [in] value Value to store
Zaitsev 10:41552d038a69 258 \param [in] ptr Pointer to location
Zaitsev 10:41552d038a69 259 \return 0 Function succeeded
Zaitsev 10:41552d038a69 260 \return 1 Function failed
Zaitsev 10:41552d038a69 261 */
Zaitsev 10:41552d038a69 262 #define __STREXB(value, ptr) __strex(value, ptr)
Zaitsev 10:41552d038a69 263
Zaitsev 10:41552d038a69 264
Zaitsev 10:41552d038a69 265 /** \brief STR Exclusive (16 bit)
Zaitsev 10:41552d038a69 266
Zaitsev 10:41552d038a69 267 This function executes a exclusive STR instruction for 16 bit values.
Zaitsev 10:41552d038a69 268
Zaitsev 10:41552d038a69 269 \param [in] value Value to store
Zaitsev 10:41552d038a69 270 \param [in] ptr Pointer to location
Zaitsev 10:41552d038a69 271 \return 0 Function succeeded
Zaitsev 10:41552d038a69 272 \return 1 Function failed
Zaitsev 10:41552d038a69 273 */
Zaitsev 10:41552d038a69 274 #define __STREXH(value, ptr) __strex(value, ptr)
Zaitsev 10:41552d038a69 275
Zaitsev 10:41552d038a69 276
Zaitsev 10:41552d038a69 277 /** \brief STR Exclusive (32 bit)
Zaitsev 10:41552d038a69 278
Zaitsev 10:41552d038a69 279 This function executes a exclusive STR instruction for 32 bit values.
Zaitsev 10:41552d038a69 280
Zaitsev 10:41552d038a69 281 \param [in] value Value to store
Zaitsev 10:41552d038a69 282 \param [in] ptr Pointer to location
Zaitsev 10:41552d038a69 283 \return 0 Function succeeded
Zaitsev 10:41552d038a69 284 \return 1 Function failed
Zaitsev 10:41552d038a69 285 */
Zaitsev 10:41552d038a69 286 #define __STREXW(value, ptr) __strex(value, ptr)
Zaitsev 10:41552d038a69 287
Zaitsev 10:41552d038a69 288
Zaitsev 10:41552d038a69 289 /** \brief Remove the exclusive lock
Zaitsev 10:41552d038a69 290
Zaitsev 10:41552d038a69 291 This function removes the exclusive lock which is created by LDREX.
Zaitsev 10:41552d038a69 292
Zaitsev 10:41552d038a69 293 */
Zaitsev 10:41552d038a69 294 #define __CLREX __clrex
Zaitsev 10:41552d038a69 295
Zaitsev 10:41552d038a69 296
Zaitsev 10:41552d038a69 297 /** \brief Signed Saturate
Zaitsev 10:41552d038a69 298
Zaitsev 10:41552d038a69 299 This function saturates a signed value.
Zaitsev 10:41552d038a69 300
Zaitsev 10:41552d038a69 301 \param [in] value Value to be saturated
Zaitsev 10:41552d038a69 302 \param [in] sat Bit position to saturate to (1..32)
Zaitsev 10:41552d038a69 303 \return Saturated value
Zaitsev 10:41552d038a69 304 */
Zaitsev 10:41552d038a69 305 #define __SSAT __ssat
Zaitsev 10:41552d038a69 306
Zaitsev 10:41552d038a69 307
Zaitsev 10:41552d038a69 308 /** \brief Unsigned Saturate
Zaitsev 10:41552d038a69 309
Zaitsev 10:41552d038a69 310 This function saturates an unsigned value.
Zaitsev 10:41552d038a69 311
Zaitsev 10:41552d038a69 312 \param [in] value Value to be saturated
Zaitsev 10:41552d038a69 313 \param [in] sat Bit position to saturate to (0..31)
Zaitsev 10:41552d038a69 314 \return Saturated value
Zaitsev 10:41552d038a69 315 */
Zaitsev 10:41552d038a69 316 #define __USAT __usat
Zaitsev 10:41552d038a69 317
Zaitsev 10:41552d038a69 318
Zaitsev 10:41552d038a69 319 /** \brief Rotate Right with Extend (32 bit)
Zaitsev 10:41552d038a69 320
Zaitsev 10:41552d038a69 321 This function moves each bit of a bitstring right by one bit.
Zaitsev 10:41552d038a69 322 The carry input is shifted in at the left end of the bitstring.
Zaitsev 10:41552d038a69 323
Zaitsev 10:41552d038a69 324 \param [in] value Value to rotate
Zaitsev 10:41552d038a69 325 \return Rotated value
Zaitsev 10:41552d038a69 326 */
Zaitsev 10:41552d038a69 327 #ifndef __NO_EMBEDDED_ASM
Zaitsev 10:41552d038a69 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
Zaitsev 10:41552d038a69 329 {
Zaitsev 10:41552d038a69 330 rrx r0, r0
Zaitsev 10:41552d038a69 331 bx lr
Zaitsev 10:41552d038a69 332 }
Zaitsev 10:41552d038a69 333 #endif
Zaitsev 10:41552d038a69 334
Zaitsev 10:41552d038a69 335
Zaitsev 10:41552d038a69 336 /** \brief LDRT Unprivileged (8 bit)
Zaitsev 10:41552d038a69 337
Zaitsev 10:41552d038a69 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
Zaitsev 10:41552d038a69 339
Zaitsev 10:41552d038a69 340 \param [in] ptr Pointer to data
Zaitsev 10:41552d038a69 341 \return value of type uint8_t at (*ptr)
Zaitsev 10:41552d038a69 342 */
Zaitsev 10:41552d038a69 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
Zaitsev 10:41552d038a69 344
Zaitsev 10:41552d038a69 345
Zaitsev 10:41552d038a69 346 /** \brief LDRT Unprivileged (16 bit)
Zaitsev 10:41552d038a69 347
Zaitsev 10:41552d038a69 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
Zaitsev 10:41552d038a69 349
Zaitsev 10:41552d038a69 350 \param [in] ptr Pointer to data
Zaitsev 10:41552d038a69 351 \return value of type uint16_t at (*ptr)
Zaitsev 10:41552d038a69 352 */
Zaitsev 10:41552d038a69 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
Zaitsev 10:41552d038a69 354
Zaitsev 10:41552d038a69 355
Zaitsev 10:41552d038a69 356 /** \brief LDRT Unprivileged (32 bit)
Zaitsev 10:41552d038a69 357
Zaitsev 10:41552d038a69 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
Zaitsev 10:41552d038a69 359
Zaitsev 10:41552d038a69 360 \param [in] ptr Pointer to data
Zaitsev 10:41552d038a69 361 \return value of type uint32_t at (*ptr)
Zaitsev 10:41552d038a69 362 */
Zaitsev 10:41552d038a69 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
Zaitsev 10:41552d038a69 364
Zaitsev 10:41552d038a69 365
Zaitsev 10:41552d038a69 366 /** \brief STRT Unprivileged (8 bit)
Zaitsev 10:41552d038a69 367
Zaitsev 10:41552d038a69 368 This function executes a Unprivileged STRT instruction for 8 bit values.
Zaitsev 10:41552d038a69 369
Zaitsev 10:41552d038a69 370 \param [in] value Value to store
Zaitsev 10:41552d038a69 371 \param [in] ptr Pointer to location
Zaitsev 10:41552d038a69 372 */
Zaitsev 10:41552d038a69 373 #define __STRBT(value, ptr) __strt(value, ptr)
Zaitsev 10:41552d038a69 374
Zaitsev 10:41552d038a69 375
Zaitsev 10:41552d038a69 376 /** \brief STRT Unprivileged (16 bit)
Zaitsev 10:41552d038a69 377
Zaitsev 10:41552d038a69 378 This function executes a Unprivileged STRT instruction for 16 bit values.
Zaitsev 10:41552d038a69 379
Zaitsev 10:41552d038a69 380 \param [in] value Value to store
Zaitsev 10:41552d038a69 381 \param [in] ptr Pointer to location
Zaitsev 10:41552d038a69 382 */
Zaitsev 10:41552d038a69 383 #define __STRHT(value, ptr) __strt(value, ptr)
Zaitsev 10:41552d038a69 384
Zaitsev 10:41552d038a69 385
Zaitsev 10:41552d038a69 386 /** \brief STRT Unprivileged (32 bit)
Zaitsev 10:41552d038a69 387
Zaitsev 10:41552d038a69 388 This function executes a Unprivileged STRT instruction for 32 bit values.
Zaitsev 10:41552d038a69 389
Zaitsev 10:41552d038a69 390 \param [in] value Value to store
Zaitsev 10:41552d038a69 391 \param [in] ptr Pointer to location
Zaitsev 10:41552d038a69 392 */
Zaitsev 10:41552d038a69 393 #define __STRT(value, ptr) __strt(value, ptr)
Zaitsev 10:41552d038a69 394
Zaitsev 10:41552d038a69 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
Zaitsev 10:41552d038a69 396
Zaitsev 10:41552d038a69 397
Zaitsev 10:41552d038a69 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
Zaitsev 10:41552d038a69 399 /* GNU gcc specific functions */
Zaitsev 10:41552d038a69 400
Zaitsev 10:41552d038a69 401 /* Define macros for porting to both thumb1 and thumb2.
Zaitsev 10:41552d038a69 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
Zaitsev 10:41552d038a69 403 * Otherwise, use general registers, specified by constrant "r" */
Zaitsev 10:41552d038a69 404 #if defined (__thumb__) && !defined (__thumb2__)
Zaitsev 10:41552d038a69 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
Zaitsev 10:41552d038a69 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
Zaitsev 10:41552d038a69 407 #else
Zaitsev 10:41552d038a69 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
Zaitsev 10:41552d038a69 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
Zaitsev 10:41552d038a69 410 #endif
Zaitsev 10:41552d038a69 411
Zaitsev 10:41552d038a69 412 /** \brief No Operation
Zaitsev 10:41552d038a69 413
Zaitsev 10:41552d038a69 414 No Operation does nothing. This instruction can be used for code alignment purposes.
Zaitsev 10:41552d038a69 415 */
Zaitsev 10:41552d038a69 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
Zaitsev 10:41552d038a69 417 {
Zaitsev 10:41552d038a69 418 __ASM volatile ("nop");
Zaitsev 10:41552d038a69 419 }
Zaitsev 10:41552d038a69 420
Zaitsev 10:41552d038a69 421
Zaitsev 10:41552d038a69 422 /** \brief Wait For Interrupt
Zaitsev 10:41552d038a69 423
Zaitsev 10:41552d038a69 424 Wait For Interrupt is a hint instruction that suspends execution
Zaitsev 10:41552d038a69 425 until one of a number of events occurs.
Zaitsev 10:41552d038a69 426 */
Zaitsev 10:41552d038a69 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
Zaitsev 10:41552d038a69 428 {
Zaitsev 10:41552d038a69 429 __ASM volatile ("wfi");
Zaitsev 10:41552d038a69 430 }
Zaitsev 10:41552d038a69 431
Zaitsev 10:41552d038a69 432
Zaitsev 10:41552d038a69 433 /** \brief Wait For Event
Zaitsev 10:41552d038a69 434
Zaitsev 10:41552d038a69 435 Wait For Event is a hint instruction that permits the processor to enter
Zaitsev 10:41552d038a69 436 a low-power state until one of a number of events occurs.
Zaitsev 10:41552d038a69 437 */
Zaitsev 10:41552d038a69 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
Zaitsev 10:41552d038a69 439 {
Zaitsev 10:41552d038a69 440 __ASM volatile ("wfe");
Zaitsev 10:41552d038a69 441 }
Zaitsev 10:41552d038a69 442
Zaitsev 10:41552d038a69 443
Zaitsev 10:41552d038a69 444 /** \brief Send Event
Zaitsev 10:41552d038a69 445
Zaitsev 10:41552d038a69 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
Zaitsev 10:41552d038a69 447 */
Zaitsev 10:41552d038a69 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
Zaitsev 10:41552d038a69 449 {
Zaitsev 10:41552d038a69 450 __ASM volatile ("sev");
Zaitsev 10:41552d038a69 451 }
Zaitsev 10:41552d038a69 452
Zaitsev 10:41552d038a69 453
Zaitsev 10:41552d038a69 454 /** \brief Instruction Synchronization Barrier
Zaitsev 10:41552d038a69 455
Zaitsev 10:41552d038a69 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
Zaitsev 10:41552d038a69 457 so that all instructions following the ISB are fetched from cache or
Zaitsev 10:41552d038a69 458 memory, after the instruction has been completed.
Zaitsev 10:41552d038a69 459 */
Zaitsev 10:41552d038a69 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
Zaitsev 10:41552d038a69 461 {
Zaitsev 10:41552d038a69 462 __ASM volatile ("isb 0xF":::"memory");
Zaitsev 10:41552d038a69 463 }
Zaitsev 10:41552d038a69 464
Zaitsev 10:41552d038a69 465
Zaitsev 10:41552d038a69 466 /** \brief Data Synchronization Barrier
Zaitsev 10:41552d038a69 467
Zaitsev 10:41552d038a69 468 This function acts as a special kind of Data Memory Barrier.
Zaitsev 10:41552d038a69 469 It completes when all explicit memory accesses before this instruction complete.
Zaitsev 10:41552d038a69 470 */
Zaitsev 10:41552d038a69 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
Zaitsev 10:41552d038a69 472 {
Zaitsev 10:41552d038a69 473 __ASM volatile ("dsb 0xF":::"memory");
Zaitsev 10:41552d038a69 474 }
Zaitsev 10:41552d038a69 475
Zaitsev 10:41552d038a69 476
Zaitsev 10:41552d038a69 477 /** \brief Data Memory Barrier
Zaitsev 10:41552d038a69 478
Zaitsev 10:41552d038a69 479 This function ensures the apparent order of the explicit memory operations before
Zaitsev 10:41552d038a69 480 and after the instruction, without ensuring their completion.
Zaitsev 10:41552d038a69 481 */
Zaitsev 10:41552d038a69 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
Zaitsev 10:41552d038a69 483 {
Zaitsev 10:41552d038a69 484 __ASM volatile ("dmb 0xF":::"memory");
Zaitsev 10:41552d038a69 485 }
Zaitsev 10:41552d038a69 486
Zaitsev 10:41552d038a69 487
Zaitsev 10:41552d038a69 488 /** \brief Reverse byte order (32 bit)
Zaitsev 10:41552d038a69 489
Zaitsev 10:41552d038a69 490 This function reverses the byte order in integer value.
Zaitsev 10:41552d038a69 491
Zaitsev 10:41552d038a69 492 \param [in] value Value to reverse
Zaitsev 10:41552d038a69 493 \return Reversed value
Zaitsev 10:41552d038a69 494 */
Zaitsev 10:41552d038a69 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
Zaitsev 10:41552d038a69 496 {
Zaitsev 10:41552d038a69 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
Zaitsev 10:41552d038a69 498 return __builtin_bswap32(value);
Zaitsev 10:41552d038a69 499 #else
Zaitsev 10:41552d038a69 500 uint32_t result;
Zaitsev 10:41552d038a69 501
Zaitsev 10:41552d038a69 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
Zaitsev 10:41552d038a69 503 return(result);
Zaitsev 10:41552d038a69 504 #endif
Zaitsev 10:41552d038a69 505 }
Zaitsev 10:41552d038a69 506
Zaitsev 10:41552d038a69 507
Zaitsev 10:41552d038a69 508 /** \brief Reverse byte order (16 bit)
Zaitsev 10:41552d038a69 509
Zaitsev 10:41552d038a69 510 This function reverses the byte order in two unsigned short values.
Zaitsev 10:41552d038a69 511
Zaitsev 10:41552d038a69 512 \param [in] value Value to reverse
Zaitsev 10:41552d038a69 513 \return Reversed value
Zaitsev 10:41552d038a69 514 */
Zaitsev 10:41552d038a69 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
Zaitsev 10:41552d038a69 516 {
Zaitsev 10:41552d038a69 517 uint32_t result;
Zaitsev 10:41552d038a69 518
Zaitsev 10:41552d038a69 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
Zaitsev 10:41552d038a69 520 return(result);
Zaitsev 10:41552d038a69 521 }
Zaitsev 10:41552d038a69 522
Zaitsev 10:41552d038a69 523
Zaitsev 10:41552d038a69 524 /** \brief Reverse byte order in signed short value
Zaitsev 10:41552d038a69 525
Zaitsev 10:41552d038a69 526 This function reverses the byte order in a signed short value with sign extension to integer.
Zaitsev 10:41552d038a69 527
Zaitsev 10:41552d038a69 528 \param [in] value Value to reverse
Zaitsev 10:41552d038a69 529 \return Reversed value
Zaitsev 10:41552d038a69 530 */
Zaitsev 10:41552d038a69 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
Zaitsev 10:41552d038a69 532 {
Zaitsev 10:41552d038a69 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
Zaitsev 10:41552d038a69 534 return (short)__builtin_bswap16(value);
Zaitsev 10:41552d038a69 535 #else
Zaitsev 10:41552d038a69 536 uint32_t result;
Zaitsev 10:41552d038a69 537
Zaitsev 10:41552d038a69 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
Zaitsev 10:41552d038a69 539 return(result);
Zaitsev 10:41552d038a69 540 #endif
Zaitsev 10:41552d038a69 541 }
Zaitsev 10:41552d038a69 542
Zaitsev 10:41552d038a69 543
Zaitsev 10:41552d038a69 544 /** \brief Rotate Right in unsigned value (32 bit)
Zaitsev 10:41552d038a69 545
Zaitsev 10:41552d038a69 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
Zaitsev 10:41552d038a69 547
Zaitsev 10:41552d038a69 548 \param [in] value Value to rotate
Zaitsev 10:41552d038a69 549 \param [in] value Number of Bits to rotate
Zaitsev 10:41552d038a69 550 \return Rotated value
Zaitsev 10:41552d038a69 551 */
Zaitsev 10:41552d038a69 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
Zaitsev 10:41552d038a69 553 {
Zaitsev 10:41552d038a69 554 return (op1 >> op2) | (op1 << (32 - op2));
Zaitsev 10:41552d038a69 555 }
Zaitsev 10:41552d038a69 556
Zaitsev 10:41552d038a69 557
Zaitsev 10:41552d038a69 558 /** \brief Breakpoint
Zaitsev 10:41552d038a69 559
Zaitsev 10:41552d038a69 560 This function causes the processor to enter Debug state.
Zaitsev 10:41552d038a69 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
Zaitsev 10:41552d038a69 562
Zaitsev 10:41552d038a69 563 \param [in] value is ignored by the processor.
Zaitsev 10:41552d038a69 564 If required, a debugger can use it to store additional information about the breakpoint.
Zaitsev 10:41552d038a69 565 */
Zaitsev 10:41552d038a69 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
Zaitsev 10:41552d038a69 567
Zaitsev 10:41552d038a69 568
Zaitsev 10:41552d038a69 569 /** \brief Reverse bit order of value
Zaitsev 10:41552d038a69 570
Zaitsev 10:41552d038a69 571 This function reverses the bit order of the given value.
Zaitsev 10:41552d038a69 572
Zaitsev 10:41552d038a69 573 \param [in] value Value to reverse
Zaitsev 10:41552d038a69 574 \return Reversed value
Zaitsev 10:41552d038a69 575 */
Zaitsev 10:41552d038a69 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
Zaitsev 10:41552d038a69 577 {
Zaitsev 10:41552d038a69 578 uint32_t result;
Zaitsev 10:41552d038a69 579
Zaitsev 10:41552d038a69 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
Zaitsev 10:41552d038a69 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
Zaitsev 10:41552d038a69 582 #else
Zaitsev 10:41552d038a69 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
Zaitsev 10:41552d038a69 584
Zaitsev 10:41552d038a69 585 result = value; // r will be reversed bits of v; first get LSB of v
Zaitsev 10:41552d038a69 586 for (value >>= 1; value; value >>= 1)
Zaitsev 10:41552d038a69 587 {
Zaitsev 10:41552d038a69 588 result <<= 1;
Zaitsev 10:41552d038a69 589 result |= value & 1;
Zaitsev 10:41552d038a69 590 s--;
Zaitsev 10:41552d038a69 591 }
Zaitsev 10:41552d038a69 592 result <<= s; // shift when v's highest bits are zero
Zaitsev 10:41552d038a69 593 #endif
Zaitsev 10:41552d038a69 594 return(result);
Zaitsev 10:41552d038a69 595 }
Zaitsev 10:41552d038a69 596
Zaitsev 10:41552d038a69 597
Zaitsev 10:41552d038a69 598 /** \brief Count leading zeros
Zaitsev 10:41552d038a69 599
Zaitsev 10:41552d038a69 600 This function counts the number of leading zeros of a data value.
Zaitsev 10:41552d038a69 601
Zaitsev 10:41552d038a69 602 \param [in] value Value to count the leading zeros
Zaitsev 10:41552d038a69 603 \return number of leading zeros in value
Zaitsev 10:41552d038a69 604 */
Zaitsev 10:41552d038a69 605 #define __CLZ __builtin_clz
Zaitsev 10:41552d038a69 606
Zaitsev 10:41552d038a69 607
Zaitsev 10:41552d038a69 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
Zaitsev 10:41552d038a69 609
Zaitsev 10:41552d038a69 610 /** \brief LDR Exclusive (8 bit)
Zaitsev 10:41552d038a69 611
Zaitsev 10:41552d038a69 612 This function executes a exclusive LDR instruction for 8 bit value.
Zaitsev 10:41552d038a69 613
Zaitsev 10:41552d038a69 614 \param [in] ptr Pointer to data
Zaitsev 10:41552d038a69 615 \return value of type uint8_t at (*ptr)
Zaitsev 10:41552d038a69 616 */
Zaitsev 10:41552d038a69 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
Zaitsev 10:41552d038a69 618 {
Zaitsev 10:41552d038a69 619 uint32_t result;
Zaitsev 10:41552d038a69 620
Zaitsev 10:41552d038a69 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
Zaitsev 10:41552d038a69 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
Zaitsev 10:41552d038a69 623 #else
Zaitsev 10:41552d038a69 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
Zaitsev 10:41552d038a69 625 accepted by assembler. So has to use following less efficient pattern.
Zaitsev 10:41552d038a69 626 */
Zaitsev 10:41552d038a69 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
Zaitsev 10:41552d038a69 628 #endif
Zaitsev 10:41552d038a69 629 return ((uint8_t) result); /* Add explicit type cast here */
Zaitsev 10:41552d038a69 630 }
Zaitsev 10:41552d038a69 631
Zaitsev 10:41552d038a69 632
Zaitsev 10:41552d038a69 633 /** \brief LDR Exclusive (16 bit)
Zaitsev 10:41552d038a69 634
Zaitsev 10:41552d038a69 635 This function executes a exclusive LDR instruction for 16 bit values.
Zaitsev 10:41552d038a69 636
Zaitsev 10:41552d038a69 637 \param [in] ptr Pointer to data
Zaitsev 10:41552d038a69 638 \return value of type uint16_t at (*ptr)
Zaitsev 10:41552d038a69 639 */
Zaitsev 10:41552d038a69 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
Zaitsev 10:41552d038a69 641 {
Zaitsev 10:41552d038a69 642 uint32_t result;
Zaitsev 10:41552d038a69 643
Zaitsev 10:41552d038a69 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
Zaitsev 10:41552d038a69 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
Zaitsev 10:41552d038a69 646 #else
Zaitsev 10:41552d038a69 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
Zaitsev 10:41552d038a69 648 accepted by assembler. So has to use following less efficient pattern.
Zaitsev 10:41552d038a69 649 */
Zaitsev 10:41552d038a69 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
Zaitsev 10:41552d038a69 651 #endif
Zaitsev 10:41552d038a69 652 return ((uint16_t) result); /* Add explicit type cast here */
Zaitsev 10:41552d038a69 653 }
Zaitsev 10:41552d038a69 654
Zaitsev 10:41552d038a69 655
Zaitsev 10:41552d038a69 656 /** \brief LDR Exclusive (32 bit)
Zaitsev 10:41552d038a69 657
Zaitsev 10:41552d038a69 658 This function executes a exclusive LDR instruction for 32 bit values.
Zaitsev 10:41552d038a69 659
Zaitsev 10:41552d038a69 660 \param [in] ptr Pointer to data
Zaitsev 10:41552d038a69 661 \return value of type uint32_t at (*ptr)
Zaitsev 10:41552d038a69 662 */
Zaitsev 10:41552d038a69 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
Zaitsev 10:41552d038a69 664 {
Zaitsev 10:41552d038a69 665 uint32_t result;
Zaitsev 10:41552d038a69 666
Zaitsev 10:41552d038a69 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
Zaitsev 10:41552d038a69 668 return(result);
Zaitsev 10:41552d038a69 669 }
Zaitsev 10:41552d038a69 670
Zaitsev 10:41552d038a69 671
Zaitsev 10:41552d038a69 672 /** \brief STR Exclusive (8 bit)
Zaitsev 10:41552d038a69 673
Zaitsev 10:41552d038a69 674 This function executes a exclusive STR instruction for 8 bit values.
Zaitsev 10:41552d038a69 675
Zaitsev 10:41552d038a69 676 \param [in] value Value to store
Zaitsev 10:41552d038a69 677 \param [in] ptr Pointer to location
Zaitsev 10:41552d038a69 678 \return 0 Function succeeded
Zaitsev 10:41552d038a69 679 \return 1 Function failed
Zaitsev 10:41552d038a69 680 */
Zaitsev 10:41552d038a69 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
Zaitsev 10:41552d038a69 682 {
Zaitsev 10:41552d038a69 683 uint32_t result;
Zaitsev 10:41552d038a69 684
Zaitsev 10:41552d038a69 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
Zaitsev 10:41552d038a69 686 return(result);
Zaitsev 10:41552d038a69 687 }
Zaitsev 10:41552d038a69 688
Zaitsev 10:41552d038a69 689
Zaitsev 10:41552d038a69 690 /** \brief STR Exclusive (16 bit)
Zaitsev 10:41552d038a69 691
Zaitsev 10:41552d038a69 692 This function executes a exclusive STR instruction for 16 bit values.
Zaitsev 10:41552d038a69 693
Zaitsev 10:41552d038a69 694 \param [in] value Value to store
Zaitsev 10:41552d038a69 695 \param [in] ptr Pointer to location
Zaitsev 10:41552d038a69 696 \return 0 Function succeeded
Zaitsev 10:41552d038a69 697 \return 1 Function failed
Zaitsev 10:41552d038a69 698 */
Zaitsev 10:41552d038a69 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
Zaitsev 10:41552d038a69 700 {
Zaitsev 10:41552d038a69 701 uint32_t result;
Zaitsev 10:41552d038a69 702
Zaitsev 10:41552d038a69 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
Zaitsev 10:41552d038a69 704 return(result);
Zaitsev 10:41552d038a69 705 }
Zaitsev 10:41552d038a69 706
Zaitsev 10:41552d038a69 707
Zaitsev 10:41552d038a69 708 /** \brief STR Exclusive (32 bit)
Zaitsev 10:41552d038a69 709
Zaitsev 10:41552d038a69 710 This function executes a exclusive STR instruction for 32 bit values.
Zaitsev 10:41552d038a69 711
Zaitsev 10:41552d038a69 712 \param [in] value Value to store
Zaitsev 10:41552d038a69 713 \param [in] ptr Pointer to location
Zaitsev 10:41552d038a69 714 \return 0 Function succeeded
Zaitsev 10:41552d038a69 715 \return 1 Function failed
Zaitsev 10:41552d038a69 716 */
Zaitsev 10:41552d038a69 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
Zaitsev 10:41552d038a69 718 {
Zaitsev 10:41552d038a69 719 uint32_t result;
Zaitsev 10:41552d038a69 720
Zaitsev 10:41552d038a69 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
Zaitsev 10:41552d038a69 722 return(result);
Zaitsev 10:41552d038a69 723 }
Zaitsev 10:41552d038a69 724
Zaitsev 10:41552d038a69 725
Zaitsev 10:41552d038a69 726 /** \brief Remove the exclusive lock
Zaitsev 10:41552d038a69 727
Zaitsev 10:41552d038a69 728 This function removes the exclusive lock which is created by LDREX.
Zaitsev 10:41552d038a69 729
Zaitsev 10:41552d038a69 730 */
Zaitsev 10:41552d038a69 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
Zaitsev 10:41552d038a69 732 {
Zaitsev 10:41552d038a69 733 __ASM volatile ("clrex" ::: "memory");
Zaitsev 10:41552d038a69 734 }
Zaitsev 10:41552d038a69 735
Zaitsev 10:41552d038a69 736
Zaitsev 10:41552d038a69 737 /** \brief Signed Saturate
Zaitsev 10:41552d038a69 738
Zaitsev 10:41552d038a69 739 This function saturates a signed value.
Zaitsev 10:41552d038a69 740
Zaitsev 10:41552d038a69 741 \param [in] value Value to be saturated
Zaitsev 10:41552d038a69 742 \param [in] sat Bit position to saturate to (1..32)
Zaitsev 10:41552d038a69 743 \return Saturated value
Zaitsev 10:41552d038a69 744 */
Zaitsev 10:41552d038a69 745 #define __SSAT(ARG1,ARG2) \
Zaitsev 10:41552d038a69 746 ({ \
Zaitsev 10:41552d038a69 747 uint32_t __RES, __ARG1 = (ARG1); \
Zaitsev 10:41552d038a69 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
Zaitsev 10:41552d038a69 749 __RES; \
Zaitsev 10:41552d038a69 750 })
Zaitsev 10:41552d038a69 751
Zaitsev 10:41552d038a69 752
Zaitsev 10:41552d038a69 753 /** \brief Unsigned Saturate
Zaitsev 10:41552d038a69 754
Zaitsev 10:41552d038a69 755 This function saturates an unsigned value.
Zaitsev 10:41552d038a69 756
Zaitsev 10:41552d038a69 757 \param [in] value Value to be saturated
Zaitsev 10:41552d038a69 758 \param [in] sat Bit position to saturate to (0..31)
Zaitsev 10:41552d038a69 759 \return Saturated value
Zaitsev 10:41552d038a69 760 */
Zaitsev 10:41552d038a69 761 #define __USAT(ARG1,ARG2) \
Zaitsev 10:41552d038a69 762 ({ \
Zaitsev 10:41552d038a69 763 uint32_t __RES, __ARG1 = (ARG1); \
Zaitsev 10:41552d038a69 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
Zaitsev 10:41552d038a69 765 __RES; \
Zaitsev 10:41552d038a69 766 })
Zaitsev 10:41552d038a69 767
Zaitsev 10:41552d038a69 768
Zaitsev 10:41552d038a69 769 /** \brief Rotate Right with Extend (32 bit)
Zaitsev 10:41552d038a69 770
Zaitsev 10:41552d038a69 771 This function moves each bit of a bitstring right by one bit.
Zaitsev 10:41552d038a69 772 The carry input is shifted in at the left end of the bitstring.
Zaitsev 10:41552d038a69 773
Zaitsev 10:41552d038a69 774 \param [in] value Value to rotate
Zaitsev 10:41552d038a69 775 \return Rotated value
Zaitsev 10:41552d038a69 776 */
Zaitsev 10:41552d038a69 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
Zaitsev 10:41552d038a69 778 {
Zaitsev 10:41552d038a69 779 uint32_t result;
Zaitsev 10:41552d038a69 780
Zaitsev 10:41552d038a69 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
Zaitsev 10:41552d038a69 782 return(result);
Zaitsev 10:41552d038a69 783 }
Zaitsev 10:41552d038a69 784
Zaitsev 10:41552d038a69 785
Zaitsev 10:41552d038a69 786 /** \brief LDRT Unprivileged (8 bit)
Zaitsev 10:41552d038a69 787
Zaitsev 10:41552d038a69 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
Zaitsev 10:41552d038a69 789
Zaitsev 10:41552d038a69 790 \param [in] ptr Pointer to data
Zaitsev 10:41552d038a69 791 \return value of type uint8_t at (*ptr)
Zaitsev 10:41552d038a69 792 */
Zaitsev 10:41552d038a69 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
Zaitsev 10:41552d038a69 794 {
Zaitsev 10:41552d038a69 795 uint32_t result;
Zaitsev 10:41552d038a69 796
Zaitsev 10:41552d038a69 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
Zaitsev 10:41552d038a69 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
Zaitsev 10:41552d038a69 799 #else
Zaitsev 10:41552d038a69 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
Zaitsev 10:41552d038a69 801 accepted by assembler. So has to use following less efficient pattern.
Zaitsev 10:41552d038a69 802 */
Zaitsev 10:41552d038a69 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
Zaitsev 10:41552d038a69 804 #endif
Zaitsev 10:41552d038a69 805 return ((uint8_t) result); /* Add explicit type cast here */
Zaitsev 10:41552d038a69 806 }
Zaitsev 10:41552d038a69 807
Zaitsev 10:41552d038a69 808
Zaitsev 10:41552d038a69 809 /** \brief LDRT Unprivileged (16 bit)
Zaitsev 10:41552d038a69 810
Zaitsev 10:41552d038a69 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
Zaitsev 10:41552d038a69 812
Zaitsev 10:41552d038a69 813 \param [in] ptr Pointer to data
Zaitsev 10:41552d038a69 814 \return value of type uint16_t at (*ptr)
Zaitsev 10:41552d038a69 815 */
Zaitsev 10:41552d038a69 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
Zaitsev 10:41552d038a69 817 {
Zaitsev 10:41552d038a69 818 uint32_t result;
Zaitsev 10:41552d038a69 819
Zaitsev 10:41552d038a69 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
Zaitsev 10:41552d038a69 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
Zaitsev 10:41552d038a69 822 #else
Zaitsev 10:41552d038a69 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
Zaitsev 10:41552d038a69 824 accepted by assembler. So has to use following less efficient pattern.
Zaitsev 10:41552d038a69 825 */
Zaitsev 10:41552d038a69 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
Zaitsev 10:41552d038a69 827 #endif
Zaitsev 10:41552d038a69 828 return ((uint16_t) result); /* Add explicit type cast here */
Zaitsev 10:41552d038a69 829 }
Zaitsev 10:41552d038a69 830
Zaitsev 10:41552d038a69 831
Zaitsev 10:41552d038a69 832 /** \brief LDRT Unprivileged (32 bit)
Zaitsev 10:41552d038a69 833
Zaitsev 10:41552d038a69 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
Zaitsev 10:41552d038a69 835
Zaitsev 10:41552d038a69 836 \param [in] ptr Pointer to data
Zaitsev 10:41552d038a69 837 \return value of type uint32_t at (*ptr)
Zaitsev 10:41552d038a69 838 */
Zaitsev 10:41552d038a69 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
Zaitsev 10:41552d038a69 840 {
Zaitsev 10:41552d038a69 841 uint32_t result;
Zaitsev 10:41552d038a69 842
Zaitsev 10:41552d038a69 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
Zaitsev 10:41552d038a69 844 return(result);
Zaitsev 10:41552d038a69 845 }
Zaitsev 10:41552d038a69 846
Zaitsev 10:41552d038a69 847
Zaitsev 10:41552d038a69 848 /** \brief STRT Unprivileged (8 bit)
Zaitsev 10:41552d038a69 849
Zaitsev 10:41552d038a69 850 This function executes a Unprivileged STRT instruction for 8 bit values.
Zaitsev 10:41552d038a69 851
Zaitsev 10:41552d038a69 852 \param [in] value Value to store
Zaitsev 10:41552d038a69 853 \param [in] ptr Pointer to location
Zaitsev 10:41552d038a69 854 */
Zaitsev 10:41552d038a69 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
Zaitsev 10:41552d038a69 856 {
Zaitsev 10:41552d038a69 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
Zaitsev 10:41552d038a69 858 }
Zaitsev 10:41552d038a69 859
Zaitsev 10:41552d038a69 860
Zaitsev 10:41552d038a69 861 /** \brief STRT Unprivileged (16 bit)
Zaitsev 10:41552d038a69 862
Zaitsev 10:41552d038a69 863 This function executes a Unprivileged STRT instruction for 16 bit values.
Zaitsev 10:41552d038a69 864
Zaitsev 10:41552d038a69 865 \param [in] value Value to store
Zaitsev 10:41552d038a69 866 \param [in] ptr Pointer to location
Zaitsev 10:41552d038a69 867 */
Zaitsev 10:41552d038a69 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
Zaitsev 10:41552d038a69 869 {
Zaitsev 10:41552d038a69 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
Zaitsev 10:41552d038a69 871 }
Zaitsev 10:41552d038a69 872
Zaitsev 10:41552d038a69 873
Zaitsev 10:41552d038a69 874 /** \brief STRT Unprivileged (32 bit)
Zaitsev 10:41552d038a69 875
Zaitsev 10:41552d038a69 876 This function executes a Unprivileged STRT instruction for 32 bit values.
Zaitsev 10:41552d038a69 877
Zaitsev 10:41552d038a69 878 \param [in] value Value to store
Zaitsev 10:41552d038a69 879 \param [in] ptr Pointer to location
Zaitsev 10:41552d038a69 880 */
Zaitsev 10:41552d038a69 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
Zaitsev 10:41552d038a69 882 {
Zaitsev 10:41552d038a69 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
Zaitsev 10:41552d038a69 884 }
Zaitsev 10:41552d038a69 885
Zaitsev 10:41552d038a69 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
Zaitsev 10:41552d038a69 887
Zaitsev 10:41552d038a69 888
Zaitsev 10:41552d038a69 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
Zaitsev 10:41552d038a69 890 /* IAR iccarm specific functions */
Zaitsev 10:41552d038a69 891 #include <cmsis_iar.h>
Zaitsev 10:41552d038a69 892
Zaitsev 10:41552d038a69 893
Zaitsev 10:41552d038a69 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
Zaitsev 10:41552d038a69 895 /* TI CCS specific functions */
Zaitsev 10:41552d038a69 896 #include <cmsis_ccs.h>
Zaitsev 10:41552d038a69 897
Zaitsev 10:41552d038a69 898
Zaitsev 10:41552d038a69 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
Zaitsev 10:41552d038a69 900 /* TASKING carm specific functions */
Zaitsev 10:41552d038a69 901 /*
Zaitsev 10:41552d038a69 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
Zaitsev 10:41552d038a69 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
Zaitsev 10:41552d038a69 904 * Including the CMSIS ones.
Zaitsev 10:41552d038a69 905 */
Zaitsev 10:41552d038a69 906
Zaitsev 10:41552d038a69 907
Zaitsev 10:41552d038a69 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
Zaitsev 10:41552d038a69 909 /* Cosmic specific functions */
Zaitsev 10:41552d038a69 910 #include <cmsis_csm.h>
Zaitsev 10:41552d038a69 911
Zaitsev 10:41552d038a69 912 #endif
Zaitsev 10:41552d038a69 913
Zaitsev 10:41552d038a69 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
Zaitsev 10:41552d038a69 915
Zaitsev 10:41552d038a69 916 #endif /* __CORE_CMINSTR_H */