Mateusz Kowalik / Application

USB Serial application

Fork of USBSerial_HelloWorld by Samuel Mokrani

mbed-dev/cmsis/core_cm7.h@11:b3f2a8bdac4d, 2017-12-16 (annotated)

Committer:
Zaitsev
Date:
Sat Dec 16 10:26:48 2017 +0000
Revision:
11:b3f2a8bdac4d
Parent:
10:41552d038a69 
A copy for D.S;

Who changed what in which revision?

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Zaitsev 10:41552d038a69 1 /**************************************************************************//**
Zaitsev 10:41552d038a69 2 * @file core_cm7.h
Zaitsev 10:41552d038a69 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
Zaitsev 10:41552d038a69 4 * @version V4.10
Zaitsev 10:41552d038a69 5 * @date 18. March 2015
Zaitsev 10:41552d038a69 6 *
Zaitsev 10:41552d038a69 7 * @note
Zaitsev 10:41552d038a69 8 *
Zaitsev 10:41552d038a69 9 ******************************************************************************/
Zaitsev 10:41552d038a69 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Zaitsev 10:41552d038a69 11
Zaitsev 10:41552d038a69 12 All rights reserved.
Zaitsev 10:41552d038a69 13 Redistribution and use in source and binary forms, with or without
Zaitsev 10:41552d038a69 14 modification, are permitted provided that the following conditions are met:
Zaitsev 10:41552d038a69 15 - Redistributions of source code must retain the above copyright
Zaitsev 10:41552d038a69 16 notice, this list of conditions and the following disclaimer.
Zaitsev 10:41552d038a69 17 - Redistributions in binary form must reproduce the above copyright
Zaitsev 10:41552d038a69 18 notice, this list of conditions and the following disclaimer in the
Zaitsev 10:41552d038a69 19 documentation and/or other materials provided with the distribution.
Zaitsev 10:41552d038a69 20 - Neither the name of ARM nor the names of its contributors may be used
Zaitsev 10:41552d038a69 21 to endorse or promote products derived from this software without
Zaitsev 10:41552d038a69 22 specific prior written permission.
Zaitsev 10:41552d038a69 23 *
Zaitsev 10:41552d038a69 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Zaitsev 10:41552d038a69 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Zaitsev 10:41552d038a69 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Zaitsev 10:41552d038a69 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Zaitsev 10:41552d038a69 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Zaitsev 10:41552d038a69 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Zaitsev 10:41552d038a69 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Zaitsev 10:41552d038a69 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Zaitsev 10:41552d038a69 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Zaitsev 10:41552d038a69 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Zaitsev 10:41552d038a69 34 POSSIBILITY OF SUCH DAMAGE.
Zaitsev 10:41552d038a69 35 ---------------------------------------------------------------------------*/
Zaitsev 10:41552d038a69 36
Zaitsev 10:41552d038a69 37
Zaitsev 10:41552d038a69 38 #if defined ( __ICCARM__ )
Zaitsev 10:41552d038a69 39 #pragma system_include /* treat file as system include file for MISRA check */
Zaitsev 10:41552d038a69 40 #endif
Zaitsev 10:41552d038a69 41
Zaitsev 10:41552d038a69 42 #ifndef __CORE_CM7_H_GENERIC
Zaitsev 10:41552d038a69 43 #define __CORE_CM7_H_GENERIC
Zaitsev 10:41552d038a69 44
Zaitsev 10:41552d038a69 45 #ifdef __cplusplus
Zaitsev 10:41552d038a69 46 extern "C" {
Zaitsev 10:41552d038a69 47 #endif
Zaitsev 10:41552d038a69 48
Zaitsev 10:41552d038a69 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Zaitsev 10:41552d038a69 50 CMSIS violates the following MISRA-C:2004 rules:
Zaitsev 10:41552d038a69 51
Zaitsev 10:41552d038a69 52 \li Required Rule 8.5, object/function definition in header file.<br>
Zaitsev 10:41552d038a69 53 Function definitions in header files are used to allow 'inlining'.
Zaitsev 10:41552d038a69 54
Zaitsev 10:41552d038a69 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Zaitsev 10:41552d038a69 56 Unions are used for effective representation of core registers.
Zaitsev 10:41552d038a69 57
Zaitsev 10:41552d038a69 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Zaitsev 10:41552d038a69 59 Function-like macros are used to allow more efficient code.
Zaitsev 10:41552d038a69 60 */
Zaitsev 10:41552d038a69 61
Zaitsev 10:41552d038a69 62
Zaitsev 10:41552d038a69 63 /*******************************************************************************
Zaitsev 10:41552d038a69 64 * CMSIS definitions
Zaitsev 10:41552d038a69 65 ******************************************************************************/
Zaitsev 10:41552d038a69 66 /** \ingroup Cortex_M7
Zaitsev 10:41552d038a69 67 @{
Zaitsev 10:41552d038a69 68 */
Zaitsev 10:41552d038a69 69
Zaitsev 10:41552d038a69 70 /* CMSIS CM7 definitions */
Zaitsev 10:41552d038a69 71 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Zaitsev 10:41552d038a69 72 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Zaitsev 10:41552d038a69 73 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
Zaitsev 10:41552d038a69 74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Zaitsev 10:41552d038a69 75
Zaitsev 10:41552d038a69 76 #define __CORTEX_M (0x07) /*!< Cortex-M Core */
Zaitsev 10:41552d038a69 77
Zaitsev 10:41552d038a69 78
Zaitsev 10:41552d038a69 79 #if defined ( __CC_ARM )
Zaitsev 10:41552d038a69 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Zaitsev 10:41552d038a69 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Zaitsev 10:41552d038a69 82 #define __STATIC_INLINE static __inline
Zaitsev 10:41552d038a69 83
Zaitsev 10:41552d038a69 84 #elif defined ( __GNUC__ )
Zaitsev 10:41552d038a69 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Zaitsev 10:41552d038a69 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Zaitsev 10:41552d038a69 87 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 88
Zaitsev 10:41552d038a69 89 #elif defined ( __ICCARM__ )
Zaitsev 10:41552d038a69 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Zaitsev 10:41552d038a69 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Zaitsev 10:41552d038a69 92 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 93
Zaitsev 10:41552d038a69 94 #elif defined ( __TMS470__ )
Zaitsev 10:41552d038a69 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Zaitsev 10:41552d038a69 96 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 97
Zaitsev 10:41552d038a69 98 #elif defined ( __TASKING__ )
Zaitsev 10:41552d038a69 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Zaitsev 10:41552d038a69 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Zaitsev 10:41552d038a69 101 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 102
Zaitsev 10:41552d038a69 103 #elif defined ( __CSMC__ )
Zaitsev 10:41552d038a69 104 #define __packed
Zaitsev 10:41552d038a69 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Zaitsev 10:41552d038a69 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Zaitsev 10:41552d038a69 107 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 108
Zaitsev 10:41552d038a69 109 #endif
Zaitsev 10:41552d038a69 110
Zaitsev 10:41552d038a69 111 /** __FPU_USED indicates whether an FPU is used or not.
Zaitsev 10:41552d038a69 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Zaitsev 10:41552d038a69 113 */
Zaitsev 10:41552d038a69 114 #if defined ( __CC_ARM )
Zaitsev 10:41552d038a69 115 #if defined __TARGET_FPU_VFP
Zaitsev 10:41552d038a69 116 #if (__FPU_PRESENT == 1)
Zaitsev 10:41552d038a69 117 #define __FPU_USED 1
Zaitsev 10:41552d038a69 118 #else
Zaitsev 10:41552d038a69 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 120 #define __FPU_USED 0
Zaitsev 10:41552d038a69 121 #endif
Zaitsev 10:41552d038a69 122 #else
Zaitsev 10:41552d038a69 123 #define __FPU_USED 0
Zaitsev 10:41552d038a69 124 #endif
Zaitsev 10:41552d038a69 125
Zaitsev 10:41552d038a69 126 #elif defined ( __GNUC__ )
Zaitsev 10:41552d038a69 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Zaitsev 10:41552d038a69 128 #if (__FPU_PRESENT == 1)
Zaitsev 10:41552d038a69 129 #define __FPU_USED 1
Zaitsev 10:41552d038a69 130 #else
Zaitsev 10:41552d038a69 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 132 #define __FPU_USED 0
Zaitsev 10:41552d038a69 133 #endif
Zaitsev 10:41552d038a69 134 #else
Zaitsev 10:41552d038a69 135 #define __FPU_USED 0
Zaitsev 10:41552d038a69 136 #endif
Zaitsev 10:41552d038a69 137
Zaitsev 10:41552d038a69 138 #elif defined ( __ICCARM__ )
Zaitsev 10:41552d038a69 139 #if defined __ARMVFP__
Zaitsev 10:41552d038a69 140 #if (__FPU_PRESENT == 1)
Zaitsev 10:41552d038a69 141 #define __FPU_USED 1
Zaitsev 10:41552d038a69 142 #else
Zaitsev 10:41552d038a69 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 144 #define __FPU_USED 0
Zaitsev 10:41552d038a69 145 #endif
Zaitsev 10:41552d038a69 146 #else
Zaitsev 10:41552d038a69 147 #define __FPU_USED 0
Zaitsev 10:41552d038a69 148 #endif
Zaitsev 10:41552d038a69 149
Zaitsev 10:41552d038a69 150 #elif defined ( __TMS470__ )
Zaitsev 10:41552d038a69 151 #if defined __TI_VFP_SUPPORT__
Zaitsev 10:41552d038a69 152 #if (__FPU_PRESENT == 1)
Zaitsev 10:41552d038a69 153 #define __FPU_USED 1
Zaitsev 10:41552d038a69 154 #else
Zaitsev 10:41552d038a69 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 156 #define __FPU_USED 0
Zaitsev 10:41552d038a69 157 #endif
Zaitsev 10:41552d038a69 158 #else
Zaitsev 10:41552d038a69 159 #define __FPU_USED 0
Zaitsev 10:41552d038a69 160 #endif
Zaitsev 10:41552d038a69 161
Zaitsev 10:41552d038a69 162 #elif defined ( __TASKING__ )
Zaitsev 10:41552d038a69 163 #if defined __FPU_VFP__
Zaitsev 10:41552d038a69 164 #if (__FPU_PRESENT == 1)
Zaitsev 10:41552d038a69 165 #define __FPU_USED 1
Zaitsev 10:41552d038a69 166 #else
Zaitsev 10:41552d038a69 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 168 #define __FPU_USED 0
Zaitsev 10:41552d038a69 169 #endif
Zaitsev 10:41552d038a69 170 #else
Zaitsev 10:41552d038a69 171 #define __FPU_USED 0
Zaitsev 10:41552d038a69 172 #endif
Zaitsev 10:41552d038a69 173
Zaitsev 10:41552d038a69 174 #elif defined ( __CSMC__ ) /* Cosmic */
Zaitsev 10:41552d038a69 175 #if ( __CSMC__ & 0x400) // FPU present for parser
Zaitsev 10:41552d038a69 176 #if (__FPU_PRESENT == 1)
Zaitsev 10:41552d038a69 177 #define __FPU_USED 1
Zaitsev 10:41552d038a69 178 #else
Zaitsev 10:41552d038a69 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 180 #define __FPU_USED 0
Zaitsev 10:41552d038a69 181 #endif
Zaitsev 10:41552d038a69 182 #else
Zaitsev 10:41552d038a69 183 #define __FPU_USED 0
Zaitsev 10:41552d038a69 184 #endif
Zaitsev 10:41552d038a69 185 #endif
Zaitsev 10:41552d038a69 186
Zaitsev 10:41552d038a69 187 #include <stdint.h> /* standard types definitions */
Zaitsev 10:41552d038a69 188 #include <core_cmInstr.h> /* Core Instruction Access */
Zaitsev 10:41552d038a69 189 #include <core_cmFunc.h> /* Core Function Access */
Zaitsev 10:41552d038a69 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
Zaitsev 10:41552d038a69 191
Zaitsev 10:41552d038a69 192 #ifdef __cplusplus
Zaitsev 10:41552d038a69 193 }
Zaitsev 10:41552d038a69 194 #endif
Zaitsev 10:41552d038a69 195
Zaitsev 10:41552d038a69 196 #endif /* __CORE_CM7_H_GENERIC */
Zaitsev 10:41552d038a69 197
Zaitsev 10:41552d038a69 198 #ifndef __CMSIS_GENERIC
Zaitsev 10:41552d038a69 199
Zaitsev 10:41552d038a69 200 #ifndef __CORE_CM7_H_DEPENDANT
Zaitsev 10:41552d038a69 201 #define __CORE_CM7_H_DEPENDANT
Zaitsev 10:41552d038a69 202
Zaitsev 10:41552d038a69 203 #ifdef __cplusplus
Zaitsev 10:41552d038a69 204 extern "C" {
Zaitsev 10:41552d038a69 205 #endif
Zaitsev 10:41552d038a69 206
Zaitsev 10:41552d038a69 207 /* check device defines and use defaults */
Zaitsev 10:41552d038a69 208 #if defined __CHECK_DEVICE_DEFINES
Zaitsev 10:41552d038a69 209 #ifndef __CM7_REV
Zaitsev 10:41552d038a69 210 #define __CM7_REV 0x0000
Zaitsev 10:41552d038a69 211 #warning "__CM7_REV not defined in device header file; using default!"
Zaitsev 10:41552d038a69 212 #endif
Zaitsev 10:41552d038a69 213
Zaitsev 10:41552d038a69 214 #ifndef __FPU_PRESENT
Zaitsev 10:41552d038a69 215 #define __FPU_PRESENT 0
Zaitsev 10:41552d038a69 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
Zaitsev 10:41552d038a69 217 #endif
Zaitsev 10:41552d038a69 218
Zaitsev 10:41552d038a69 219 #ifndef __MPU_PRESENT
Zaitsev 10:41552d038a69 220 #define __MPU_PRESENT 0
Zaitsev 10:41552d038a69 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
Zaitsev 10:41552d038a69 222 #endif
Zaitsev 10:41552d038a69 223
Zaitsev 10:41552d038a69 224 #ifndef __ICACHE_PRESENT
Zaitsev 10:41552d038a69 225 #define __ICACHE_PRESENT 0
Zaitsev 10:41552d038a69 226 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
Zaitsev 10:41552d038a69 227 #endif
Zaitsev 10:41552d038a69 228
Zaitsev 10:41552d038a69 229 #ifndef __DCACHE_PRESENT
Zaitsev 10:41552d038a69 230 #define __DCACHE_PRESENT 0
Zaitsev 10:41552d038a69 231 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
Zaitsev 10:41552d038a69 232 #endif
Zaitsev 10:41552d038a69 233
Zaitsev 10:41552d038a69 234 #ifndef __DTCM_PRESENT
Zaitsev 10:41552d038a69 235 #define __DTCM_PRESENT 0
Zaitsev 10:41552d038a69 236 #warning "__DTCM_PRESENT not defined in device header file; using default!"
Zaitsev 10:41552d038a69 237 #endif
Zaitsev 10:41552d038a69 238
Zaitsev 10:41552d038a69 239 #ifndef __NVIC_PRIO_BITS
Zaitsev 10:41552d038a69 240 #define __NVIC_PRIO_BITS 3
Zaitsev 10:41552d038a69 241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Zaitsev 10:41552d038a69 242 #endif
Zaitsev 10:41552d038a69 243
Zaitsev 10:41552d038a69 244 #ifndef __Vendor_SysTickConfig
Zaitsev 10:41552d038a69 245 #define __Vendor_SysTickConfig 0
Zaitsev 10:41552d038a69 246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Zaitsev 10:41552d038a69 247 #endif
Zaitsev 10:41552d038a69 248 #endif
Zaitsev 10:41552d038a69 249
Zaitsev 10:41552d038a69 250 /* IO definitions (access restrictions to peripheral registers) */
Zaitsev 10:41552d038a69 251 /**
Zaitsev 10:41552d038a69 252 \defgroup CMSIS_glob_defs CMSIS Global Defines
Zaitsev 10:41552d038a69 253
Zaitsev 10:41552d038a69 254 <strong>IO Type Qualifiers</strong> are used
Zaitsev 10:41552d038a69 255 \li to specify the access to peripheral variables.
Zaitsev 10:41552d038a69 256 \li for automatic generation of peripheral register debug information.
Zaitsev 10:41552d038a69 257 */
Zaitsev 10:41552d038a69 258 #ifdef __cplusplus
Zaitsev 10:41552d038a69 259 #define __I volatile /*!< Defines 'read only' permissions */
Zaitsev 10:41552d038a69 260 #else
Zaitsev 10:41552d038a69 261 #define __I volatile const /*!< Defines 'read only' permissions */
Zaitsev 10:41552d038a69 262 #endif
Zaitsev 10:41552d038a69 263 #define __O volatile /*!< Defines 'write only' permissions */
Zaitsev 10:41552d038a69 264 #define __IO volatile /*!< Defines 'read / write' permissions */
Zaitsev 10:41552d038a69 265
Zaitsev 10:41552d038a69 266 #ifdef __cplusplus
Zaitsev 10:41552d038a69 267 #define __IM volatile /*!< Defines 'read only' permissions */
Zaitsev 10:41552d038a69 268 #else
Zaitsev 10:41552d038a69 269 #define __IM volatile const /*!< Defines 'read only' permissions */
Zaitsev 10:41552d038a69 270 #endif
Zaitsev 10:41552d038a69 271 #define __OM volatile /*!< Defines 'write only' permissions */
Zaitsev 10:41552d038a69 272 #define __IOM volatile /*!< Defines 'read / write' permissions */
Zaitsev 10:41552d038a69 273
Zaitsev 10:41552d038a69 274 /*@} end of group Cortex_M7 */
Zaitsev 10:41552d038a69 275
Zaitsev 10:41552d038a69 276
Zaitsev 10:41552d038a69 277
Zaitsev 10:41552d038a69 278 /*******************************************************************************
Zaitsev 10:41552d038a69 279 * Register Abstraction
Zaitsev 10:41552d038a69 280 Core Register contain:
Zaitsev 10:41552d038a69 281 - Core Register
Zaitsev 10:41552d038a69 282 - Core NVIC Register
Zaitsev 10:41552d038a69 283 - Core SCB Register
Zaitsev 10:41552d038a69 284 - Core SysTick Register
Zaitsev 10:41552d038a69 285 - Core Debug Register
Zaitsev 10:41552d038a69 286 - Core MPU Register
Zaitsev 10:41552d038a69 287 - Core FPU Register
Zaitsev 10:41552d038a69 288 ******************************************************************************/
Zaitsev 10:41552d038a69 289 /** \defgroup CMSIS_core_register Defines and Type Definitions
Zaitsev 10:41552d038a69 290 \brief Type definitions and defines for Cortex-M processor based devices.
Zaitsev 10:41552d038a69 291 */
Zaitsev 10:41552d038a69 292
Zaitsev 10:41552d038a69 293 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 294 \defgroup CMSIS_CORE Status and Control Registers
Zaitsev 10:41552d038a69 295 \brief Core Register type definitions.
Zaitsev 10:41552d038a69 296 @{
Zaitsev 10:41552d038a69 297 */
Zaitsev 10:41552d038a69 298
Zaitsev 10:41552d038a69 299 /** \brief Union type to access the Application Program Status Register (APSR).
Zaitsev 10:41552d038a69 300 */
Zaitsev 10:41552d038a69 301 typedef union
Zaitsev 10:41552d038a69 302 {
Zaitsev 10:41552d038a69 303 struct
Zaitsev 10:41552d038a69 304 {
Zaitsev 10:41552d038a69 305 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Zaitsev 10:41552d038a69 306 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Zaitsev 10:41552d038a69 307 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Zaitsev 10:41552d038a69 308 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Zaitsev 10:41552d038a69 309 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Zaitsev 10:41552d038a69 310 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Zaitsev 10:41552d038a69 311 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Zaitsev 10:41552d038a69 312 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Zaitsev 10:41552d038a69 313 } b; /*!< Structure used for bit access */
Zaitsev 10:41552d038a69 314 uint32_t w; /*!< Type used for word access */
Zaitsev 10:41552d038a69 315 } APSR_Type;
Zaitsev 10:41552d038a69 316
Zaitsev 10:41552d038a69 317 /* APSR Register Definitions */
Zaitsev 10:41552d038a69 318 #define APSR_N_Pos 31 /*!< APSR: N Position */
Zaitsev 10:41552d038a69 319 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Zaitsev 10:41552d038a69 320
Zaitsev 10:41552d038a69 321 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Zaitsev 10:41552d038a69 322 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Zaitsev 10:41552d038a69 323
Zaitsev 10:41552d038a69 324 #define APSR_C_Pos 29 /*!< APSR: C Position */
Zaitsev 10:41552d038a69 325 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Zaitsev 10:41552d038a69 326
Zaitsev 10:41552d038a69 327 #define APSR_V_Pos 28 /*!< APSR: V Position */
Zaitsev 10:41552d038a69 328 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Zaitsev 10:41552d038a69 329
Zaitsev 10:41552d038a69 330 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
Zaitsev 10:41552d038a69 331 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Zaitsev 10:41552d038a69 332
Zaitsev 10:41552d038a69 333 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
Zaitsev 10:41552d038a69 334 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
Zaitsev 10:41552d038a69 335
Zaitsev 10:41552d038a69 336
Zaitsev 10:41552d038a69 337 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Zaitsev 10:41552d038a69 338 */
Zaitsev 10:41552d038a69 339 typedef union
Zaitsev 10:41552d038a69 340 {
Zaitsev 10:41552d038a69 341 struct
Zaitsev 10:41552d038a69 342 {
Zaitsev 10:41552d038a69 343 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Zaitsev 10:41552d038a69 344 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Zaitsev 10:41552d038a69 345 } b; /*!< Structure used for bit access */
Zaitsev 10:41552d038a69 346 uint32_t w; /*!< Type used for word access */
Zaitsev 10:41552d038a69 347 } IPSR_Type;
Zaitsev 10:41552d038a69 348
Zaitsev 10:41552d038a69 349 /* IPSR Register Definitions */
Zaitsev 10:41552d038a69 350 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Zaitsev 10:41552d038a69 351 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Zaitsev 10:41552d038a69 352
Zaitsev 10:41552d038a69 353
Zaitsev 10:41552d038a69 354 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Zaitsev 10:41552d038a69 355 */
Zaitsev 10:41552d038a69 356 typedef union
Zaitsev 10:41552d038a69 357 {
Zaitsev 10:41552d038a69 358 struct
Zaitsev 10:41552d038a69 359 {
Zaitsev 10:41552d038a69 360 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Zaitsev 10:41552d038a69 361 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Zaitsev 10:41552d038a69 362 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Zaitsev 10:41552d038a69 363 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Zaitsev 10:41552d038a69 364 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Zaitsev 10:41552d038a69 365 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Zaitsev 10:41552d038a69 366 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Zaitsev 10:41552d038a69 367 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Zaitsev 10:41552d038a69 368 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Zaitsev 10:41552d038a69 369 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Zaitsev 10:41552d038a69 370 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Zaitsev 10:41552d038a69 371 } b; /*!< Structure used for bit access */
Zaitsev 10:41552d038a69 372 uint32_t w; /*!< Type used for word access */
Zaitsev 10:41552d038a69 373 } xPSR_Type;
Zaitsev 10:41552d038a69 374
Zaitsev 10:41552d038a69 375 /* xPSR Register Definitions */
Zaitsev 10:41552d038a69 376 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Zaitsev 10:41552d038a69 377 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Zaitsev 10:41552d038a69 378
Zaitsev 10:41552d038a69 379 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Zaitsev 10:41552d038a69 380 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Zaitsev 10:41552d038a69 381
Zaitsev 10:41552d038a69 382 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Zaitsev 10:41552d038a69 383 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Zaitsev 10:41552d038a69 384
Zaitsev 10:41552d038a69 385 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Zaitsev 10:41552d038a69 386 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Zaitsev 10:41552d038a69 387
Zaitsev 10:41552d038a69 388 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
Zaitsev 10:41552d038a69 389 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Zaitsev 10:41552d038a69 390
Zaitsev 10:41552d038a69 391 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
Zaitsev 10:41552d038a69 392 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Zaitsev 10:41552d038a69 393
Zaitsev 10:41552d038a69 394 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Zaitsev 10:41552d038a69 395 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Zaitsev 10:41552d038a69 396
Zaitsev 10:41552d038a69 397 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
Zaitsev 10:41552d038a69 398 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
Zaitsev 10:41552d038a69 399
Zaitsev 10:41552d038a69 400 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Zaitsev 10:41552d038a69 401 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Zaitsev 10:41552d038a69 402
Zaitsev 10:41552d038a69 403
Zaitsev 10:41552d038a69 404 /** \brief Union type to access the Control Registers (CONTROL).
Zaitsev 10:41552d038a69 405 */
Zaitsev 10:41552d038a69 406 typedef union
Zaitsev 10:41552d038a69 407 {
Zaitsev 10:41552d038a69 408 struct
Zaitsev 10:41552d038a69 409 {
Zaitsev 10:41552d038a69 410 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Zaitsev 10:41552d038a69 411 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Zaitsev 10:41552d038a69 412 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Zaitsev 10:41552d038a69 413 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Zaitsev 10:41552d038a69 414 } b; /*!< Structure used for bit access */
Zaitsev 10:41552d038a69 415 uint32_t w; /*!< Type used for word access */
Zaitsev 10:41552d038a69 416 } CONTROL_Type;
Zaitsev 10:41552d038a69 417
Zaitsev 10:41552d038a69 418 /* CONTROL Register Definitions */
Zaitsev 10:41552d038a69 419 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
Zaitsev 10:41552d038a69 420 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
Zaitsev 10:41552d038a69 421
Zaitsev 10:41552d038a69 422 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Zaitsev 10:41552d038a69 423 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Zaitsev 10:41552d038a69 424
Zaitsev 10:41552d038a69 425 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Zaitsev 10:41552d038a69 426 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Zaitsev 10:41552d038a69 427
Zaitsev 10:41552d038a69 428 /*@} end of group CMSIS_CORE */
Zaitsev 10:41552d038a69 429
Zaitsev 10:41552d038a69 430
Zaitsev 10:41552d038a69 431 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 432 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Zaitsev 10:41552d038a69 433 \brief Type definitions for the NVIC Registers
Zaitsev 10:41552d038a69 434 @{
Zaitsev 10:41552d038a69 435 */
Zaitsev 10:41552d038a69 436
Zaitsev 10:41552d038a69 437 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Zaitsev 10:41552d038a69 438 */
Zaitsev 10:41552d038a69 439 typedef struct
Zaitsev 10:41552d038a69 440 {
Zaitsev 10:41552d038a69 441 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Zaitsev 10:41552d038a69 442 uint32_t RESERVED0[24];
Zaitsev 10:41552d038a69 443 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Zaitsev 10:41552d038a69 444 uint32_t RSERVED1[24];
Zaitsev 10:41552d038a69 445 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Zaitsev 10:41552d038a69 446 uint32_t RESERVED2[24];
Zaitsev 10:41552d038a69 447 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Zaitsev 10:41552d038a69 448 uint32_t RESERVED3[24];
Zaitsev 10:41552d038a69 449 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Zaitsev 10:41552d038a69 450 uint32_t RESERVED4[56];
Zaitsev 10:41552d038a69 451 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Zaitsev 10:41552d038a69 452 uint32_t RESERVED5[644];
Zaitsev 10:41552d038a69 453 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Zaitsev 10:41552d038a69 454 } NVIC_Type;
Zaitsev 10:41552d038a69 455
Zaitsev 10:41552d038a69 456 /* Software Triggered Interrupt Register Definitions */
Zaitsev 10:41552d038a69 457 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Zaitsev 10:41552d038a69 458 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
Zaitsev 10:41552d038a69 459
Zaitsev 10:41552d038a69 460 /*@} end of group CMSIS_NVIC */
Zaitsev 10:41552d038a69 461
Zaitsev 10:41552d038a69 462
Zaitsev 10:41552d038a69 463 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 464 \defgroup CMSIS_SCB System Control Block (SCB)
Zaitsev 10:41552d038a69 465 \brief Type definitions for the System Control Block Registers
Zaitsev 10:41552d038a69 466 @{
Zaitsev 10:41552d038a69 467 */
Zaitsev 10:41552d038a69 468
Zaitsev 10:41552d038a69 469 /** \brief Structure type to access the System Control Block (SCB).
Zaitsev 10:41552d038a69 470 */
Zaitsev 10:41552d038a69 471 typedef struct
Zaitsev 10:41552d038a69 472 {
Zaitsev 10:41552d038a69 473 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Zaitsev 10:41552d038a69 474 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Zaitsev 10:41552d038a69 475 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Zaitsev 10:41552d038a69 476 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Zaitsev 10:41552d038a69 477 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Zaitsev 10:41552d038a69 478 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Zaitsev 10:41552d038a69 479 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Zaitsev 10:41552d038a69 480 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Zaitsev 10:41552d038a69 481 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Zaitsev 10:41552d038a69 482 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Zaitsev 10:41552d038a69 483 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Zaitsev 10:41552d038a69 484 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Zaitsev 10:41552d038a69 485 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Zaitsev 10:41552d038a69 486 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Zaitsev 10:41552d038a69 487 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Zaitsev 10:41552d038a69 488 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Zaitsev 10:41552d038a69 489 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Zaitsev 10:41552d038a69 490 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Zaitsev 10:41552d038a69 491 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Zaitsev 10:41552d038a69 492 uint32_t RESERVED0[1];
Zaitsev 10:41552d038a69 493 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
Zaitsev 10:41552d038a69 494 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
Zaitsev 10:41552d038a69 495 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
Zaitsev 10:41552d038a69 496 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
Zaitsev 10:41552d038a69 497 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Zaitsev 10:41552d038a69 498 uint32_t RESERVED3[93];
Zaitsev 10:41552d038a69 499 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
Zaitsev 10:41552d038a69 500 uint32_t RESERVED4[15];
Zaitsev 10:41552d038a69 501 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
Zaitsev 10:41552d038a69 502 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
Zaitsev 10:41552d038a69 503 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
Zaitsev 10:41552d038a69 504 uint32_t RESERVED5[1];
Zaitsev 10:41552d038a69 505 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
Zaitsev 10:41552d038a69 506 uint32_t RESERVED6[1];
Zaitsev 10:41552d038a69 507 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
Zaitsev 10:41552d038a69 508 __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
Zaitsev 10:41552d038a69 509 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
Zaitsev 10:41552d038a69 510 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
Zaitsev 10:41552d038a69 511 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
Zaitsev 10:41552d038a69 512 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
Zaitsev 10:41552d038a69 513 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
Zaitsev 10:41552d038a69 514 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
Zaitsev 10:41552d038a69 515 uint32_t RESERVED7[6];
Zaitsev 10:41552d038a69 516 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
Zaitsev 10:41552d038a69 517 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
Zaitsev 10:41552d038a69 518 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
Zaitsev 10:41552d038a69 519 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
Zaitsev 10:41552d038a69 520 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
Zaitsev 10:41552d038a69 521 uint32_t RESERVED8[1];
Zaitsev 10:41552d038a69 522 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
Zaitsev 10:41552d038a69 523 } SCB_Type;
Zaitsev 10:41552d038a69 524
Zaitsev 10:41552d038a69 525 /* SCB CPUID Register Definitions */
Zaitsev 10:41552d038a69 526 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Zaitsev 10:41552d038a69 527 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Zaitsev 10:41552d038a69 528
Zaitsev 10:41552d038a69 529 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Zaitsev 10:41552d038a69 530 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Zaitsev 10:41552d038a69 531
Zaitsev 10:41552d038a69 532 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Zaitsev 10:41552d038a69 533 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Zaitsev 10:41552d038a69 534
Zaitsev 10:41552d038a69 535 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Zaitsev 10:41552d038a69 536 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Zaitsev 10:41552d038a69 537
Zaitsev 10:41552d038a69 538 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Zaitsev 10:41552d038a69 539 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Zaitsev 10:41552d038a69 540
Zaitsev 10:41552d038a69 541 /* SCB Interrupt Control State Register Definitions */
Zaitsev 10:41552d038a69 542 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Zaitsev 10:41552d038a69 543 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Zaitsev 10:41552d038a69 544
Zaitsev 10:41552d038a69 545 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Zaitsev 10:41552d038a69 546 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Zaitsev 10:41552d038a69 547
Zaitsev 10:41552d038a69 548 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Zaitsev 10:41552d038a69 549 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Zaitsev 10:41552d038a69 550
Zaitsev 10:41552d038a69 551 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Zaitsev 10:41552d038a69 552 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Zaitsev 10:41552d038a69 553
Zaitsev 10:41552d038a69 554 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Zaitsev 10:41552d038a69 555 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Zaitsev 10:41552d038a69 556
Zaitsev 10:41552d038a69 557 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Zaitsev 10:41552d038a69 558 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Zaitsev 10:41552d038a69 559
Zaitsev 10:41552d038a69 560 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Zaitsev 10:41552d038a69 561 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Zaitsev 10:41552d038a69 562
Zaitsev 10:41552d038a69 563 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Zaitsev 10:41552d038a69 564 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Zaitsev 10:41552d038a69 565
Zaitsev 10:41552d038a69 566 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
Zaitsev 10:41552d038a69 567 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Zaitsev 10:41552d038a69 568
Zaitsev 10:41552d038a69 569 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Zaitsev 10:41552d038a69 570 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Zaitsev 10:41552d038a69 571
Zaitsev 10:41552d038a69 572 /* SCB Vector Table Offset Register Definitions */
Zaitsev 10:41552d038a69 573 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Zaitsev 10:41552d038a69 574 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Zaitsev 10:41552d038a69 575
Zaitsev 10:41552d038a69 576 /* SCB Application Interrupt and Reset Control Register Definitions */
Zaitsev 10:41552d038a69 577 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Zaitsev 10:41552d038a69 578 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Zaitsev 10:41552d038a69 579
Zaitsev 10:41552d038a69 580 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Zaitsev 10:41552d038a69 581 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Zaitsev 10:41552d038a69 582
Zaitsev 10:41552d038a69 583 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Zaitsev 10:41552d038a69 584 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Zaitsev 10:41552d038a69 585
Zaitsev 10:41552d038a69 586 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
Zaitsev 10:41552d038a69 587 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Zaitsev 10:41552d038a69 588
Zaitsev 10:41552d038a69 589 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Zaitsev 10:41552d038a69 590 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Zaitsev 10:41552d038a69 591
Zaitsev 10:41552d038a69 592 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Zaitsev 10:41552d038a69 593 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Zaitsev 10:41552d038a69 594
Zaitsev 10:41552d038a69 595 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Zaitsev 10:41552d038a69 596 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
Zaitsev 10:41552d038a69 597
Zaitsev 10:41552d038a69 598 /* SCB System Control Register Definitions */
Zaitsev 10:41552d038a69 599 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Zaitsev 10:41552d038a69 600 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Zaitsev 10:41552d038a69 601
Zaitsev 10:41552d038a69 602 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Zaitsev 10:41552d038a69 603 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Zaitsev 10:41552d038a69 604
Zaitsev 10:41552d038a69 605 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Zaitsev 10:41552d038a69 606 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Zaitsev 10:41552d038a69 607
Zaitsev 10:41552d038a69 608 /* SCB Configuration Control Register Definitions */
Zaitsev 10:41552d038a69 609 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
Zaitsev 10:41552d038a69 610 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
Zaitsev 10:41552d038a69 611
Zaitsev 10:41552d038a69 612 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
Zaitsev 10:41552d038a69 613 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
Zaitsev 10:41552d038a69 614
Zaitsev 10:41552d038a69 615 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
Zaitsev 10:41552d038a69 616 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
Zaitsev 10:41552d038a69 617
Zaitsev 10:41552d038a69 618 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Zaitsev 10:41552d038a69 619 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Zaitsev 10:41552d038a69 620
Zaitsev 10:41552d038a69 621 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
Zaitsev 10:41552d038a69 622 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Zaitsev 10:41552d038a69 623
Zaitsev 10:41552d038a69 624 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
Zaitsev 10:41552d038a69 625 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Zaitsev 10:41552d038a69 626
Zaitsev 10:41552d038a69 627 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Zaitsev 10:41552d038a69 628 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Zaitsev 10:41552d038a69 629
Zaitsev 10:41552d038a69 630 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
Zaitsev 10:41552d038a69 631 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Zaitsev 10:41552d038a69 632
Zaitsev 10:41552d038a69 633 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Zaitsev 10:41552d038a69 634 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
Zaitsev 10:41552d038a69 635
Zaitsev 10:41552d038a69 636 /* SCB System Handler Control and State Register Definitions */
Zaitsev 10:41552d038a69 637 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
Zaitsev 10:41552d038a69 638 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Zaitsev 10:41552d038a69 639
Zaitsev 10:41552d038a69 640 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
Zaitsev 10:41552d038a69 641 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Zaitsev 10:41552d038a69 642
Zaitsev 10:41552d038a69 643 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
Zaitsev 10:41552d038a69 644 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Zaitsev 10:41552d038a69 645
Zaitsev 10:41552d038a69 646 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Zaitsev 10:41552d038a69 647 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Zaitsev 10:41552d038a69 648
Zaitsev 10:41552d038a69 649 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
Zaitsev 10:41552d038a69 650 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Zaitsev 10:41552d038a69 651
Zaitsev 10:41552d038a69 652 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
Zaitsev 10:41552d038a69 653 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Zaitsev 10:41552d038a69 654
Zaitsev 10:41552d038a69 655 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
Zaitsev 10:41552d038a69 656 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Zaitsev 10:41552d038a69 657
Zaitsev 10:41552d038a69 658 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
Zaitsev 10:41552d038a69 659 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Zaitsev 10:41552d038a69 660
Zaitsev 10:41552d038a69 661 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
Zaitsev 10:41552d038a69 662 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Zaitsev 10:41552d038a69 663
Zaitsev 10:41552d038a69 664 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
Zaitsev 10:41552d038a69 665 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Zaitsev 10:41552d038a69 666
Zaitsev 10:41552d038a69 667 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
Zaitsev 10:41552d038a69 668 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Zaitsev 10:41552d038a69 669
Zaitsev 10:41552d038a69 670 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
Zaitsev 10:41552d038a69 671 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Zaitsev 10:41552d038a69 672
Zaitsev 10:41552d038a69 673 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
Zaitsev 10:41552d038a69 674 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Zaitsev 10:41552d038a69 675
Zaitsev 10:41552d038a69 676 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Zaitsev 10:41552d038a69 677 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
Zaitsev 10:41552d038a69 678
Zaitsev 10:41552d038a69 679 /* SCB Configurable Fault Status Registers Definitions */
Zaitsev 10:41552d038a69 680 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
Zaitsev 10:41552d038a69 681 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Zaitsev 10:41552d038a69 682
Zaitsev 10:41552d038a69 683 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
Zaitsev 10:41552d038a69 684 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Zaitsev 10:41552d038a69 685
Zaitsev 10:41552d038a69 686 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Zaitsev 10:41552d038a69 687 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Zaitsev 10:41552d038a69 688
Zaitsev 10:41552d038a69 689 /* SCB Hard Fault Status Registers Definitions */
Zaitsev 10:41552d038a69 690 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
Zaitsev 10:41552d038a69 691 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Zaitsev 10:41552d038a69 692
Zaitsev 10:41552d038a69 693 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
Zaitsev 10:41552d038a69 694 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Zaitsev 10:41552d038a69 695
Zaitsev 10:41552d038a69 696 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
Zaitsev 10:41552d038a69 697 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Zaitsev 10:41552d038a69 698
Zaitsev 10:41552d038a69 699 /* SCB Debug Fault Status Register Definitions */
Zaitsev 10:41552d038a69 700 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
Zaitsev 10:41552d038a69 701 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Zaitsev 10:41552d038a69 702
Zaitsev 10:41552d038a69 703 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
Zaitsev 10:41552d038a69 704 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Zaitsev 10:41552d038a69 705
Zaitsev 10:41552d038a69 706 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
Zaitsev 10:41552d038a69 707 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Zaitsev 10:41552d038a69 708
Zaitsev 10:41552d038a69 709 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
Zaitsev 10:41552d038a69 710 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Zaitsev 10:41552d038a69 711
Zaitsev 10:41552d038a69 712 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Zaitsev 10:41552d038a69 713 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
Zaitsev 10:41552d038a69 714
Zaitsev 10:41552d038a69 715 /* Cache Level ID register */
Zaitsev 10:41552d038a69 716 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
Zaitsev 10:41552d038a69 717 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
Zaitsev 10:41552d038a69 718
Zaitsev 10:41552d038a69 719 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
Zaitsev 10:41552d038a69 720 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
Zaitsev 10:41552d038a69 721
Zaitsev 10:41552d038a69 722 /* Cache Type register */
Zaitsev 10:41552d038a69 723 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
Zaitsev 10:41552d038a69 724 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
Zaitsev 10:41552d038a69 725
Zaitsev 10:41552d038a69 726 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
Zaitsev 10:41552d038a69 727 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
Zaitsev 10:41552d038a69 728
Zaitsev 10:41552d038a69 729 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
Zaitsev 10:41552d038a69 730 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
Zaitsev 10:41552d038a69 731
Zaitsev 10:41552d038a69 732 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
Zaitsev 10:41552d038a69 733 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
Zaitsev 10:41552d038a69 734
Zaitsev 10:41552d038a69 735 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
Zaitsev 10:41552d038a69 736 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
Zaitsev 10:41552d038a69 737
Zaitsev 10:41552d038a69 738 /* Cache Size ID Register */
Zaitsev 10:41552d038a69 739 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
Zaitsev 10:41552d038a69 740 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
Zaitsev 10:41552d038a69 741
Zaitsev 10:41552d038a69 742 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
Zaitsev 10:41552d038a69 743 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
Zaitsev 10:41552d038a69 744
Zaitsev 10:41552d038a69 745 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
Zaitsev 10:41552d038a69 746 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
Zaitsev 10:41552d038a69 747
Zaitsev 10:41552d038a69 748 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
Zaitsev 10:41552d038a69 749 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
Zaitsev 10:41552d038a69 750
Zaitsev 10:41552d038a69 751 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
Zaitsev 10:41552d038a69 752 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
Zaitsev 10:41552d038a69 753
Zaitsev 10:41552d038a69 754 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
Zaitsev 10:41552d038a69 755 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
Zaitsev 10:41552d038a69 756
Zaitsev 10:41552d038a69 757 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
Zaitsev 10:41552d038a69 758 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
Zaitsev 10:41552d038a69 759
Zaitsev 10:41552d038a69 760 /* Cache Size Selection Register */
Zaitsev 10:41552d038a69 761 #define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
Zaitsev 10:41552d038a69 762 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
Zaitsev 10:41552d038a69 763
Zaitsev 10:41552d038a69 764 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
Zaitsev 10:41552d038a69 765 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
Zaitsev 10:41552d038a69 766
Zaitsev 10:41552d038a69 767 /* SCB Software Triggered Interrupt Register */
Zaitsev 10:41552d038a69 768 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
Zaitsev 10:41552d038a69 769 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
Zaitsev 10:41552d038a69 770
Zaitsev 10:41552d038a69 771 /* Instruction Tightly-Coupled Memory Control Register*/
Zaitsev 10:41552d038a69 772 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
Zaitsev 10:41552d038a69 773 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
Zaitsev 10:41552d038a69 774
Zaitsev 10:41552d038a69 775 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
Zaitsev 10:41552d038a69 776 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
Zaitsev 10:41552d038a69 777
Zaitsev 10:41552d038a69 778 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
Zaitsev 10:41552d038a69 779 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
Zaitsev 10:41552d038a69 780
Zaitsev 10:41552d038a69 781 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
Zaitsev 10:41552d038a69 782 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
Zaitsev 10:41552d038a69 783
Zaitsev 10:41552d038a69 784 /* Data Tightly-Coupled Memory Control Registers */
Zaitsev 10:41552d038a69 785 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
Zaitsev 10:41552d038a69 786 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
Zaitsev 10:41552d038a69 787
Zaitsev 10:41552d038a69 788 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
Zaitsev 10:41552d038a69 789 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
Zaitsev 10:41552d038a69 790
Zaitsev 10:41552d038a69 791 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
Zaitsev 10:41552d038a69 792 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
Zaitsev 10:41552d038a69 793
Zaitsev 10:41552d038a69 794 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
Zaitsev 10:41552d038a69 795 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
Zaitsev 10:41552d038a69 796
Zaitsev 10:41552d038a69 797 /* AHBP Control Register */
Zaitsev 10:41552d038a69 798 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
Zaitsev 10:41552d038a69 799 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
Zaitsev 10:41552d038a69 800
Zaitsev 10:41552d038a69 801 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
Zaitsev 10:41552d038a69 802 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
Zaitsev 10:41552d038a69 803
Zaitsev 10:41552d038a69 804 /* L1 Cache Control Register */
Zaitsev 10:41552d038a69 805 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
Zaitsev 10:41552d038a69 806 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
Zaitsev 10:41552d038a69 807
Zaitsev 10:41552d038a69 808 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
Zaitsev 10:41552d038a69 809 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
Zaitsev 10:41552d038a69 810
Zaitsev 10:41552d038a69 811 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
Zaitsev 10:41552d038a69 812 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
Zaitsev 10:41552d038a69 813
Zaitsev 10:41552d038a69 814 /* AHBS control register */
Zaitsev 10:41552d038a69 815 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
Zaitsev 10:41552d038a69 816 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
Zaitsev 10:41552d038a69 817
Zaitsev 10:41552d038a69 818 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
Zaitsev 10:41552d038a69 819 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
Zaitsev 10:41552d038a69 820
Zaitsev 10:41552d038a69 821 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
Zaitsev 10:41552d038a69 822 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
Zaitsev 10:41552d038a69 823
Zaitsev 10:41552d038a69 824 /* Auxiliary Bus Fault Status Register */
Zaitsev 10:41552d038a69 825 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
Zaitsev 10:41552d038a69 826 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
Zaitsev 10:41552d038a69 827
Zaitsev 10:41552d038a69 828 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
Zaitsev 10:41552d038a69 829 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
Zaitsev 10:41552d038a69 830
Zaitsev 10:41552d038a69 831 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
Zaitsev 10:41552d038a69 832 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
Zaitsev 10:41552d038a69 833
Zaitsev 10:41552d038a69 834 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
Zaitsev 10:41552d038a69 835 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
Zaitsev 10:41552d038a69 836
Zaitsev 10:41552d038a69 837 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
Zaitsev 10:41552d038a69 838 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
Zaitsev 10:41552d038a69 839
Zaitsev 10:41552d038a69 840 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
Zaitsev 10:41552d038a69 841 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
Zaitsev 10:41552d038a69 842
Zaitsev 10:41552d038a69 843 /*@} end of group CMSIS_SCB */
Zaitsev 10:41552d038a69 844
Zaitsev 10:41552d038a69 845
Zaitsev 10:41552d038a69 846 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 847 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Zaitsev 10:41552d038a69 848 \brief Type definitions for the System Control and ID Register not in the SCB
Zaitsev 10:41552d038a69 849 @{
Zaitsev 10:41552d038a69 850 */
Zaitsev 10:41552d038a69 851
Zaitsev 10:41552d038a69 852 /** \brief Structure type to access the System Control and ID Register not in the SCB.
Zaitsev 10:41552d038a69 853 */
Zaitsev 10:41552d038a69 854 typedef struct
Zaitsev 10:41552d038a69 855 {
Zaitsev 10:41552d038a69 856 uint32_t RESERVED0[1];
Zaitsev 10:41552d038a69 857 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Zaitsev 10:41552d038a69 858 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Zaitsev 10:41552d038a69 859 } SCnSCB_Type;
Zaitsev 10:41552d038a69 860
Zaitsev 10:41552d038a69 861 /* Interrupt Controller Type Register Definitions */
Zaitsev 10:41552d038a69 862 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Zaitsev 10:41552d038a69 863 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
Zaitsev 10:41552d038a69 864
Zaitsev 10:41552d038a69 865 /* Auxiliary Control Register Definitions */
Zaitsev 10:41552d038a69 866 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
Zaitsev 10:41552d038a69 867 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
Zaitsev 10:41552d038a69 868
Zaitsev 10:41552d038a69 869 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
Zaitsev 10:41552d038a69 870 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
Zaitsev 10:41552d038a69 871
Zaitsev 10:41552d038a69 872 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
Zaitsev 10:41552d038a69 873 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
Zaitsev 10:41552d038a69 874
Zaitsev 10:41552d038a69 875 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
Zaitsev 10:41552d038a69 876 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
Zaitsev 10:41552d038a69 877
Zaitsev 10:41552d038a69 878 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Zaitsev 10:41552d038a69 879 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Zaitsev 10:41552d038a69 880
Zaitsev 10:41552d038a69 881 /*@} end of group CMSIS_SCnotSCB */
Zaitsev 10:41552d038a69 882
Zaitsev 10:41552d038a69 883
Zaitsev 10:41552d038a69 884 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 885 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Zaitsev 10:41552d038a69 886 \brief Type definitions for the System Timer Registers.
Zaitsev 10:41552d038a69 887 @{
Zaitsev 10:41552d038a69 888 */
Zaitsev 10:41552d038a69 889
Zaitsev 10:41552d038a69 890 /** \brief Structure type to access the System Timer (SysTick).
Zaitsev 10:41552d038a69 891 */
Zaitsev 10:41552d038a69 892 typedef struct
Zaitsev 10:41552d038a69 893 {
Zaitsev 10:41552d038a69 894 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Zaitsev 10:41552d038a69 895 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Zaitsev 10:41552d038a69 896 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Zaitsev 10:41552d038a69 897 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Zaitsev 10:41552d038a69 898 } SysTick_Type;
Zaitsev 10:41552d038a69 899
Zaitsev 10:41552d038a69 900 /* SysTick Control / Status Register Definitions */
Zaitsev 10:41552d038a69 901 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Zaitsev 10:41552d038a69 902 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Zaitsev 10:41552d038a69 903
Zaitsev 10:41552d038a69 904 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Zaitsev 10:41552d038a69 905 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Zaitsev 10:41552d038a69 906
Zaitsev 10:41552d038a69 907 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Zaitsev 10:41552d038a69 908 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Zaitsev 10:41552d038a69 909
Zaitsev 10:41552d038a69 910 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Zaitsev 10:41552d038a69 911 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Zaitsev 10:41552d038a69 912
Zaitsev 10:41552d038a69 913 /* SysTick Reload Register Definitions */
Zaitsev 10:41552d038a69 914 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Zaitsev 10:41552d038a69 915 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Zaitsev 10:41552d038a69 916
Zaitsev 10:41552d038a69 917 /* SysTick Current Register Definitions */
Zaitsev 10:41552d038a69 918 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Zaitsev 10:41552d038a69 919 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Zaitsev 10:41552d038a69 920
Zaitsev 10:41552d038a69 921 /* SysTick Calibration Register Definitions */
Zaitsev 10:41552d038a69 922 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Zaitsev 10:41552d038a69 923 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Zaitsev 10:41552d038a69 924
Zaitsev 10:41552d038a69 925 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Zaitsev 10:41552d038a69 926 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Zaitsev 10:41552d038a69 927
Zaitsev 10:41552d038a69 928 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Zaitsev 10:41552d038a69 929 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Zaitsev 10:41552d038a69 930
Zaitsev 10:41552d038a69 931 /*@} end of group CMSIS_SysTick */
Zaitsev 10:41552d038a69 932
Zaitsev 10:41552d038a69 933
Zaitsev 10:41552d038a69 934 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 935 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Zaitsev 10:41552d038a69 936 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Zaitsev 10:41552d038a69 937 @{
Zaitsev 10:41552d038a69 938 */
Zaitsev 10:41552d038a69 939
Zaitsev 10:41552d038a69 940 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Zaitsev 10:41552d038a69 941 */
Zaitsev 10:41552d038a69 942 typedef struct
Zaitsev 10:41552d038a69 943 {
Zaitsev 10:41552d038a69 944 __O union
Zaitsev 10:41552d038a69 945 {
Zaitsev 10:41552d038a69 946 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Zaitsev 10:41552d038a69 947 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Zaitsev 10:41552d038a69 948 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Zaitsev 10:41552d038a69 949 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Zaitsev 10:41552d038a69 950 uint32_t RESERVED0[864];
Zaitsev 10:41552d038a69 951 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Zaitsev 10:41552d038a69 952 uint32_t RESERVED1[15];
Zaitsev 10:41552d038a69 953 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Zaitsev 10:41552d038a69 954 uint32_t RESERVED2[15];
Zaitsev 10:41552d038a69 955 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Zaitsev 10:41552d038a69 956 uint32_t RESERVED3[29];
Zaitsev 10:41552d038a69 957 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Zaitsev 10:41552d038a69 958 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Zaitsev 10:41552d038a69 959 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Zaitsev 10:41552d038a69 960 uint32_t RESERVED4[43];
Zaitsev 10:41552d038a69 961 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Zaitsev 10:41552d038a69 962 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Zaitsev 10:41552d038a69 963 uint32_t RESERVED5[6];
Zaitsev 10:41552d038a69 964 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Zaitsev 10:41552d038a69 965 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Zaitsev 10:41552d038a69 966 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Zaitsev 10:41552d038a69 967 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Zaitsev 10:41552d038a69 968 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Zaitsev 10:41552d038a69 969 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Zaitsev 10:41552d038a69 970 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Zaitsev 10:41552d038a69 971 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Zaitsev 10:41552d038a69 972 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Zaitsev 10:41552d038a69 973 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Zaitsev 10:41552d038a69 974 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Zaitsev 10:41552d038a69 975 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Zaitsev 10:41552d038a69 976 } ITM_Type;
Zaitsev 10:41552d038a69 977
Zaitsev 10:41552d038a69 978 /* ITM Trace Privilege Register Definitions */
Zaitsev 10:41552d038a69 979 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Zaitsev 10:41552d038a69 980 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
Zaitsev 10:41552d038a69 981
Zaitsev 10:41552d038a69 982 /* ITM Trace Control Register Definitions */
Zaitsev 10:41552d038a69 983 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
Zaitsev 10:41552d038a69 984 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Zaitsev 10:41552d038a69 985
Zaitsev 10:41552d038a69 986 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
Zaitsev 10:41552d038a69 987 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
Zaitsev 10:41552d038a69 988
Zaitsev 10:41552d038a69 989 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
Zaitsev 10:41552d038a69 990 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Zaitsev 10:41552d038a69 991
Zaitsev 10:41552d038a69 992 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
Zaitsev 10:41552d038a69 993 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Zaitsev 10:41552d038a69 994
Zaitsev 10:41552d038a69 995 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
Zaitsev 10:41552d038a69 996 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Zaitsev 10:41552d038a69 997
Zaitsev 10:41552d038a69 998 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
Zaitsev 10:41552d038a69 999 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Zaitsev 10:41552d038a69 1000
Zaitsev 10:41552d038a69 1001 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
Zaitsev 10:41552d038a69 1002 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Zaitsev 10:41552d038a69 1003
Zaitsev 10:41552d038a69 1004 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
Zaitsev 10:41552d038a69 1005 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Zaitsev 10:41552d038a69 1006
Zaitsev 10:41552d038a69 1007 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Zaitsev 10:41552d038a69 1008 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
Zaitsev 10:41552d038a69 1009
Zaitsev 10:41552d038a69 1010 /* ITM Integration Write Register Definitions */
Zaitsev 10:41552d038a69 1011 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Zaitsev 10:41552d038a69 1012 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
Zaitsev 10:41552d038a69 1013
Zaitsev 10:41552d038a69 1014 /* ITM Integration Read Register Definitions */
Zaitsev 10:41552d038a69 1015 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Zaitsev 10:41552d038a69 1016 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
Zaitsev 10:41552d038a69 1017
Zaitsev 10:41552d038a69 1018 /* ITM Integration Mode Control Register Definitions */
Zaitsev 10:41552d038a69 1019 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Zaitsev 10:41552d038a69 1020 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
Zaitsev 10:41552d038a69 1021
Zaitsev 10:41552d038a69 1022 /* ITM Lock Status Register Definitions */
Zaitsev 10:41552d038a69 1023 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
Zaitsev 10:41552d038a69 1024 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Zaitsev 10:41552d038a69 1025
Zaitsev 10:41552d038a69 1026 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
Zaitsev 10:41552d038a69 1027 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Zaitsev 10:41552d038a69 1028
Zaitsev 10:41552d038a69 1029 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Zaitsev 10:41552d038a69 1030 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
Zaitsev 10:41552d038a69 1031
Zaitsev 10:41552d038a69 1032 /*@}*/ /* end of group CMSIS_ITM */
Zaitsev 10:41552d038a69 1033
Zaitsev 10:41552d038a69 1034
Zaitsev 10:41552d038a69 1035 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 1036 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Zaitsev 10:41552d038a69 1037 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Zaitsev 10:41552d038a69 1038 @{
Zaitsev 10:41552d038a69 1039 */
Zaitsev 10:41552d038a69 1040
Zaitsev 10:41552d038a69 1041 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Zaitsev 10:41552d038a69 1042 */
Zaitsev 10:41552d038a69 1043 typedef struct
Zaitsev 10:41552d038a69 1044 {
Zaitsev 10:41552d038a69 1045 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Zaitsev 10:41552d038a69 1046 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Zaitsev 10:41552d038a69 1047 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Zaitsev 10:41552d038a69 1048 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Zaitsev 10:41552d038a69 1049 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Zaitsev 10:41552d038a69 1050 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Zaitsev 10:41552d038a69 1051 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Zaitsev 10:41552d038a69 1052 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Zaitsev 10:41552d038a69 1053 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Zaitsev 10:41552d038a69 1054 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
Zaitsev 10:41552d038a69 1055 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Zaitsev 10:41552d038a69 1056 uint32_t RESERVED0[1];
Zaitsev 10:41552d038a69 1057 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Zaitsev 10:41552d038a69 1058 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
Zaitsev 10:41552d038a69 1059 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Zaitsev 10:41552d038a69 1060 uint32_t RESERVED1[1];
Zaitsev 10:41552d038a69 1061 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Zaitsev 10:41552d038a69 1062 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
Zaitsev 10:41552d038a69 1063 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Zaitsev 10:41552d038a69 1064 uint32_t RESERVED2[1];
Zaitsev 10:41552d038a69 1065 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Zaitsev 10:41552d038a69 1066 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
Zaitsev 10:41552d038a69 1067 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Zaitsev 10:41552d038a69 1068 uint32_t RESERVED3[981];
Zaitsev 10:41552d038a69 1069 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
Zaitsev 10:41552d038a69 1070 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
Zaitsev 10:41552d038a69 1071 } DWT_Type;
Zaitsev 10:41552d038a69 1072
Zaitsev 10:41552d038a69 1073 /* DWT Control Register Definitions */
Zaitsev 10:41552d038a69 1074 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
Zaitsev 10:41552d038a69 1075 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Zaitsev 10:41552d038a69 1076
Zaitsev 10:41552d038a69 1077 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
Zaitsev 10:41552d038a69 1078 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Zaitsev 10:41552d038a69 1079
Zaitsev 10:41552d038a69 1080 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
Zaitsev 10:41552d038a69 1081 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Zaitsev 10:41552d038a69 1082
Zaitsev 10:41552d038a69 1083 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
Zaitsev 10:41552d038a69 1084 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Zaitsev 10:41552d038a69 1085
Zaitsev 10:41552d038a69 1086 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
Zaitsev 10:41552d038a69 1087 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Zaitsev 10:41552d038a69 1088
Zaitsev 10:41552d038a69 1089 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
Zaitsev 10:41552d038a69 1090 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Zaitsev 10:41552d038a69 1091
Zaitsev 10:41552d038a69 1092 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
Zaitsev 10:41552d038a69 1093 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Zaitsev 10:41552d038a69 1094
Zaitsev 10:41552d038a69 1095 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
Zaitsev 10:41552d038a69 1096 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Zaitsev 10:41552d038a69 1097
Zaitsev 10:41552d038a69 1098 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
Zaitsev 10:41552d038a69 1099 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Zaitsev 10:41552d038a69 1100
Zaitsev 10:41552d038a69 1101 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
Zaitsev 10:41552d038a69 1102 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Zaitsev 10:41552d038a69 1103
Zaitsev 10:41552d038a69 1104 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
Zaitsev 10:41552d038a69 1105 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Zaitsev 10:41552d038a69 1106
Zaitsev 10:41552d038a69 1107 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
Zaitsev 10:41552d038a69 1108 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Zaitsev 10:41552d038a69 1109
Zaitsev 10:41552d038a69 1110 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
Zaitsev 10:41552d038a69 1111 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Zaitsev 10:41552d038a69 1112
Zaitsev 10:41552d038a69 1113 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
Zaitsev 10:41552d038a69 1114 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Zaitsev 10:41552d038a69 1115
Zaitsev 10:41552d038a69 1116 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
Zaitsev 10:41552d038a69 1117 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Zaitsev 10:41552d038a69 1118
Zaitsev 10:41552d038a69 1119 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
Zaitsev 10:41552d038a69 1120 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Zaitsev 10:41552d038a69 1121
Zaitsev 10:41552d038a69 1122 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
Zaitsev 10:41552d038a69 1123 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Zaitsev 10:41552d038a69 1124
Zaitsev 10:41552d038a69 1125 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Zaitsev 10:41552d038a69 1126 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
Zaitsev 10:41552d038a69 1127
Zaitsev 10:41552d038a69 1128 /* DWT CPI Count Register Definitions */
Zaitsev 10:41552d038a69 1129 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Zaitsev 10:41552d038a69 1130 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
Zaitsev 10:41552d038a69 1131
Zaitsev 10:41552d038a69 1132 /* DWT Exception Overhead Count Register Definitions */
Zaitsev 10:41552d038a69 1133 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Zaitsev 10:41552d038a69 1134 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
Zaitsev 10:41552d038a69 1135
Zaitsev 10:41552d038a69 1136 /* DWT Sleep Count Register Definitions */
Zaitsev 10:41552d038a69 1137 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Zaitsev 10:41552d038a69 1138 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Zaitsev 10:41552d038a69 1139
Zaitsev 10:41552d038a69 1140 /* DWT LSU Count Register Definitions */
Zaitsev 10:41552d038a69 1141 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Zaitsev 10:41552d038a69 1142 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
Zaitsev 10:41552d038a69 1143
Zaitsev 10:41552d038a69 1144 /* DWT Folded-instruction Count Register Definitions */
Zaitsev 10:41552d038a69 1145 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Zaitsev 10:41552d038a69 1146 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
Zaitsev 10:41552d038a69 1147
Zaitsev 10:41552d038a69 1148 /* DWT Comparator Mask Register Definitions */
Zaitsev 10:41552d038a69 1149 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Zaitsev 10:41552d038a69 1150 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
Zaitsev 10:41552d038a69 1151
Zaitsev 10:41552d038a69 1152 /* DWT Comparator Function Register Definitions */
Zaitsev 10:41552d038a69 1153 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
Zaitsev 10:41552d038a69 1154 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Zaitsev 10:41552d038a69 1155
Zaitsev 10:41552d038a69 1156 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
Zaitsev 10:41552d038a69 1157 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
Zaitsev 10:41552d038a69 1158
Zaitsev 10:41552d038a69 1159 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
Zaitsev 10:41552d038a69 1160 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
Zaitsev 10:41552d038a69 1161
Zaitsev 10:41552d038a69 1162 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
Zaitsev 10:41552d038a69 1163 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Zaitsev 10:41552d038a69 1164
Zaitsev 10:41552d038a69 1165 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
Zaitsev 10:41552d038a69 1166 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
Zaitsev 10:41552d038a69 1167
Zaitsev 10:41552d038a69 1168 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
Zaitsev 10:41552d038a69 1169 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
Zaitsev 10:41552d038a69 1170
Zaitsev 10:41552d038a69 1171 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
Zaitsev 10:41552d038a69 1172 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
Zaitsev 10:41552d038a69 1173
Zaitsev 10:41552d038a69 1174 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
Zaitsev 10:41552d038a69 1175 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
Zaitsev 10:41552d038a69 1176
Zaitsev 10:41552d038a69 1177 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Zaitsev 10:41552d038a69 1178 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
Zaitsev 10:41552d038a69 1179
Zaitsev 10:41552d038a69 1180 /*@}*/ /* end of group CMSIS_DWT */
Zaitsev 10:41552d038a69 1181
Zaitsev 10:41552d038a69 1182
Zaitsev 10:41552d038a69 1183 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 1184 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Zaitsev 10:41552d038a69 1185 \brief Type definitions for the Trace Port Interface (TPI)
Zaitsev 10:41552d038a69 1186 @{
Zaitsev 10:41552d038a69 1187 */
Zaitsev 10:41552d038a69 1188
Zaitsev 10:41552d038a69 1189 /** \brief Structure type to access the Trace Port Interface Register (TPI).
Zaitsev 10:41552d038a69 1190 */
Zaitsev 10:41552d038a69 1191 typedef struct
Zaitsev 10:41552d038a69 1192 {
Zaitsev 10:41552d038a69 1193 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Zaitsev 10:41552d038a69 1194 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Zaitsev 10:41552d038a69 1195 uint32_t RESERVED0[2];
Zaitsev 10:41552d038a69 1196 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Zaitsev 10:41552d038a69 1197 uint32_t RESERVED1[55];
Zaitsev 10:41552d038a69 1198 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Zaitsev 10:41552d038a69 1199 uint32_t RESERVED2[131];
Zaitsev 10:41552d038a69 1200 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Zaitsev 10:41552d038a69 1201 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Zaitsev 10:41552d038a69 1202 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Zaitsev 10:41552d038a69 1203 uint32_t RESERVED3[759];
Zaitsev 10:41552d038a69 1204 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Zaitsev 10:41552d038a69 1205 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Zaitsev 10:41552d038a69 1206 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Zaitsev 10:41552d038a69 1207 uint32_t RESERVED4[1];
Zaitsev 10:41552d038a69 1208 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Zaitsev 10:41552d038a69 1209 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Zaitsev 10:41552d038a69 1210 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Zaitsev 10:41552d038a69 1211 uint32_t RESERVED5[39];
Zaitsev 10:41552d038a69 1212 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Zaitsev 10:41552d038a69 1213 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Zaitsev 10:41552d038a69 1214 uint32_t RESERVED7[8];
Zaitsev 10:41552d038a69 1215 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Zaitsev 10:41552d038a69 1216 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Zaitsev 10:41552d038a69 1217 } TPI_Type;
Zaitsev 10:41552d038a69 1218
Zaitsev 10:41552d038a69 1219 /* TPI Asynchronous Clock Prescaler Register Definitions */
Zaitsev 10:41552d038a69 1220 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Zaitsev 10:41552d038a69 1221 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
Zaitsev 10:41552d038a69 1222
Zaitsev 10:41552d038a69 1223 /* TPI Selected Pin Protocol Register Definitions */
Zaitsev 10:41552d038a69 1224 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Zaitsev 10:41552d038a69 1225 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Zaitsev 10:41552d038a69 1226
Zaitsev 10:41552d038a69 1227 /* TPI Formatter and Flush Status Register Definitions */
Zaitsev 10:41552d038a69 1228 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
Zaitsev 10:41552d038a69 1229 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Zaitsev 10:41552d038a69 1230
Zaitsev 10:41552d038a69 1231 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
Zaitsev 10:41552d038a69 1232 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Zaitsev 10:41552d038a69 1233
Zaitsev 10:41552d038a69 1234 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
Zaitsev 10:41552d038a69 1235 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Zaitsev 10:41552d038a69 1236
Zaitsev 10:41552d038a69 1237 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Zaitsev 10:41552d038a69 1238 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Zaitsev 10:41552d038a69 1239
Zaitsev 10:41552d038a69 1240 /* TPI Formatter and Flush Control Register Definitions */
Zaitsev 10:41552d038a69 1241 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
Zaitsev 10:41552d038a69 1242 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Zaitsev 10:41552d038a69 1243
Zaitsev 10:41552d038a69 1244 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
Zaitsev 10:41552d038a69 1245 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Zaitsev 10:41552d038a69 1246
Zaitsev 10:41552d038a69 1247 /* TPI TRIGGER Register Definitions */
Zaitsev 10:41552d038a69 1248 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Zaitsev 10:41552d038a69 1249 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Zaitsev 10:41552d038a69 1250
Zaitsev 10:41552d038a69 1251 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Zaitsev 10:41552d038a69 1252 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
Zaitsev 10:41552d038a69 1253 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Zaitsev 10:41552d038a69 1254
Zaitsev 10:41552d038a69 1255 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
Zaitsev 10:41552d038a69 1256 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Zaitsev 10:41552d038a69 1257
Zaitsev 10:41552d038a69 1258 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
Zaitsev 10:41552d038a69 1259 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Zaitsev 10:41552d038a69 1260
Zaitsev 10:41552d038a69 1261 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
Zaitsev 10:41552d038a69 1262 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Zaitsev 10:41552d038a69 1263
Zaitsev 10:41552d038a69 1264 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
Zaitsev 10:41552d038a69 1265 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Zaitsev 10:41552d038a69 1266
Zaitsev 10:41552d038a69 1267 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
Zaitsev 10:41552d038a69 1268 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Zaitsev 10:41552d038a69 1269
Zaitsev 10:41552d038a69 1270 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Zaitsev 10:41552d038a69 1271 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Zaitsev 10:41552d038a69 1272
Zaitsev 10:41552d038a69 1273 /* TPI ITATBCTR2 Register Definitions */
Zaitsev 10:41552d038a69 1274 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Zaitsev 10:41552d038a69 1275 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Zaitsev 10:41552d038a69 1276
Zaitsev 10:41552d038a69 1277 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Zaitsev 10:41552d038a69 1278 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
Zaitsev 10:41552d038a69 1279 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Zaitsev 10:41552d038a69 1280
Zaitsev 10:41552d038a69 1281 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
Zaitsev 10:41552d038a69 1282 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Zaitsev 10:41552d038a69 1283
Zaitsev 10:41552d038a69 1284 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
Zaitsev 10:41552d038a69 1285 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Zaitsev 10:41552d038a69 1286
Zaitsev 10:41552d038a69 1287 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
Zaitsev 10:41552d038a69 1288 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Zaitsev 10:41552d038a69 1289
Zaitsev 10:41552d038a69 1290 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
Zaitsev 10:41552d038a69 1291 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Zaitsev 10:41552d038a69 1292
Zaitsev 10:41552d038a69 1293 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
Zaitsev 10:41552d038a69 1294 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Zaitsev 10:41552d038a69 1295
Zaitsev 10:41552d038a69 1296 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Zaitsev 10:41552d038a69 1297 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Zaitsev 10:41552d038a69 1298
Zaitsev 10:41552d038a69 1299 /* TPI ITATBCTR0 Register Definitions */
Zaitsev 10:41552d038a69 1300 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Zaitsev 10:41552d038a69 1301 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Zaitsev 10:41552d038a69 1302
Zaitsev 10:41552d038a69 1303 /* TPI Integration Mode Control Register Definitions */
Zaitsev 10:41552d038a69 1304 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Zaitsev 10:41552d038a69 1305 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Zaitsev 10:41552d038a69 1306
Zaitsev 10:41552d038a69 1307 /* TPI DEVID Register Definitions */
Zaitsev 10:41552d038a69 1308 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
Zaitsev 10:41552d038a69 1309 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Zaitsev 10:41552d038a69 1310
Zaitsev 10:41552d038a69 1311 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
Zaitsev 10:41552d038a69 1312 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Zaitsev 10:41552d038a69 1313
Zaitsev 10:41552d038a69 1314 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
Zaitsev 10:41552d038a69 1315 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Zaitsev 10:41552d038a69 1316
Zaitsev 10:41552d038a69 1317 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
Zaitsev 10:41552d038a69 1318 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Zaitsev 10:41552d038a69 1319
Zaitsev 10:41552d038a69 1320 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
Zaitsev 10:41552d038a69 1321 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Zaitsev 10:41552d038a69 1322
Zaitsev 10:41552d038a69 1323 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Zaitsev 10:41552d038a69 1324 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Zaitsev 10:41552d038a69 1325
Zaitsev 10:41552d038a69 1326 /* TPI DEVTYPE Register Definitions */
Zaitsev 10:41552d038a69 1327 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
Zaitsev 10:41552d038a69 1328 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Zaitsev 10:41552d038a69 1329
Zaitsev 10:41552d038a69 1330 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Zaitsev 10:41552d038a69 1331 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Zaitsev 10:41552d038a69 1332
Zaitsev 10:41552d038a69 1333 /*@}*/ /* end of group CMSIS_TPI */
Zaitsev 10:41552d038a69 1334
Zaitsev 10:41552d038a69 1335
Zaitsev 10:41552d038a69 1336 #if (__MPU_PRESENT == 1)
Zaitsev 10:41552d038a69 1337 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 1338 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Zaitsev 10:41552d038a69 1339 \brief Type definitions for the Memory Protection Unit (MPU)
Zaitsev 10:41552d038a69 1340 @{
Zaitsev 10:41552d038a69 1341 */
Zaitsev 10:41552d038a69 1342
Zaitsev 10:41552d038a69 1343 /** \brief Structure type to access the Memory Protection Unit (MPU).
Zaitsev 10:41552d038a69 1344 */
Zaitsev 10:41552d038a69 1345 typedef struct
Zaitsev 10:41552d038a69 1346 {
Zaitsev 10:41552d038a69 1347 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Zaitsev 10:41552d038a69 1348 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Zaitsev 10:41552d038a69 1349 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Zaitsev 10:41552d038a69 1350 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Zaitsev 10:41552d038a69 1351 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Zaitsev 10:41552d038a69 1352 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Zaitsev 10:41552d038a69 1353 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Zaitsev 10:41552d038a69 1354 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Zaitsev 10:41552d038a69 1355 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Zaitsev 10:41552d038a69 1356 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Zaitsev 10:41552d038a69 1357 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Zaitsev 10:41552d038a69 1358 } MPU_Type;
Zaitsev 10:41552d038a69 1359
Zaitsev 10:41552d038a69 1360 /* MPU Type Register */
Zaitsev 10:41552d038a69 1361 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Zaitsev 10:41552d038a69 1362 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Zaitsev 10:41552d038a69 1363
Zaitsev 10:41552d038a69 1364 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Zaitsev 10:41552d038a69 1365 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Zaitsev 10:41552d038a69 1366
Zaitsev 10:41552d038a69 1367 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Zaitsev 10:41552d038a69 1368 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Zaitsev 10:41552d038a69 1369
Zaitsev 10:41552d038a69 1370 /* MPU Control Register */
Zaitsev 10:41552d038a69 1371 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Zaitsev 10:41552d038a69 1372 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Zaitsev 10:41552d038a69 1373
Zaitsev 10:41552d038a69 1374 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Zaitsev 10:41552d038a69 1375 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Zaitsev 10:41552d038a69 1376
Zaitsev 10:41552d038a69 1377 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Zaitsev 10:41552d038a69 1378 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Zaitsev 10:41552d038a69 1379
Zaitsev 10:41552d038a69 1380 /* MPU Region Number Register */
Zaitsev 10:41552d038a69 1381 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Zaitsev 10:41552d038a69 1382 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Zaitsev 10:41552d038a69 1383
Zaitsev 10:41552d038a69 1384 /* MPU Region Base Address Register */
Zaitsev 10:41552d038a69 1385 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
Zaitsev 10:41552d038a69 1386 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Zaitsev 10:41552d038a69 1387
Zaitsev 10:41552d038a69 1388 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Zaitsev 10:41552d038a69 1389 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Zaitsev 10:41552d038a69 1390
Zaitsev 10:41552d038a69 1391 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Zaitsev 10:41552d038a69 1392 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Zaitsev 10:41552d038a69 1393
Zaitsev 10:41552d038a69 1394 /* MPU Region Attribute and Size Register */
Zaitsev 10:41552d038a69 1395 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Zaitsev 10:41552d038a69 1396 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Zaitsev 10:41552d038a69 1397
Zaitsev 10:41552d038a69 1398 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Zaitsev 10:41552d038a69 1399 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Zaitsev 10:41552d038a69 1400
Zaitsev 10:41552d038a69 1401 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Zaitsev 10:41552d038a69 1402 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Zaitsev 10:41552d038a69 1403
Zaitsev 10:41552d038a69 1404 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Zaitsev 10:41552d038a69 1405 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Zaitsev 10:41552d038a69 1406
Zaitsev 10:41552d038a69 1407 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Zaitsev 10:41552d038a69 1408 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Zaitsev 10:41552d038a69 1409
Zaitsev 10:41552d038a69 1410 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Zaitsev 10:41552d038a69 1411 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Zaitsev 10:41552d038a69 1412
Zaitsev 10:41552d038a69 1413 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Zaitsev 10:41552d038a69 1414 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Zaitsev 10:41552d038a69 1415
Zaitsev 10:41552d038a69 1416 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Zaitsev 10:41552d038a69 1417 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Zaitsev 10:41552d038a69 1418
Zaitsev 10:41552d038a69 1419 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Zaitsev 10:41552d038a69 1420 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Zaitsev 10:41552d038a69 1421
Zaitsev 10:41552d038a69 1422 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Zaitsev 10:41552d038a69 1423 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Zaitsev 10:41552d038a69 1424
Zaitsev 10:41552d038a69 1425 /*@} end of group CMSIS_MPU */
Zaitsev 10:41552d038a69 1426 #endif
Zaitsev 10:41552d038a69 1427
Zaitsev 10:41552d038a69 1428
Zaitsev 10:41552d038a69 1429 #if (__FPU_PRESENT == 1)
Zaitsev 10:41552d038a69 1430 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 1431 \defgroup CMSIS_FPU Floating Point Unit (FPU)
Zaitsev 10:41552d038a69 1432 \brief Type definitions for the Floating Point Unit (FPU)
Zaitsev 10:41552d038a69 1433 @{
Zaitsev 10:41552d038a69 1434 */
Zaitsev 10:41552d038a69 1435
Zaitsev 10:41552d038a69 1436 /** \brief Structure type to access the Floating Point Unit (FPU).
Zaitsev 10:41552d038a69 1437 */
Zaitsev 10:41552d038a69 1438 typedef struct
Zaitsev 10:41552d038a69 1439 {
Zaitsev 10:41552d038a69 1440 uint32_t RESERVED0[1];
Zaitsev 10:41552d038a69 1441 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
Zaitsev 10:41552d038a69 1442 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
Zaitsev 10:41552d038a69 1443 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
Zaitsev 10:41552d038a69 1444 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
Zaitsev 10:41552d038a69 1445 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
Zaitsev 10:41552d038a69 1446 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
Zaitsev 10:41552d038a69 1447 } FPU_Type;
Zaitsev 10:41552d038a69 1448
Zaitsev 10:41552d038a69 1449 /* Floating-Point Context Control Register */
Zaitsev 10:41552d038a69 1450 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
Zaitsev 10:41552d038a69 1451 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
Zaitsev 10:41552d038a69 1452
Zaitsev 10:41552d038a69 1453 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
Zaitsev 10:41552d038a69 1454 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
Zaitsev 10:41552d038a69 1455
Zaitsev 10:41552d038a69 1456 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
Zaitsev 10:41552d038a69 1457 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
Zaitsev 10:41552d038a69 1458
Zaitsev 10:41552d038a69 1459 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
Zaitsev 10:41552d038a69 1460 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
Zaitsev 10:41552d038a69 1461
Zaitsev 10:41552d038a69 1462 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
Zaitsev 10:41552d038a69 1463 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
Zaitsev 10:41552d038a69 1464
Zaitsev 10:41552d038a69 1465 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
Zaitsev 10:41552d038a69 1466 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
Zaitsev 10:41552d038a69 1467
Zaitsev 10:41552d038a69 1468 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
Zaitsev 10:41552d038a69 1469 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
Zaitsev 10:41552d038a69 1470
Zaitsev 10:41552d038a69 1471 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
Zaitsev 10:41552d038a69 1472 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
Zaitsev 10:41552d038a69 1473
Zaitsev 10:41552d038a69 1474 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
Zaitsev 10:41552d038a69 1475 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
Zaitsev 10:41552d038a69 1476
Zaitsev 10:41552d038a69 1477 /* Floating-Point Context Address Register */
Zaitsev 10:41552d038a69 1478 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
Zaitsev 10:41552d038a69 1479 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
Zaitsev 10:41552d038a69 1480
Zaitsev 10:41552d038a69 1481 /* Floating-Point Default Status Control Register */
Zaitsev 10:41552d038a69 1482 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
Zaitsev 10:41552d038a69 1483 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
Zaitsev 10:41552d038a69 1484
Zaitsev 10:41552d038a69 1485 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
Zaitsev 10:41552d038a69 1486 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
Zaitsev 10:41552d038a69 1487
Zaitsev 10:41552d038a69 1488 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
Zaitsev 10:41552d038a69 1489 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
Zaitsev 10:41552d038a69 1490
Zaitsev 10:41552d038a69 1491 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
Zaitsev 10:41552d038a69 1492 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
Zaitsev 10:41552d038a69 1493
Zaitsev 10:41552d038a69 1494 /* Media and FP Feature Register 0 */
Zaitsev 10:41552d038a69 1495 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
Zaitsev 10:41552d038a69 1496 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
Zaitsev 10:41552d038a69 1497
Zaitsev 10:41552d038a69 1498 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
Zaitsev 10:41552d038a69 1499 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
Zaitsev 10:41552d038a69 1500
Zaitsev 10:41552d038a69 1501 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
Zaitsev 10:41552d038a69 1502 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
Zaitsev 10:41552d038a69 1503
Zaitsev 10:41552d038a69 1504 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
Zaitsev 10:41552d038a69 1505 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
Zaitsev 10:41552d038a69 1506
Zaitsev 10:41552d038a69 1507 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
Zaitsev 10:41552d038a69 1508 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
Zaitsev 10:41552d038a69 1509
Zaitsev 10:41552d038a69 1510 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
Zaitsev 10:41552d038a69 1511 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
Zaitsev 10:41552d038a69 1512
Zaitsev 10:41552d038a69 1513 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
Zaitsev 10:41552d038a69 1514 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
Zaitsev 10:41552d038a69 1515
Zaitsev 10:41552d038a69 1516 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
Zaitsev 10:41552d038a69 1517 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
Zaitsev 10:41552d038a69 1518
Zaitsev 10:41552d038a69 1519 /* Media and FP Feature Register 1 */
Zaitsev 10:41552d038a69 1520 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
Zaitsev 10:41552d038a69 1521 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
Zaitsev 10:41552d038a69 1522
Zaitsev 10:41552d038a69 1523 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
Zaitsev 10:41552d038a69 1524 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
Zaitsev 10:41552d038a69 1525
Zaitsev 10:41552d038a69 1526 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
Zaitsev 10:41552d038a69 1527 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
Zaitsev 10:41552d038a69 1528
Zaitsev 10:41552d038a69 1529 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
Zaitsev 10:41552d038a69 1530 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
Zaitsev 10:41552d038a69 1531
Zaitsev 10:41552d038a69 1532 /* Media and FP Feature Register 2 */
Zaitsev 10:41552d038a69 1533
Zaitsev 10:41552d038a69 1534 /*@} end of group CMSIS_FPU */
Zaitsev 10:41552d038a69 1535 #endif
Zaitsev 10:41552d038a69 1536
Zaitsev 10:41552d038a69 1537
Zaitsev 10:41552d038a69 1538 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 1539 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Zaitsev 10:41552d038a69 1540 \brief Type definitions for the Core Debug Registers
Zaitsev 10:41552d038a69 1541 @{
Zaitsev 10:41552d038a69 1542 */
Zaitsev 10:41552d038a69 1543
Zaitsev 10:41552d038a69 1544 /** \brief Structure type to access the Core Debug Register (CoreDebug).
Zaitsev 10:41552d038a69 1545 */
Zaitsev 10:41552d038a69 1546 typedef struct
Zaitsev 10:41552d038a69 1547 {
Zaitsev 10:41552d038a69 1548 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Zaitsev 10:41552d038a69 1549 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Zaitsev 10:41552d038a69 1550 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Zaitsev 10:41552d038a69 1551 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Zaitsev 10:41552d038a69 1552 } CoreDebug_Type;
Zaitsev 10:41552d038a69 1553
Zaitsev 10:41552d038a69 1554 /* Debug Halting Control and Status Register */
Zaitsev 10:41552d038a69 1555 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
Zaitsev 10:41552d038a69 1556 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Zaitsev 10:41552d038a69 1557
Zaitsev 10:41552d038a69 1558 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
Zaitsev 10:41552d038a69 1559 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Zaitsev 10:41552d038a69 1560
Zaitsev 10:41552d038a69 1561 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Zaitsev 10:41552d038a69 1562 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Zaitsev 10:41552d038a69 1563
Zaitsev 10:41552d038a69 1564 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
Zaitsev 10:41552d038a69 1565 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Zaitsev 10:41552d038a69 1566
Zaitsev 10:41552d038a69 1567 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
Zaitsev 10:41552d038a69 1568 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Zaitsev 10:41552d038a69 1569
Zaitsev 10:41552d038a69 1570 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
Zaitsev 10:41552d038a69 1571 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Zaitsev 10:41552d038a69 1572
Zaitsev 10:41552d038a69 1573 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
Zaitsev 10:41552d038a69 1574 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Zaitsev 10:41552d038a69 1575
Zaitsev 10:41552d038a69 1576 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Zaitsev 10:41552d038a69 1577 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Zaitsev 10:41552d038a69 1578
Zaitsev 10:41552d038a69 1579 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
Zaitsev 10:41552d038a69 1580 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Zaitsev 10:41552d038a69 1581
Zaitsev 10:41552d038a69 1582 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
Zaitsev 10:41552d038a69 1583 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Zaitsev 10:41552d038a69 1584
Zaitsev 10:41552d038a69 1585 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
Zaitsev 10:41552d038a69 1586 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Zaitsev 10:41552d038a69 1587
Zaitsev 10:41552d038a69 1588 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Zaitsev 10:41552d038a69 1589 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Zaitsev 10:41552d038a69 1590
Zaitsev 10:41552d038a69 1591 /* Debug Core Register Selector Register */
Zaitsev 10:41552d038a69 1592 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
Zaitsev 10:41552d038a69 1593 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Zaitsev 10:41552d038a69 1594
Zaitsev 10:41552d038a69 1595 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Zaitsev 10:41552d038a69 1596 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Zaitsev 10:41552d038a69 1597
Zaitsev 10:41552d038a69 1598 /* Debug Exception and Monitor Control Register */
Zaitsev 10:41552d038a69 1599 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
Zaitsev 10:41552d038a69 1600 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Zaitsev 10:41552d038a69 1601
Zaitsev 10:41552d038a69 1602 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
Zaitsev 10:41552d038a69 1603 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Zaitsev 10:41552d038a69 1604
Zaitsev 10:41552d038a69 1605 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
Zaitsev 10:41552d038a69 1606 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Zaitsev 10:41552d038a69 1607
Zaitsev 10:41552d038a69 1608 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
Zaitsev 10:41552d038a69 1609 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Zaitsev 10:41552d038a69 1610
Zaitsev 10:41552d038a69 1611 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
Zaitsev 10:41552d038a69 1612 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Zaitsev 10:41552d038a69 1613
Zaitsev 10:41552d038a69 1614 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
Zaitsev 10:41552d038a69 1615 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Zaitsev 10:41552d038a69 1616
Zaitsev 10:41552d038a69 1617 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
Zaitsev 10:41552d038a69 1618 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Zaitsev 10:41552d038a69 1619
Zaitsev 10:41552d038a69 1620 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
Zaitsev 10:41552d038a69 1621 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Zaitsev 10:41552d038a69 1622
Zaitsev 10:41552d038a69 1623 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
Zaitsev 10:41552d038a69 1624 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Zaitsev 10:41552d038a69 1625
Zaitsev 10:41552d038a69 1626 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
Zaitsev 10:41552d038a69 1627 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Zaitsev 10:41552d038a69 1628
Zaitsev 10:41552d038a69 1629 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Zaitsev 10:41552d038a69 1630 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Zaitsev 10:41552d038a69 1631
Zaitsev 10:41552d038a69 1632 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
Zaitsev 10:41552d038a69 1633 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Zaitsev 10:41552d038a69 1634
Zaitsev 10:41552d038a69 1635 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Zaitsev 10:41552d038a69 1636 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Zaitsev 10:41552d038a69 1637
Zaitsev 10:41552d038a69 1638 /*@} end of group CMSIS_CoreDebug */
Zaitsev 10:41552d038a69 1639
Zaitsev 10:41552d038a69 1640
Zaitsev 10:41552d038a69 1641 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 1642 \defgroup CMSIS_core_base Core Definitions
Zaitsev 10:41552d038a69 1643 \brief Definitions for base addresses, unions, and structures.
Zaitsev 10:41552d038a69 1644 @{
Zaitsev 10:41552d038a69 1645 */
Zaitsev 10:41552d038a69 1646
Zaitsev 10:41552d038a69 1647 /* Memory mapping of Cortex-M4 Hardware */
Zaitsev 10:41552d038a69 1648 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Zaitsev 10:41552d038a69 1649 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Zaitsev 10:41552d038a69 1650 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Zaitsev 10:41552d038a69 1651 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Zaitsev 10:41552d038a69 1652 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Zaitsev 10:41552d038a69 1653 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Zaitsev 10:41552d038a69 1654 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Zaitsev 10:41552d038a69 1655 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Zaitsev 10:41552d038a69 1656
Zaitsev 10:41552d038a69 1657 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Zaitsev 10:41552d038a69 1658 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Zaitsev 10:41552d038a69 1659 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Zaitsev 10:41552d038a69 1660 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Zaitsev 10:41552d038a69 1661 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Zaitsev 10:41552d038a69 1662 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Zaitsev 10:41552d038a69 1663 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Zaitsev 10:41552d038a69 1664 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Zaitsev 10:41552d038a69 1665
Zaitsev 10:41552d038a69 1666 #if (__MPU_PRESENT == 1)
Zaitsev 10:41552d038a69 1667 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Zaitsev 10:41552d038a69 1668 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Zaitsev 10:41552d038a69 1669 #endif
Zaitsev 10:41552d038a69 1670
Zaitsev 10:41552d038a69 1671 #if (__FPU_PRESENT == 1)
Zaitsev 10:41552d038a69 1672 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
Zaitsev 10:41552d038a69 1673 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
Zaitsev 10:41552d038a69 1674 #endif
Zaitsev 10:41552d038a69 1675
Zaitsev 10:41552d038a69 1676 /*@} */
Zaitsev 10:41552d038a69 1677
Zaitsev 10:41552d038a69 1678
Zaitsev 10:41552d038a69 1679
Zaitsev 10:41552d038a69 1680 /*******************************************************************************
Zaitsev 10:41552d038a69 1681 * Hardware Abstraction Layer
Zaitsev 10:41552d038a69 1682 Core Function Interface contains:
Zaitsev 10:41552d038a69 1683 - Core NVIC Functions
Zaitsev 10:41552d038a69 1684 - Core SysTick Functions
Zaitsev 10:41552d038a69 1685 - Core Debug Functions
Zaitsev 10:41552d038a69 1686 - Core Register Access Functions
Zaitsev 10:41552d038a69 1687 ******************************************************************************/
Zaitsev 10:41552d038a69 1688 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Zaitsev 10:41552d038a69 1689 */
Zaitsev 10:41552d038a69 1690
Zaitsev 10:41552d038a69 1691
Zaitsev 10:41552d038a69 1692
Zaitsev 10:41552d038a69 1693 /* ########################## NVIC functions #################################### */
Zaitsev 10:41552d038a69 1694 /** \ingroup CMSIS_Core_FunctionInterface
Zaitsev 10:41552d038a69 1695 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Zaitsev 10:41552d038a69 1696 \brief Functions that manage interrupts and exceptions via the NVIC.
Zaitsev 10:41552d038a69 1697 @{
Zaitsev 10:41552d038a69 1698 */
Zaitsev 10:41552d038a69 1699
Zaitsev 10:41552d038a69 1700 /** \brief Set Priority Grouping
Zaitsev 10:41552d038a69 1701
Zaitsev 10:41552d038a69 1702 The function sets the priority grouping field using the required unlock sequence.
Zaitsev 10:41552d038a69 1703 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Zaitsev 10:41552d038a69 1704 Only values from 0..7 are used.
Zaitsev 10:41552d038a69 1705 In case of a conflict between priority grouping and available
Zaitsev 10:41552d038a69 1706 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Zaitsev 10:41552d038a69 1707
Zaitsev 10:41552d038a69 1708 \param [in] PriorityGroup Priority grouping field.
Zaitsev 10:41552d038a69 1709 */
Zaitsev 10:41552d038a69 1710 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Zaitsev 10:41552d038a69 1711 {
Zaitsev 10:41552d038a69 1712 uint32_t reg_value;
Zaitsev 10:41552d038a69 1713 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Zaitsev 10:41552d038a69 1714
Zaitsev 10:41552d038a69 1715 reg_value = SCB->AIRCR; /* read old register configuration */
Zaitsev 10:41552d038a69 1716 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Zaitsev 10:41552d038a69 1717 reg_value = (reg_value |
Zaitsev 10:41552d038a69 1718 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Zaitsev 10:41552d038a69 1719 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Zaitsev 10:41552d038a69 1720 SCB->AIRCR = reg_value;
Zaitsev 10:41552d038a69 1721 }
Zaitsev 10:41552d038a69 1722
Zaitsev 10:41552d038a69 1723
Zaitsev 10:41552d038a69 1724 /** \brief Get Priority Grouping
Zaitsev 10:41552d038a69 1725
Zaitsev 10:41552d038a69 1726 The function reads the priority grouping field from the NVIC Interrupt Controller.
Zaitsev 10:41552d038a69 1727
Zaitsev 10:41552d038a69 1728 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Zaitsev 10:41552d038a69 1729 */
Zaitsev 10:41552d038a69 1730 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Zaitsev 10:41552d038a69 1731 {
Zaitsev 10:41552d038a69 1732 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Zaitsev 10:41552d038a69 1733 }
Zaitsev 10:41552d038a69 1734
Zaitsev 10:41552d038a69 1735
Zaitsev 10:41552d038a69 1736 /** \brief Enable External Interrupt
Zaitsev 10:41552d038a69 1737
Zaitsev 10:41552d038a69 1738 The function enables a device-specific interrupt in the NVIC interrupt controller.
Zaitsev 10:41552d038a69 1739
Zaitsev 10:41552d038a69 1740 \param [in] IRQn External interrupt number. Value cannot be negative.
Zaitsev 10:41552d038a69 1741 */
Zaitsev 10:41552d038a69 1742 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1743 {
Zaitsev 10:41552d038a69 1744 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Zaitsev 10:41552d038a69 1745 }
Zaitsev 10:41552d038a69 1746
Zaitsev 10:41552d038a69 1747
Zaitsev 10:41552d038a69 1748 /** \brief Disable External Interrupt
Zaitsev 10:41552d038a69 1749
Zaitsev 10:41552d038a69 1750 The function disables a device-specific interrupt in the NVIC interrupt controller.
Zaitsev 10:41552d038a69 1751
Zaitsev 10:41552d038a69 1752 \param [in] IRQn External interrupt number. Value cannot be negative.
Zaitsev 10:41552d038a69 1753 */
Zaitsev 10:41552d038a69 1754 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1755 {
Zaitsev 10:41552d038a69 1756 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Zaitsev 10:41552d038a69 1757 __DSB();
Zaitsev 10:41552d038a69 1758 __ISB();
Zaitsev 10:41552d038a69 1759 }
Zaitsev 10:41552d038a69 1760
Zaitsev 10:41552d038a69 1761
Zaitsev 10:41552d038a69 1762 /** \brief Get Pending Interrupt
Zaitsev 10:41552d038a69 1763
Zaitsev 10:41552d038a69 1764 The function reads the pending register in the NVIC and returns the pending bit
Zaitsev 10:41552d038a69 1765 for the specified interrupt.
Zaitsev 10:41552d038a69 1766
Zaitsev 10:41552d038a69 1767 \param [in] IRQn Interrupt number.
Zaitsev 10:41552d038a69 1768
Zaitsev 10:41552d038a69 1769 \return 0 Interrupt status is not pending.
Zaitsev 10:41552d038a69 1770 \return 1 Interrupt status is pending.
Zaitsev 10:41552d038a69 1771 */
Zaitsev 10:41552d038a69 1772 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1773 {
Zaitsev 10:41552d038a69 1774 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Zaitsev 10:41552d038a69 1775 }
Zaitsev 10:41552d038a69 1776
Zaitsev 10:41552d038a69 1777
Zaitsev 10:41552d038a69 1778 /** \brief Set Pending Interrupt
Zaitsev 10:41552d038a69 1779
Zaitsev 10:41552d038a69 1780 The function sets the pending bit of an external interrupt.
Zaitsev 10:41552d038a69 1781
Zaitsev 10:41552d038a69 1782 \param [in] IRQn Interrupt number. Value cannot be negative.
Zaitsev 10:41552d038a69 1783 */
Zaitsev 10:41552d038a69 1784 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1785 {
Zaitsev 10:41552d038a69 1786 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Zaitsev 10:41552d038a69 1787 }
Zaitsev 10:41552d038a69 1788
Zaitsev 10:41552d038a69 1789
Zaitsev 10:41552d038a69 1790 /** \brief Clear Pending Interrupt
Zaitsev 10:41552d038a69 1791
Zaitsev 10:41552d038a69 1792 The function clears the pending bit of an external interrupt.
Zaitsev 10:41552d038a69 1793
Zaitsev 10:41552d038a69 1794 \param [in] IRQn External interrupt number. Value cannot be negative.
Zaitsev 10:41552d038a69 1795 */
Zaitsev 10:41552d038a69 1796 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1797 {
Zaitsev 10:41552d038a69 1798 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Zaitsev 10:41552d038a69 1799 }
Zaitsev 10:41552d038a69 1800
Zaitsev 10:41552d038a69 1801
Zaitsev 10:41552d038a69 1802 /** \brief Get Active Interrupt
Zaitsev 10:41552d038a69 1803
Zaitsev 10:41552d038a69 1804 The function reads the active register in NVIC and returns the active bit.
Zaitsev 10:41552d038a69 1805
Zaitsev 10:41552d038a69 1806 \param [in] IRQn Interrupt number.
Zaitsev 10:41552d038a69 1807
Zaitsev 10:41552d038a69 1808 \return 0 Interrupt status is not active.
Zaitsev 10:41552d038a69 1809 \return 1 Interrupt status is active.
Zaitsev 10:41552d038a69 1810 */
Zaitsev 10:41552d038a69 1811 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1812 {
Zaitsev 10:41552d038a69 1813 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Zaitsev 10:41552d038a69 1814 }
Zaitsev 10:41552d038a69 1815
Zaitsev 10:41552d038a69 1816
Zaitsev 10:41552d038a69 1817 /** \brief Set Interrupt Priority
Zaitsev 10:41552d038a69 1818
Zaitsev 10:41552d038a69 1819 The function sets the priority of an interrupt.
Zaitsev 10:41552d038a69 1820
Zaitsev 10:41552d038a69 1821 \note The priority cannot be set for every core interrupt.
Zaitsev 10:41552d038a69 1822
Zaitsev 10:41552d038a69 1823 \param [in] IRQn Interrupt number.
Zaitsev 10:41552d038a69 1824 \param [in] priority Priority to set.
Zaitsev 10:41552d038a69 1825 */
Zaitsev 10:41552d038a69 1826 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Zaitsev 10:41552d038a69 1827 {
Zaitsev 10:41552d038a69 1828 if((int32_t)IRQn < 0) {
Zaitsev 10:41552d038a69 1829 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Zaitsev 10:41552d038a69 1830 }
Zaitsev 10:41552d038a69 1831 else {
Zaitsev 10:41552d038a69 1832 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Zaitsev 10:41552d038a69 1833 }
Zaitsev 10:41552d038a69 1834 }
Zaitsev 10:41552d038a69 1835
Zaitsev 10:41552d038a69 1836
Zaitsev 10:41552d038a69 1837 /** \brief Get Interrupt Priority
Zaitsev 10:41552d038a69 1838
Zaitsev 10:41552d038a69 1839 The function reads the priority of an interrupt. The interrupt
Zaitsev 10:41552d038a69 1840 number can be positive to specify an external (device specific)
Zaitsev 10:41552d038a69 1841 interrupt, or negative to specify an internal (core) interrupt.
Zaitsev 10:41552d038a69 1842
Zaitsev 10:41552d038a69 1843
Zaitsev 10:41552d038a69 1844 \param [in] IRQn Interrupt number.
Zaitsev 10:41552d038a69 1845 \return Interrupt Priority. Value is aligned automatically to the implemented
Zaitsev 10:41552d038a69 1846 priority bits of the microcontroller.
Zaitsev 10:41552d038a69 1847 */
Zaitsev 10:41552d038a69 1848 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1849 {
Zaitsev 10:41552d038a69 1850
Zaitsev 10:41552d038a69 1851 if((int32_t)IRQn < 0) {
Zaitsev 10:41552d038a69 1852 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Zaitsev 10:41552d038a69 1853 }
Zaitsev 10:41552d038a69 1854 else {
Zaitsev 10:41552d038a69 1855 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Zaitsev 10:41552d038a69 1856 }
Zaitsev 10:41552d038a69 1857 }
Zaitsev 10:41552d038a69 1858
Zaitsev 10:41552d038a69 1859
Zaitsev 10:41552d038a69 1860 /** \brief Encode Priority
Zaitsev 10:41552d038a69 1861
Zaitsev 10:41552d038a69 1862 The function encodes the priority for an interrupt with the given priority group,
Zaitsev 10:41552d038a69 1863 preemptive priority value, and subpriority value.
Zaitsev 10:41552d038a69 1864 In case of a conflict between priority grouping and available
Zaitsev 10:41552d038a69 1865 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Zaitsev 10:41552d038a69 1866
Zaitsev 10:41552d038a69 1867 \param [in] PriorityGroup Used priority group.
Zaitsev 10:41552d038a69 1868 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Zaitsev 10:41552d038a69 1869 \param [in] SubPriority Subpriority value (starting from 0).
Zaitsev 10:41552d038a69 1870 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Zaitsev 10:41552d038a69 1871 */
Zaitsev 10:41552d038a69 1872 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Zaitsev 10:41552d038a69 1873 {
Zaitsev 10:41552d038a69 1874 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Zaitsev 10:41552d038a69 1875 uint32_t PreemptPriorityBits;
Zaitsev 10:41552d038a69 1876 uint32_t SubPriorityBits;
Zaitsev 10:41552d038a69 1877
Zaitsev 10:41552d038a69 1878 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Zaitsev 10:41552d038a69 1879 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Zaitsev 10:41552d038a69 1880
Zaitsev 10:41552d038a69 1881 return (
Zaitsev 10:41552d038a69 1882 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Zaitsev 10:41552d038a69 1883 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Zaitsev 10:41552d038a69 1884 );
Zaitsev 10:41552d038a69 1885 }
Zaitsev 10:41552d038a69 1886
Zaitsev 10:41552d038a69 1887
Zaitsev 10:41552d038a69 1888 /** \brief Decode Priority
Zaitsev 10:41552d038a69 1889
Zaitsev 10:41552d038a69 1890 The function decodes an interrupt priority value with a given priority group to
Zaitsev 10:41552d038a69 1891 preemptive priority value and subpriority value.
Zaitsev 10:41552d038a69 1892 In case of a conflict between priority grouping and available
Zaitsev 10:41552d038a69 1893 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Zaitsev 10:41552d038a69 1894
Zaitsev 10:41552d038a69 1895 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Zaitsev 10:41552d038a69 1896 \param [in] PriorityGroup Used priority group.
Zaitsev 10:41552d038a69 1897 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Zaitsev 10:41552d038a69 1898 \param [out] pSubPriority Subpriority value (starting from 0).
Zaitsev 10:41552d038a69 1899 */
Zaitsev 10:41552d038a69 1900 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Zaitsev 10:41552d038a69 1901 {
Zaitsev 10:41552d038a69 1902 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Zaitsev 10:41552d038a69 1903 uint32_t PreemptPriorityBits;
Zaitsev 10:41552d038a69 1904 uint32_t SubPriorityBits;
Zaitsev 10:41552d038a69 1905
Zaitsev 10:41552d038a69 1906 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Zaitsev 10:41552d038a69 1907 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Zaitsev 10:41552d038a69 1908
Zaitsev 10:41552d038a69 1909 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Zaitsev 10:41552d038a69 1910 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Zaitsev 10:41552d038a69 1911 }
Zaitsev 10:41552d038a69 1912
Zaitsev 10:41552d038a69 1913
Zaitsev 10:41552d038a69 1914 /** \brief System Reset
Zaitsev 10:41552d038a69 1915
Zaitsev 10:41552d038a69 1916 The function initiates a system reset request to reset the MCU.
Zaitsev 10:41552d038a69 1917 */
Zaitsev 10:41552d038a69 1918 __STATIC_INLINE void NVIC_SystemReset(void)
Zaitsev 10:41552d038a69 1919 {
Zaitsev 10:41552d038a69 1920 __DSB(); /* Ensure all outstanding memory accesses included
Zaitsev 10:41552d038a69 1921 buffered write are completed before reset */
Zaitsev 10:41552d038a69 1922 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Zaitsev 10:41552d038a69 1923 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Zaitsev 10:41552d038a69 1924 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Zaitsev 10:41552d038a69 1925 __DSB(); /* Ensure completion of memory access */
Zaitsev 10:41552d038a69 1926 while(1) { __NOP(); } /* wait until reset */
Zaitsev 10:41552d038a69 1927 }
Zaitsev 10:41552d038a69 1928
Zaitsev 10:41552d038a69 1929 /*@} end of CMSIS_Core_NVICFunctions */
Zaitsev 10:41552d038a69 1930
Zaitsev 10:41552d038a69 1931
Zaitsev 10:41552d038a69 1932 /* ########################## FPU functions #################################### */
Zaitsev 10:41552d038a69 1933 /** \ingroup CMSIS_Core_FunctionInterface
Zaitsev 10:41552d038a69 1934 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Zaitsev 10:41552d038a69 1935 \brief Function that provides FPU type.
Zaitsev 10:41552d038a69 1936 @{
Zaitsev 10:41552d038a69 1937 */
Zaitsev 10:41552d038a69 1938
Zaitsev 10:41552d038a69 1939 /**
Zaitsev 10:41552d038a69 1940 \fn uint32_t SCB_GetFPUType(void)
Zaitsev 10:41552d038a69 1941 \brief get FPU type
Zaitsev 10:41552d038a69 1942 \returns
Zaitsev 10:41552d038a69 1943 - \b 0: No FPU
Zaitsev 10:41552d038a69 1944 - \b 1: Single precision FPU
Zaitsev 10:41552d038a69 1945 - \b 2: Double + Single precision FPU
Zaitsev 10:41552d038a69 1946 */
Zaitsev 10:41552d038a69 1947 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Zaitsev 10:41552d038a69 1948 {
Zaitsev 10:41552d038a69 1949 uint32_t mvfr0;
Zaitsev 10:41552d038a69 1950
Zaitsev 10:41552d038a69 1951 mvfr0 = SCB->MVFR0;
Zaitsev 10:41552d038a69 1952 if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
Zaitsev 10:41552d038a69 1953 return 2UL; // Double + Single precision FPU
Zaitsev 10:41552d038a69 1954 } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
Zaitsev 10:41552d038a69 1955 return 1UL; // Single precision FPU
Zaitsev 10:41552d038a69 1956 } else {
Zaitsev 10:41552d038a69 1957 return 0UL; // No FPU
Zaitsev 10:41552d038a69 1958 }
Zaitsev 10:41552d038a69 1959 }
Zaitsev 10:41552d038a69 1960
Zaitsev 10:41552d038a69 1961
Zaitsev 10:41552d038a69 1962 /*@} end of CMSIS_Core_FpuFunctions */
Zaitsev 10:41552d038a69 1963
Zaitsev 10:41552d038a69 1964
Zaitsev 10:41552d038a69 1965
Zaitsev 10:41552d038a69 1966 /* ########################## Cache functions #################################### */
Zaitsev 10:41552d038a69 1967 /** \ingroup CMSIS_Core_FunctionInterface
Zaitsev 10:41552d038a69 1968 \defgroup CMSIS_Core_CacheFunctions Cache Functions
Zaitsev 10:41552d038a69 1969 \brief Functions that configure Instruction and Data cache.
Zaitsev 10:41552d038a69 1970 @{
Zaitsev 10:41552d038a69 1971 */
Zaitsev 10:41552d038a69 1972
Zaitsev 10:41552d038a69 1973 /* Cache Size ID Register Macros */
Zaitsev 10:41552d038a69 1974 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
Zaitsev 10:41552d038a69 1975 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
Zaitsev 10:41552d038a69 1976 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
Zaitsev 10:41552d038a69 1977
Zaitsev 10:41552d038a69 1978
Zaitsev 10:41552d038a69 1979 /** \brief Enable I-Cache
Zaitsev 10:41552d038a69 1980
Zaitsev 10:41552d038a69 1981 The function turns on I-Cache
Zaitsev 10:41552d038a69 1982 */
Zaitsev 10:41552d038a69 1983 __STATIC_INLINE void SCB_EnableICache (void)
Zaitsev 10:41552d038a69 1984 {
Zaitsev 10:41552d038a69 1985 #if (__ICACHE_PRESENT == 1)
Zaitsev 10:41552d038a69 1986 __DSB();
Zaitsev 10:41552d038a69 1987 __ISB();
Zaitsev 10:41552d038a69 1988 SCB->ICIALLU = 0UL; // invalidate I-Cache
Zaitsev 10:41552d038a69 1989 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
Zaitsev 10:41552d038a69 1990 __DSB();
Zaitsev 10:41552d038a69 1991 __ISB();
Zaitsev 10:41552d038a69 1992 #endif
Zaitsev 10:41552d038a69 1993 }
Zaitsev 10:41552d038a69 1994
Zaitsev 10:41552d038a69 1995
Zaitsev 10:41552d038a69 1996 /** \brief Disable I-Cache
Zaitsev 10:41552d038a69 1997
Zaitsev 10:41552d038a69 1998 The function turns off I-Cache
Zaitsev 10:41552d038a69 1999 */
Zaitsev 10:41552d038a69 2000 __STATIC_INLINE void SCB_DisableICache (void)
Zaitsev 10:41552d038a69 2001 {
Zaitsev 10:41552d038a69 2002 #if (__ICACHE_PRESENT == 1)
Zaitsev 10:41552d038a69 2003 __DSB();
Zaitsev 10:41552d038a69 2004 __ISB();
Zaitsev 10:41552d038a69 2005 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
Zaitsev 10:41552d038a69 2006 SCB->ICIALLU = 0UL; // invalidate I-Cache
Zaitsev 10:41552d038a69 2007 __DSB();
Zaitsev 10:41552d038a69 2008 __ISB();
Zaitsev 10:41552d038a69 2009 #endif
Zaitsev 10:41552d038a69 2010 }
Zaitsev 10:41552d038a69 2011
Zaitsev 10:41552d038a69 2012
Zaitsev 10:41552d038a69 2013 /** \brief Invalidate I-Cache
Zaitsev 10:41552d038a69 2014
Zaitsev 10:41552d038a69 2015 The function invalidates I-Cache
Zaitsev 10:41552d038a69 2016 */
Zaitsev 10:41552d038a69 2017 __STATIC_INLINE void SCB_InvalidateICache (void)
Zaitsev 10:41552d038a69 2018 {
Zaitsev 10:41552d038a69 2019 #if (__ICACHE_PRESENT == 1)
Zaitsev 10:41552d038a69 2020 __DSB();
Zaitsev 10:41552d038a69 2021 __ISB();
Zaitsev 10:41552d038a69 2022 SCB->ICIALLU = 0UL;
Zaitsev 10:41552d038a69 2023 __DSB();
Zaitsev 10:41552d038a69 2024 __ISB();
Zaitsev 10:41552d038a69 2025 #endif
Zaitsev 10:41552d038a69 2026 }
Zaitsev 10:41552d038a69 2027
Zaitsev 10:41552d038a69 2028
Zaitsev 10:41552d038a69 2029 /** \brief Enable D-Cache
Zaitsev 10:41552d038a69 2030
Zaitsev 10:41552d038a69 2031 The function turns on D-Cache
Zaitsev 10:41552d038a69 2032 */
Zaitsev 10:41552d038a69 2033 __STATIC_INLINE void SCB_EnableDCache (void)
Zaitsev 10:41552d038a69 2034 {
Zaitsev 10:41552d038a69 2035 #if (__DCACHE_PRESENT == 1)
Zaitsev 10:41552d038a69 2036 uint32_t ccsidr, sshift, wshift, sw;
Zaitsev 10:41552d038a69 2037 uint32_t sets, ways;
Zaitsev 10:41552d038a69 2038
Zaitsev 10:41552d038a69 2039 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Zaitsev 10:41552d038a69 2040 ccsidr = SCB->CCSIDR;
Zaitsev 10:41552d038a69 2041 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Zaitsev 10:41552d038a69 2042 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Zaitsev 10:41552d038a69 2043 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Zaitsev 10:41552d038a69 2044 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Zaitsev 10:41552d038a69 2045
Zaitsev 10:41552d038a69 2046 __DSB();
Zaitsev 10:41552d038a69 2047
Zaitsev 10:41552d038a69 2048 do { // invalidate D-Cache
Zaitsev 10:41552d038a69 2049 uint32_t tmpways = ways;
Zaitsev 10:41552d038a69 2050 do {
Zaitsev 10:41552d038a69 2051 sw = ((tmpways << wshift) | (sets << sshift));
Zaitsev 10:41552d038a69 2052 SCB->DCISW = sw;
Zaitsev 10:41552d038a69 2053 } while(tmpways--);
Zaitsev 10:41552d038a69 2054 } while(sets--);
Zaitsev 10:41552d038a69 2055 __DSB();
Zaitsev 10:41552d038a69 2056
Zaitsev 10:41552d038a69 2057 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
Zaitsev 10:41552d038a69 2058
Zaitsev 10:41552d038a69 2059 __DSB();
Zaitsev 10:41552d038a69 2060 __ISB();
Zaitsev 10:41552d038a69 2061 #endif
Zaitsev 10:41552d038a69 2062 }
Zaitsev 10:41552d038a69 2063
Zaitsev 10:41552d038a69 2064
Zaitsev 10:41552d038a69 2065 /** \brief Disable D-Cache
Zaitsev 10:41552d038a69 2066
Zaitsev 10:41552d038a69 2067 The function turns off D-Cache
Zaitsev 10:41552d038a69 2068 */
Zaitsev 10:41552d038a69 2069 __STATIC_INLINE void SCB_DisableDCache (void)
Zaitsev 10:41552d038a69 2070 {
Zaitsev 10:41552d038a69 2071 #if (__DCACHE_PRESENT == 1)
Zaitsev 10:41552d038a69 2072 uint32_t ccsidr, sshift, wshift, sw;
Zaitsev 10:41552d038a69 2073 uint32_t sets, ways;
Zaitsev 10:41552d038a69 2074
Zaitsev 10:41552d038a69 2075 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Zaitsev 10:41552d038a69 2076 ccsidr = SCB->CCSIDR;
Zaitsev 10:41552d038a69 2077 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Zaitsev 10:41552d038a69 2078 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Zaitsev 10:41552d038a69 2079 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Zaitsev 10:41552d038a69 2080 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Zaitsev 10:41552d038a69 2081
Zaitsev 10:41552d038a69 2082 __DSB();
Zaitsev 10:41552d038a69 2083
Zaitsev 10:41552d038a69 2084 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
Zaitsev 10:41552d038a69 2085
Zaitsev 10:41552d038a69 2086 do { // clean & invalidate D-Cache
Zaitsev 10:41552d038a69 2087 uint32_t tmpways = ways;
Zaitsev 10:41552d038a69 2088 do {
Zaitsev 10:41552d038a69 2089 sw = ((tmpways << wshift) | (sets << sshift));
Zaitsev 10:41552d038a69 2090 SCB->DCCISW = sw;
Zaitsev 10:41552d038a69 2091 } while(tmpways--);
Zaitsev 10:41552d038a69 2092 } while(sets--);
Zaitsev 10:41552d038a69 2093
Zaitsev 10:41552d038a69 2094
Zaitsev 10:41552d038a69 2095 __DSB();
Zaitsev 10:41552d038a69 2096 __ISB();
Zaitsev 10:41552d038a69 2097 #endif
Zaitsev 10:41552d038a69 2098 }
Zaitsev 10:41552d038a69 2099
Zaitsev 10:41552d038a69 2100
Zaitsev 10:41552d038a69 2101 /** \brief Invalidate D-Cache
Zaitsev 10:41552d038a69 2102
Zaitsev 10:41552d038a69 2103 The function invalidates D-Cache
Zaitsev 10:41552d038a69 2104 */
Zaitsev 10:41552d038a69 2105 __STATIC_INLINE void SCB_InvalidateDCache (void)
Zaitsev 10:41552d038a69 2106 {
Zaitsev 10:41552d038a69 2107 #if (__DCACHE_PRESENT == 1)
Zaitsev 10:41552d038a69 2108 uint32_t ccsidr, sshift, wshift, sw;
Zaitsev 10:41552d038a69 2109 uint32_t sets, ways;
Zaitsev 10:41552d038a69 2110
Zaitsev 10:41552d038a69 2111 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Zaitsev 10:41552d038a69 2112 ccsidr = SCB->CCSIDR;
Zaitsev 10:41552d038a69 2113 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Zaitsev 10:41552d038a69 2114 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Zaitsev 10:41552d038a69 2115 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Zaitsev 10:41552d038a69 2116 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Zaitsev 10:41552d038a69 2117
Zaitsev 10:41552d038a69 2118 __DSB();
Zaitsev 10:41552d038a69 2119
Zaitsev 10:41552d038a69 2120 do { // invalidate D-Cache
Zaitsev 10:41552d038a69 2121 uint32_t tmpways = ways;
Zaitsev 10:41552d038a69 2122 do {
Zaitsev 10:41552d038a69 2123 sw = ((tmpways << wshift) | (sets << sshift));
Zaitsev 10:41552d038a69 2124 SCB->DCISW = sw;
Zaitsev 10:41552d038a69 2125 } while(tmpways--);
Zaitsev 10:41552d038a69 2126 } while(sets--);
Zaitsev 10:41552d038a69 2127
Zaitsev 10:41552d038a69 2128 __DSB();
Zaitsev 10:41552d038a69 2129 __ISB();
Zaitsev 10:41552d038a69 2130 #endif
Zaitsev 10:41552d038a69 2131 }
Zaitsev 10:41552d038a69 2132
Zaitsev 10:41552d038a69 2133
Zaitsev 10:41552d038a69 2134 /** \brief Clean D-Cache
Zaitsev 10:41552d038a69 2135
Zaitsev 10:41552d038a69 2136 The function cleans D-Cache
Zaitsev 10:41552d038a69 2137 */
Zaitsev 10:41552d038a69 2138 __STATIC_INLINE void SCB_CleanDCache (void)
Zaitsev 10:41552d038a69 2139 {
Zaitsev 10:41552d038a69 2140 #if (__DCACHE_PRESENT == 1)
Zaitsev 10:41552d038a69 2141 uint32_t ccsidr, sshift, wshift, sw;
Zaitsev 10:41552d038a69 2142 uint32_t sets, ways;
Zaitsev 10:41552d038a69 2143
Zaitsev 10:41552d038a69 2144 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Zaitsev 10:41552d038a69 2145 ccsidr = SCB->CCSIDR;
Zaitsev 10:41552d038a69 2146 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Zaitsev 10:41552d038a69 2147 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Zaitsev 10:41552d038a69 2148 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Zaitsev 10:41552d038a69 2149 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Zaitsev 10:41552d038a69 2150
Zaitsev 10:41552d038a69 2151 __DSB();
Zaitsev 10:41552d038a69 2152
Zaitsev 10:41552d038a69 2153 do { // clean D-Cache
Zaitsev 10:41552d038a69 2154 uint32_t tmpways = ways;
Zaitsev 10:41552d038a69 2155 do {
Zaitsev 10:41552d038a69 2156 sw = ((tmpways << wshift) | (sets << sshift));
Zaitsev 10:41552d038a69 2157 SCB->DCCSW = sw;
Zaitsev 10:41552d038a69 2158 } while(tmpways--);
Zaitsev 10:41552d038a69 2159 } while(sets--);
Zaitsev 10:41552d038a69 2160
Zaitsev 10:41552d038a69 2161 __DSB();
Zaitsev 10:41552d038a69 2162 __ISB();
Zaitsev 10:41552d038a69 2163 #endif
Zaitsev 10:41552d038a69 2164 }
Zaitsev 10:41552d038a69 2165
Zaitsev 10:41552d038a69 2166
Zaitsev 10:41552d038a69 2167 /** \brief Clean & Invalidate D-Cache
Zaitsev 10:41552d038a69 2168
Zaitsev 10:41552d038a69 2169 The function cleans and Invalidates D-Cache
Zaitsev 10:41552d038a69 2170 */
Zaitsev 10:41552d038a69 2171 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
Zaitsev 10:41552d038a69 2172 {
Zaitsev 10:41552d038a69 2173 #if (__DCACHE_PRESENT == 1)
Zaitsev 10:41552d038a69 2174 uint32_t ccsidr, sshift, wshift, sw;
Zaitsev 10:41552d038a69 2175 uint32_t sets, ways;
Zaitsev 10:41552d038a69 2176
Zaitsev 10:41552d038a69 2177 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Zaitsev 10:41552d038a69 2178 ccsidr = SCB->CCSIDR;
Zaitsev 10:41552d038a69 2179 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Zaitsev 10:41552d038a69 2180 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Zaitsev 10:41552d038a69 2181 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Zaitsev 10:41552d038a69 2182 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Zaitsev 10:41552d038a69 2183
Zaitsev 10:41552d038a69 2184 __DSB();
Zaitsev 10:41552d038a69 2185
Zaitsev 10:41552d038a69 2186 do { // clean & invalidate D-Cache
Zaitsev 10:41552d038a69 2187 uint32_t tmpways = ways;
Zaitsev 10:41552d038a69 2188 do {
Zaitsev 10:41552d038a69 2189 sw = ((tmpways << wshift) | (sets << sshift));
Zaitsev 10:41552d038a69 2190 SCB->DCCISW = sw;
Zaitsev 10:41552d038a69 2191 } while(tmpways--);
Zaitsev 10:41552d038a69 2192 } while(sets--);
Zaitsev 10:41552d038a69 2193
Zaitsev 10:41552d038a69 2194 __DSB();
Zaitsev 10:41552d038a69 2195 __ISB();
Zaitsev 10:41552d038a69 2196 #endif
Zaitsev 10:41552d038a69 2197 }
Zaitsev 10:41552d038a69 2198
Zaitsev 10:41552d038a69 2199
Zaitsev 10:41552d038a69 2200 /**
Zaitsev 10:41552d038a69 2201 \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Zaitsev 10:41552d038a69 2202 \brief D-Cache Invalidate by address
Zaitsev 10:41552d038a69 2203 \param[in] addr address (aligned to 32-byte boundary)
Zaitsev 10:41552d038a69 2204 \param[in] dsize size of memory block (in number of bytes)
Zaitsev 10:41552d038a69 2205 */
Zaitsev 10:41552d038a69 2206 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Zaitsev 10:41552d038a69 2207 {
Zaitsev 10:41552d038a69 2208 #if (__DCACHE_PRESENT == 1)
Zaitsev 10:41552d038a69 2209 int32_t op_size = dsize;
Zaitsev 10:41552d038a69 2210 uint32_t op_addr = (uint32_t)addr;
Zaitsev 10:41552d038a69 2211 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Zaitsev 10:41552d038a69 2212
Zaitsev 10:41552d038a69 2213 __DSB();
Zaitsev 10:41552d038a69 2214
Zaitsev 10:41552d038a69 2215 while (op_size > 0) {
Zaitsev 10:41552d038a69 2216 SCB->DCIMVAC = op_addr;
Zaitsev 10:41552d038a69 2217 op_addr += linesize;
Zaitsev 10:41552d038a69 2218 op_size -= (int32_t)linesize;
Zaitsev 10:41552d038a69 2219 }
Zaitsev 10:41552d038a69 2220
Zaitsev 10:41552d038a69 2221 __DSB();
Zaitsev 10:41552d038a69 2222 __ISB();
Zaitsev 10:41552d038a69 2223 #endif
Zaitsev 10:41552d038a69 2224 }
Zaitsev 10:41552d038a69 2225
Zaitsev 10:41552d038a69 2226
Zaitsev 10:41552d038a69 2227 /**
Zaitsev 10:41552d038a69 2228 \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Zaitsev 10:41552d038a69 2229 \brief D-Cache Clean by address
Zaitsev 10:41552d038a69 2230 \param[in] addr address (aligned to 32-byte boundary)
Zaitsev 10:41552d038a69 2231 \param[in] dsize size of memory block (in number of bytes)
Zaitsev 10:41552d038a69 2232 */
Zaitsev 10:41552d038a69 2233 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
Zaitsev 10:41552d038a69 2234 {
Zaitsev 10:41552d038a69 2235 #if (__DCACHE_PRESENT == 1)
Zaitsev 10:41552d038a69 2236 int32_t op_size = dsize;
Zaitsev 10:41552d038a69 2237 uint32_t op_addr = (uint32_t) addr;
Zaitsev 10:41552d038a69 2238 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Zaitsev 10:41552d038a69 2239
Zaitsev 10:41552d038a69 2240 __DSB();
Zaitsev 10:41552d038a69 2241
Zaitsev 10:41552d038a69 2242 while (op_size > 0) {
Zaitsev 10:41552d038a69 2243 SCB->DCCMVAC = op_addr;
Zaitsev 10:41552d038a69 2244 op_addr += linesize;
Zaitsev 10:41552d038a69 2245 op_size -= (int32_t)linesize;
Zaitsev 10:41552d038a69 2246 }
Zaitsev 10:41552d038a69 2247
Zaitsev 10:41552d038a69 2248 __DSB();
Zaitsev 10:41552d038a69 2249 __ISB();
Zaitsev 10:41552d038a69 2250 #endif
Zaitsev 10:41552d038a69 2251 }
Zaitsev 10:41552d038a69 2252
Zaitsev 10:41552d038a69 2253
Zaitsev 10:41552d038a69 2254 /**
Zaitsev 10:41552d038a69 2255 \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Zaitsev 10:41552d038a69 2256 \brief D-Cache Clean and Invalidate by address
Zaitsev 10:41552d038a69 2257 \param[in] addr address (aligned to 32-byte boundary)
Zaitsev 10:41552d038a69 2258 \param[in] dsize size of memory block (in number of bytes)
Zaitsev 10:41552d038a69 2259 */
Zaitsev 10:41552d038a69 2260 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Zaitsev 10:41552d038a69 2261 {
Zaitsev 10:41552d038a69 2262 #if (__DCACHE_PRESENT == 1)
Zaitsev 10:41552d038a69 2263 int32_t op_size = dsize;
Zaitsev 10:41552d038a69 2264 uint32_t op_addr = (uint32_t) addr;
Zaitsev 10:41552d038a69 2265 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Zaitsev 10:41552d038a69 2266
Zaitsev 10:41552d038a69 2267 __DSB();
Zaitsev 10:41552d038a69 2268
Zaitsev 10:41552d038a69 2269 while (op_size > 0) {
Zaitsev 10:41552d038a69 2270 SCB->DCCIMVAC = op_addr;
Zaitsev 10:41552d038a69 2271 op_addr += linesize;
Zaitsev 10:41552d038a69 2272 op_size -= (int32_t)linesize;
Zaitsev 10:41552d038a69 2273 }
Zaitsev 10:41552d038a69 2274
Zaitsev 10:41552d038a69 2275 __DSB();
Zaitsev 10:41552d038a69 2276 __ISB();
Zaitsev 10:41552d038a69 2277 #endif
Zaitsev 10:41552d038a69 2278 }
Zaitsev 10:41552d038a69 2279
Zaitsev 10:41552d038a69 2280
Zaitsev 10:41552d038a69 2281 /*@} end of CMSIS_Core_CacheFunctions */
Zaitsev 10:41552d038a69 2282
Zaitsev 10:41552d038a69 2283
Zaitsev 10:41552d038a69 2284
Zaitsev 10:41552d038a69 2285 /* ################################## SysTick function ############################################ */
Zaitsev 10:41552d038a69 2286 /** \ingroup CMSIS_Core_FunctionInterface
Zaitsev 10:41552d038a69 2287 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Zaitsev 10:41552d038a69 2288 \brief Functions that configure the System.
Zaitsev 10:41552d038a69 2289 @{
Zaitsev 10:41552d038a69 2290 */
Zaitsev 10:41552d038a69 2291
Zaitsev 10:41552d038a69 2292 #if (__Vendor_SysTickConfig == 0)
Zaitsev 10:41552d038a69 2293
Zaitsev 10:41552d038a69 2294 /** \brief System Tick Configuration
Zaitsev 10:41552d038a69 2295
Zaitsev 10:41552d038a69 2296 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Zaitsev 10:41552d038a69 2297 Counter is in free running mode to generate periodic interrupts.
Zaitsev 10:41552d038a69 2298
Zaitsev 10:41552d038a69 2299 \param [in] ticks Number of ticks between two interrupts.
Zaitsev 10:41552d038a69 2300
Zaitsev 10:41552d038a69 2301 \return 0 Function succeeded.
Zaitsev 10:41552d038a69 2302 \return 1 Function failed.
Zaitsev 10:41552d038a69 2303
Zaitsev 10:41552d038a69 2304 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Zaitsev 10:41552d038a69 2305 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Zaitsev 10:41552d038a69 2306 must contain a vendor-specific implementation of this function.
Zaitsev 10:41552d038a69 2307
Zaitsev 10:41552d038a69 2308 */
Zaitsev 10:41552d038a69 2309 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Zaitsev 10:41552d038a69 2310 {
Zaitsev 10:41552d038a69 2311 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Zaitsev 10:41552d038a69 2312
Zaitsev 10:41552d038a69 2313 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Zaitsev 10:41552d038a69 2314 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Zaitsev 10:41552d038a69 2315 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Zaitsev 10:41552d038a69 2316 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Zaitsev 10:41552d038a69 2317 SysTick_CTRL_TICKINT_Msk |
Zaitsev 10:41552d038a69 2318 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Zaitsev 10:41552d038a69 2319 return (0UL); /* Function successful */
Zaitsev 10:41552d038a69 2320 }
Zaitsev 10:41552d038a69 2321
Zaitsev 10:41552d038a69 2322 #endif
Zaitsev 10:41552d038a69 2323
Zaitsev 10:41552d038a69 2324 /*@} end of CMSIS_Core_SysTickFunctions */
Zaitsev 10:41552d038a69 2325
Zaitsev 10:41552d038a69 2326
Zaitsev 10:41552d038a69 2327
Zaitsev 10:41552d038a69 2328 /* ##################################### Debug In/Output function ########################################### */
Zaitsev 10:41552d038a69 2329 /** \ingroup CMSIS_Core_FunctionInterface
Zaitsev 10:41552d038a69 2330 \defgroup CMSIS_core_DebugFunctions ITM Functions
Zaitsev 10:41552d038a69 2331 \brief Functions that access the ITM debug interface.
Zaitsev 10:41552d038a69 2332 @{
Zaitsev 10:41552d038a69 2333 */
Zaitsev 10:41552d038a69 2334
Zaitsev 10:41552d038a69 2335 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Zaitsev 10:41552d038a69 2336 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Zaitsev 10:41552d038a69 2337
Zaitsev 10:41552d038a69 2338
Zaitsev 10:41552d038a69 2339 /** \brief ITM Send Character
Zaitsev 10:41552d038a69 2340
Zaitsev 10:41552d038a69 2341 The function transmits a character via the ITM channel 0, and
Zaitsev 10:41552d038a69 2342 \li Just returns when no debugger is connected that has booked the output.
Zaitsev 10:41552d038a69 2343 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Zaitsev 10:41552d038a69 2344
Zaitsev 10:41552d038a69 2345 \param [in] ch Character to transmit.
Zaitsev 10:41552d038a69 2346
Zaitsev 10:41552d038a69 2347 \returns Character to transmit.
Zaitsev 10:41552d038a69 2348 */
Zaitsev 10:41552d038a69 2349 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Zaitsev 10:41552d038a69 2350 {
Zaitsev 10:41552d038a69 2351 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Zaitsev 10:41552d038a69 2352 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Zaitsev 10:41552d038a69 2353 {
Zaitsev 10:41552d038a69 2354 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Zaitsev 10:41552d038a69 2355 ITM->PORT[0].u8 = (uint8_t)ch;
Zaitsev 10:41552d038a69 2356 }
Zaitsev 10:41552d038a69 2357 return (ch);
Zaitsev 10:41552d038a69 2358 }
Zaitsev 10:41552d038a69 2359
Zaitsev 10:41552d038a69 2360
Zaitsev 10:41552d038a69 2361 /** \brief ITM Receive Character
Zaitsev 10:41552d038a69 2362
Zaitsev 10:41552d038a69 2363 The function inputs a character via the external variable \ref ITM_RxBuffer.
Zaitsev 10:41552d038a69 2364
Zaitsev 10:41552d038a69 2365 \return Received character.
Zaitsev 10:41552d038a69 2366 \return -1 No character pending.
Zaitsev 10:41552d038a69 2367 */
Zaitsev 10:41552d038a69 2368 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Zaitsev 10:41552d038a69 2369 int32_t ch = -1; /* no character available */
Zaitsev 10:41552d038a69 2370
Zaitsev 10:41552d038a69 2371 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Zaitsev 10:41552d038a69 2372 ch = ITM_RxBuffer;
Zaitsev 10:41552d038a69 2373 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Zaitsev 10:41552d038a69 2374 }
Zaitsev 10:41552d038a69 2375
Zaitsev 10:41552d038a69 2376 return (ch);
Zaitsev 10:41552d038a69 2377 }
Zaitsev 10:41552d038a69 2378
Zaitsev 10:41552d038a69 2379
Zaitsev 10:41552d038a69 2380 /** \brief ITM Check Character
Zaitsev 10:41552d038a69 2381
Zaitsev 10:41552d038a69 2382 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Zaitsev 10:41552d038a69 2383
Zaitsev 10:41552d038a69 2384 \return 0 No character available.
Zaitsev 10:41552d038a69 2385 \return 1 Character available.
Zaitsev 10:41552d038a69 2386 */
Zaitsev 10:41552d038a69 2387 __STATIC_INLINE int32_t ITM_CheckChar (void) {
Zaitsev 10:41552d038a69 2388
Zaitsev 10:41552d038a69 2389 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Zaitsev 10:41552d038a69 2390 return (0); /* no character available */
Zaitsev 10:41552d038a69 2391 } else {
Zaitsev 10:41552d038a69 2392 return (1); /* character available */
Zaitsev 10:41552d038a69 2393 }
Zaitsev 10:41552d038a69 2394 }
Zaitsev 10:41552d038a69 2395
Zaitsev 10:41552d038a69 2396 /*@} end of CMSIS_core_DebugFunctions */
Zaitsev 10:41552d038a69 2397
Zaitsev 10:41552d038a69 2398
Zaitsev 10:41552d038a69 2399
Zaitsev 10:41552d038a69 2400
Zaitsev 10:41552d038a69 2401 #ifdef __cplusplus
Zaitsev 10:41552d038a69 2402 }
Zaitsev 10:41552d038a69 2403 #endif
Zaitsev 10:41552d038a69 2404
Zaitsev 10:41552d038a69 2405 #endif /* __CORE_CM7_H_DEPENDANT */
Zaitsev 10:41552d038a69 2406
Zaitsev 10:41552d038a69 2407 #endif /* __CMSIS_GENERIC */