Mateusz Kowalik / Application

USB Serial application

Fork of USBSerial_HelloWorld by Samuel Mokrani

mbed-dev/cmsis/core_cm3.h@11:b3f2a8bdac4d, 2017-12-16 (annotated)

Committer:
Zaitsev
Date:
Sat Dec 16 10:26:48 2017 +0000
Revision:
11:b3f2a8bdac4d
Parent:
10:41552d038a69 
A copy for D.S;

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Zaitsev 10:41552d038a69 1 /**************************************************************************//**
Zaitsev 10:41552d038a69 2 * @file core_cm3.h
Zaitsev 10:41552d038a69 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Zaitsev 10:41552d038a69 4 * @version V4.10
Zaitsev 10:41552d038a69 5 * @date 18. March 2015
Zaitsev 10:41552d038a69 6 *
Zaitsev 10:41552d038a69 7 * @note
Zaitsev 10:41552d038a69 8 *
Zaitsev 10:41552d038a69 9 ******************************************************************************/
Zaitsev 10:41552d038a69 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Zaitsev 10:41552d038a69 11
Zaitsev 10:41552d038a69 12 All rights reserved.
Zaitsev 10:41552d038a69 13 Redistribution and use in source and binary forms, with or without
Zaitsev 10:41552d038a69 14 modification, are permitted provided that the following conditions are met:
Zaitsev 10:41552d038a69 15 - Redistributions of source code must retain the above copyright
Zaitsev 10:41552d038a69 16 notice, this list of conditions and the following disclaimer.
Zaitsev 10:41552d038a69 17 - Redistributions in binary form must reproduce the above copyright
Zaitsev 10:41552d038a69 18 notice, this list of conditions and the following disclaimer in the
Zaitsev 10:41552d038a69 19 documentation and/or other materials provided with the distribution.
Zaitsev 10:41552d038a69 20 - Neither the name of ARM nor the names of its contributors may be used
Zaitsev 10:41552d038a69 21 to endorse or promote products derived from this software without
Zaitsev 10:41552d038a69 22 specific prior written permission.
Zaitsev 10:41552d038a69 23 *
Zaitsev 10:41552d038a69 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Zaitsev 10:41552d038a69 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Zaitsev 10:41552d038a69 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Zaitsev 10:41552d038a69 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Zaitsev 10:41552d038a69 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Zaitsev 10:41552d038a69 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Zaitsev 10:41552d038a69 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Zaitsev 10:41552d038a69 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Zaitsev 10:41552d038a69 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Zaitsev 10:41552d038a69 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Zaitsev 10:41552d038a69 34 POSSIBILITY OF SUCH DAMAGE.
Zaitsev 10:41552d038a69 35 ---------------------------------------------------------------------------*/
Zaitsev 10:41552d038a69 36
Zaitsev 10:41552d038a69 37
Zaitsev 10:41552d038a69 38 #if defined ( __ICCARM__ )
Zaitsev 10:41552d038a69 39 #pragma system_include /* treat file as system include file for MISRA check */
Zaitsev 10:41552d038a69 40 #endif
Zaitsev 10:41552d038a69 41
Zaitsev 10:41552d038a69 42 #ifndef __CORE_CM3_H_GENERIC
Zaitsev 10:41552d038a69 43 #define __CORE_CM3_H_GENERIC
Zaitsev 10:41552d038a69 44
Zaitsev 10:41552d038a69 45 #ifdef __cplusplus
Zaitsev 10:41552d038a69 46 extern "C" {
Zaitsev 10:41552d038a69 47 #endif
Zaitsev 10:41552d038a69 48
Zaitsev 10:41552d038a69 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Zaitsev 10:41552d038a69 50 CMSIS violates the following MISRA-C:2004 rules:
Zaitsev 10:41552d038a69 51
Zaitsev 10:41552d038a69 52 \li Required Rule 8.5, object/function definition in header file.<br>
Zaitsev 10:41552d038a69 53 Function definitions in header files are used to allow 'inlining'.
Zaitsev 10:41552d038a69 54
Zaitsev 10:41552d038a69 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Zaitsev 10:41552d038a69 56 Unions are used for effective representation of core registers.
Zaitsev 10:41552d038a69 57
Zaitsev 10:41552d038a69 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Zaitsev 10:41552d038a69 59 Function-like macros are used to allow more efficient code.
Zaitsev 10:41552d038a69 60 */
Zaitsev 10:41552d038a69 61
Zaitsev 10:41552d038a69 62
Zaitsev 10:41552d038a69 63 /*******************************************************************************
Zaitsev 10:41552d038a69 64 * CMSIS definitions
Zaitsev 10:41552d038a69 65 ******************************************************************************/
Zaitsev 10:41552d038a69 66 /** \ingroup Cortex_M3
Zaitsev 10:41552d038a69 67 @{
Zaitsev 10:41552d038a69 68 */
Zaitsev 10:41552d038a69 69
Zaitsev 10:41552d038a69 70 /* CMSIS CM3 definitions */
Zaitsev 10:41552d038a69 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Zaitsev 10:41552d038a69 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Zaitsev 10:41552d038a69 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
Zaitsev 10:41552d038a69 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Zaitsev 10:41552d038a69 75
Zaitsev 10:41552d038a69 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
Zaitsev 10:41552d038a69 77
Zaitsev 10:41552d038a69 78
Zaitsev 10:41552d038a69 79 #if defined ( __CC_ARM )
Zaitsev 10:41552d038a69 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Zaitsev 10:41552d038a69 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Zaitsev 10:41552d038a69 82 #define __STATIC_INLINE static __inline
Zaitsev 10:41552d038a69 83
Zaitsev 10:41552d038a69 84 #elif defined ( __GNUC__ )
Zaitsev 10:41552d038a69 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Zaitsev 10:41552d038a69 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Zaitsev 10:41552d038a69 87 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 88
Zaitsev 10:41552d038a69 89 #elif defined ( __ICCARM__ )
Zaitsev 10:41552d038a69 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Zaitsev 10:41552d038a69 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Zaitsev 10:41552d038a69 92 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 93
Zaitsev 10:41552d038a69 94 #elif defined ( __TMS470__ )
Zaitsev 10:41552d038a69 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Zaitsev 10:41552d038a69 96 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 97
Zaitsev 10:41552d038a69 98 #elif defined ( __TASKING__ )
Zaitsev 10:41552d038a69 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Zaitsev 10:41552d038a69 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Zaitsev 10:41552d038a69 101 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 102
Zaitsev 10:41552d038a69 103 #elif defined ( __CSMC__ )
Zaitsev 10:41552d038a69 104 #define __packed
Zaitsev 10:41552d038a69 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Zaitsev 10:41552d038a69 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Zaitsev 10:41552d038a69 107 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 108
Zaitsev 10:41552d038a69 109 #endif
Zaitsev 10:41552d038a69 110
Zaitsev 10:41552d038a69 111 /** __FPU_USED indicates whether an FPU is used or not.
Zaitsev 10:41552d038a69 112 This core does not support an FPU at all
Zaitsev 10:41552d038a69 113 */
Zaitsev 10:41552d038a69 114 #define __FPU_USED 0
Zaitsev 10:41552d038a69 115
Zaitsev 10:41552d038a69 116 #if defined ( __CC_ARM )
Zaitsev 10:41552d038a69 117 #if defined __TARGET_FPU_VFP
Zaitsev 10:41552d038a69 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 119 #endif
Zaitsev 10:41552d038a69 120
Zaitsev 10:41552d038a69 121 #elif defined ( __GNUC__ )
Zaitsev 10:41552d038a69 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Zaitsev 10:41552d038a69 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 124 #endif
Zaitsev 10:41552d038a69 125
Zaitsev 10:41552d038a69 126 #elif defined ( __ICCARM__ )
Zaitsev 10:41552d038a69 127 #if defined __ARMVFP__
Zaitsev 10:41552d038a69 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 129 #endif
Zaitsev 10:41552d038a69 130
Zaitsev 10:41552d038a69 131 #elif defined ( __TMS470__ )
Zaitsev 10:41552d038a69 132 #if defined __TI__VFP_SUPPORT____
Zaitsev 10:41552d038a69 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 134 #endif
Zaitsev 10:41552d038a69 135
Zaitsev 10:41552d038a69 136 #elif defined ( __TASKING__ )
Zaitsev 10:41552d038a69 137 #if defined __FPU_VFP__
Zaitsev 10:41552d038a69 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 139 #endif
Zaitsev 10:41552d038a69 140
Zaitsev 10:41552d038a69 141 #elif defined ( __CSMC__ ) /* Cosmic */
Zaitsev 10:41552d038a69 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Zaitsev 10:41552d038a69 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 144 #endif
Zaitsev 10:41552d038a69 145 #endif
Zaitsev 10:41552d038a69 146
Zaitsev 10:41552d038a69 147 #include <stdint.h> /* standard types definitions */
Zaitsev 10:41552d038a69 148 #include <core_cmInstr.h> /* Core Instruction Access */
Zaitsev 10:41552d038a69 149 #include <core_cmFunc.h> /* Core Function Access */
Zaitsev 10:41552d038a69 150
Zaitsev 10:41552d038a69 151 #ifdef __cplusplus
Zaitsev 10:41552d038a69 152 }
Zaitsev 10:41552d038a69 153 #endif
Zaitsev 10:41552d038a69 154
Zaitsev 10:41552d038a69 155 #endif /* __CORE_CM3_H_GENERIC */
Zaitsev 10:41552d038a69 156
Zaitsev 10:41552d038a69 157 #ifndef __CMSIS_GENERIC
Zaitsev 10:41552d038a69 158
Zaitsev 10:41552d038a69 159 #ifndef __CORE_CM3_H_DEPENDANT
Zaitsev 10:41552d038a69 160 #define __CORE_CM3_H_DEPENDANT
Zaitsev 10:41552d038a69 161
Zaitsev 10:41552d038a69 162 #ifdef __cplusplus
Zaitsev 10:41552d038a69 163 extern "C" {
Zaitsev 10:41552d038a69 164 #endif
Zaitsev 10:41552d038a69 165
Zaitsev 10:41552d038a69 166 /* check device defines and use defaults */
Zaitsev 10:41552d038a69 167 #if defined __CHECK_DEVICE_DEFINES
Zaitsev 10:41552d038a69 168 #ifndef __CM3_REV
Zaitsev 10:41552d038a69 169 #define __CM3_REV 0x0200
Zaitsev 10:41552d038a69 170 #warning "__CM3_REV not defined in device header file; using default!"
Zaitsev 10:41552d038a69 171 #endif
Zaitsev 10:41552d038a69 172
Zaitsev 10:41552d038a69 173 #ifndef __MPU_PRESENT
Zaitsev 10:41552d038a69 174 #define __MPU_PRESENT 0
Zaitsev 10:41552d038a69 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Zaitsev 10:41552d038a69 176 #endif
Zaitsev 10:41552d038a69 177
Zaitsev 10:41552d038a69 178 #ifndef __NVIC_PRIO_BITS
Zaitsev 10:41552d038a69 179 #define __NVIC_PRIO_BITS 4
Zaitsev 10:41552d038a69 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Zaitsev 10:41552d038a69 181 #endif
Zaitsev 10:41552d038a69 182
Zaitsev 10:41552d038a69 183 #ifndef __Vendor_SysTickConfig
Zaitsev 10:41552d038a69 184 #define __Vendor_SysTickConfig 0
Zaitsev 10:41552d038a69 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Zaitsev 10:41552d038a69 186 #endif
Zaitsev 10:41552d038a69 187 #endif
Zaitsev 10:41552d038a69 188
Zaitsev 10:41552d038a69 189 /* IO definitions (access restrictions to peripheral registers) */
Zaitsev 10:41552d038a69 190 /**
Zaitsev 10:41552d038a69 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
Zaitsev 10:41552d038a69 192
Zaitsev 10:41552d038a69 193 <strong>IO Type Qualifiers</strong> are used
Zaitsev 10:41552d038a69 194 \li to specify the access to peripheral variables.
Zaitsev 10:41552d038a69 195 \li for automatic generation of peripheral register debug information.
Zaitsev 10:41552d038a69 196 */
Zaitsev 10:41552d038a69 197 #ifdef __cplusplus
Zaitsev 10:41552d038a69 198 #define __I volatile /*!< Defines 'read only' permissions */
Zaitsev 10:41552d038a69 199 #else
Zaitsev 10:41552d038a69 200 #define __I volatile const /*!< Defines 'read only' permissions */
Zaitsev 10:41552d038a69 201 #endif
Zaitsev 10:41552d038a69 202 #define __O volatile /*!< Defines 'write only' permissions */
Zaitsev 10:41552d038a69 203 #define __IO volatile /*!< Defines 'read / write' permissions */
Zaitsev 10:41552d038a69 204
Zaitsev 10:41552d038a69 205 #ifdef __cplusplus
Zaitsev 10:41552d038a69 206 #define __IM volatile /*!< Defines 'read only' permissions */
Zaitsev 10:41552d038a69 207 #else
Zaitsev 10:41552d038a69 208 #define __IM volatile const /*!< Defines 'read only' permissions */
Zaitsev 10:41552d038a69 209 #endif
Zaitsev 10:41552d038a69 210 #define __OM volatile /*!< Defines 'write only' permissions */
Zaitsev 10:41552d038a69 211 #define __IOM volatile /*!< Defines 'read / write' permissions */
Zaitsev 10:41552d038a69 212
Zaitsev 10:41552d038a69 213 /*@} end of group Cortex_M3 */
Zaitsev 10:41552d038a69 214
Zaitsev 10:41552d038a69 215
Zaitsev 10:41552d038a69 216
Zaitsev 10:41552d038a69 217 /*******************************************************************************
Zaitsev 10:41552d038a69 218 * Register Abstraction
Zaitsev 10:41552d038a69 219 Core Register contain:
Zaitsev 10:41552d038a69 220 - Core Register
Zaitsev 10:41552d038a69 221 - Core NVIC Register
Zaitsev 10:41552d038a69 222 - Core SCB Register
Zaitsev 10:41552d038a69 223 - Core SysTick Register
Zaitsev 10:41552d038a69 224 - Core Debug Register
Zaitsev 10:41552d038a69 225 - Core MPU Register
Zaitsev 10:41552d038a69 226 ******************************************************************************/
Zaitsev 10:41552d038a69 227 /** \defgroup CMSIS_core_register Defines and Type Definitions
Zaitsev 10:41552d038a69 228 \brief Type definitions and defines for Cortex-M processor based devices.
Zaitsev 10:41552d038a69 229 */
Zaitsev 10:41552d038a69 230
Zaitsev 10:41552d038a69 231 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 232 \defgroup CMSIS_CORE Status and Control Registers
Zaitsev 10:41552d038a69 233 \brief Core Register type definitions.
Zaitsev 10:41552d038a69 234 @{
Zaitsev 10:41552d038a69 235 */
Zaitsev 10:41552d038a69 236
Zaitsev 10:41552d038a69 237 /** \brief Union type to access the Application Program Status Register (APSR).
Zaitsev 10:41552d038a69 238 */
Zaitsev 10:41552d038a69 239 typedef union
Zaitsev 10:41552d038a69 240 {
Zaitsev 10:41552d038a69 241 struct
Zaitsev 10:41552d038a69 242 {
Zaitsev 10:41552d038a69 243 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Zaitsev 10:41552d038a69 244 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Zaitsev 10:41552d038a69 245 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Zaitsev 10:41552d038a69 246 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Zaitsev 10:41552d038a69 247 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Zaitsev 10:41552d038a69 248 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Zaitsev 10:41552d038a69 249 } b; /*!< Structure used for bit access */
Zaitsev 10:41552d038a69 250 uint32_t w; /*!< Type used for word access */
Zaitsev 10:41552d038a69 251 } APSR_Type;
Zaitsev 10:41552d038a69 252
Zaitsev 10:41552d038a69 253 /* APSR Register Definitions */
Zaitsev 10:41552d038a69 254 #define APSR_N_Pos 31 /*!< APSR: N Position */
Zaitsev 10:41552d038a69 255 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Zaitsev 10:41552d038a69 256
Zaitsev 10:41552d038a69 257 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Zaitsev 10:41552d038a69 258 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Zaitsev 10:41552d038a69 259
Zaitsev 10:41552d038a69 260 #define APSR_C_Pos 29 /*!< APSR: C Position */
Zaitsev 10:41552d038a69 261 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Zaitsev 10:41552d038a69 262
Zaitsev 10:41552d038a69 263 #define APSR_V_Pos 28 /*!< APSR: V Position */
Zaitsev 10:41552d038a69 264 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Zaitsev 10:41552d038a69 265
Zaitsev 10:41552d038a69 266 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
Zaitsev 10:41552d038a69 267 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Zaitsev 10:41552d038a69 268
Zaitsev 10:41552d038a69 269
Zaitsev 10:41552d038a69 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Zaitsev 10:41552d038a69 271 */
Zaitsev 10:41552d038a69 272 typedef union
Zaitsev 10:41552d038a69 273 {
Zaitsev 10:41552d038a69 274 struct
Zaitsev 10:41552d038a69 275 {
Zaitsev 10:41552d038a69 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Zaitsev 10:41552d038a69 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Zaitsev 10:41552d038a69 278 } b; /*!< Structure used for bit access */
Zaitsev 10:41552d038a69 279 uint32_t w; /*!< Type used for word access */
Zaitsev 10:41552d038a69 280 } IPSR_Type;
Zaitsev 10:41552d038a69 281
Zaitsev 10:41552d038a69 282 /* IPSR Register Definitions */
Zaitsev 10:41552d038a69 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Zaitsev 10:41552d038a69 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Zaitsev 10:41552d038a69 285
Zaitsev 10:41552d038a69 286
Zaitsev 10:41552d038a69 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Zaitsev 10:41552d038a69 288 */
Zaitsev 10:41552d038a69 289 typedef union
Zaitsev 10:41552d038a69 290 {
Zaitsev 10:41552d038a69 291 struct
Zaitsev 10:41552d038a69 292 {
Zaitsev 10:41552d038a69 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Zaitsev 10:41552d038a69 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Zaitsev 10:41552d038a69 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Zaitsev 10:41552d038a69 296 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Zaitsev 10:41552d038a69 297 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Zaitsev 10:41552d038a69 298 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Zaitsev 10:41552d038a69 299 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Zaitsev 10:41552d038a69 300 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Zaitsev 10:41552d038a69 301 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Zaitsev 10:41552d038a69 302 } b; /*!< Structure used for bit access */
Zaitsev 10:41552d038a69 303 uint32_t w; /*!< Type used for word access */
Zaitsev 10:41552d038a69 304 } xPSR_Type;
Zaitsev 10:41552d038a69 305
Zaitsev 10:41552d038a69 306 /* xPSR Register Definitions */
Zaitsev 10:41552d038a69 307 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Zaitsev 10:41552d038a69 308 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Zaitsev 10:41552d038a69 309
Zaitsev 10:41552d038a69 310 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Zaitsev 10:41552d038a69 311 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Zaitsev 10:41552d038a69 312
Zaitsev 10:41552d038a69 313 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Zaitsev 10:41552d038a69 314 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Zaitsev 10:41552d038a69 315
Zaitsev 10:41552d038a69 316 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Zaitsev 10:41552d038a69 317 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Zaitsev 10:41552d038a69 318
Zaitsev 10:41552d038a69 319 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
Zaitsev 10:41552d038a69 320 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Zaitsev 10:41552d038a69 321
Zaitsev 10:41552d038a69 322 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
Zaitsev 10:41552d038a69 323 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Zaitsev 10:41552d038a69 324
Zaitsev 10:41552d038a69 325 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Zaitsev 10:41552d038a69 326 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Zaitsev 10:41552d038a69 327
Zaitsev 10:41552d038a69 328 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Zaitsev 10:41552d038a69 329 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Zaitsev 10:41552d038a69 330
Zaitsev 10:41552d038a69 331
Zaitsev 10:41552d038a69 332 /** \brief Union type to access the Control Registers (CONTROL).
Zaitsev 10:41552d038a69 333 */
Zaitsev 10:41552d038a69 334 typedef union
Zaitsev 10:41552d038a69 335 {
Zaitsev 10:41552d038a69 336 struct
Zaitsev 10:41552d038a69 337 {
Zaitsev 10:41552d038a69 338 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Zaitsev 10:41552d038a69 339 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Zaitsev 10:41552d038a69 340 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Zaitsev 10:41552d038a69 341 } b; /*!< Structure used for bit access */
Zaitsev 10:41552d038a69 342 uint32_t w; /*!< Type used for word access */
Zaitsev 10:41552d038a69 343 } CONTROL_Type;
Zaitsev 10:41552d038a69 344
Zaitsev 10:41552d038a69 345 /* CONTROL Register Definitions */
Zaitsev 10:41552d038a69 346 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Zaitsev 10:41552d038a69 347 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Zaitsev 10:41552d038a69 348
Zaitsev 10:41552d038a69 349 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Zaitsev 10:41552d038a69 350 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Zaitsev 10:41552d038a69 351
Zaitsev 10:41552d038a69 352 /*@} end of group CMSIS_CORE */
Zaitsev 10:41552d038a69 353
Zaitsev 10:41552d038a69 354
Zaitsev 10:41552d038a69 355 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 356 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Zaitsev 10:41552d038a69 357 \brief Type definitions for the NVIC Registers
Zaitsev 10:41552d038a69 358 @{
Zaitsev 10:41552d038a69 359 */
Zaitsev 10:41552d038a69 360
Zaitsev 10:41552d038a69 361 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Zaitsev 10:41552d038a69 362 */
Zaitsev 10:41552d038a69 363 typedef struct
Zaitsev 10:41552d038a69 364 {
Zaitsev 10:41552d038a69 365 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Zaitsev 10:41552d038a69 366 uint32_t RESERVED0[24];
Zaitsev 10:41552d038a69 367 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Zaitsev 10:41552d038a69 368 uint32_t RSERVED1[24];
Zaitsev 10:41552d038a69 369 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Zaitsev 10:41552d038a69 370 uint32_t RESERVED2[24];
Zaitsev 10:41552d038a69 371 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Zaitsev 10:41552d038a69 372 uint32_t RESERVED3[24];
Zaitsev 10:41552d038a69 373 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Zaitsev 10:41552d038a69 374 uint32_t RESERVED4[56];
Zaitsev 10:41552d038a69 375 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Zaitsev 10:41552d038a69 376 uint32_t RESERVED5[644];
Zaitsev 10:41552d038a69 377 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Zaitsev 10:41552d038a69 378 } NVIC_Type;
Zaitsev 10:41552d038a69 379
Zaitsev 10:41552d038a69 380 /* Software Triggered Interrupt Register Definitions */
Zaitsev 10:41552d038a69 381 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Zaitsev 10:41552d038a69 382 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
Zaitsev 10:41552d038a69 383
Zaitsev 10:41552d038a69 384 /*@} end of group CMSIS_NVIC */
Zaitsev 10:41552d038a69 385
Zaitsev 10:41552d038a69 386
Zaitsev 10:41552d038a69 387 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 388 \defgroup CMSIS_SCB System Control Block (SCB)
Zaitsev 10:41552d038a69 389 \brief Type definitions for the System Control Block Registers
Zaitsev 10:41552d038a69 390 @{
Zaitsev 10:41552d038a69 391 */
Zaitsev 10:41552d038a69 392
Zaitsev 10:41552d038a69 393 /** \brief Structure type to access the System Control Block (SCB).
Zaitsev 10:41552d038a69 394 */
Zaitsev 10:41552d038a69 395 typedef struct
Zaitsev 10:41552d038a69 396 {
Zaitsev 10:41552d038a69 397 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Zaitsev 10:41552d038a69 398 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Zaitsev 10:41552d038a69 399 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Zaitsev 10:41552d038a69 400 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Zaitsev 10:41552d038a69 401 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Zaitsev 10:41552d038a69 402 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Zaitsev 10:41552d038a69 403 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Zaitsev 10:41552d038a69 404 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Zaitsev 10:41552d038a69 405 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Zaitsev 10:41552d038a69 406 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Zaitsev 10:41552d038a69 407 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Zaitsev 10:41552d038a69 408 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Zaitsev 10:41552d038a69 409 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Zaitsev 10:41552d038a69 410 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Zaitsev 10:41552d038a69 411 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Zaitsev 10:41552d038a69 412 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Zaitsev 10:41552d038a69 413 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Zaitsev 10:41552d038a69 414 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Zaitsev 10:41552d038a69 415 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Zaitsev 10:41552d038a69 416 uint32_t RESERVED0[5];
Zaitsev 10:41552d038a69 417 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Zaitsev 10:41552d038a69 418 } SCB_Type;
Zaitsev 10:41552d038a69 419
Zaitsev 10:41552d038a69 420 /* SCB CPUID Register Definitions */
Zaitsev 10:41552d038a69 421 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Zaitsev 10:41552d038a69 422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Zaitsev 10:41552d038a69 423
Zaitsev 10:41552d038a69 424 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Zaitsev 10:41552d038a69 425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Zaitsev 10:41552d038a69 426
Zaitsev 10:41552d038a69 427 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Zaitsev 10:41552d038a69 428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Zaitsev 10:41552d038a69 429
Zaitsev 10:41552d038a69 430 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Zaitsev 10:41552d038a69 431 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Zaitsev 10:41552d038a69 432
Zaitsev 10:41552d038a69 433 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Zaitsev 10:41552d038a69 434 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Zaitsev 10:41552d038a69 435
Zaitsev 10:41552d038a69 436 /* SCB Interrupt Control State Register Definitions */
Zaitsev 10:41552d038a69 437 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Zaitsev 10:41552d038a69 438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Zaitsev 10:41552d038a69 439
Zaitsev 10:41552d038a69 440 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Zaitsev 10:41552d038a69 441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Zaitsev 10:41552d038a69 442
Zaitsev 10:41552d038a69 443 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Zaitsev 10:41552d038a69 444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Zaitsev 10:41552d038a69 445
Zaitsev 10:41552d038a69 446 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Zaitsev 10:41552d038a69 447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Zaitsev 10:41552d038a69 448
Zaitsev 10:41552d038a69 449 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Zaitsev 10:41552d038a69 450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Zaitsev 10:41552d038a69 451
Zaitsev 10:41552d038a69 452 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Zaitsev 10:41552d038a69 453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Zaitsev 10:41552d038a69 454
Zaitsev 10:41552d038a69 455 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Zaitsev 10:41552d038a69 456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Zaitsev 10:41552d038a69 457
Zaitsev 10:41552d038a69 458 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Zaitsev 10:41552d038a69 459 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Zaitsev 10:41552d038a69 460
Zaitsev 10:41552d038a69 461 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
Zaitsev 10:41552d038a69 462 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Zaitsev 10:41552d038a69 463
Zaitsev 10:41552d038a69 464 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Zaitsev 10:41552d038a69 465 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Zaitsev 10:41552d038a69 466
Zaitsev 10:41552d038a69 467 /* SCB Vector Table Offset Register Definitions */
Zaitsev 10:41552d038a69 468 #if (__CM3_REV < 0x0201) /* core r2p1 */
Zaitsev 10:41552d038a69 469 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
Zaitsev 10:41552d038a69 470 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
Zaitsev 10:41552d038a69 471
Zaitsev 10:41552d038a69 472 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Zaitsev 10:41552d038a69 473 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Zaitsev 10:41552d038a69 474 #else
Zaitsev 10:41552d038a69 475 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Zaitsev 10:41552d038a69 476 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Zaitsev 10:41552d038a69 477 #endif
Zaitsev 10:41552d038a69 478
Zaitsev 10:41552d038a69 479 /* SCB Application Interrupt and Reset Control Register Definitions */
Zaitsev 10:41552d038a69 480 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Zaitsev 10:41552d038a69 481 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Zaitsev 10:41552d038a69 482
Zaitsev 10:41552d038a69 483 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Zaitsev 10:41552d038a69 484 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Zaitsev 10:41552d038a69 485
Zaitsev 10:41552d038a69 486 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Zaitsev 10:41552d038a69 487 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Zaitsev 10:41552d038a69 488
Zaitsev 10:41552d038a69 489 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
Zaitsev 10:41552d038a69 490 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Zaitsev 10:41552d038a69 491
Zaitsev 10:41552d038a69 492 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Zaitsev 10:41552d038a69 493 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Zaitsev 10:41552d038a69 494
Zaitsev 10:41552d038a69 495 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Zaitsev 10:41552d038a69 496 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Zaitsev 10:41552d038a69 497
Zaitsev 10:41552d038a69 498 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Zaitsev 10:41552d038a69 499 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
Zaitsev 10:41552d038a69 500
Zaitsev 10:41552d038a69 501 /* SCB System Control Register Definitions */
Zaitsev 10:41552d038a69 502 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Zaitsev 10:41552d038a69 503 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Zaitsev 10:41552d038a69 504
Zaitsev 10:41552d038a69 505 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Zaitsev 10:41552d038a69 506 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Zaitsev 10:41552d038a69 507
Zaitsev 10:41552d038a69 508 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Zaitsev 10:41552d038a69 509 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Zaitsev 10:41552d038a69 510
Zaitsev 10:41552d038a69 511 /* SCB Configuration Control Register Definitions */
Zaitsev 10:41552d038a69 512 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Zaitsev 10:41552d038a69 513 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Zaitsev 10:41552d038a69 514
Zaitsev 10:41552d038a69 515 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
Zaitsev 10:41552d038a69 516 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Zaitsev 10:41552d038a69 517
Zaitsev 10:41552d038a69 518 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
Zaitsev 10:41552d038a69 519 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Zaitsev 10:41552d038a69 520
Zaitsev 10:41552d038a69 521 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Zaitsev 10:41552d038a69 522 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Zaitsev 10:41552d038a69 523
Zaitsev 10:41552d038a69 524 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
Zaitsev 10:41552d038a69 525 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Zaitsev 10:41552d038a69 526
Zaitsev 10:41552d038a69 527 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Zaitsev 10:41552d038a69 528 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
Zaitsev 10:41552d038a69 529
Zaitsev 10:41552d038a69 530 /* SCB System Handler Control and State Register Definitions */
Zaitsev 10:41552d038a69 531 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
Zaitsev 10:41552d038a69 532 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Zaitsev 10:41552d038a69 533
Zaitsev 10:41552d038a69 534 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
Zaitsev 10:41552d038a69 535 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Zaitsev 10:41552d038a69 536
Zaitsev 10:41552d038a69 537 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
Zaitsev 10:41552d038a69 538 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Zaitsev 10:41552d038a69 539
Zaitsev 10:41552d038a69 540 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Zaitsev 10:41552d038a69 541 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Zaitsev 10:41552d038a69 542
Zaitsev 10:41552d038a69 543 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
Zaitsev 10:41552d038a69 544 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Zaitsev 10:41552d038a69 545
Zaitsev 10:41552d038a69 546 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
Zaitsev 10:41552d038a69 547 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Zaitsev 10:41552d038a69 548
Zaitsev 10:41552d038a69 549 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
Zaitsev 10:41552d038a69 550 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Zaitsev 10:41552d038a69 551
Zaitsev 10:41552d038a69 552 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
Zaitsev 10:41552d038a69 553 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Zaitsev 10:41552d038a69 554
Zaitsev 10:41552d038a69 555 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
Zaitsev 10:41552d038a69 556 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Zaitsev 10:41552d038a69 557
Zaitsev 10:41552d038a69 558 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
Zaitsev 10:41552d038a69 559 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Zaitsev 10:41552d038a69 560
Zaitsev 10:41552d038a69 561 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
Zaitsev 10:41552d038a69 562 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Zaitsev 10:41552d038a69 563
Zaitsev 10:41552d038a69 564 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
Zaitsev 10:41552d038a69 565 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Zaitsev 10:41552d038a69 566
Zaitsev 10:41552d038a69 567 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
Zaitsev 10:41552d038a69 568 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Zaitsev 10:41552d038a69 569
Zaitsev 10:41552d038a69 570 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Zaitsev 10:41552d038a69 571 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
Zaitsev 10:41552d038a69 572
Zaitsev 10:41552d038a69 573 /* SCB Configurable Fault Status Registers Definitions */
Zaitsev 10:41552d038a69 574 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
Zaitsev 10:41552d038a69 575 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Zaitsev 10:41552d038a69 576
Zaitsev 10:41552d038a69 577 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
Zaitsev 10:41552d038a69 578 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Zaitsev 10:41552d038a69 579
Zaitsev 10:41552d038a69 580 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Zaitsev 10:41552d038a69 581 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Zaitsev 10:41552d038a69 582
Zaitsev 10:41552d038a69 583 /* SCB Hard Fault Status Registers Definitions */
Zaitsev 10:41552d038a69 584 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
Zaitsev 10:41552d038a69 585 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Zaitsev 10:41552d038a69 586
Zaitsev 10:41552d038a69 587 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
Zaitsev 10:41552d038a69 588 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Zaitsev 10:41552d038a69 589
Zaitsev 10:41552d038a69 590 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
Zaitsev 10:41552d038a69 591 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Zaitsev 10:41552d038a69 592
Zaitsev 10:41552d038a69 593 /* SCB Debug Fault Status Register Definitions */
Zaitsev 10:41552d038a69 594 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
Zaitsev 10:41552d038a69 595 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Zaitsev 10:41552d038a69 596
Zaitsev 10:41552d038a69 597 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
Zaitsev 10:41552d038a69 598 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Zaitsev 10:41552d038a69 599
Zaitsev 10:41552d038a69 600 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
Zaitsev 10:41552d038a69 601 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Zaitsev 10:41552d038a69 602
Zaitsev 10:41552d038a69 603 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
Zaitsev 10:41552d038a69 604 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Zaitsev 10:41552d038a69 605
Zaitsev 10:41552d038a69 606 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Zaitsev 10:41552d038a69 607 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
Zaitsev 10:41552d038a69 608
Zaitsev 10:41552d038a69 609 /*@} end of group CMSIS_SCB */
Zaitsev 10:41552d038a69 610
Zaitsev 10:41552d038a69 611
Zaitsev 10:41552d038a69 612 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 613 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Zaitsev 10:41552d038a69 614 \brief Type definitions for the System Control and ID Register not in the SCB
Zaitsev 10:41552d038a69 615 @{
Zaitsev 10:41552d038a69 616 */
Zaitsev 10:41552d038a69 617
Zaitsev 10:41552d038a69 618 /** \brief Structure type to access the System Control and ID Register not in the SCB.
Zaitsev 10:41552d038a69 619 */
Zaitsev 10:41552d038a69 620 typedef struct
Zaitsev 10:41552d038a69 621 {
Zaitsev 10:41552d038a69 622 uint32_t RESERVED0[1];
Zaitsev 10:41552d038a69 623 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Zaitsev 10:41552d038a69 624 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
Zaitsev 10:41552d038a69 625 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Zaitsev 10:41552d038a69 626 #else
Zaitsev 10:41552d038a69 627 uint32_t RESERVED1[1];
Zaitsev 10:41552d038a69 628 #endif
Zaitsev 10:41552d038a69 629 } SCnSCB_Type;
Zaitsev 10:41552d038a69 630
Zaitsev 10:41552d038a69 631 /* Interrupt Controller Type Register Definitions */
Zaitsev 10:41552d038a69 632 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Zaitsev 10:41552d038a69 633 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
Zaitsev 10:41552d038a69 634
Zaitsev 10:41552d038a69 635 /* Auxiliary Control Register Definitions */
Zaitsev 10:41552d038a69 636
Zaitsev 10:41552d038a69 637 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
Zaitsev 10:41552d038a69 638 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
Zaitsev 10:41552d038a69 639
Zaitsev 10:41552d038a69 640 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
Zaitsev 10:41552d038a69 641 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
Zaitsev 10:41552d038a69 642
Zaitsev 10:41552d038a69 643 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Zaitsev 10:41552d038a69 644 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Zaitsev 10:41552d038a69 645
Zaitsev 10:41552d038a69 646 /*@} end of group CMSIS_SCnotSCB */
Zaitsev 10:41552d038a69 647
Zaitsev 10:41552d038a69 648
Zaitsev 10:41552d038a69 649 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 650 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Zaitsev 10:41552d038a69 651 \brief Type definitions for the System Timer Registers.
Zaitsev 10:41552d038a69 652 @{
Zaitsev 10:41552d038a69 653 */
Zaitsev 10:41552d038a69 654
Zaitsev 10:41552d038a69 655 /** \brief Structure type to access the System Timer (SysTick).
Zaitsev 10:41552d038a69 656 */
Zaitsev 10:41552d038a69 657 typedef struct
Zaitsev 10:41552d038a69 658 {
Zaitsev 10:41552d038a69 659 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Zaitsev 10:41552d038a69 660 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Zaitsev 10:41552d038a69 661 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Zaitsev 10:41552d038a69 662 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Zaitsev 10:41552d038a69 663 } SysTick_Type;
Zaitsev 10:41552d038a69 664
Zaitsev 10:41552d038a69 665 /* SysTick Control / Status Register Definitions */
Zaitsev 10:41552d038a69 666 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Zaitsev 10:41552d038a69 667 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Zaitsev 10:41552d038a69 668
Zaitsev 10:41552d038a69 669 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Zaitsev 10:41552d038a69 670 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Zaitsev 10:41552d038a69 671
Zaitsev 10:41552d038a69 672 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Zaitsev 10:41552d038a69 673 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Zaitsev 10:41552d038a69 674
Zaitsev 10:41552d038a69 675 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Zaitsev 10:41552d038a69 676 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Zaitsev 10:41552d038a69 677
Zaitsev 10:41552d038a69 678 /* SysTick Reload Register Definitions */
Zaitsev 10:41552d038a69 679 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Zaitsev 10:41552d038a69 680 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Zaitsev 10:41552d038a69 681
Zaitsev 10:41552d038a69 682 /* SysTick Current Register Definitions */
Zaitsev 10:41552d038a69 683 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Zaitsev 10:41552d038a69 684 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Zaitsev 10:41552d038a69 685
Zaitsev 10:41552d038a69 686 /* SysTick Calibration Register Definitions */
Zaitsev 10:41552d038a69 687 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Zaitsev 10:41552d038a69 688 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Zaitsev 10:41552d038a69 689
Zaitsev 10:41552d038a69 690 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Zaitsev 10:41552d038a69 691 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Zaitsev 10:41552d038a69 692
Zaitsev 10:41552d038a69 693 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Zaitsev 10:41552d038a69 694 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Zaitsev 10:41552d038a69 695
Zaitsev 10:41552d038a69 696 /*@} end of group CMSIS_SysTick */
Zaitsev 10:41552d038a69 697
Zaitsev 10:41552d038a69 698
Zaitsev 10:41552d038a69 699 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 700 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Zaitsev 10:41552d038a69 701 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Zaitsev 10:41552d038a69 702 @{
Zaitsev 10:41552d038a69 703 */
Zaitsev 10:41552d038a69 704
Zaitsev 10:41552d038a69 705 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Zaitsev 10:41552d038a69 706 */
Zaitsev 10:41552d038a69 707 typedef struct
Zaitsev 10:41552d038a69 708 {
Zaitsev 10:41552d038a69 709 __O union
Zaitsev 10:41552d038a69 710 {
Zaitsev 10:41552d038a69 711 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Zaitsev 10:41552d038a69 712 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Zaitsev 10:41552d038a69 713 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Zaitsev 10:41552d038a69 714 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Zaitsev 10:41552d038a69 715 uint32_t RESERVED0[864];
Zaitsev 10:41552d038a69 716 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Zaitsev 10:41552d038a69 717 uint32_t RESERVED1[15];
Zaitsev 10:41552d038a69 718 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Zaitsev 10:41552d038a69 719 uint32_t RESERVED2[15];
Zaitsev 10:41552d038a69 720 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Zaitsev 10:41552d038a69 721 uint32_t RESERVED3[29];
Zaitsev 10:41552d038a69 722 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Zaitsev 10:41552d038a69 723 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Zaitsev 10:41552d038a69 724 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Zaitsev 10:41552d038a69 725 uint32_t RESERVED4[43];
Zaitsev 10:41552d038a69 726 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Zaitsev 10:41552d038a69 727 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Zaitsev 10:41552d038a69 728 uint32_t RESERVED5[6];
Zaitsev 10:41552d038a69 729 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Zaitsev 10:41552d038a69 730 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Zaitsev 10:41552d038a69 731 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Zaitsev 10:41552d038a69 732 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Zaitsev 10:41552d038a69 733 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Zaitsev 10:41552d038a69 734 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Zaitsev 10:41552d038a69 735 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Zaitsev 10:41552d038a69 736 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Zaitsev 10:41552d038a69 737 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Zaitsev 10:41552d038a69 738 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Zaitsev 10:41552d038a69 739 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Zaitsev 10:41552d038a69 740 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Zaitsev 10:41552d038a69 741 } ITM_Type;
Zaitsev 10:41552d038a69 742
Zaitsev 10:41552d038a69 743 /* ITM Trace Privilege Register Definitions */
Zaitsev 10:41552d038a69 744 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Zaitsev 10:41552d038a69 745 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
Zaitsev 10:41552d038a69 746
Zaitsev 10:41552d038a69 747 /* ITM Trace Control Register Definitions */
Zaitsev 10:41552d038a69 748 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
Zaitsev 10:41552d038a69 749 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Zaitsev 10:41552d038a69 750
Zaitsev 10:41552d038a69 751 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
Zaitsev 10:41552d038a69 752 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
Zaitsev 10:41552d038a69 753
Zaitsev 10:41552d038a69 754 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
Zaitsev 10:41552d038a69 755 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Zaitsev 10:41552d038a69 756
Zaitsev 10:41552d038a69 757 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
Zaitsev 10:41552d038a69 758 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Zaitsev 10:41552d038a69 759
Zaitsev 10:41552d038a69 760 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
Zaitsev 10:41552d038a69 761 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Zaitsev 10:41552d038a69 762
Zaitsev 10:41552d038a69 763 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
Zaitsev 10:41552d038a69 764 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Zaitsev 10:41552d038a69 765
Zaitsev 10:41552d038a69 766 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
Zaitsev 10:41552d038a69 767 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Zaitsev 10:41552d038a69 768
Zaitsev 10:41552d038a69 769 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
Zaitsev 10:41552d038a69 770 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Zaitsev 10:41552d038a69 771
Zaitsev 10:41552d038a69 772 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Zaitsev 10:41552d038a69 773 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
Zaitsev 10:41552d038a69 774
Zaitsev 10:41552d038a69 775 /* ITM Integration Write Register Definitions */
Zaitsev 10:41552d038a69 776 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Zaitsev 10:41552d038a69 777 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
Zaitsev 10:41552d038a69 778
Zaitsev 10:41552d038a69 779 /* ITM Integration Read Register Definitions */
Zaitsev 10:41552d038a69 780 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Zaitsev 10:41552d038a69 781 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
Zaitsev 10:41552d038a69 782
Zaitsev 10:41552d038a69 783 /* ITM Integration Mode Control Register Definitions */
Zaitsev 10:41552d038a69 784 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Zaitsev 10:41552d038a69 785 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
Zaitsev 10:41552d038a69 786
Zaitsev 10:41552d038a69 787 /* ITM Lock Status Register Definitions */
Zaitsev 10:41552d038a69 788 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
Zaitsev 10:41552d038a69 789 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Zaitsev 10:41552d038a69 790
Zaitsev 10:41552d038a69 791 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
Zaitsev 10:41552d038a69 792 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Zaitsev 10:41552d038a69 793
Zaitsev 10:41552d038a69 794 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Zaitsev 10:41552d038a69 795 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
Zaitsev 10:41552d038a69 796
Zaitsev 10:41552d038a69 797 /*@}*/ /* end of group CMSIS_ITM */
Zaitsev 10:41552d038a69 798
Zaitsev 10:41552d038a69 799
Zaitsev 10:41552d038a69 800 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 801 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Zaitsev 10:41552d038a69 802 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Zaitsev 10:41552d038a69 803 @{
Zaitsev 10:41552d038a69 804 */
Zaitsev 10:41552d038a69 805
Zaitsev 10:41552d038a69 806 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Zaitsev 10:41552d038a69 807 */
Zaitsev 10:41552d038a69 808 typedef struct
Zaitsev 10:41552d038a69 809 {
Zaitsev 10:41552d038a69 810 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Zaitsev 10:41552d038a69 811 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Zaitsev 10:41552d038a69 812 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Zaitsev 10:41552d038a69 813 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Zaitsev 10:41552d038a69 814 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Zaitsev 10:41552d038a69 815 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Zaitsev 10:41552d038a69 816 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Zaitsev 10:41552d038a69 817 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Zaitsev 10:41552d038a69 818 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Zaitsev 10:41552d038a69 819 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
Zaitsev 10:41552d038a69 820 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Zaitsev 10:41552d038a69 821 uint32_t RESERVED0[1];
Zaitsev 10:41552d038a69 822 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Zaitsev 10:41552d038a69 823 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
Zaitsev 10:41552d038a69 824 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Zaitsev 10:41552d038a69 825 uint32_t RESERVED1[1];
Zaitsev 10:41552d038a69 826 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Zaitsev 10:41552d038a69 827 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
Zaitsev 10:41552d038a69 828 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Zaitsev 10:41552d038a69 829 uint32_t RESERVED2[1];
Zaitsev 10:41552d038a69 830 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Zaitsev 10:41552d038a69 831 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
Zaitsev 10:41552d038a69 832 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Zaitsev 10:41552d038a69 833 } DWT_Type;
Zaitsev 10:41552d038a69 834
Zaitsev 10:41552d038a69 835 /* DWT Control Register Definitions */
Zaitsev 10:41552d038a69 836 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
Zaitsev 10:41552d038a69 837 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Zaitsev 10:41552d038a69 838
Zaitsev 10:41552d038a69 839 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
Zaitsev 10:41552d038a69 840 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Zaitsev 10:41552d038a69 841
Zaitsev 10:41552d038a69 842 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
Zaitsev 10:41552d038a69 843 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Zaitsev 10:41552d038a69 844
Zaitsev 10:41552d038a69 845 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
Zaitsev 10:41552d038a69 846 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Zaitsev 10:41552d038a69 847
Zaitsev 10:41552d038a69 848 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
Zaitsev 10:41552d038a69 849 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Zaitsev 10:41552d038a69 850
Zaitsev 10:41552d038a69 851 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
Zaitsev 10:41552d038a69 852 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Zaitsev 10:41552d038a69 853
Zaitsev 10:41552d038a69 854 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
Zaitsev 10:41552d038a69 855 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Zaitsev 10:41552d038a69 856
Zaitsev 10:41552d038a69 857 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
Zaitsev 10:41552d038a69 858 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Zaitsev 10:41552d038a69 859
Zaitsev 10:41552d038a69 860 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
Zaitsev 10:41552d038a69 861 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Zaitsev 10:41552d038a69 862
Zaitsev 10:41552d038a69 863 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
Zaitsev 10:41552d038a69 864 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Zaitsev 10:41552d038a69 865
Zaitsev 10:41552d038a69 866 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
Zaitsev 10:41552d038a69 867 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Zaitsev 10:41552d038a69 868
Zaitsev 10:41552d038a69 869 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
Zaitsev 10:41552d038a69 870 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Zaitsev 10:41552d038a69 871
Zaitsev 10:41552d038a69 872 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
Zaitsev 10:41552d038a69 873 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Zaitsev 10:41552d038a69 874
Zaitsev 10:41552d038a69 875 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
Zaitsev 10:41552d038a69 876 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Zaitsev 10:41552d038a69 877
Zaitsev 10:41552d038a69 878 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
Zaitsev 10:41552d038a69 879 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Zaitsev 10:41552d038a69 880
Zaitsev 10:41552d038a69 881 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
Zaitsev 10:41552d038a69 882 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Zaitsev 10:41552d038a69 883
Zaitsev 10:41552d038a69 884 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
Zaitsev 10:41552d038a69 885 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Zaitsev 10:41552d038a69 886
Zaitsev 10:41552d038a69 887 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Zaitsev 10:41552d038a69 888 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
Zaitsev 10:41552d038a69 889
Zaitsev 10:41552d038a69 890 /* DWT CPI Count Register Definitions */
Zaitsev 10:41552d038a69 891 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Zaitsev 10:41552d038a69 892 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
Zaitsev 10:41552d038a69 893
Zaitsev 10:41552d038a69 894 /* DWT Exception Overhead Count Register Definitions */
Zaitsev 10:41552d038a69 895 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Zaitsev 10:41552d038a69 896 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
Zaitsev 10:41552d038a69 897
Zaitsev 10:41552d038a69 898 /* DWT Sleep Count Register Definitions */
Zaitsev 10:41552d038a69 899 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Zaitsev 10:41552d038a69 900 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Zaitsev 10:41552d038a69 901
Zaitsev 10:41552d038a69 902 /* DWT LSU Count Register Definitions */
Zaitsev 10:41552d038a69 903 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Zaitsev 10:41552d038a69 904 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
Zaitsev 10:41552d038a69 905
Zaitsev 10:41552d038a69 906 /* DWT Folded-instruction Count Register Definitions */
Zaitsev 10:41552d038a69 907 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Zaitsev 10:41552d038a69 908 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
Zaitsev 10:41552d038a69 909
Zaitsev 10:41552d038a69 910 /* DWT Comparator Mask Register Definitions */
Zaitsev 10:41552d038a69 911 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Zaitsev 10:41552d038a69 912 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
Zaitsev 10:41552d038a69 913
Zaitsev 10:41552d038a69 914 /* DWT Comparator Function Register Definitions */
Zaitsev 10:41552d038a69 915 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
Zaitsev 10:41552d038a69 916 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Zaitsev 10:41552d038a69 917
Zaitsev 10:41552d038a69 918 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
Zaitsev 10:41552d038a69 919 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
Zaitsev 10:41552d038a69 920
Zaitsev 10:41552d038a69 921 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
Zaitsev 10:41552d038a69 922 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
Zaitsev 10:41552d038a69 923
Zaitsev 10:41552d038a69 924 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
Zaitsev 10:41552d038a69 925 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Zaitsev 10:41552d038a69 926
Zaitsev 10:41552d038a69 927 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
Zaitsev 10:41552d038a69 928 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
Zaitsev 10:41552d038a69 929
Zaitsev 10:41552d038a69 930 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
Zaitsev 10:41552d038a69 931 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
Zaitsev 10:41552d038a69 932
Zaitsev 10:41552d038a69 933 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
Zaitsev 10:41552d038a69 934 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
Zaitsev 10:41552d038a69 935
Zaitsev 10:41552d038a69 936 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
Zaitsev 10:41552d038a69 937 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
Zaitsev 10:41552d038a69 938
Zaitsev 10:41552d038a69 939 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Zaitsev 10:41552d038a69 940 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
Zaitsev 10:41552d038a69 941
Zaitsev 10:41552d038a69 942 /*@}*/ /* end of group CMSIS_DWT */
Zaitsev 10:41552d038a69 943
Zaitsev 10:41552d038a69 944
Zaitsev 10:41552d038a69 945 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 946 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Zaitsev 10:41552d038a69 947 \brief Type definitions for the Trace Port Interface (TPI)
Zaitsev 10:41552d038a69 948 @{
Zaitsev 10:41552d038a69 949 */
Zaitsev 10:41552d038a69 950
Zaitsev 10:41552d038a69 951 /** \brief Structure type to access the Trace Port Interface Register (TPI).
Zaitsev 10:41552d038a69 952 */
Zaitsev 10:41552d038a69 953 typedef struct
Zaitsev 10:41552d038a69 954 {
Zaitsev 10:41552d038a69 955 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Zaitsev 10:41552d038a69 956 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Zaitsev 10:41552d038a69 957 uint32_t RESERVED0[2];
Zaitsev 10:41552d038a69 958 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Zaitsev 10:41552d038a69 959 uint32_t RESERVED1[55];
Zaitsev 10:41552d038a69 960 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Zaitsev 10:41552d038a69 961 uint32_t RESERVED2[131];
Zaitsev 10:41552d038a69 962 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Zaitsev 10:41552d038a69 963 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Zaitsev 10:41552d038a69 964 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Zaitsev 10:41552d038a69 965 uint32_t RESERVED3[759];
Zaitsev 10:41552d038a69 966 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Zaitsev 10:41552d038a69 967 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Zaitsev 10:41552d038a69 968 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Zaitsev 10:41552d038a69 969 uint32_t RESERVED4[1];
Zaitsev 10:41552d038a69 970 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Zaitsev 10:41552d038a69 971 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Zaitsev 10:41552d038a69 972 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Zaitsev 10:41552d038a69 973 uint32_t RESERVED5[39];
Zaitsev 10:41552d038a69 974 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Zaitsev 10:41552d038a69 975 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Zaitsev 10:41552d038a69 976 uint32_t RESERVED7[8];
Zaitsev 10:41552d038a69 977 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Zaitsev 10:41552d038a69 978 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Zaitsev 10:41552d038a69 979 } TPI_Type;
Zaitsev 10:41552d038a69 980
Zaitsev 10:41552d038a69 981 /* TPI Asynchronous Clock Prescaler Register Definitions */
Zaitsev 10:41552d038a69 982 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Zaitsev 10:41552d038a69 983 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
Zaitsev 10:41552d038a69 984
Zaitsev 10:41552d038a69 985 /* TPI Selected Pin Protocol Register Definitions */
Zaitsev 10:41552d038a69 986 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Zaitsev 10:41552d038a69 987 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Zaitsev 10:41552d038a69 988
Zaitsev 10:41552d038a69 989 /* TPI Formatter and Flush Status Register Definitions */
Zaitsev 10:41552d038a69 990 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
Zaitsev 10:41552d038a69 991 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Zaitsev 10:41552d038a69 992
Zaitsev 10:41552d038a69 993 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
Zaitsev 10:41552d038a69 994 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Zaitsev 10:41552d038a69 995
Zaitsev 10:41552d038a69 996 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
Zaitsev 10:41552d038a69 997 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Zaitsev 10:41552d038a69 998
Zaitsev 10:41552d038a69 999 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Zaitsev 10:41552d038a69 1000 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Zaitsev 10:41552d038a69 1001
Zaitsev 10:41552d038a69 1002 /* TPI Formatter and Flush Control Register Definitions */
Zaitsev 10:41552d038a69 1003 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
Zaitsev 10:41552d038a69 1004 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Zaitsev 10:41552d038a69 1005
Zaitsev 10:41552d038a69 1006 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
Zaitsev 10:41552d038a69 1007 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Zaitsev 10:41552d038a69 1008
Zaitsev 10:41552d038a69 1009 /* TPI TRIGGER Register Definitions */
Zaitsev 10:41552d038a69 1010 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Zaitsev 10:41552d038a69 1011 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Zaitsev 10:41552d038a69 1012
Zaitsev 10:41552d038a69 1013 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Zaitsev 10:41552d038a69 1014 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
Zaitsev 10:41552d038a69 1015 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Zaitsev 10:41552d038a69 1016
Zaitsev 10:41552d038a69 1017 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
Zaitsev 10:41552d038a69 1018 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Zaitsev 10:41552d038a69 1019
Zaitsev 10:41552d038a69 1020 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
Zaitsev 10:41552d038a69 1021 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Zaitsev 10:41552d038a69 1022
Zaitsev 10:41552d038a69 1023 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
Zaitsev 10:41552d038a69 1024 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Zaitsev 10:41552d038a69 1025
Zaitsev 10:41552d038a69 1026 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
Zaitsev 10:41552d038a69 1027 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Zaitsev 10:41552d038a69 1028
Zaitsev 10:41552d038a69 1029 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
Zaitsev 10:41552d038a69 1030 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Zaitsev 10:41552d038a69 1031
Zaitsev 10:41552d038a69 1032 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Zaitsev 10:41552d038a69 1033 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Zaitsev 10:41552d038a69 1034
Zaitsev 10:41552d038a69 1035 /* TPI ITATBCTR2 Register Definitions */
Zaitsev 10:41552d038a69 1036 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Zaitsev 10:41552d038a69 1037 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Zaitsev 10:41552d038a69 1038
Zaitsev 10:41552d038a69 1039 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Zaitsev 10:41552d038a69 1040 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
Zaitsev 10:41552d038a69 1041 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Zaitsev 10:41552d038a69 1042
Zaitsev 10:41552d038a69 1043 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
Zaitsev 10:41552d038a69 1044 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Zaitsev 10:41552d038a69 1045
Zaitsev 10:41552d038a69 1046 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
Zaitsev 10:41552d038a69 1047 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Zaitsev 10:41552d038a69 1048
Zaitsev 10:41552d038a69 1049 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
Zaitsev 10:41552d038a69 1050 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Zaitsev 10:41552d038a69 1051
Zaitsev 10:41552d038a69 1052 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
Zaitsev 10:41552d038a69 1053 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Zaitsev 10:41552d038a69 1054
Zaitsev 10:41552d038a69 1055 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
Zaitsev 10:41552d038a69 1056 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Zaitsev 10:41552d038a69 1057
Zaitsev 10:41552d038a69 1058 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Zaitsev 10:41552d038a69 1059 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Zaitsev 10:41552d038a69 1060
Zaitsev 10:41552d038a69 1061 /* TPI ITATBCTR0 Register Definitions */
Zaitsev 10:41552d038a69 1062 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Zaitsev 10:41552d038a69 1063 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Zaitsev 10:41552d038a69 1064
Zaitsev 10:41552d038a69 1065 /* TPI Integration Mode Control Register Definitions */
Zaitsev 10:41552d038a69 1066 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Zaitsev 10:41552d038a69 1067 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Zaitsev 10:41552d038a69 1068
Zaitsev 10:41552d038a69 1069 /* TPI DEVID Register Definitions */
Zaitsev 10:41552d038a69 1070 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
Zaitsev 10:41552d038a69 1071 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Zaitsev 10:41552d038a69 1072
Zaitsev 10:41552d038a69 1073 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
Zaitsev 10:41552d038a69 1074 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Zaitsev 10:41552d038a69 1075
Zaitsev 10:41552d038a69 1076 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
Zaitsev 10:41552d038a69 1077 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Zaitsev 10:41552d038a69 1078
Zaitsev 10:41552d038a69 1079 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
Zaitsev 10:41552d038a69 1080 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Zaitsev 10:41552d038a69 1081
Zaitsev 10:41552d038a69 1082 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
Zaitsev 10:41552d038a69 1083 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Zaitsev 10:41552d038a69 1084
Zaitsev 10:41552d038a69 1085 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Zaitsev 10:41552d038a69 1086 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Zaitsev 10:41552d038a69 1087
Zaitsev 10:41552d038a69 1088 /* TPI DEVTYPE Register Definitions */
Zaitsev 10:41552d038a69 1089 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
Zaitsev 10:41552d038a69 1090 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Zaitsev 10:41552d038a69 1091
Zaitsev 10:41552d038a69 1092 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Zaitsev 10:41552d038a69 1093 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Zaitsev 10:41552d038a69 1094
Zaitsev 10:41552d038a69 1095 /*@}*/ /* end of group CMSIS_TPI */
Zaitsev 10:41552d038a69 1096
Zaitsev 10:41552d038a69 1097
Zaitsev 10:41552d038a69 1098 #if (__MPU_PRESENT == 1)
Zaitsev 10:41552d038a69 1099 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 1100 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Zaitsev 10:41552d038a69 1101 \brief Type definitions for the Memory Protection Unit (MPU)
Zaitsev 10:41552d038a69 1102 @{
Zaitsev 10:41552d038a69 1103 */
Zaitsev 10:41552d038a69 1104
Zaitsev 10:41552d038a69 1105 /** \brief Structure type to access the Memory Protection Unit (MPU).
Zaitsev 10:41552d038a69 1106 */
Zaitsev 10:41552d038a69 1107 typedef struct
Zaitsev 10:41552d038a69 1108 {
Zaitsev 10:41552d038a69 1109 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Zaitsev 10:41552d038a69 1110 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Zaitsev 10:41552d038a69 1111 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Zaitsev 10:41552d038a69 1112 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Zaitsev 10:41552d038a69 1113 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Zaitsev 10:41552d038a69 1114 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Zaitsev 10:41552d038a69 1115 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Zaitsev 10:41552d038a69 1116 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Zaitsev 10:41552d038a69 1117 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Zaitsev 10:41552d038a69 1118 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Zaitsev 10:41552d038a69 1119 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Zaitsev 10:41552d038a69 1120 } MPU_Type;
Zaitsev 10:41552d038a69 1121
Zaitsev 10:41552d038a69 1122 /* MPU Type Register */
Zaitsev 10:41552d038a69 1123 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Zaitsev 10:41552d038a69 1124 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Zaitsev 10:41552d038a69 1125
Zaitsev 10:41552d038a69 1126 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Zaitsev 10:41552d038a69 1127 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Zaitsev 10:41552d038a69 1128
Zaitsev 10:41552d038a69 1129 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Zaitsev 10:41552d038a69 1130 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Zaitsev 10:41552d038a69 1131
Zaitsev 10:41552d038a69 1132 /* MPU Control Register */
Zaitsev 10:41552d038a69 1133 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Zaitsev 10:41552d038a69 1134 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Zaitsev 10:41552d038a69 1135
Zaitsev 10:41552d038a69 1136 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Zaitsev 10:41552d038a69 1137 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Zaitsev 10:41552d038a69 1138
Zaitsev 10:41552d038a69 1139 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Zaitsev 10:41552d038a69 1140 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Zaitsev 10:41552d038a69 1141
Zaitsev 10:41552d038a69 1142 /* MPU Region Number Register */
Zaitsev 10:41552d038a69 1143 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Zaitsev 10:41552d038a69 1144 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Zaitsev 10:41552d038a69 1145
Zaitsev 10:41552d038a69 1146 /* MPU Region Base Address Register */
Zaitsev 10:41552d038a69 1147 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
Zaitsev 10:41552d038a69 1148 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Zaitsev 10:41552d038a69 1149
Zaitsev 10:41552d038a69 1150 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Zaitsev 10:41552d038a69 1151 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Zaitsev 10:41552d038a69 1152
Zaitsev 10:41552d038a69 1153 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Zaitsev 10:41552d038a69 1154 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Zaitsev 10:41552d038a69 1155
Zaitsev 10:41552d038a69 1156 /* MPU Region Attribute and Size Register */
Zaitsev 10:41552d038a69 1157 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Zaitsev 10:41552d038a69 1158 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Zaitsev 10:41552d038a69 1159
Zaitsev 10:41552d038a69 1160 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Zaitsev 10:41552d038a69 1161 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Zaitsev 10:41552d038a69 1162
Zaitsev 10:41552d038a69 1163 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Zaitsev 10:41552d038a69 1164 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Zaitsev 10:41552d038a69 1165
Zaitsev 10:41552d038a69 1166 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Zaitsev 10:41552d038a69 1167 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Zaitsev 10:41552d038a69 1168
Zaitsev 10:41552d038a69 1169 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Zaitsev 10:41552d038a69 1170 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Zaitsev 10:41552d038a69 1171
Zaitsev 10:41552d038a69 1172 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Zaitsev 10:41552d038a69 1173 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Zaitsev 10:41552d038a69 1174
Zaitsev 10:41552d038a69 1175 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Zaitsev 10:41552d038a69 1176 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Zaitsev 10:41552d038a69 1177
Zaitsev 10:41552d038a69 1178 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Zaitsev 10:41552d038a69 1179 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Zaitsev 10:41552d038a69 1180
Zaitsev 10:41552d038a69 1181 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Zaitsev 10:41552d038a69 1182 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Zaitsev 10:41552d038a69 1183
Zaitsev 10:41552d038a69 1184 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Zaitsev 10:41552d038a69 1185 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Zaitsev 10:41552d038a69 1186
Zaitsev 10:41552d038a69 1187 /*@} end of group CMSIS_MPU */
Zaitsev 10:41552d038a69 1188 #endif
Zaitsev 10:41552d038a69 1189
Zaitsev 10:41552d038a69 1190
Zaitsev 10:41552d038a69 1191 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 1192 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Zaitsev 10:41552d038a69 1193 \brief Type definitions for the Core Debug Registers
Zaitsev 10:41552d038a69 1194 @{
Zaitsev 10:41552d038a69 1195 */
Zaitsev 10:41552d038a69 1196
Zaitsev 10:41552d038a69 1197 /** \brief Structure type to access the Core Debug Register (CoreDebug).
Zaitsev 10:41552d038a69 1198 */
Zaitsev 10:41552d038a69 1199 typedef struct
Zaitsev 10:41552d038a69 1200 {
Zaitsev 10:41552d038a69 1201 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Zaitsev 10:41552d038a69 1202 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Zaitsev 10:41552d038a69 1203 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Zaitsev 10:41552d038a69 1204 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Zaitsev 10:41552d038a69 1205 } CoreDebug_Type;
Zaitsev 10:41552d038a69 1206
Zaitsev 10:41552d038a69 1207 /* Debug Halting Control and Status Register */
Zaitsev 10:41552d038a69 1208 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
Zaitsev 10:41552d038a69 1209 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Zaitsev 10:41552d038a69 1210
Zaitsev 10:41552d038a69 1211 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
Zaitsev 10:41552d038a69 1212 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Zaitsev 10:41552d038a69 1213
Zaitsev 10:41552d038a69 1214 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Zaitsev 10:41552d038a69 1215 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Zaitsev 10:41552d038a69 1216
Zaitsev 10:41552d038a69 1217 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
Zaitsev 10:41552d038a69 1218 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Zaitsev 10:41552d038a69 1219
Zaitsev 10:41552d038a69 1220 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
Zaitsev 10:41552d038a69 1221 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Zaitsev 10:41552d038a69 1222
Zaitsev 10:41552d038a69 1223 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
Zaitsev 10:41552d038a69 1224 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Zaitsev 10:41552d038a69 1225
Zaitsev 10:41552d038a69 1226 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
Zaitsev 10:41552d038a69 1227 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Zaitsev 10:41552d038a69 1228
Zaitsev 10:41552d038a69 1229 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Zaitsev 10:41552d038a69 1230 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Zaitsev 10:41552d038a69 1231
Zaitsev 10:41552d038a69 1232 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
Zaitsev 10:41552d038a69 1233 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Zaitsev 10:41552d038a69 1234
Zaitsev 10:41552d038a69 1235 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
Zaitsev 10:41552d038a69 1236 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Zaitsev 10:41552d038a69 1237
Zaitsev 10:41552d038a69 1238 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
Zaitsev 10:41552d038a69 1239 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Zaitsev 10:41552d038a69 1240
Zaitsev 10:41552d038a69 1241 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Zaitsev 10:41552d038a69 1242 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Zaitsev 10:41552d038a69 1243
Zaitsev 10:41552d038a69 1244 /* Debug Core Register Selector Register */
Zaitsev 10:41552d038a69 1245 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
Zaitsev 10:41552d038a69 1246 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Zaitsev 10:41552d038a69 1247
Zaitsev 10:41552d038a69 1248 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Zaitsev 10:41552d038a69 1249 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Zaitsev 10:41552d038a69 1250
Zaitsev 10:41552d038a69 1251 /* Debug Exception and Monitor Control Register */
Zaitsev 10:41552d038a69 1252 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
Zaitsev 10:41552d038a69 1253 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Zaitsev 10:41552d038a69 1254
Zaitsev 10:41552d038a69 1255 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
Zaitsev 10:41552d038a69 1256 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Zaitsev 10:41552d038a69 1257
Zaitsev 10:41552d038a69 1258 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
Zaitsev 10:41552d038a69 1259 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Zaitsev 10:41552d038a69 1260
Zaitsev 10:41552d038a69 1261 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
Zaitsev 10:41552d038a69 1262 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Zaitsev 10:41552d038a69 1263
Zaitsev 10:41552d038a69 1264 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
Zaitsev 10:41552d038a69 1265 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Zaitsev 10:41552d038a69 1266
Zaitsev 10:41552d038a69 1267 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
Zaitsev 10:41552d038a69 1268 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Zaitsev 10:41552d038a69 1269
Zaitsev 10:41552d038a69 1270 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
Zaitsev 10:41552d038a69 1271 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Zaitsev 10:41552d038a69 1272
Zaitsev 10:41552d038a69 1273 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
Zaitsev 10:41552d038a69 1274 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Zaitsev 10:41552d038a69 1275
Zaitsev 10:41552d038a69 1276 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
Zaitsev 10:41552d038a69 1277 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Zaitsev 10:41552d038a69 1278
Zaitsev 10:41552d038a69 1279 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
Zaitsev 10:41552d038a69 1280 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Zaitsev 10:41552d038a69 1281
Zaitsev 10:41552d038a69 1282 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Zaitsev 10:41552d038a69 1283 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Zaitsev 10:41552d038a69 1284
Zaitsev 10:41552d038a69 1285 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
Zaitsev 10:41552d038a69 1286 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Zaitsev 10:41552d038a69 1287
Zaitsev 10:41552d038a69 1288 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Zaitsev 10:41552d038a69 1289 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Zaitsev 10:41552d038a69 1290
Zaitsev 10:41552d038a69 1291 /*@} end of group CMSIS_CoreDebug */
Zaitsev 10:41552d038a69 1292
Zaitsev 10:41552d038a69 1293
Zaitsev 10:41552d038a69 1294 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 1295 \defgroup CMSIS_core_base Core Definitions
Zaitsev 10:41552d038a69 1296 \brief Definitions for base addresses, unions, and structures.
Zaitsev 10:41552d038a69 1297 @{
Zaitsev 10:41552d038a69 1298 */
Zaitsev 10:41552d038a69 1299
Zaitsev 10:41552d038a69 1300 /* Memory mapping of Cortex-M3 Hardware */
Zaitsev 10:41552d038a69 1301 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Zaitsev 10:41552d038a69 1302 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Zaitsev 10:41552d038a69 1303 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Zaitsev 10:41552d038a69 1304 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Zaitsev 10:41552d038a69 1305 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Zaitsev 10:41552d038a69 1306 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Zaitsev 10:41552d038a69 1307 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Zaitsev 10:41552d038a69 1308 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Zaitsev 10:41552d038a69 1309
Zaitsev 10:41552d038a69 1310 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Zaitsev 10:41552d038a69 1311 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Zaitsev 10:41552d038a69 1312 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Zaitsev 10:41552d038a69 1313 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Zaitsev 10:41552d038a69 1314 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Zaitsev 10:41552d038a69 1315 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Zaitsev 10:41552d038a69 1316 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Zaitsev 10:41552d038a69 1317 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Zaitsev 10:41552d038a69 1318
Zaitsev 10:41552d038a69 1319 #if (__MPU_PRESENT == 1)
Zaitsev 10:41552d038a69 1320 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Zaitsev 10:41552d038a69 1321 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Zaitsev 10:41552d038a69 1322 #endif
Zaitsev 10:41552d038a69 1323
Zaitsev 10:41552d038a69 1324 /*@} */
Zaitsev 10:41552d038a69 1325
Zaitsev 10:41552d038a69 1326
Zaitsev 10:41552d038a69 1327
Zaitsev 10:41552d038a69 1328 /*******************************************************************************
Zaitsev 10:41552d038a69 1329 * Hardware Abstraction Layer
Zaitsev 10:41552d038a69 1330 Core Function Interface contains:
Zaitsev 10:41552d038a69 1331 - Core NVIC Functions
Zaitsev 10:41552d038a69 1332 - Core SysTick Functions
Zaitsev 10:41552d038a69 1333 - Core Debug Functions
Zaitsev 10:41552d038a69 1334 - Core Register Access Functions
Zaitsev 10:41552d038a69 1335 ******************************************************************************/
Zaitsev 10:41552d038a69 1336 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Zaitsev 10:41552d038a69 1337 */
Zaitsev 10:41552d038a69 1338
Zaitsev 10:41552d038a69 1339
Zaitsev 10:41552d038a69 1340
Zaitsev 10:41552d038a69 1341 /* ########################## NVIC functions #################################### */
Zaitsev 10:41552d038a69 1342 /** \ingroup CMSIS_Core_FunctionInterface
Zaitsev 10:41552d038a69 1343 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Zaitsev 10:41552d038a69 1344 \brief Functions that manage interrupts and exceptions via the NVIC.
Zaitsev 10:41552d038a69 1345 @{
Zaitsev 10:41552d038a69 1346 */
Zaitsev 10:41552d038a69 1347
Zaitsev 10:41552d038a69 1348 #ifdef CMSIS_NVIC_VIRTUAL
Zaitsev 10:41552d038a69 1349 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Zaitsev 10:41552d038a69 1350 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Zaitsev 10:41552d038a69 1351 #endif
Zaitsev 10:41552d038a69 1352 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Zaitsev 10:41552d038a69 1353 #else
Zaitsev 10:41552d038a69 1354 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Zaitsev 10:41552d038a69 1355 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Zaitsev 10:41552d038a69 1356 #define NVIC_EnableIRQ __NVIC_EnableIRQ
Zaitsev 10:41552d038a69 1357 #define NVIC_DisableIRQ __NVIC_DisableIRQ
Zaitsev 10:41552d038a69 1358 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Zaitsev 10:41552d038a69 1359 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Zaitsev 10:41552d038a69 1360 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Zaitsev 10:41552d038a69 1361 #define NVIC_GetActive __NVIC_GetActive
Zaitsev 10:41552d038a69 1362 #define NVIC_SetPriority __NVIC_SetPriority
Zaitsev 10:41552d038a69 1363 #define NVIC_GetPriority __NVIC_GetPriority
Zaitsev 10:41552d038a69 1364 #define NVIC_SystemReset __NVIC_SystemReset
Zaitsev 10:41552d038a69 1365 #endif /* CMSIS_NVIC_VIRTUAL */
Zaitsev 10:41552d038a69 1366
Zaitsev 10:41552d038a69 1367 #ifdef CMSIS_VECTAB_VIRTUAL
Zaitsev 10:41552d038a69 1368 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Zaitsev 10:41552d038a69 1369 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Zaitsev 10:41552d038a69 1370 #endif
Zaitsev 10:41552d038a69 1371 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Zaitsev 10:41552d038a69 1372 #else
Zaitsev 10:41552d038a69 1373 #define NVIC_SetVector __NVIC_SetVector
Zaitsev 10:41552d038a69 1374 #define NVIC_GetVector __NVIC_GetVector
Zaitsev 10:41552d038a69 1375 #endif /* CMSIS_VECTAB_VIRTUAL */
Zaitsev 10:41552d038a69 1376
Zaitsev 10:41552d038a69 1377 /** \brief Set Priority Grouping
Zaitsev 10:41552d038a69 1378
Zaitsev 10:41552d038a69 1379 The function sets the priority grouping field using the required unlock sequence.
Zaitsev 10:41552d038a69 1380 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Zaitsev 10:41552d038a69 1381 Only values from 0..7 are used.
Zaitsev 10:41552d038a69 1382 In case of a conflict between priority grouping and available
Zaitsev 10:41552d038a69 1383 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Zaitsev 10:41552d038a69 1384
Zaitsev 10:41552d038a69 1385 \param [in] PriorityGroup Priority grouping field.
Zaitsev 10:41552d038a69 1386 */
Zaitsev 10:41552d038a69 1387 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Zaitsev 10:41552d038a69 1388 {
Zaitsev 10:41552d038a69 1389 uint32_t reg_value;
Zaitsev 10:41552d038a69 1390 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Zaitsev 10:41552d038a69 1391
Zaitsev 10:41552d038a69 1392 reg_value = SCB->AIRCR; /* read old register configuration */
Zaitsev 10:41552d038a69 1393 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Zaitsev 10:41552d038a69 1394 reg_value = (reg_value |
Zaitsev 10:41552d038a69 1395 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Zaitsev 10:41552d038a69 1396 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Zaitsev 10:41552d038a69 1397 SCB->AIRCR = reg_value;
Zaitsev 10:41552d038a69 1398 }
Zaitsev 10:41552d038a69 1399
Zaitsev 10:41552d038a69 1400
Zaitsev 10:41552d038a69 1401 /** \brief Get Priority Grouping
Zaitsev 10:41552d038a69 1402
Zaitsev 10:41552d038a69 1403 The function reads the priority grouping field from the NVIC Interrupt Controller.
Zaitsev 10:41552d038a69 1404
Zaitsev 10:41552d038a69 1405 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Zaitsev 10:41552d038a69 1406 */
Zaitsev 10:41552d038a69 1407 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Zaitsev 10:41552d038a69 1408 {
Zaitsev 10:41552d038a69 1409 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Zaitsev 10:41552d038a69 1410 }
Zaitsev 10:41552d038a69 1411
Zaitsev 10:41552d038a69 1412
Zaitsev 10:41552d038a69 1413 /** \brief Enable External Interrupt
Zaitsev 10:41552d038a69 1414
Zaitsev 10:41552d038a69 1415 The function enables a device-specific interrupt in the NVIC interrupt controller.
Zaitsev 10:41552d038a69 1416
Zaitsev 10:41552d038a69 1417 \param [in] IRQn External interrupt number. Value cannot be negative.
Zaitsev 10:41552d038a69 1418 */
Zaitsev 10:41552d038a69 1419 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1420 {
Zaitsev 10:41552d038a69 1421 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Zaitsev 10:41552d038a69 1422 }
Zaitsev 10:41552d038a69 1423
Zaitsev 10:41552d038a69 1424
Zaitsev 10:41552d038a69 1425 /** \brief Disable External Interrupt
Zaitsev 10:41552d038a69 1426
Zaitsev 10:41552d038a69 1427 The function disables a device-specific interrupt in the NVIC interrupt controller.
Zaitsev 10:41552d038a69 1428
Zaitsev 10:41552d038a69 1429 \param [in] IRQn External interrupt number. Value cannot be negative.
Zaitsev 10:41552d038a69 1430 */
Zaitsev 10:41552d038a69 1431 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1432 {
Zaitsev 10:41552d038a69 1433 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Zaitsev 10:41552d038a69 1434 __DSB();
Zaitsev 10:41552d038a69 1435 __ISB();
Zaitsev 10:41552d038a69 1436 }
Zaitsev 10:41552d038a69 1437
Zaitsev 10:41552d038a69 1438
Zaitsev 10:41552d038a69 1439 /** \brief Get Pending Interrupt
Zaitsev 10:41552d038a69 1440
Zaitsev 10:41552d038a69 1441 The function reads the pending register in the NVIC and returns the pending bit
Zaitsev 10:41552d038a69 1442 for the specified interrupt.
Zaitsev 10:41552d038a69 1443
Zaitsev 10:41552d038a69 1444 \param [in] IRQn Interrupt number.
Zaitsev 10:41552d038a69 1445
Zaitsev 10:41552d038a69 1446 \return 0 Interrupt status is not pending.
Zaitsev 10:41552d038a69 1447 \return 1 Interrupt status is pending.
Zaitsev 10:41552d038a69 1448 */
Zaitsev 10:41552d038a69 1449 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1450 {
Zaitsev 10:41552d038a69 1451 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Zaitsev 10:41552d038a69 1452 }
Zaitsev 10:41552d038a69 1453
Zaitsev 10:41552d038a69 1454
Zaitsev 10:41552d038a69 1455 /** \brief Set Pending Interrupt
Zaitsev 10:41552d038a69 1456
Zaitsev 10:41552d038a69 1457 The function sets the pending bit of an external interrupt.
Zaitsev 10:41552d038a69 1458
Zaitsev 10:41552d038a69 1459 \param [in] IRQn Interrupt number. Value cannot be negative.
Zaitsev 10:41552d038a69 1460 */
Zaitsev 10:41552d038a69 1461 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1462 {
Zaitsev 10:41552d038a69 1463 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Zaitsev 10:41552d038a69 1464 }
Zaitsev 10:41552d038a69 1465
Zaitsev 10:41552d038a69 1466
Zaitsev 10:41552d038a69 1467 /** \brief Clear Pending Interrupt
Zaitsev 10:41552d038a69 1468
Zaitsev 10:41552d038a69 1469 The function clears the pending bit of an external interrupt.
Zaitsev 10:41552d038a69 1470
Zaitsev 10:41552d038a69 1471 \param [in] IRQn External interrupt number. Value cannot be negative.
Zaitsev 10:41552d038a69 1472 */
Zaitsev 10:41552d038a69 1473 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1474 {
Zaitsev 10:41552d038a69 1475 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Zaitsev 10:41552d038a69 1476 }
Zaitsev 10:41552d038a69 1477
Zaitsev 10:41552d038a69 1478
Zaitsev 10:41552d038a69 1479 /** \brief Get Active Interrupt
Zaitsev 10:41552d038a69 1480
Zaitsev 10:41552d038a69 1481 The function reads the active register in NVIC and returns the active bit.
Zaitsev 10:41552d038a69 1482
Zaitsev 10:41552d038a69 1483 \param [in] IRQn Interrupt number.
Zaitsev 10:41552d038a69 1484
Zaitsev 10:41552d038a69 1485 \return 0 Interrupt status is not active.
Zaitsev 10:41552d038a69 1486 \return 1 Interrupt status is active.
Zaitsev 10:41552d038a69 1487 */
Zaitsev 10:41552d038a69 1488 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1489 {
Zaitsev 10:41552d038a69 1490 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Zaitsev 10:41552d038a69 1491 }
Zaitsev 10:41552d038a69 1492
Zaitsev 10:41552d038a69 1493
Zaitsev 10:41552d038a69 1494 /** \brief Set Interrupt Priority
Zaitsev 10:41552d038a69 1495
Zaitsev 10:41552d038a69 1496 The function sets the priority of an interrupt.
Zaitsev 10:41552d038a69 1497
Zaitsev 10:41552d038a69 1498 \note The priority cannot be set for every core interrupt.
Zaitsev 10:41552d038a69 1499
Zaitsev 10:41552d038a69 1500 \param [in] IRQn Interrupt number.
Zaitsev 10:41552d038a69 1501 \param [in] priority Priority to set.
Zaitsev 10:41552d038a69 1502 */
Zaitsev 10:41552d038a69 1503 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Zaitsev 10:41552d038a69 1504 {
Zaitsev 10:41552d038a69 1505 if((int32_t)IRQn < 0) {
Zaitsev 10:41552d038a69 1506 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Zaitsev 10:41552d038a69 1507 }
Zaitsev 10:41552d038a69 1508 else {
Zaitsev 10:41552d038a69 1509 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Zaitsev 10:41552d038a69 1510 }
Zaitsev 10:41552d038a69 1511 }
Zaitsev 10:41552d038a69 1512
Zaitsev 10:41552d038a69 1513
Zaitsev 10:41552d038a69 1514 /** \brief Get Interrupt Priority
Zaitsev 10:41552d038a69 1515
Zaitsev 10:41552d038a69 1516 The function reads the priority of an interrupt. The interrupt
Zaitsev 10:41552d038a69 1517 number can be positive to specify an external (device specific)
Zaitsev 10:41552d038a69 1518 interrupt, or negative to specify an internal (core) interrupt.
Zaitsev 10:41552d038a69 1519
Zaitsev 10:41552d038a69 1520
Zaitsev 10:41552d038a69 1521 \param [in] IRQn Interrupt number.
Zaitsev 10:41552d038a69 1522 \return Interrupt Priority. Value is aligned automatically to the implemented
Zaitsev 10:41552d038a69 1523 priority bits of the microcontroller.
Zaitsev 10:41552d038a69 1524 */
Zaitsev 10:41552d038a69 1525 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 1526 {
Zaitsev 10:41552d038a69 1527
Zaitsev 10:41552d038a69 1528 if((int32_t)IRQn < 0) {
Zaitsev 10:41552d038a69 1529 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Zaitsev 10:41552d038a69 1530 }
Zaitsev 10:41552d038a69 1531 else {
Zaitsev 10:41552d038a69 1532 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Zaitsev 10:41552d038a69 1533 }
Zaitsev 10:41552d038a69 1534 }
Zaitsev 10:41552d038a69 1535
Zaitsev 10:41552d038a69 1536
Zaitsev 10:41552d038a69 1537 /** \brief Encode Priority
Zaitsev 10:41552d038a69 1538
Zaitsev 10:41552d038a69 1539 The function encodes the priority for an interrupt with the given priority group,
Zaitsev 10:41552d038a69 1540 preemptive priority value, and subpriority value.
Zaitsev 10:41552d038a69 1541 In case of a conflict between priority grouping and available
Zaitsev 10:41552d038a69 1542 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Zaitsev 10:41552d038a69 1543
Zaitsev 10:41552d038a69 1544 \param [in] PriorityGroup Used priority group.
Zaitsev 10:41552d038a69 1545 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Zaitsev 10:41552d038a69 1546 \param [in] SubPriority Subpriority value (starting from 0).
Zaitsev 10:41552d038a69 1547 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Zaitsev 10:41552d038a69 1548 */
Zaitsev 10:41552d038a69 1549 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Zaitsev 10:41552d038a69 1550 {
Zaitsev 10:41552d038a69 1551 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Zaitsev 10:41552d038a69 1552 uint32_t PreemptPriorityBits;
Zaitsev 10:41552d038a69 1553 uint32_t SubPriorityBits;
Zaitsev 10:41552d038a69 1554
Zaitsev 10:41552d038a69 1555 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Zaitsev 10:41552d038a69 1556 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Zaitsev 10:41552d038a69 1557
Zaitsev 10:41552d038a69 1558 return (
Zaitsev 10:41552d038a69 1559 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Zaitsev 10:41552d038a69 1560 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Zaitsev 10:41552d038a69 1561 );
Zaitsev 10:41552d038a69 1562 }
Zaitsev 10:41552d038a69 1563
Zaitsev 10:41552d038a69 1564
Zaitsev 10:41552d038a69 1565 /** \brief Decode Priority
Zaitsev 10:41552d038a69 1566
Zaitsev 10:41552d038a69 1567 The function decodes an interrupt priority value with a given priority group to
Zaitsev 10:41552d038a69 1568 preemptive priority value and subpriority value.
Zaitsev 10:41552d038a69 1569 In case of a conflict between priority grouping and available
Zaitsev 10:41552d038a69 1570 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Zaitsev 10:41552d038a69 1571
Zaitsev 10:41552d038a69 1572 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Zaitsev 10:41552d038a69 1573 \param [in] PriorityGroup Used priority group.
Zaitsev 10:41552d038a69 1574 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Zaitsev 10:41552d038a69 1575 \param [out] pSubPriority Subpriority value (starting from 0).
Zaitsev 10:41552d038a69 1576 */
Zaitsev 10:41552d038a69 1577 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Zaitsev 10:41552d038a69 1578 {
Zaitsev 10:41552d038a69 1579 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Zaitsev 10:41552d038a69 1580 uint32_t PreemptPriorityBits;
Zaitsev 10:41552d038a69 1581 uint32_t SubPriorityBits;
Zaitsev 10:41552d038a69 1582
Zaitsev 10:41552d038a69 1583 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Zaitsev 10:41552d038a69 1584 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Zaitsev 10:41552d038a69 1585
Zaitsev 10:41552d038a69 1586 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Zaitsev 10:41552d038a69 1587 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Zaitsev 10:41552d038a69 1588 }
Zaitsev 10:41552d038a69 1589
Zaitsev 10:41552d038a69 1590
Zaitsev 10:41552d038a69 1591 /** \brief System Reset
Zaitsev 10:41552d038a69 1592
Zaitsev 10:41552d038a69 1593 The function initiates a system reset request to reset the MCU.
Zaitsev 10:41552d038a69 1594 */
Zaitsev 10:41552d038a69 1595 __STATIC_INLINE void __NVIC_SystemReset(void)
Zaitsev 10:41552d038a69 1596 {
Zaitsev 10:41552d038a69 1597 __DSB(); /* Ensure all outstanding memory accesses included
Zaitsev 10:41552d038a69 1598 buffered write are completed before reset */
Zaitsev 10:41552d038a69 1599 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Zaitsev 10:41552d038a69 1600 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Zaitsev 10:41552d038a69 1601 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Zaitsev 10:41552d038a69 1602 __DSB(); /* Ensure completion of memory access */
Zaitsev 10:41552d038a69 1603 while(1) { __NOP(); } /* wait until reset */
Zaitsev 10:41552d038a69 1604 }
Zaitsev 10:41552d038a69 1605
Zaitsev 10:41552d038a69 1606 /*@} end of CMSIS_Core_NVICFunctions */
Zaitsev 10:41552d038a69 1607
Zaitsev 10:41552d038a69 1608
Zaitsev 10:41552d038a69 1609
Zaitsev 10:41552d038a69 1610 /* ################################## SysTick function ############################################ */
Zaitsev 10:41552d038a69 1611 /** \ingroup CMSIS_Core_FunctionInterface
Zaitsev 10:41552d038a69 1612 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Zaitsev 10:41552d038a69 1613 \brief Functions that configure the System.
Zaitsev 10:41552d038a69 1614 @{
Zaitsev 10:41552d038a69 1615 */
Zaitsev 10:41552d038a69 1616
Zaitsev 10:41552d038a69 1617 #if (__Vendor_SysTickConfig == 0)
Zaitsev 10:41552d038a69 1618
Zaitsev 10:41552d038a69 1619 /** \brief System Tick Configuration
Zaitsev 10:41552d038a69 1620
Zaitsev 10:41552d038a69 1621 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Zaitsev 10:41552d038a69 1622 Counter is in free running mode to generate periodic interrupts.
Zaitsev 10:41552d038a69 1623
Zaitsev 10:41552d038a69 1624 \param [in] ticks Number of ticks between two interrupts.
Zaitsev 10:41552d038a69 1625
Zaitsev 10:41552d038a69 1626 \return 0 Function succeeded.
Zaitsev 10:41552d038a69 1627 \return 1 Function failed.
Zaitsev 10:41552d038a69 1628
Zaitsev 10:41552d038a69 1629 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Zaitsev 10:41552d038a69 1630 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Zaitsev 10:41552d038a69 1631 must contain a vendor-specific implementation of this function.
Zaitsev 10:41552d038a69 1632
Zaitsev 10:41552d038a69 1633 */
Zaitsev 10:41552d038a69 1634 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Zaitsev 10:41552d038a69 1635 {
Zaitsev 10:41552d038a69 1636 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Zaitsev 10:41552d038a69 1637
Zaitsev 10:41552d038a69 1638 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Zaitsev 10:41552d038a69 1639 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Zaitsev 10:41552d038a69 1640 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Zaitsev 10:41552d038a69 1641 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Zaitsev 10:41552d038a69 1642 SysTick_CTRL_TICKINT_Msk |
Zaitsev 10:41552d038a69 1643 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Zaitsev 10:41552d038a69 1644 return (0UL); /* Function successful */
Zaitsev 10:41552d038a69 1645 }
Zaitsev 10:41552d038a69 1646
Zaitsev 10:41552d038a69 1647 #endif
Zaitsev 10:41552d038a69 1648
Zaitsev 10:41552d038a69 1649 /*@} end of CMSIS_Core_SysTickFunctions */
Zaitsev 10:41552d038a69 1650
Zaitsev 10:41552d038a69 1651
Zaitsev 10:41552d038a69 1652
Zaitsev 10:41552d038a69 1653 /* ##################################### Debug In/Output function ########################################### */
Zaitsev 10:41552d038a69 1654 /** \ingroup CMSIS_Core_FunctionInterface
Zaitsev 10:41552d038a69 1655 \defgroup CMSIS_core_DebugFunctions ITM Functions
Zaitsev 10:41552d038a69 1656 \brief Functions that access the ITM debug interface.
Zaitsev 10:41552d038a69 1657 @{
Zaitsev 10:41552d038a69 1658 */
Zaitsev 10:41552d038a69 1659
Zaitsev 10:41552d038a69 1660 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Zaitsev 10:41552d038a69 1661 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Zaitsev 10:41552d038a69 1662
Zaitsev 10:41552d038a69 1663
Zaitsev 10:41552d038a69 1664 /** \brief ITM Send Character
Zaitsev 10:41552d038a69 1665
Zaitsev 10:41552d038a69 1666 The function transmits a character via the ITM channel 0, and
Zaitsev 10:41552d038a69 1667 \li Just returns when no debugger is connected that has booked the output.
Zaitsev 10:41552d038a69 1668 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Zaitsev 10:41552d038a69 1669
Zaitsev 10:41552d038a69 1670 \param [in] ch Character to transmit.
Zaitsev 10:41552d038a69 1671
Zaitsev 10:41552d038a69 1672 \returns Character to transmit.
Zaitsev 10:41552d038a69 1673 */
Zaitsev 10:41552d038a69 1674 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Zaitsev 10:41552d038a69 1675 {
Zaitsev 10:41552d038a69 1676 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Zaitsev 10:41552d038a69 1677 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Zaitsev 10:41552d038a69 1678 {
Zaitsev 10:41552d038a69 1679 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Zaitsev 10:41552d038a69 1680 ITM->PORT[0].u8 = (uint8_t)ch;
Zaitsev 10:41552d038a69 1681 }
Zaitsev 10:41552d038a69 1682 return (ch);
Zaitsev 10:41552d038a69 1683 }
Zaitsev 10:41552d038a69 1684
Zaitsev 10:41552d038a69 1685
Zaitsev 10:41552d038a69 1686 /** \brief ITM Receive Character
Zaitsev 10:41552d038a69 1687
Zaitsev 10:41552d038a69 1688 The function inputs a character via the external variable \ref ITM_RxBuffer.
Zaitsev 10:41552d038a69 1689
Zaitsev 10:41552d038a69 1690 \return Received character.
Zaitsev 10:41552d038a69 1691 \return -1 No character pending.
Zaitsev 10:41552d038a69 1692 */
Zaitsev 10:41552d038a69 1693 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Zaitsev 10:41552d038a69 1694 int32_t ch = -1; /* no character available */
Zaitsev 10:41552d038a69 1695
Zaitsev 10:41552d038a69 1696 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Zaitsev 10:41552d038a69 1697 ch = ITM_RxBuffer;
Zaitsev 10:41552d038a69 1698 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Zaitsev 10:41552d038a69 1699 }
Zaitsev 10:41552d038a69 1700
Zaitsev 10:41552d038a69 1701 return (ch);
Zaitsev 10:41552d038a69 1702 }
Zaitsev 10:41552d038a69 1703
Zaitsev 10:41552d038a69 1704
Zaitsev 10:41552d038a69 1705 /** \brief ITM Check Character
Zaitsev 10:41552d038a69 1706
Zaitsev 10:41552d038a69 1707 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Zaitsev 10:41552d038a69 1708
Zaitsev 10:41552d038a69 1709 \return 0 No character available.
Zaitsev 10:41552d038a69 1710 \return 1 Character available.
Zaitsev 10:41552d038a69 1711 */
Zaitsev 10:41552d038a69 1712 __STATIC_INLINE int32_t ITM_CheckChar (void) {
Zaitsev 10:41552d038a69 1713
Zaitsev 10:41552d038a69 1714 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Zaitsev 10:41552d038a69 1715 return (0); /* no character available */
Zaitsev 10:41552d038a69 1716 } else {
Zaitsev 10:41552d038a69 1717 return (1); /* character available */
Zaitsev 10:41552d038a69 1718 }
Zaitsev 10:41552d038a69 1719 }
Zaitsev 10:41552d038a69 1720
Zaitsev 10:41552d038a69 1721 /*@} end of CMSIS_core_DebugFunctions */
Zaitsev 10:41552d038a69 1722
Zaitsev 10:41552d038a69 1723
Zaitsev 10:41552d038a69 1724
Zaitsev 10:41552d038a69 1725
Zaitsev 10:41552d038a69 1726 #ifdef __cplusplus
Zaitsev 10:41552d038a69 1727 }
Zaitsev 10:41552d038a69 1728 #endif
Zaitsev 10:41552d038a69 1729
Zaitsev 10:41552d038a69 1730 #endif /* __CORE_CM3_H_DEPENDANT */
Zaitsev 10:41552d038a69 1731
Zaitsev 10:41552d038a69 1732 #endif /* __CMSIS_GENERIC */