Mateusz Kowalik / Application

USB Serial application

Fork of USBSerial_HelloWorld by Samuel Mokrani

mbed-dev/cmsis/core_cm0plus.h@10:41552d038a69, 2017-01-10 (annotated)

Committer:
Zaitsev
Date:
Tue Jan 10 20:42:26 2017 +0000
Revision:
10:41552d038a69
USB Serial bi-directional bridge

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zaitsev 10:41552d038a69 1 /**************************************************************************//**
Zaitsev 10:41552d038a69 2 * @file core_cm0plus.h
Zaitsev 10:41552d038a69 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Zaitsev 10:41552d038a69 4 * @version V4.10
Zaitsev 10:41552d038a69 5 * @date 18. March 2015
Zaitsev 10:41552d038a69 6 *
Zaitsev 10:41552d038a69 7 * @note
Zaitsev 10:41552d038a69 8 *
Zaitsev 10:41552d038a69 9 ******************************************************************************/
Zaitsev 10:41552d038a69 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Zaitsev 10:41552d038a69 11
Zaitsev 10:41552d038a69 12 All rights reserved.
Zaitsev 10:41552d038a69 13 Redistribution and use in source and binary forms, with or without
Zaitsev 10:41552d038a69 14 modification, are permitted provided that the following conditions are met:
Zaitsev 10:41552d038a69 15 - Redistributions of source code must retain the above copyright
Zaitsev 10:41552d038a69 16 notice, this list of conditions and the following disclaimer.
Zaitsev 10:41552d038a69 17 - Redistributions in binary form must reproduce the above copyright
Zaitsev 10:41552d038a69 18 notice, this list of conditions and the following disclaimer in the
Zaitsev 10:41552d038a69 19 documentation and/or other materials provided with the distribution.
Zaitsev 10:41552d038a69 20 - Neither the name of ARM nor the names of its contributors may be used
Zaitsev 10:41552d038a69 21 to endorse or promote products derived from this software without
Zaitsev 10:41552d038a69 22 specific prior written permission.
Zaitsev 10:41552d038a69 23 *
Zaitsev 10:41552d038a69 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Zaitsev 10:41552d038a69 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Zaitsev 10:41552d038a69 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Zaitsev 10:41552d038a69 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Zaitsev 10:41552d038a69 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Zaitsev 10:41552d038a69 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Zaitsev 10:41552d038a69 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Zaitsev 10:41552d038a69 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Zaitsev 10:41552d038a69 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Zaitsev 10:41552d038a69 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Zaitsev 10:41552d038a69 34 POSSIBILITY OF SUCH DAMAGE.
Zaitsev 10:41552d038a69 35 ---------------------------------------------------------------------------*/
Zaitsev 10:41552d038a69 36
Zaitsev 10:41552d038a69 37
Zaitsev 10:41552d038a69 38 #if defined ( __ICCARM__ )
Zaitsev 10:41552d038a69 39 #pragma system_include /* treat file as system include file for MISRA check */
Zaitsev 10:41552d038a69 40 #endif
Zaitsev 10:41552d038a69 41
Zaitsev 10:41552d038a69 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Zaitsev 10:41552d038a69 43 #define __CORE_CM0PLUS_H_GENERIC
Zaitsev 10:41552d038a69 44
Zaitsev 10:41552d038a69 45 #ifdef __cplusplus
Zaitsev 10:41552d038a69 46 extern "C" {
Zaitsev 10:41552d038a69 47 #endif
Zaitsev 10:41552d038a69 48
Zaitsev 10:41552d038a69 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Zaitsev 10:41552d038a69 50 CMSIS violates the following MISRA-C:2004 rules:
Zaitsev 10:41552d038a69 51
Zaitsev 10:41552d038a69 52 \li Required Rule 8.5, object/function definition in header file.<br>
Zaitsev 10:41552d038a69 53 Function definitions in header files are used to allow 'inlining'.
Zaitsev 10:41552d038a69 54
Zaitsev 10:41552d038a69 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Zaitsev 10:41552d038a69 56 Unions are used for effective representation of core registers.
Zaitsev 10:41552d038a69 57
Zaitsev 10:41552d038a69 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Zaitsev 10:41552d038a69 59 Function-like macros are used to allow more efficient code.
Zaitsev 10:41552d038a69 60 */
Zaitsev 10:41552d038a69 61
Zaitsev 10:41552d038a69 62
Zaitsev 10:41552d038a69 63 /*******************************************************************************
Zaitsev 10:41552d038a69 64 * CMSIS definitions
Zaitsev 10:41552d038a69 65 ******************************************************************************/
Zaitsev 10:41552d038a69 66 /** \ingroup Cortex-M0+
Zaitsev 10:41552d038a69 67 @{
Zaitsev 10:41552d038a69 68 */
Zaitsev 10:41552d038a69 69
Zaitsev 10:41552d038a69 70 /* CMSIS CM0P definitions */
Zaitsev 10:41552d038a69 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Zaitsev 10:41552d038a69 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Zaitsev 10:41552d038a69 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Zaitsev 10:41552d038a69 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Zaitsev 10:41552d038a69 75
Zaitsev 10:41552d038a69 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Zaitsev 10:41552d038a69 77
Zaitsev 10:41552d038a69 78
Zaitsev 10:41552d038a69 79 #if defined ( __CC_ARM )
Zaitsev 10:41552d038a69 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Zaitsev 10:41552d038a69 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Zaitsev 10:41552d038a69 82 #define __STATIC_INLINE static __inline
Zaitsev 10:41552d038a69 83
Zaitsev 10:41552d038a69 84 #elif defined ( __GNUC__ )
Zaitsev 10:41552d038a69 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Zaitsev 10:41552d038a69 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Zaitsev 10:41552d038a69 87 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 88
Zaitsev 10:41552d038a69 89 #elif defined ( __ICCARM__ )
Zaitsev 10:41552d038a69 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Zaitsev 10:41552d038a69 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Zaitsev 10:41552d038a69 92 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 93
Zaitsev 10:41552d038a69 94 #elif defined ( __TMS470__ )
Zaitsev 10:41552d038a69 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Zaitsev 10:41552d038a69 96 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 97
Zaitsev 10:41552d038a69 98 #elif defined ( __TASKING__ )
Zaitsev 10:41552d038a69 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Zaitsev 10:41552d038a69 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Zaitsev 10:41552d038a69 101 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 102
Zaitsev 10:41552d038a69 103 #elif defined ( __CSMC__ )
Zaitsev 10:41552d038a69 104 #define __packed
Zaitsev 10:41552d038a69 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Zaitsev 10:41552d038a69 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Zaitsev 10:41552d038a69 107 #define __STATIC_INLINE static inline
Zaitsev 10:41552d038a69 108
Zaitsev 10:41552d038a69 109 #endif
Zaitsev 10:41552d038a69 110
Zaitsev 10:41552d038a69 111 /** __FPU_USED indicates whether an FPU is used or not.
Zaitsev 10:41552d038a69 112 This core does not support an FPU at all
Zaitsev 10:41552d038a69 113 */
Zaitsev 10:41552d038a69 114 #define __FPU_USED 0
Zaitsev 10:41552d038a69 115
Zaitsev 10:41552d038a69 116 #if defined ( __CC_ARM )
Zaitsev 10:41552d038a69 117 #if defined __TARGET_FPU_VFP
Zaitsev 10:41552d038a69 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 119 #endif
Zaitsev 10:41552d038a69 120
Zaitsev 10:41552d038a69 121 #elif defined ( __GNUC__ )
Zaitsev 10:41552d038a69 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Zaitsev 10:41552d038a69 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 124 #endif
Zaitsev 10:41552d038a69 125
Zaitsev 10:41552d038a69 126 #elif defined ( __ICCARM__ )
Zaitsev 10:41552d038a69 127 #if defined __ARMVFP__
Zaitsev 10:41552d038a69 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 129 #endif
Zaitsev 10:41552d038a69 130
Zaitsev 10:41552d038a69 131 #elif defined ( __TMS470__ )
Zaitsev 10:41552d038a69 132 #if defined __TI__VFP_SUPPORT____
Zaitsev 10:41552d038a69 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 134 #endif
Zaitsev 10:41552d038a69 135
Zaitsev 10:41552d038a69 136 #elif defined ( __TASKING__ )
Zaitsev 10:41552d038a69 137 #if defined __FPU_VFP__
Zaitsev 10:41552d038a69 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 139 #endif
Zaitsev 10:41552d038a69 140
Zaitsev 10:41552d038a69 141 #elif defined ( __CSMC__ ) /* Cosmic */
Zaitsev 10:41552d038a69 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Zaitsev 10:41552d038a69 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Zaitsev 10:41552d038a69 144 #endif
Zaitsev 10:41552d038a69 145 #endif
Zaitsev 10:41552d038a69 146
Zaitsev 10:41552d038a69 147 #include <stdint.h> /* standard types definitions */
Zaitsev 10:41552d038a69 148 #include <core_cmInstr.h> /* Core Instruction Access */
Zaitsev 10:41552d038a69 149 #include <core_cmFunc.h> /* Core Function Access */
Zaitsev 10:41552d038a69 150
Zaitsev 10:41552d038a69 151 #ifdef __cplusplus
Zaitsev 10:41552d038a69 152 }
Zaitsev 10:41552d038a69 153 #endif
Zaitsev 10:41552d038a69 154
Zaitsev 10:41552d038a69 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
Zaitsev 10:41552d038a69 156
Zaitsev 10:41552d038a69 157 #ifndef __CMSIS_GENERIC
Zaitsev 10:41552d038a69 158
Zaitsev 10:41552d038a69 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Zaitsev 10:41552d038a69 160 #define __CORE_CM0PLUS_H_DEPENDANT
Zaitsev 10:41552d038a69 161
Zaitsev 10:41552d038a69 162 #ifdef __cplusplus
Zaitsev 10:41552d038a69 163 extern "C" {
Zaitsev 10:41552d038a69 164 #endif
Zaitsev 10:41552d038a69 165
Zaitsev 10:41552d038a69 166 /* check device defines and use defaults */
Zaitsev 10:41552d038a69 167 #if defined __CHECK_DEVICE_DEFINES
Zaitsev 10:41552d038a69 168 #ifndef __CM0PLUS_REV
Zaitsev 10:41552d038a69 169 #define __CM0PLUS_REV 0x0000
Zaitsev 10:41552d038a69 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Zaitsev 10:41552d038a69 171 #endif
Zaitsev 10:41552d038a69 172
Zaitsev 10:41552d038a69 173 #ifndef __MPU_PRESENT
Zaitsev 10:41552d038a69 174 #define __MPU_PRESENT 0
Zaitsev 10:41552d038a69 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Zaitsev 10:41552d038a69 176 #endif
Zaitsev 10:41552d038a69 177
Zaitsev 10:41552d038a69 178 #ifndef __VTOR_PRESENT
Zaitsev 10:41552d038a69 179 #define __VTOR_PRESENT 0
Zaitsev 10:41552d038a69 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Zaitsev 10:41552d038a69 181 #endif
Zaitsev 10:41552d038a69 182
Zaitsev 10:41552d038a69 183 #ifndef __NVIC_PRIO_BITS
Zaitsev 10:41552d038a69 184 #define __NVIC_PRIO_BITS 2
Zaitsev 10:41552d038a69 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Zaitsev 10:41552d038a69 186 #endif
Zaitsev 10:41552d038a69 187
Zaitsev 10:41552d038a69 188 #ifndef __Vendor_SysTickConfig
Zaitsev 10:41552d038a69 189 #define __Vendor_SysTickConfig 0
Zaitsev 10:41552d038a69 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Zaitsev 10:41552d038a69 191 #endif
Zaitsev 10:41552d038a69 192 #endif
Zaitsev 10:41552d038a69 193
Zaitsev 10:41552d038a69 194 /* IO definitions (access restrictions to peripheral registers) */
Zaitsev 10:41552d038a69 195 /**
Zaitsev 10:41552d038a69 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
Zaitsev 10:41552d038a69 197
Zaitsev 10:41552d038a69 198 <strong>IO Type Qualifiers</strong> are used
Zaitsev 10:41552d038a69 199 \li to specify the access to peripheral variables.
Zaitsev 10:41552d038a69 200 \li for automatic generation of peripheral register debug information.
Zaitsev 10:41552d038a69 201 */
Zaitsev 10:41552d038a69 202 #ifdef __cplusplus
Zaitsev 10:41552d038a69 203 #define __I volatile /*!< Defines 'read only' permissions */
Zaitsev 10:41552d038a69 204 #else
Zaitsev 10:41552d038a69 205 #define __I volatile const /*!< Defines 'read only' permissions */
Zaitsev 10:41552d038a69 206 #endif
Zaitsev 10:41552d038a69 207 #define __O volatile /*!< Defines 'write only' permissions */
Zaitsev 10:41552d038a69 208 #define __IO volatile /*!< Defines 'read / write' permissions */
Zaitsev 10:41552d038a69 209
Zaitsev 10:41552d038a69 210 #ifdef __cplusplus
Zaitsev 10:41552d038a69 211 #define __IM volatile /*!< Defines 'read only' permissions */
Zaitsev 10:41552d038a69 212 #else
Zaitsev 10:41552d038a69 213 #define __IM volatile const /*!< Defines 'read only' permissions */
Zaitsev 10:41552d038a69 214 #endif
Zaitsev 10:41552d038a69 215 #define __OM volatile /*!< Defines 'write only' permissions */
Zaitsev 10:41552d038a69 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
Zaitsev 10:41552d038a69 217
Zaitsev 10:41552d038a69 218 /*@} end of group Cortex-M0+ */
Zaitsev 10:41552d038a69 219
Zaitsev 10:41552d038a69 220
Zaitsev 10:41552d038a69 221
Zaitsev 10:41552d038a69 222 /*******************************************************************************
Zaitsev 10:41552d038a69 223 * Register Abstraction
Zaitsev 10:41552d038a69 224 Core Register contain:
Zaitsev 10:41552d038a69 225 - Core Register
Zaitsev 10:41552d038a69 226 - Core NVIC Register
Zaitsev 10:41552d038a69 227 - Core SCB Register
Zaitsev 10:41552d038a69 228 - Core SysTick Register
Zaitsev 10:41552d038a69 229 - Core MPU Register
Zaitsev 10:41552d038a69 230 ******************************************************************************/
Zaitsev 10:41552d038a69 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
Zaitsev 10:41552d038a69 232 \brief Type definitions and defines for Cortex-M processor based devices.
Zaitsev 10:41552d038a69 233 */
Zaitsev 10:41552d038a69 234
Zaitsev 10:41552d038a69 235 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 236 \defgroup CMSIS_CORE Status and Control Registers
Zaitsev 10:41552d038a69 237 \brief Core Register type definitions.
Zaitsev 10:41552d038a69 238 @{
Zaitsev 10:41552d038a69 239 */
Zaitsev 10:41552d038a69 240
Zaitsev 10:41552d038a69 241 /** \brief Union type to access the Application Program Status Register (APSR).
Zaitsev 10:41552d038a69 242 */
Zaitsev 10:41552d038a69 243 typedef union
Zaitsev 10:41552d038a69 244 {
Zaitsev 10:41552d038a69 245 struct
Zaitsev 10:41552d038a69 246 {
Zaitsev 10:41552d038a69 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Zaitsev 10:41552d038a69 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Zaitsev 10:41552d038a69 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Zaitsev 10:41552d038a69 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Zaitsev 10:41552d038a69 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Zaitsev 10:41552d038a69 252 } b; /*!< Structure used for bit access */
Zaitsev 10:41552d038a69 253 uint32_t w; /*!< Type used for word access */
Zaitsev 10:41552d038a69 254 } APSR_Type;
Zaitsev 10:41552d038a69 255
Zaitsev 10:41552d038a69 256 /* APSR Register Definitions */
Zaitsev 10:41552d038a69 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Zaitsev 10:41552d038a69 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Zaitsev 10:41552d038a69 259
Zaitsev 10:41552d038a69 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Zaitsev 10:41552d038a69 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Zaitsev 10:41552d038a69 262
Zaitsev 10:41552d038a69 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Zaitsev 10:41552d038a69 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Zaitsev 10:41552d038a69 265
Zaitsev 10:41552d038a69 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Zaitsev 10:41552d038a69 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Zaitsev 10:41552d038a69 268
Zaitsev 10:41552d038a69 269
Zaitsev 10:41552d038a69 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Zaitsev 10:41552d038a69 271 */
Zaitsev 10:41552d038a69 272 typedef union
Zaitsev 10:41552d038a69 273 {
Zaitsev 10:41552d038a69 274 struct
Zaitsev 10:41552d038a69 275 {
Zaitsev 10:41552d038a69 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Zaitsev 10:41552d038a69 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Zaitsev 10:41552d038a69 278 } b; /*!< Structure used for bit access */
Zaitsev 10:41552d038a69 279 uint32_t w; /*!< Type used for word access */
Zaitsev 10:41552d038a69 280 } IPSR_Type;
Zaitsev 10:41552d038a69 281
Zaitsev 10:41552d038a69 282 /* IPSR Register Definitions */
Zaitsev 10:41552d038a69 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Zaitsev 10:41552d038a69 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Zaitsev 10:41552d038a69 285
Zaitsev 10:41552d038a69 286
Zaitsev 10:41552d038a69 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Zaitsev 10:41552d038a69 288 */
Zaitsev 10:41552d038a69 289 typedef union
Zaitsev 10:41552d038a69 290 {
Zaitsev 10:41552d038a69 291 struct
Zaitsev 10:41552d038a69 292 {
Zaitsev 10:41552d038a69 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Zaitsev 10:41552d038a69 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Zaitsev 10:41552d038a69 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Zaitsev 10:41552d038a69 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Zaitsev 10:41552d038a69 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Zaitsev 10:41552d038a69 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Zaitsev 10:41552d038a69 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Zaitsev 10:41552d038a69 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Zaitsev 10:41552d038a69 301 } b; /*!< Structure used for bit access */
Zaitsev 10:41552d038a69 302 uint32_t w; /*!< Type used for word access */
Zaitsev 10:41552d038a69 303 } xPSR_Type;
Zaitsev 10:41552d038a69 304
Zaitsev 10:41552d038a69 305 /* xPSR Register Definitions */
Zaitsev 10:41552d038a69 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Zaitsev 10:41552d038a69 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Zaitsev 10:41552d038a69 308
Zaitsev 10:41552d038a69 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Zaitsev 10:41552d038a69 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Zaitsev 10:41552d038a69 311
Zaitsev 10:41552d038a69 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Zaitsev 10:41552d038a69 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Zaitsev 10:41552d038a69 314
Zaitsev 10:41552d038a69 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Zaitsev 10:41552d038a69 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Zaitsev 10:41552d038a69 317
Zaitsev 10:41552d038a69 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Zaitsev 10:41552d038a69 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Zaitsev 10:41552d038a69 320
Zaitsev 10:41552d038a69 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Zaitsev 10:41552d038a69 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Zaitsev 10:41552d038a69 323
Zaitsev 10:41552d038a69 324
Zaitsev 10:41552d038a69 325 /** \brief Union type to access the Control Registers (CONTROL).
Zaitsev 10:41552d038a69 326 */
Zaitsev 10:41552d038a69 327 typedef union
Zaitsev 10:41552d038a69 328 {
Zaitsev 10:41552d038a69 329 struct
Zaitsev 10:41552d038a69 330 {
Zaitsev 10:41552d038a69 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Zaitsev 10:41552d038a69 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Zaitsev 10:41552d038a69 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Zaitsev 10:41552d038a69 334 } b; /*!< Structure used for bit access */
Zaitsev 10:41552d038a69 335 uint32_t w; /*!< Type used for word access */
Zaitsev 10:41552d038a69 336 } CONTROL_Type;
Zaitsev 10:41552d038a69 337
Zaitsev 10:41552d038a69 338 /* CONTROL Register Definitions */
Zaitsev 10:41552d038a69 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Zaitsev 10:41552d038a69 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Zaitsev 10:41552d038a69 341
Zaitsev 10:41552d038a69 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Zaitsev 10:41552d038a69 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Zaitsev 10:41552d038a69 344
Zaitsev 10:41552d038a69 345 /*@} end of group CMSIS_CORE */
Zaitsev 10:41552d038a69 346
Zaitsev 10:41552d038a69 347
Zaitsev 10:41552d038a69 348 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Zaitsev 10:41552d038a69 350 \brief Type definitions for the NVIC Registers
Zaitsev 10:41552d038a69 351 @{
Zaitsev 10:41552d038a69 352 */
Zaitsev 10:41552d038a69 353
Zaitsev 10:41552d038a69 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Zaitsev 10:41552d038a69 355 */
Zaitsev 10:41552d038a69 356 typedef struct
Zaitsev 10:41552d038a69 357 {
Zaitsev 10:41552d038a69 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Zaitsev 10:41552d038a69 359 uint32_t RESERVED0[31];
Zaitsev 10:41552d038a69 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Zaitsev 10:41552d038a69 361 uint32_t RSERVED1[31];
Zaitsev 10:41552d038a69 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Zaitsev 10:41552d038a69 363 uint32_t RESERVED2[31];
Zaitsev 10:41552d038a69 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Zaitsev 10:41552d038a69 365 uint32_t RESERVED3[31];
Zaitsev 10:41552d038a69 366 uint32_t RESERVED4[64];
Zaitsev 10:41552d038a69 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Zaitsev 10:41552d038a69 368 } NVIC_Type;
Zaitsev 10:41552d038a69 369
Zaitsev 10:41552d038a69 370 /*@} end of group CMSIS_NVIC */
Zaitsev 10:41552d038a69 371
Zaitsev 10:41552d038a69 372
Zaitsev 10:41552d038a69 373 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 374 \defgroup CMSIS_SCB System Control Block (SCB)
Zaitsev 10:41552d038a69 375 \brief Type definitions for the System Control Block Registers
Zaitsev 10:41552d038a69 376 @{
Zaitsev 10:41552d038a69 377 */
Zaitsev 10:41552d038a69 378
Zaitsev 10:41552d038a69 379 /** \brief Structure type to access the System Control Block (SCB).
Zaitsev 10:41552d038a69 380 */
Zaitsev 10:41552d038a69 381 typedef struct
Zaitsev 10:41552d038a69 382 {
Zaitsev 10:41552d038a69 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Zaitsev 10:41552d038a69 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Zaitsev 10:41552d038a69 385 #if (__VTOR_PRESENT == 1)
Zaitsev 10:41552d038a69 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Zaitsev 10:41552d038a69 387 #else
Zaitsev 10:41552d038a69 388 uint32_t RESERVED0;
Zaitsev 10:41552d038a69 389 #endif
Zaitsev 10:41552d038a69 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Zaitsev 10:41552d038a69 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Zaitsev 10:41552d038a69 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Zaitsev 10:41552d038a69 393 uint32_t RESERVED1;
Zaitsev 10:41552d038a69 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Zaitsev 10:41552d038a69 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Zaitsev 10:41552d038a69 396 } SCB_Type;
Zaitsev 10:41552d038a69 397
Zaitsev 10:41552d038a69 398 /* SCB CPUID Register Definitions */
Zaitsev 10:41552d038a69 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Zaitsev 10:41552d038a69 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Zaitsev 10:41552d038a69 401
Zaitsev 10:41552d038a69 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Zaitsev 10:41552d038a69 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Zaitsev 10:41552d038a69 404
Zaitsev 10:41552d038a69 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Zaitsev 10:41552d038a69 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Zaitsev 10:41552d038a69 407
Zaitsev 10:41552d038a69 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Zaitsev 10:41552d038a69 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Zaitsev 10:41552d038a69 410
Zaitsev 10:41552d038a69 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Zaitsev 10:41552d038a69 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Zaitsev 10:41552d038a69 413
Zaitsev 10:41552d038a69 414 /* SCB Interrupt Control State Register Definitions */
Zaitsev 10:41552d038a69 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Zaitsev 10:41552d038a69 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Zaitsev 10:41552d038a69 417
Zaitsev 10:41552d038a69 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Zaitsev 10:41552d038a69 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Zaitsev 10:41552d038a69 420
Zaitsev 10:41552d038a69 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Zaitsev 10:41552d038a69 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Zaitsev 10:41552d038a69 423
Zaitsev 10:41552d038a69 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Zaitsev 10:41552d038a69 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Zaitsev 10:41552d038a69 426
Zaitsev 10:41552d038a69 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Zaitsev 10:41552d038a69 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Zaitsev 10:41552d038a69 429
Zaitsev 10:41552d038a69 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Zaitsev 10:41552d038a69 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Zaitsev 10:41552d038a69 432
Zaitsev 10:41552d038a69 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Zaitsev 10:41552d038a69 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Zaitsev 10:41552d038a69 435
Zaitsev 10:41552d038a69 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Zaitsev 10:41552d038a69 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Zaitsev 10:41552d038a69 438
Zaitsev 10:41552d038a69 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Zaitsev 10:41552d038a69 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Zaitsev 10:41552d038a69 441
Zaitsev 10:41552d038a69 442 #if (__VTOR_PRESENT == 1)
Zaitsev 10:41552d038a69 443 /* SCB Interrupt Control State Register Definitions */
Zaitsev 10:41552d038a69 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Zaitsev 10:41552d038a69 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Zaitsev 10:41552d038a69 446 #endif
Zaitsev 10:41552d038a69 447
Zaitsev 10:41552d038a69 448 /* SCB Application Interrupt and Reset Control Register Definitions */
Zaitsev 10:41552d038a69 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Zaitsev 10:41552d038a69 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Zaitsev 10:41552d038a69 451
Zaitsev 10:41552d038a69 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Zaitsev 10:41552d038a69 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Zaitsev 10:41552d038a69 454
Zaitsev 10:41552d038a69 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Zaitsev 10:41552d038a69 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Zaitsev 10:41552d038a69 457
Zaitsev 10:41552d038a69 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Zaitsev 10:41552d038a69 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Zaitsev 10:41552d038a69 460
Zaitsev 10:41552d038a69 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Zaitsev 10:41552d038a69 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Zaitsev 10:41552d038a69 463
Zaitsev 10:41552d038a69 464 /* SCB System Control Register Definitions */
Zaitsev 10:41552d038a69 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Zaitsev 10:41552d038a69 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Zaitsev 10:41552d038a69 467
Zaitsev 10:41552d038a69 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Zaitsev 10:41552d038a69 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Zaitsev 10:41552d038a69 470
Zaitsev 10:41552d038a69 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Zaitsev 10:41552d038a69 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Zaitsev 10:41552d038a69 473
Zaitsev 10:41552d038a69 474 /* SCB Configuration Control Register Definitions */
Zaitsev 10:41552d038a69 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Zaitsev 10:41552d038a69 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Zaitsev 10:41552d038a69 477
Zaitsev 10:41552d038a69 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Zaitsev 10:41552d038a69 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Zaitsev 10:41552d038a69 480
Zaitsev 10:41552d038a69 481 /* SCB System Handler Control and State Register Definitions */
Zaitsev 10:41552d038a69 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Zaitsev 10:41552d038a69 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Zaitsev 10:41552d038a69 484
Zaitsev 10:41552d038a69 485 /*@} end of group CMSIS_SCB */
Zaitsev 10:41552d038a69 486
Zaitsev 10:41552d038a69 487
Zaitsev 10:41552d038a69 488 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Zaitsev 10:41552d038a69 490 \brief Type definitions for the System Timer Registers.
Zaitsev 10:41552d038a69 491 @{
Zaitsev 10:41552d038a69 492 */
Zaitsev 10:41552d038a69 493
Zaitsev 10:41552d038a69 494 /** \brief Structure type to access the System Timer (SysTick).
Zaitsev 10:41552d038a69 495 */
Zaitsev 10:41552d038a69 496 typedef struct
Zaitsev 10:41552d038a69 497 {
Zaitsev 10:41552d038a69 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Zaitsev 10:41552d038a69 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Zaitsev 10:41552d038a69 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Zaitsev 10:41552d038a69 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Zaitsev 10:41552d038a69 502 } SysTick_Type;
Zaitsev 10:41552d038a69 503
Zaitsev 10:41552d038a69 504 /* SysTick Control / Status Register Definitions */
Zaitsev 10:41552d038a69 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Zaitsev 10:41552d038a69 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Zaitsev 10:41552d038a69 507
Zaitsev 10:41552d038a69 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Zaitsev 10:41552d038a69 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Zaitsev 10:41552d038a69 510
Zaitsev 10:41552d038a69 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Zaitsev 10:41552d038a69 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Zaitsev 10:41552d038a69 513
Zaitsev 10:41552d038a69 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Zaitsev 10:41552d038a69 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Zaitsev 10:41552d038a69 516
Zaitsev 10:41552d038a69 517 /* SysTick Reload Register Definitions */
Zaitsev 10:41552d038a69 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Zaitsev 10:41552d038a69 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Zaitsev 10:41552d038a69 520
Zaitsev 10:41552d038a69 521 /* SysTick Current Register Definitions */
Zaitsev 10:41552d038a69 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Zaitsev 10:41552d038a69 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Zaitsev 10:41552d038a69 524
Zaitsev 10:41552d038a69 525 /* SysTick Calibration Register Definitions */
Zaitsev 10:41552d038a69 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Zaitsev 10:41552d038a69 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Zaitsev 10:41552d038a69 528
Zaitsev 10:41552d038a69 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Zaitsev 10:41552d038a69 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Zaitsev 10:41552d038a69 531
Zaitsev 10:41552d038a69 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Zaitsev 10:41552d038a69 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Zaitsev 10:41552d038a69 534
Zaitsev 10:41552d038a69 535 /*@} end of group CMSIS_SysTick */
Zaitsev 10:41552d038a69 536
Zaitsev 10:41552d038a69 537 #if (__MPU_PRESENT == 1)
Zaitsev 10:41552d038a69 538 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Zaitsev 10:41552d038a69 540 \brief Type definitions for the Memory Protection Unit (MPU)
Zaitsev 10:41552d038a69 541 @{
Zaitsev 10:41552d038a69 542 */
Zaitsev 10:41552d038a69 543
Zaitsev 10:41552d038a69 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
Zaitsev 10:41552d038a69 545 */
Zaitsev 10:41552d038a69 546 typedef struct
Zaitsev 10:41552d038a69 547 {
Zaitsev 10:41552d038a69 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Zaitsev 10:41552d038a69 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Zaitsev 10:41552d038a69 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Zaitsev 10:41552d038a69 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Zaitsev 10:41552d038a69 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Zaitsev 10:41552d038a69 553 } MPU_Type;
Zaitsev 10:41552d038a69 554
Zaitsev 10:41552d038a69 555 /* MPU Type Register */
Zaitsev 10:41552d038a69 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Zaitsev 10:41552d038a69 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Zaitsev 10:41552d038a69 558
Zaitsev 10:41552d038a69 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Zaitsev 10:41552d038a69 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Zaitsev 10:41552d038a69 561
Zaitsev 10:41552d038a69 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Zaitsev 10:41552d038a69 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Zaitsev 10:41552d038a69 564
Zaitsev 10:41552d038a69 565 /* MPU Control Register */
Zaitsev 10:41552d038a69 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Zaitsev 10:41552d038a69 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Zaitsev 10:41552d038a69 568
Zaitsev 10:41552d038a69 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Zaitsev 10:41552d038a69 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Zaitsev 10:41552d038a69 571
Zaitsev 10:41552d038a69 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Zaitsev 10:41552d038a69 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Zaitsev 10:41552d038a69 574
Zaitsev 10:41552d038a69 575 /* MPU Region Number Register */
Zaitsev 10:41552d038a69 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Zaitsev 10:41552d038a69 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Zaitsev 10:41552d038a69 578
Zaitsev 10:41552d038a69 579 /* MPU Region Base Address Register */
Zaitsev 10:41552d038a69 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Zaitsev 10:41552d038a69 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Zaitsev 10:41552d038a69 582
Zaitsev 10:41552d038a69 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Zaitsev 10:41552d038a69 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Zaitsev 10:41552d038a69 585
Zaitsev 10:41552d038a69 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Zaitsev 10:41552d038a69 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Zaitsev 10:41552d038a69 588
Zaitsev 10:41552d038a69 589 /* MPU Region Attribute and Size Register */
Zaitsev 10:41552d038a69 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Zaitsev 10:41552d038a69 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Zaitsev 10:41552d038a69 592
Zaitsev 10:41552d038a69 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Zaitsev 10:41552d038a69 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Zaitsev 10:41552d038a69 595
Zaitsev 10:41552d038a69 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Zaitsev 10:41552d038a69 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Zaitsev 10:41552d038a69 598
Zaitsev 10:41552d038a69 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Zaitsev 10:41552d038a69 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Zaitsev 10:41552d038a69 601
Zaitsev 10:41552d038a69 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Zaitsev 10:41552d038a69 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Zaitsev 10:41552d038a69 604
Zaitsev 10:41552d038a69 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Zaitsev 10:41552d038a69 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Zaitsev 10:41552d038a69 607
Zaitsev 10:41552d038a69 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Zaitsev 10:41552d038a69 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Zaitsev 10:41552d038a69 610
Zaitsev 10:41552d038a69 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Zaitsev 10:41552d038a69 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Zaitsev 10:41552d038a69 613
Zaitsev 10:41552d038a69 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Zaitsev 10:41552d038a69 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Zaitsev 10:41552d038a69 616
Zaitsev 10:41552d038a69 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Zaitsev 10:41552d038a69 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Zaitsev 10:41552d038a69 619
Zaitsev 10:41552d038a69 620 /*@} end of group CMSIS_MPU */
Zaitsev 10:41552d038a69 621 #endif
Zaitsev 10:41552d038a69 622
Zaitsev 10:41552d038a69 623
Zaitsev 10:41552d038a69 624 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Zaitsev 10:41552d038a69 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Zaitsev 10:41552d038a69 627 are only accessible over DAP and not via processor. Therefore
Zaitsev 10:41552d038a69 628 they are not covered by the Cortex-M0 header file.
Zaitsev 10:41552d038a69 629 @{
Zaitsev 10:41552d038a69 630 */
Zaitsev 10:41552d038a69 631 /*@} end of group CMSIS_CoreDebug */
Zaitsev 10:41552d038a69 632
Zaitsev 10:41552d038a69 633
Zaitsev 10:41552d038a69 634 /** \ingroup CMSIS_core_register
Zaitsev 10:41552d038a69 635 \defgroup CMSIS_core_base Core Definitions
Zaitsev 10:41552d038a69 636 \brief Definitions for base addresses, unions, and structures.
Zaitsev 10:41552d038a69 637 @{
Zaitsev 10:41552d038a69 638 */
Zaitsev 10:41552d038a69 639
Zaitsev 10:41552d038a69 640 /* Memory mapping of Cortex-M0+ Hardware */
Zaitsev 10:41552d038a69 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Zaitsev 10:41552d038a69 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Zaitsev 10:41552d038a69 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Zaitsev 10:41552d038a69 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Zaitsev 10:41552d038a69 645
Zaitsev 10:41552d038a69 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Zaitsev 10:41552d038a69 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Zaitsev 10:41552d038a69 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Zaitsev 10:41552d038a69 649
Zaitsev 10:41552d038a69 650 #if (__MPU_PRESENT == 1)
Zaitsev 10:41552d038a69 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Zaitsev 10:41552d038a69 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Zaitsev 10:41552d038a69 653 #endif
Zaitsev 10:41552d038a69 654
Zaitsev 10:41552d038a69 655 /*@} */
Zaitsev 10:41552d038a69 656
Zaitsev 10:41552d038a69 657
Zaitsev 10:41552d038a69 658
Zaitsev 10:41552d038a69 659 /*******************************************************************************
Zaitsev 10:41552d038a69 660 * Hardware Abstraction Layer
Zaitsev 10:41552d038a69 661 Core Function Interface contains:
Zaitsev 10:41552d038a69 662 - Core NVIC Functions
Zaitsev 10:41552d038a69 663 - Core SysTick Functions
Zaitsev 10:41552d038a69 664 - Core Register Access Functions
Zaitsev 10:41552d038a69 665 ******************************************************************************/
Zaitsev 10:41552d038a69 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Zaitsev 10:41552d038a69 667 */
Zaitsev 10:41552d038a69 668
Zaitsev 10:41552d038a69 669
Zaitsev 10:41552d038a69 670
Zaitsev 10:41552d038a69 671 /* ########################## NVIC functions #################################### */
Zaitsev 10:41552d038a69 672 /** \ingroup CMSIS_Core_FunctionInterface
Zaitsev 10:41552d038a69 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Zaitsev 10:41552d038a69 674 \brief Functions that manage interrupts and exceptions via the NVIC.
Zaitsev 10:41552d038a69 675 @{
Zaitsev 10:41552d038a69 676 */
Zaitsev 10:41552d038a69 677
Zaitsev 10:41552d038a69 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Zaitsev 10:41552d038a69 679 /* The following MACROS handle generation of the register offset and byte masks */
Zaitsev 10:41552d038a69 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Zaitsev 10:41552d038a69 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Zaitsev 10:41552d038a69 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Zaitsev 10:41552d038a69 683
Zaitsev 10:41552d038a69 684
Zaitsev 10:41552d038a69 685 /** \brief Enable External Interrupt
Zaitsev 10:41552d038a69 686
Zaitsev 10:41552d038a69 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
Zaitsev 10:41552d038a69 688
Zaitsev 10:41552d038a69 689 \param [in] IRQn External interrupt number. Value cannot be negative.
Zaitsev 10:41552d038a69 690 */
Zaitsev 10:41552d038a69 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 692 {
Zaitsev 10:41552d038a69 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Zaitsev 10:41552d038a69 694 }
Zaitsev 10:41552d038a69 695
Zaitsev 10:41552d038a69 696
Zaitsev 10:41552d038a69 697 /** \brief Disable External Interrupt
Zaitsev 10:41552d038a69 698
Zaitsev 10:41552d038a69 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
Zaitsev 10:41552d038a69 700
Zaitsev 10:41552d038a69 701 \param [in] IRQn External interrupt number. Value cannot be negative.
Zaitsev 10:41552d038a69 702 */
Zaitsev 10:41552d038a69 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 704 {
Zaitsev 10:41552d038a69 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Zaitsev 10:41552d038a69 706 __DSB();
Zaitsev 10:41552d038a69 707 __ISB();
Zaitsev 10:41552d038a69 708 }
Zaitsev 10:41552d038a69 709
Zaitsev 10:41552d038a69 710
Zaitsev 10:41552d038a69 711 /** \brief Get Pending Interrupt
Zaitsev 10:41552d038a69 712
Zaitsev 10:41552d038a69 713 The function reads the pending register in the NVIC and returns the pending bit
Zaitsev 10:41552d038a69 714 for the specified interrupt.
Zaitsev 10:41552d038a69 715
Zaitsev 10:41552d038a69 716 \param [in] IRQn Interrupt number.
Zaitsev 10:41552d038a69 717
Zaitsev 10:41552d038a69 718 \return 0 Interrupt status is not pending.
Zaitsev 10:41552d038a69 719 \return 1 Interrupt status is pending.
Zaitsev 10:41552d038a69 720 */
Zaitsev 10:41552d038a69 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 722 {
Zaitsev 10:41552d038a69 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Zaitsev 10:41552d038a69 724 }
Zaitsev 10:41552d038a69 725
Zaitsev 10:41552d038a69 726
Zaitsev 10:41552d038a69 727 /** \brief Set Pending Interrupt
Zaitsev 10:41552d038a69 728
Zaitsev 10:41552d038a69 729 The function sets the pending bit of an external interrupt.
Zaitsev 10:41552d038a69 730
Zaitsev 10:41552d038a69 731 \param [in] IRQn Interrupt number. Value cannot be negative.
Zaitsev 10:41552d038a69 732 */
Zaitsev 10:41552d038a69 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 734 {
Zaitsev 10:41552d038a69 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Zaitsev 10:41552d038a69 736 }
Zaitsev 10:41552d038a69 737
Zaitsev 10:41552d038a69 738
Zaitsev 10:41552d038a69 739 /** \brief Clear Pending Interrupt
Zaitsev 10:41552d038a69 740
Zaitsev 10:41552d038a69 741 The function clears the pending bit of an external interrupt.
Zaitsev 10:41552d038a69 742
Zaitsev 10:41552d038a69 743 \param [in] IRQn External interrupt number. Value cannot be negative.
Zaitsev 10:41552d038a69 744 */
Zaitsev 10:41552d038a69 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 746 {
Zaitsev 10:41552d038a69 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Zaitsev 10:41552d038a69 748 }
Zaitsev 10:41552d038a69 749
Zaitsev 10:41552d038a69 750
Zaitsev 10:41552d038a69 751 /** \brief Set Interrupt Priority
Zaitsev 10:41552d038a69 752
Zaitsev 10:41552d038a69 753 The function sets the priority of an interrupt.
Zaitsev 10:41552d038a69 754
Zaitsev 10:41552d038a69 755 \note The priority cannot be set for every core interrupt.
Zaitsev 10:41552d038a69 756
Zaitsev 10:41552d038a69 757 \param [in] IRQn Interrupt number.
Zaitsev 10:41552d038a69 758 \param [in] priority Priority to set.
Zaitsev 10:41552d038a69 759 */
Zaitsev 10:41552d038a69 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Zaitsev 10:41552d038a69 761 {
Zaitsev 10:41552d038a69 762 if((int32_t)(IRQn) < 0) {
Zaitsev 10:41552d038a69 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Zaitsev 10:41552d038a69 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Zaitsev 10:41552d038a69 765 }
Zaitsev 10:41552d038a69 766 else {
Zaitsev 10:41552d038a69 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Zaitsev 10:41552d038a69 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Zaitsev 10:41552d038a69 769 }
Zaitsev 10:41552d038a69 770 }
Zaitsev 10:41552d038a69 771
Zaitsev 10:41552d038a69 772
Zaitsev 10:41552d038a69 773 /** \brief Get Interrupt Priority
Zaitsev 10:41552d038a69 774
Zaitsev 10:41552d038a69 775 The function reads the priority of an interrupt. The interrupt
Zaitsev 10:41552d038a69 776 number can be positive to specify an external (device specific)
Zaitsev 10:41552d038a69 777 interrupt, or negative to specify an internal (core) interrupt.
Zaitsev 10:41552d038a69 778
Zaitsev 10:41552d038a69 779
Zaitsev 10:41552d038a69 780 \param [in] IRQn Interrupt number.
Zaitsev 10:41552d038a69 781 \return Interrupt Priority. Value is aligned automatically to the implemented
Zaitsev 10:41552d038a69 782 priority bits of the microcontroller.
Zaitsev 10:41552d038a69 783 */
Zaitsev 10:41552d038a69 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Zaitsev 10:41552d038a69 785 {
Zaitsev 10:41552d038a69 786
Zaitsev 10:41552d038a69 787 if((int32_t)(IRQn) < 0) {
Zaitsev 10:41552d038a69 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Zaitsev 10:41552d038a69 789 }
Zaitsev 10:41552d038a69 790 else {
Zaitsev 10:41552d038a69 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Zaitsev 10:41552d038a69 792 }
Zaitsev 10:41552d038a69 793 }
Zaitsev 10:41552d038a69 794
Zaitsev 10:41552d038a69 795
Zaitsev 10:41552d038a69 796 /** \brief System Reset
Zaitsev 10:41552d038a69 797
Zaitsev 10:41552d038a69 798 The function initiates a system reset request to reset the MCU.
Zaitsev 10:41552d038a69 799 */
Zaitsev 10:41552d038a69 800 __STATIC_INLINE void NVIC_SystemReset(void)
Zaitsev 10:41552d038a69 801 {
Zaitsev 10:41552d038a69 802 __DSB(); /* Ensure all outstanding memory accesses included
Zaitsev 10:41552d038a69 803 buffered write are completed before reset */
Zaitsev 10:41552d038a69 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Zaitsev 10:41552d038a69 805 SCB_AIRCR_SYSRESETREQ_Msk);
Zaitsev 10:41552d038a69 806 __DSB(); /* Ensure completion of memory access */
Zaitsev 10:41552d038a69 807 while(1) { __NOP(); } /* wait until reset */
Zaitsev 10:41552d038a69 808 }
Zaitsev 10:41552d038a69 809
Zaitsev 10:41552d038a69 810 /*@} end of CMSIS_Core_NVICFunctions */
Zaitsev 10:41552d038a69 811
Zaitsev 10:41552d038a69 812
Zaitsev 10:41552d038a69 813
Zaitsev 10:41552d038a69 814 /* ################################## SysTick function ############################################ */
Zaitsev 10:41552d038a69 815 /** \ingroup CMSIS_Core_FunctionInterface
Zaitsev 10:41552d038a69 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Zaitsev 10:41552d038a69 817 \brief Functions that configure the System.
Zaitsev 10:41552d038a69 818 @{
Zaitsev 10:41552d038a69 819 */
Zaitsev 10:41552d038a69 820
Zaitsev 10:41552d038a69 821 #if (__Vendor_SysTickConfig == 0)
Zaitsev 10:41552d038a69 822
Zaitsev 10:41552d038a69 823 /** \brief System Tick Configuration
Zaitsev 10:41552d038a69 824
Zaitsev 10:41552d038a69 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Zaitsev 10:41552d038a69 826 Counter is in free running mode to generate periodic interrupts.
Zaitsev 10:41552d038a69 827
Zaitsev 10:41552d038a69 828 \param [in] ticks Number of ticks between two interrupts.
Zaitsev 10:41552d038a69 829
Zaitsev 10:41552d038a69 830 \return 0 Function succeeded.
Zaitsev 10:41552d038a69 831 \return 1 Function failed.
Zaitsev 10:41552d038a69 832
Zaitsev 10:41552d038a69 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Zaitsev 10:41552d038a69 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Zaitsev 10:41552d038a69 835 must contain a vendor-specific implementation of this function.
Zaitsev 10:41552d038a69 836
Zaitsev 10:41552d038a69 837 */
Zaitsev 10:41552d038a69 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Zaitsev 10:41552d038a69 839 {
Zaitsev 10:41552d038a69 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Zaitsev 10:41552d038a69 841
Zaitsev 10:41552d038a69 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Zaitsev 10:41552d038a69 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Zaitsev 10:41552d038a69 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Zaitsev 10:41552d038a69 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Zaitsev 10:41552d038a69 846 SysTick_CTRL_TICKINT_Msk |
Zaitsev 10:41552d038a69 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Zaitsev 10:41552d038a69 848 return (0UL); /* Function successful */
Zaitsev 10:41552d038a69 849 }
Zaitsev 10:41552d038a69 850
Zaitsev 10:41552d038a69 851 #endif
Zaitsev 10:41552d038a69 852
Zaitsev 10:41552d038a69 853 /*@} end of CMSIS_Core_SysTickFunctions */
Zaitsev 10:41552d038a69 854
Zaitsev 10:41552d038a69 855
Zaitsev 10:41552d038a69 856
Zaitsev 10:41552d038a69 857
Zaitsev 10:41552d038a69 858 #ifdef __cplusplus
Zaitsev 10:41552d038a69 859 }
Zaitsev 10:41552d038a69 860 #endif
Zaitsev 10:41552d038a69 861
Zaitsev 10:41552d038a69 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Zaitsev 10:41552d038a69 863
Zaitsev 10:41552d038a69 864 #endif /* __CMSIS_GENERIC */