Yehowshua Immanuel / MMA8452

I think there was a bug with debug mode

Dependents:   Generic_Platformer

MMA8452.cpp@12:172540ff6b8b, 2014-03-04 (annotated)

Committer:
ashleymills
Date:
Tue Mar 04 17:50:47 2014 +0000
Revision:
12:172540ff6b8b
Parent:
11:dfd1e0afcb7b
Child:
13:4bd8b4cd479d
Added basic raw reading back in after remake.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ashleymills 11:dfd1e0afcb7b 1 // Author: Nicholas Herriot, Ashley Mills
nherriot 0:bcf2aa85d7f9 2 /* Copyright (c) 2013 Vodafone, MIT License
nherriot 0:bcf2aa85d7f9 3 *
nherriot 0:bcf2aa85d7f9 4 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
nherriot 0:bcf2aa85d7f9 5 * and associated documentation files (the "Software"), to deal in the Software without restriction,
nherriot 0:bcf2aa85d7f9 6 * including without limitation the rights to use, copy, modify, merge, publish, distribute,
nherriot 0:bcf2aa85d7f9 7 * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
nherriot 0:bcf2aa85d7f9 8 * furnished to do so, subject to the following conditions:
nherriot 0:bcf2aa85d7f9 9 *
nherriot 0:bcf2aa85d7f9 10 * The above copyright notice and this permission notice shall be included in all copies or
nherriot 0:bcf2aa85d7f9 11 * substantial portions of the Software.
nherriot 0:bcf2aa85d7f9 12 *
nherriot 0:bcf2aa85d7f9 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
nherriot 0:bcf2aa85d7f9 14 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
nherriot 0:bcf2aa85d7f9 15 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
nherriot 0:bcf2aa85d7f9 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
nherriot 0:bcf2aa85d7f9 17 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
nherriot 0:bcf2aa85d7f9 18 */
nherriot 0:bcf2aa85d7f9 19
ashleymills 11:dfd1e0afcb7b 20 #include "MMA8452.h"
ashleymills 11:dfd1e0afcb7b 21 #include "mbed.h"
ashleymills 11:dfd1e0afcb7b 22
ashleymills 11:dfd1e0afcb7b 23 extern Serial pc;
nherriot 0:bcf2aa85d7f9 24
nherriot 0:bcf2aa85d7f9 25 // Connect module at I2C address using I2C port pins sda and scl
ashleymills 11:dfd1e0afcb7b 26 MMA8452::MMA8452(PinName sda, PinName scl, int frequency) : _i2c(sda, scl) , _frequency(frequency) {
ashleymills 11:dfd1e0afcb7b 27 DBG("Creating MMA8452");
ashleymills 12:172540ff6b8b 28
ashleymills 12:172540ff6b8b 29 // set I2C frequency
ashleymills 11:dfd1e0afcb7b 30 _i2c.frequency(_frequency);
ashleymills 11:dfd1e0afcb7b 31
ashleymills 12:172540ff6b8b 32 // setup read and write addresses for convenience
ashleymills 11:dfd1e0afcb7b 33 _readAddress = MMA8452_ADDRESS | 0x01;
ashleymills 11:dfd1e0afcb7b 34 _writeAddress = MMA8452_ADDRESS & 0xFE;
ashleymills 12:172540ff6b8b 35
ashleymills 12:172540ff6b8b 36 // set some defaults
ashleymills 12:172540ff6b8b 37 _bitDepth = BIT_DEPTH_UNKNOWN;
ashleymills 12:172540ff6b8b 38 setBitDepth(BIT_DEPTH_12);
ashleymills 11:dfd1e0afcb7b 39 DBG("Done");
nherriot 0:bcf2aa85d7f9 40 }
nherriot 0:bcf2aa85d7f9 41
nherriot 0:bcf2aa85d7f9 42
nherriot 0:bcf2aa85d7f9 43 // Destroys instance
ashleymills 10:ca9ba7ad4e94 44 MMA8452::~MMA8452() {}
nherriot 0:bcf2aa85d7f9 45
nherriot 0:bcf2aa85d7f9 46 // Setting the control register bit 1 to true to activate the MMA8452
ashleymills 10:ca9ba7ad4e94 47 int MMA8452::activate() {
ashleymills 6:f6bde04bf8be 48 // perform write and return error code
ashleymills 12:172540ff6b8b 49 return logicalORRegister(MMA8452_CTRL_REG_1,MMA8452_ACTIVE_MASK);
nherriot 3:ffb0b1650ca2 50 }
nherriot 3:ffb0b1650ca2 51
ashleymills 11:dfd1e0afcb7b 52 // Setting the control register bit 1 to 0 to standby the MMA8452
ashleymills 11:dfd1e0afcb7b 53 int MMA8452::standby() {
ashleymills 11:dfd1e0afcb7b 54 // perform write and return error code
ashleymills 12:172540ff6b8b 55 return logicalANDRegister(MMA8452_CTRL_REG_1,MMA8452_STANDBY_MASK);
nherriot 5:b3d0abd97e55 56 }
nherriot 5:b3d0abd97e55 57
ashleymills 11:dfd1e0afcb7b 58 // this reads a register, applies a bitmask with logical AND, sets a value with logical OR,
ashleymills 11:dfd1e0afcb7b 59 // and optionally goes into and out of standby at the beginning and end of the function respectively
ashleymills 11:dfd1e0afcb7b 60 int MMA8452::maskAndApplyRegister(char reg, char mask, char value, int toggleActivation) {
ashleymills 11:dfd1e0afcb7b 61 if(toggleActivation) {
ashleymills 11:dfd1e0afcb7b 62 if(standby()) {
ashleymills 11:dfd1e0afcb7b 63 return 1;
ashleymills 11:dfd1e0afcb7b 64 }
ashleymills 11:dfd1e0afcb7b 65 }
ashleymills 11:dfd1e0afcb7b 66
ashleymills 11:dfd1e0afcb7b 67 // read from register
ashleymills 11:dfd1e0afcb7b 68 char oldValue = 0;
ashleymills 11:dfd1e0afcb7b 69 if(readRegister(reg,&oldValue)) {
ashleymills 11:dfd1e0afcb7b 70 return 1;
ashleymills 11:dfd1e0afcb7b 71 }
ashleymills 11:dfd1e0afcb7b 72
ashleymills 11:dfd1e0afcb7b 73 // apply bitmask
ashleymills 11:dfd1e0afcb7b 74 oldValue &= mask;
ashleymills 11:dfd1e0afcb7b 75
ashleymills 11:dfd1e0afcb7b 76 // set value
ashleymills 11:dfd1e0afcb7b 77 oldValue |= value;
ashleymills 11:dfd1e0afcb7b 78
ashleymills 11:dfd1e0afcb7b 79 // write back to register
ashleymills 11:dfd1e0afcb7b 80 if(writeRegister(reg,oldValue)) {
ashleymills 11:dfd1e0afcb7b 81 return 1;
ashleymills 11:dfd1e0afcb7b 82 }
ashleymills 11:dfd1e0afcb7b 83
ashleymills 11:dfd1e0afcb7b 84 if(toggleActivation) {
ashleymills 11:dfd1e0afcb7b 85 if(activate()) {
ashleymills 11:dfd1e0afcb7b 86 return 1;
ashleymills 11:dfd1e0afcb7b 87 }
ashleymills 11:dfd1e0afcb7b 88 }
ashleymills 11:dfd1e0afcb7b 89 return 0;
nherriot 0:bcf2aa85d7f9 90 }
nherriot 0:bcf2aa85d7f9 91
ashleymills 11:dfd1e0afcb7b 92 int MMA8452::setDynamicRange(DynamicRange range, int toggleActivation) {
ashleymills 11:dfd1e0afcb7b 93 return maskAndApplyRegister(
ashleymills 11:dfd1e0afcb7b 94 MMA8452_XYZ_DATA_CFG,
ashleymills 11:dfd1e0afcb7b 95 MMA8452_DYNAMIC_RANGE_MASK,
ashleymills 11:dfd1e0afcb7b 96 range,
ashleymills 11:dfd1e0afcb7b 97 toggleActivation
ashleymills 11:dfd1e0afcb7b 98 );
nherriot 0:bcf2aa85d7f9 99 }
nherriot 0:bcf2aa85d7f9 100
ashleymills 11:dfd1e0afcb7b 101 int MMA8452::setDataRate(DataRateHz dataRate, int toggleActivation) {
ashleymills 11:dfd1e0afcb7b 102 return maskAndApplyRegister(
ashleymills 11:dfd1e0afcb7b 103 MMA8452_CTRL_REG_1,
ashleymills 11:dfd1e0afcb7b 104 MMA8452_DATA_RATE_MASK,
ashleymills 11:dfd1e0afcb7b 105 dataRate<<MMA8452_DATA_RATE_MASK_SHIFT,
ashleymills 11:dfd1e0afcb7b 106 toggleActivation
ashleymills 11:dfd1e0afcb7b 107 );
nherriot 3:ffb0b1650ca2 108 }
nherriot 3:ffb0b1650ca2 109
ashleymills 11:dfd1e0afcb7b 110 int MMA8452::setBitDepth(BitDepth depth,int toggleActivation) {
ashleymills 12:172540ff6b8b 111 _bitDepth = depth;
ashleymills 11:dfd1e0afcb7b 112 return maskAndApplyRegister(
ashleymills 11:dfd1e0afcb7b 113 MMA8452_CTRL_REG_1,
ashleymills 11:dfd1e0afcb7b 114 MMA8452_BIT_DEPTH_MASK,
ashleymills 11:dfd1e0afcb7b 115 depth<<MMA8452_BIT_DEPTH_MASK_SHIFT,
ashleymills 11:dfd1e0afcb7b 116 toggleActivation
ashleymills 11:dfd1e0afcb7b 117 );
nherriot 3:ffb0b1650ca2 118 }
nherriot 3:ffb0b1650ca2 119
ashleymills 12:172540ff6b8b 120 int MMA8452::isXYZReady() {
ashleymills 12:172540ff6b8b 121 char rval = 0;
ashleymills 12:172540ff6b8b 122 if(readRegister(MMA8452_STATUS,&rval)) {
ashleymills 12:172540ff6b8b 123 return 0;
ashleymills 12:172540ff6b8b 124 }
ashleymills 12:172540ff6b8b 125 return (rval&MMA8452_STATUS_ZYXDR_MASK);
nherriot 1:ef026bf28798 126 }
ashleymills 12:172540ff6b8b 127
ashleymills 12:172540ff6b8b 128 int MMA8452::getDeviceID(char *dst) {
ashleymills 12:172540ff6b8b 129 return readRegister(MMA8452_WHO_AM_I,dst);
nherriot 3:ffb0b1650ca2 130 }
nherriot 3:ffb0b1650ca2 131
ashleymills 12:172540ff6b8b 132 int MMA8452::getStatus(char* dst) {
ashleymills 12:172540ff6b8b 133 return readRegister(MMA8452_STATUS,dst);
nherriot 3:ffb0b1650ca2 134 }
nherriot 0:bcf2aa85d7f9 135
ashleymills 11:dfd1e0afcb7b 136 MMA8452::DynamicRange MMA8452::getDynamicRange() {
ashleymills 11:dfd1e0afcb7b 137 char rval = 0;
ashleymills 12:172540ff6b8b 138 if(readRegister(MMA8452_XYZ_DATA_CFG,&rval)) {
ashleymills 11:dfd1e0afcb7b 139 return MMA8452::DYNAMIC_RANGE_UNKNOWN;
ashleymills 11:dfd1e0afcb7b 140 }
ashleymills 11:dfd1e0afcb7b 141 rval &= (MMA8452_DYNAMIC_RANGE_MASK^0xFF);
ashleymills 11:dfd1e0afcb7b 142 return (MMA8452::DynamicRange)rval;
ashleymills 11:dfd1e0afcb7b 143 }
ashleymills 11:dfd1e0afcb7b 144
ashleymills 11:dfd1e0afcb7b 145 MMA8452::DataRateHz MMA8452::getDataRate() {
ashleymills 11:dfd1e0afcb7b 146 char rval = 0;
ashleymills 11:dfd1e0afcb7b 147 if(readRegister(MMA8452_CTRL_REG_1,&rval)) {
ashleymills 11:dfd1e0afcb7b 148 return MMA8452::RATE_UNKNOWN;
ashleymills 11:dfd1e0afcb7b 149 }
ashleymills 11:dfd1e0afcb7b 150 // logical AND with inverse of mask
ashleymills 11:dfd1e0afcb7b 151 rval = rval&(MMA8452_DATA_RATE_MASK^0xFF);
ashleymills 11:dfd1e0afcb7b 152 // shift back into position
ashleymills 11:dfd1e0afcb7b 153 rval >>= MMA8452_DATA_RATE_MASK_SHIFT;
ashleymills 11:dfd1e0afcb7b 154 return (MMA8452::DataRateHz)rval;
ashleymills 11:dfd1e0afcb7b 155 }
ashleymills 11:dfd1e0afcb7b 156
nherriot 0:bcf2aa85d7f9 157 // Reads xyz
ashleymills 12:172540ff6b8b 158 int MMA8452::readRawXYZ(char *dst) {
ashleymills 12:172540ff6b8b 159 if(_bitDepth==BIT_DEPTH_UNKNOWN) {
ashleymills 12:172540ff6b8b 160 return 1;
ashleymills 12:172540ff6b8b 161 }
ashleymills 12:172540ff6b8b 162 int readLen = 3;
ashleymills 12:172540ff6b8b 163 if(_bitDepth==BIT_DEPTH_12) {
ashleymills 12:172540ff6b8b 164 readLen = 6;
ashleymills 12:172540ff6b8b 165 }
ashleymills 12:172540ff6b8b 166 return readRegister(MMA8452_OUT_X_MSB,dst,readLen);
nherriot 1:ef026bf28798 167 }
nherriot 0:bcf2aa85d7f9 168
ashleymills 11:dfd1e0afcb7b 169 // apply an AND mask to a register. read register value, apply mask, write it back
ashleymills 11:dfd1e0afcb7b 170 int MMA8452::logicalANDRegister(char addr, char mask) {
ashleymills 11:dfd1e0afcb7b 171 char value = 0;
ashleymills 11:dfd1e0afcb7b 172 // read register value
ashleymills 11:dfd1e0afcb7b 173 if(readRegister(addr,&value)) {
ashleymills 11:dfd1e0afcb7b 174 return 0;
ashleymills 11:dfd1e0afcb7b 175 }
ashleymills 11:dfd1e0afcb7b 176 // apply mask
ashleymills 11:dfd1e0afcb7b 177 value &= mask;
ashleymills 11:dfd1e0afcb7b 178 return writeRegister(addr,value);
ashleymills 11:dfd1e0afcb7b 179 }
ashleymills 11:dfd1e0afcb7b 180
ashleymills 11:dfd1e0afcb7b 181
ashleymills 11:dfd1e0afcb7b 182 // apply an OR mask to a register. read register value, apply mask, write it back
ashleymills 11:dfd1e0afcb7b 183 int MMA8452::logicalORRegister(char addr, char mask) {
ashleymills 11:dfd1e0afcb7b 184 char value = 0;
ashleymills 11:dfd1e0afcb7b 185 // read register value
ashleymills 11:dfd1e0afcb7b 186 if(readRegister(addr,&value)) {
ashleymills 11:dfd1e0afcb7b 187 return 0;
ashleymills 11:dfd1e0afcb7b 188 }
ashleymills 11:dfd1e0afcb7b 189 // apply mask
ashleymills 11:dfd1e0afcb7b 190 value |= mask;
ashleymills 11:dfd1e0afcb7b 191 return writeRegister(addr,value);
ashleymills 11:dfd1e0afcb7b 192 }
ashleymills 11:dfd1e0afcb7b 193
ashleymills 11:dfd1e0afcb7b 194 // apply an OR mask to a register. read register value, apply mask, write it back
ashleymills 11:dfd1e0afcb7b 195 int MMA8452::logicalXORRegister(char addr, char mask) {
ashleymills 11:dfd1e0afcb7b 196 char value = 0;
ashleymills 11:dfd1e0afcb7b 197 // read register value
ashleymills 11:dfd1e0afcb7b 198 if(readRegister(addr,&value)) {
ashleymills 11:dfd1e0afcb7b 199 return 0;
ashleymills 11:dfd1e0afcb7b 200 }
ashleymills 11:dfd1e0afcb7b 201 // apply mask
ashleymills 11:dfd1e0afcb7b 202 value ^= mask;
ashleymills 11:dfd1e0afcb7b 203 return writeRegister(addr,value);
ashleymills 11:dfd1e0afcb7b 204 }
ashleymills 11:dfd1e0afcb7b 205
ashleymills 11:dfd1e0afcb7b 206 // Write register (The device must be placed in Standby Mode to change the value of the registers)
ashleymills 11:dfd1e0afcb7b 207 int MMA8452::writeRegister(char addr, char data) {
ashleymills 11:dfd1e0afcb7b 208 // what this actually does is the following
ashleymills 11:dfd1e0afcb7b 209 // 1. tell I2C bus to start transaction
ashleymills 11:dfd1e0afcb7b 210 // 2. tell slave we want to write (slave address & write flag)
ashleymills 11:dfd1e0afcb7b 211 // 3. send the write address
ashleymills 11:dfd1e0afcb7b 212 // 4. send the data to write
ashleymills 11:dfd1e0afcb7b 213 // 5. tell I2C bus to end transaction
ashleymills 11:dfd1e0afcb7b 214
ashleymills 11:dfd1e0afcb7b 215 // we can wrap this up in the I2C library write function
ashleymills 11:dfd1e0afcb7b 216 char buf[2] = {0,0};
ashleymills 11:dfd1e0afcb7b 217 buf[0] = addr;
ashleymills 11:dfd1e0afcb7b 218 buf[1] = data;
ashleymills 11:dfd1e0afcb7b 219 return _i2c.write(MMA8452_ADDRESS, buf,2);
ashleymills 11:dfd1e0afcb7b 220 // note, could also do return writeRegister(addr,&data,1);
nherriot 0:bcf2aa85d7f9 221 }
nherriot 0:bcf2aa85d7f9 222
ashleymills 11:dfd1e0afcb7b 223
ashleymills 11:dfd1e0afcb7b 224 int MMA8452::writeRegister(char addr, char *data, int nbytes) {
ashleymills 11:dfd1e0afcb7b 225 // writing multiple bytes is a little bit annoying because
ashleymills 11:dfd1e0afcb7b 226 // the I2C library doesn't support sending the address separately
ashleymills 11:dfd1e0afcb7b 227 // so we just do it manually
nherriot 0:bcf2aa85d7f9 228
ashleymills 11:dfd1e0afcb7b 229 // 1. tell I2C bus to start transaction
ashleymills 11:dfd1e0afcb7b 230 _i2c.start();
ashleymills 11:dfd1e0afcb7b 231 // 2. tell slave we want to write (slave address & write flag)
ashleymills 11:dfd1e0afcb7b 232 if(_i2c.write(_writeAddress)!=1) {
ashleymills 11:dfd1e0afcb7b 233 return 1;
ashleymills 11:dfd1e0afcb7b 234 }
ashleymills 11:dfd1e0afcb7b 235 // 3. send the write address
ashleymills 11:dfd1e0afcb7b 236 if(_i2c.write(addr)!=1) {
ashleymills 11:dfd1e0afcb7b 237 return 1;
ashleymills 11:dfd1e0afcb7b 238 }
ashleymills 11:dfd1e0afcb7b 239 // 4. send the data to write
ashleymills 11:dfd1e0afcb7b 240 for(int i=0; i<nbytes; i++) {
ashleymills 11:dfd1e0afcb7b 241 if(_i2c.write(data[i])!=1) {
ashleymills 11:dfd1e0afcb7b 242 return 1;
ashleymills 11:dfd1e0afcb7b 243 }
ashleymills 11:dfd1e0afcb7b 244 }
ashleymills 11:dfd1e0afcb7b 245 // 5. tell I2C bus to end transaction
ashleymills 11:dfd1e0afcb7b 246 _i2c.stop();
ashleymills 11:dfd1e0afcb7b 247 return 0;
ashleymills 11:dfd1e0afcb7b 248 }
ashleymills 11:dfd1e0afcb7b 249
ashleymills 11:dfd1e0afcb7b 250 int MMA8452::readRegister(char addr, char *dst, int nbytes) {
ashleymills 11:dfd1e0afcb7b 251 // this is a bit odd, but basically proceeds like this
ashleymills 11:dfd1e0afcb7b 252 // 1. Send a start command
ashleymills 11:dfd1e0afcb7b 253 // 2. Tell the slave we want to write (slave address & write flag)
ashleymills 11:dfd1e0afcb7b 254 // 3. Send the address of the register (addr)
ashleymills 11:dfd1e0afcb7b 255 // 4. Send another start command to delineate read portion
ashleymills 11:dfd1e0afcb7b 256 // 5. Tell the slave we want to read (slave address & read flag)
ashleymills 11:dfd1e0afcb7b 257 // 6. Read the register value bytes
ashleymills 11:dfd1e0afcb7b 258 // 7. Send a stop command
ashleymills 11:dfd1e0afcb7b 259
ashleymills 11:dfd1e0afcb7b 260 // we can wrap this process in the I2C library read and write commands
ashleymills 11:dfd1e0afcb7b 261 if(_i2c.write(MMA8452_ADDRESS,&addr,1,true)) {
ashleymills 11:dfd1e0afcb7b 262 return 1;
ashleymills 8:89272163f395 263 }
ashleymills 11:dfd1e0afcb7b 264 return _i2c.read(MMA8452_ADDRESS,dst,nbytes);
ashleymills 11:dfd1e0afcb7b 265 }
ashleymills 11:dfd1e0afcb7b 266
ashleymills 11:dfd1e0afcb7b 267 // most registers are 1 byte, so here is a convenience function
ashleymills 11:dfd1e0afcb7b 268 int MMA8452::readRegister(char addr, char *dst) {
ashleymills 11:dfd1e0afcb7b 269 return readRegister(addr,dst,1);
nherriot 0:bcf2aa85d7f9 270 }
ashleymills 11:dfd1e0afcb7b 271
ashleymills 11:dfd1e0afcb7b 272 void MMA8452::debugRegister(char reg) {
ashleymills 11:dfd1e0afcb7b 273 // get register value
ashleymills 11:dfd1e0afcb7b 274 char v = 0;
ashleymills 11:dfd1e0afcb7b 275 if(readRegister(reg,&v)) {
ashleymills 12:172540ff6b8b 276 DBG("Error reading specified register");
ashleymills 11:dfd1e0afcb7b 277 return;
ashleymills 11:dfd1e0afcb7b 278 }
ashleymills 11:dfd1e0afcb7b 279 // print out details
ashleymills 11:dfd1e0afcb7b 280 switch(reg) {
ashleymills 11:dfd1e0afcb7b 281 case MMA8452_CTRL_REG_1:
ashleymills 11:dfd1e0afcb7b 282 DBG("CTRL_REG_1 has value: 0x%x",v);
ashleymills 11:dfd1e0afcb7b 283 DBG(" 7 ALSP_RATE_1: %d",(v&0x80)>>7);
ashleymills 11:dfd1e0afcb7b 284 DBG(" 6 ALSP_RATE_0: %d",(v&0x40)>>6);
ashleymills 11:dfd1e0afcb7b 285 DBG(" 5 DR2: %d", (v&0x20)>>5);
ashleymills 11:dfd1e0afcb7b 286 DBG(" 4 DR1: %d", (v&0x10)>>4);
ashleymills 11:dfd1e0afcb7b 287 DBG(" 3 DR0: %d", (v&0x08)>>3);
ashleymills 11:dfd1e0afcb7b 288 DBG(" 2 LNOISE: %d", (v&0x04)>>2);
ashleymills 11:dfd1e0afcb7b 289 DBG(" 1 FREAD: %d", (v&0x02)>>1);
ashleymills 11:dfd1e0afcb7b 290 DBG(" 0 ACTIVE: %d", (v&0x01));
ashleymills 11:dfd1e0afcb7b 291 break;
ashleymills 11:dfd1e0afcb7b 292
ashleymills 11:dfd1e0afcb7b 293 case MMA8452_XYZ_DATA_CFG:
ashleymills 11:dfd1e0afcb7b 294 DBG("XYZ_DATA_CFG has value: 0x%x",v);
ashleymills 11:dfd1e0afcb7b 295 DBG(" 7 Unused: %d", (v&0x80)>>7);
ashleymills 11:dfd1e0afcb7b 296 DBG(" 6 0: %d", (v&0x40)>>6);
ashleymills 11:dfd1e0afcb7b 297 DBG(" 5 0: %d", (v&0x20)>>5);
ashleymills 11:dfd1e0afcb7b 298 DBG(" 4 HPF_Out: %d",(v&0x10)>>4);
ashleymills 11:dfd1e0afcb7b 299 DBG(" 3 0: %d", (v&0x08)>>3);
ashleymills 11:dfd1e0afcb7b 300 DBG(" 2 0: %d", (v&0x04)>>2);
ashleymills 11:dfd1e0afcb7b 301 DBG(" 1 FS1: %d", (v&0x02)>>1);
ashleymills 11:dfd1e0afcb7b 302 DBG(" 0 FS0: %d", (v&0x01));
ashleymills 11:dfd1e0afcb7b 303 switch(v&0x03) {
ashleymills 11:dfd1e0afcb7b 304 case 0:
ashleymills 11:dfd1e0afcb7b 305 DBG("Dynamic range: 2G");
ashleymills 11:dfd1e0afcb7b 306 break;
ashleymills 11:dfd1e0afcb7b 307 case 1:
ashleymills 11:dfd1e0afcb7b 308 DBG("Dynamic range: 4G");
ashleymills 11:dfd1e0afcb7b 309 break;
ashleymills 11:dfd1e0afcb7b 310 case 2:
ashleymills 11:dfd1e0afcb7b 311 DBG("Dynamic range: 8G");
ashleymills 11:dfd1e0afcb7b 312 break;
ashleymills 11:dfd1e0afcb7b 313 default:
ashleymills 11:dfd1e0afcb7b 314 DBG("Unknown dynamic range");
ashleymills 11:dfd1e0afcb7b 315 break;
ashleymills 11:dfd1e0afcb7b 316 }
ashleymills 11:dfd1e0afcb7b 317 break;
ashleymills 11:dfd1e0afcb7b 318
ashleymills 12:172540ff6b8b 319 case MMA8452_STATUS:
ashleymills 12:172540ff6b8b 320 DBG("STATUS has value: 0x%x",v);
ashleymills 12:172540ff6b8b 321 DBG(" 7 ZYXOW: %d",(v&0x80)>>7);
ashleymills 12:172540ff6b8b 322 DBG(" 6 ZOW: %d", (v&0x40)>>6);
ashleymills 12:172540ff6b8b 323 DBG(" 5 YOW: %d", (v&0x20)>>5);
ashleymills 12:172540ff6b8b 324 DBG(" 4 XOW: %d", (v&0x10)>>4);
ashleymills 12:172540ff6b8b 325 DBG(" 3 ZYXDR: %d",(v&0x08)>>3);
ashleymills 12:172540ff6b8b 326 DBG(" 2 ZDR: %d", (v&0x04)>>2);
ashleymills 12:172540ff6b8b 327 DBG(" 1 YDR: %d", (v&0x02)>>1);
ashleymills 12:172540ff6b8b 328 DBG(" 0 XDR: %d", (v&0x01));
ashleymills 12:172540ff6b8b 329 break;
ashleymills 12:172540ff6b8b 330
ashleymills 11:dfd1e0afcb7b 331 default:
ashleymills 11:dfd1e0afcb7b 332 DBG("Unknown register address: 0x%x",reg);
ashleymills 11:dfd1e0afcb7b 333 break;
ashleymills 11:dfd1e0afcb7b 334 }
ashleymills 11:dfd1e0afcb7b 335 }