Taouil Yassine
/
nrf52-sdk
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nrf51-sdk
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nrf51.h
00001 /* 00002 * Copyright (c) Nordic Semiconductor ASA 00003 * All rights reserved. 00004 * 00005 * Redistribution and use in source and binary forms, with or without modification, 00006 * are permitted provided that the following conditions are met: 00007 * 00008 * 1. Redistributions of source code must retain the above copyright notice, this 00009 * list of conditions and the following disclaimer. 00010 * 00011 * 2. Redistributions in binary form must reproduce the above copyright notice, this 00012 * list of conditions and the following disclaimer in the documentation and/or 00013 * other materials provided with the distribution. 00014 * 00015 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other 00016 * contributors to this software may be used to endorse or promote products 00017 * derived from this software without specific prior written permission. 00018 * 00019 * 00020 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00021 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00022 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00023 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00024 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00025 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00026 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00027 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00028 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00029 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00030 * 00031 */ 00032 00033 #ifndef NRF51_H 00034 #define NRF51_H 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 00041 /* ------------------------- Interrupt Number Definition ------------------------ */ 00042 00043 typedef enum { 00044 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ 00045 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ 00046 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ 00047 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ 00048 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ 00049 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ 00050 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ 00051 SysTick_IRQn = -1, /*!< 15 System Tick Timer */ 00052 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */ 00053 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 00054 RADIO_IRQn = 1, /*!< 1 RADIO */ 00055 UART0_IRQn = 2, /*!< 2 UART0 */ 00056 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */ 00057 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */ 00058 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 00059 ADC_IRQn = 7, /*!< 7 ADC */ 00060 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 00061 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 00062 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 00063 RTC0_IRQn = 11, /*!< 11 RTC0 */ 00064 TEMP_IRQn = 12, /*!< 12 TEMP */ 00065 RNG_IRQn = 13, /*!< 13 RNG */ 00066 ECB_IRQn = 14, /*!< 14 ECB */ 00067 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 00068 WDT_IRQn = 16, /*!< 16 WDT */ 00069 RTC1_IRQn = 17, /*!< 17 RTC1 */ 00070 QDEC_IRQn = 18, /*!< 18 QDEC */ 00071 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ 00072 SWI0_IRQn = 20, /*!< 20 SWI0 */ 00073 SWI1_IRQn = 21, /*!< 21 SWI1 */ 00074 SWI2_IRQn = 22, /*!< 22 SWI2 */ 00075 SWI3_IRQn = 23, /*!< 23 SWI3 */ 00076 SWI4_IRQn = 24, /*!< 24 SWI4 */ 00077 SWI5_IRQn = 25 /*!< 25 SWI5 */ 00078 } IRQn_Type ; 00079 00080 00081 /** @addtogroup Configuration_of_CMSIS 00082 * @{ 00083 */ 00084 00085 00086 /* ================================================================================ */ 00087 /* ================ Processor and Core Peripheral Section ================ */ 00088 /* ================================================================================ */ 00089 00090 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ 00091 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */ 00092 #define __MPU_PRESENT 0 /*!< MPU present or not */ 00093 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 00094 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00095 /** @} */ /* End of group Configuration_of_CMSIS */ 00096 00097 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ 00098 #include "system_nrf51.h" /*!< nrf51 System */ 00099 00100 00101 /* ================================================================================ */ 00102 /* ================ Device Specific Peripheral Section ================ */ 00103 /* ================================================================================ */ 00104 00105 00106 /** @addtogroup Device_Peripheral_Registers 00107 * @{ 00108 */ 00109 00110 00111 /* ------------------- Start of section using anonymous unions ------------------ */ 00112 #if defined(__CC_ARM) 00113 #pragma push 00114 #pragma anon_unions 00115 #elif defined(__ICCARM__) 00116 #pragma language=extended 00117 #elif defined(__GNUC__) 00118 /* anonymous unions are enabled by default */ 00119 #elif defined(__TMS470__) 00120 /* anonymous unions are enabled by default */ 00121 #elif defined(__TASKING__) 00122 #pragma warning 586 00123 #else 00124 #warning Not supported compiler type 00125 #endif 00126 00127 00128 typedef struct { 00129 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */ 00130 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */ 00131 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */ 00132 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */ 00133 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */ 00134 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */ 00135 } AMLI_RAMPRI_Type; 00136 00137 typedef struct { 00138 __IO uint32_t SCK; /*!< Pin select for SCK. */ 00139 __IO uint32_t MOSI; /*!< Pin select for MOSI. */ 00140 __IO uint32_t MISO; /*!< Pin select for MISO. */ 00141 } SPIM_PSEL_Type; 00142 00143 typedef struct { 00144 __IO uint32_t PTR; /*!< Data pointer. */ 00145 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */ 00146 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */ 00147 } SPIM_RXD_Type; 00148 00149 typedef struct { 00150 __IO uint32_t PTR; /*!< Data pointer. */ 00151 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */ 00152 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */ 00153 } SPIM_TXD_Type; 00154 00155 typedef struct { 00156 __O uint32_t EN; /*!< Enable channel group. */ 00157 __O uint32_t DIS; /*!< Disable channel group. */ 00158 } PPI_TASKS_CHG_Type; 00159 00160 typedef struct { 00161 __IO uint32_t EEP; /*!< Channel event end-point. */ 00162 __IO uint32_t TEP; /*!< Channel task end-point. */ 00163 } PPI_CH_Type; 00164 00165 00166 /* ================================================================================ */ 00167 /* ================ POWER ================ */ 00168 /* ================================================================================ */ 00169 00170 00171 /** 00172 * @brief Power Control. (POWER) 00173 */ 00174 00175 typedef struct { /*!< POWER Structure */ 00176 __I uint32_t RESERVED0[30]; 00177 __O uint32_t TASKS_CONSTLAT ; /*!< Enable constant latency mode. */ 00178 __O uint32_t TASKS_LOWPWR ; /*!< Enable low power mode (variable latency). */ 00179 __I uint32_t RESERVED1[34]; 00180 __IO uint32_t EVENTS_POFWARN ; /*!< Power failure warning. */ 00181 __I uint32_t RESERVED2[126]; 00182 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00183 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00184 __I uint32_t RESERVED3[61]; 00185 __IO uint32_t RESETREAS ; /*!< Reset reason. */ 00186 __I uint32_t RESERVED4[9]; 00187 __I uint32_t RAMSTATUS ; /*!< Ram status register. */ 00188 __I uint32_t RESERVED5[53]; 00189 __O uint32_t SYSTEMOFF ; /*!< System off register. */ 00190 __I uint32_t RESERVED6[3]; 00191 __IO uint32_t POFCON ; /*!< Power failure configuration. */ 00192 __I uint32_t RESERVED7[2]; 00193 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained 00194 register. */ 00195 __I uint32_t RESERVED8; 00196 __IO uint32_t RAMON ; /*!< Ram on/off. */ 00197 __I uint32_t RESERVED9[7]; 00198 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register 00199 is a retained register. */ 00200 __I uint32_t RESERVED10[3]; 00201 __IO uint32_t RAMONB ; /*!< Ram on/off. */ 00202 __I uint32_t RESERVED11[8]; 00203 __IO uint32_t DCDCEN ; /*!< DCDC converter enable configuration register. */ 00204 __I uint32_t RESERVED12[291]; 00205 __IO uint32_t DCDCFORCE ; /*!< DCDC power-up force register. */ 00206 } NRF_POWER_Type; 00207 00208 00209 /* ================================================================================ */ 00210 /* ================ CLOCK ================ */ 00211 /* ================================================================================ */ 00212 00213 00214 /** 00215 * @brief Clock control. (CLOCK) 00216 */ 00217 00218 typedef struct { /*!< CLOCK Structure */ 00219 __O uint32_t TASKS_HFCLKSTART ; /*!< Start HFCLK clock source. */ 00220 __O uint32_t TASKS_HFCLKSTOP ; /*!< Stop HFCLK clock source. */ 00221 __O uint32_t TASKS_LFCLKSTART ; /*!< Start LFCLK clock source. */ 00222 __O uint32_t TASKS_LFCLKSTOP ; /*!< Stop LFCLK clock source. */ 00223 __O uint32_t TASKS_CAL ; /*!< Start calibration of LFCLK RC oscillator. */ 00224 __O uint32_t TASKS_CTSTART ; /*!< Start calibration timer. */ 00225 __O uint32_t TASKS_CTSTOP ; /*!< Stop calibration timer. */ 00226 __I uint32_t RESERVED0[57]; 00227 __IO uint32_t EVENTS_HFCLKSTARTED ; /*!< HFCLK oscillator started. */ 00228 __IO uint32_t EVENTS_LFCLKSTARTED ; /*!< LFCLK oscillator started. */ 00229 __I uint32_t RESERVED1; 00230 __IO uint32_t EVENTS_DONE ; /*!< Calibration of LFCLK RC oscillator completed. */ 00231 __IO uint32_t EVENTS_CTTO ; /*!< Calibration timer timeout. */ 00232 __I uint32_t RESERVED2[124]; 00233 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00234 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00235 __I uint32_t RESERVED3[63]; 00236 __I uint32_t HFCLKRUN ; /*!< Task HFCLKSTART trigger status. */ 00237 __I uint32_t HFCLKSTAT ; /*!< High frequency clock status. */ 00238 __I uint32_t RESERVED4; 00239 __I uint32_t LFCLKRUN ; /*!< Task LFCLKSTART triggered status. */ 00240 __I uint32_t LFCLKSTAT ; /*!< Low frequency clock status. */ 00241 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is 00242 triggered. */ 00243 __I uint32_t RESERVED5[62]; 00244 __IO uint32_t LFCLKSRC ; /*!< Clock source for the LFCLK clock. */ 00245 __I uint32_t RESERVED6[7]; 00246 __IO uint32_t CTIV ; /*!< Calibration timer interval. */ 00247 __I uint32_t RESERVED7[5]; 00248 __IO uint32_t XTALFREQ ; /*!< Crystal frequency. */ 00249 } NRF_CLOCK_Type; 00250 00251 00252 /* ================================================================================ */ 00253 /* ================ MPU ================ */ 00254 /* ================================================================================ */ 00255 00256 00257 /** 00258 * @brief Memory Protection Unit. (MPU) 00259 */ 00260 00261 typedef struct { /*!< MPU Structure */ 00262 __I uint32_t RESERVED0[330]; 00263 __IO uint32_t PERR0 ; /*!< Configuration of peripherals in mpu regions. */ 00264 __IO uint32_t RLENR0 ; /*!< Length of RAM region 0. */ 00265 __I uint32_t RESERVED1[52]; 00266 __IO uint32_t PROTENSET0 ; /*!< Erase and write protection bit enable set register. */ 00267 __IO uint32_t PROTENSET1 ; /*!< Erase and write protection bit enable set register. */ 00268 __IO uint32_t DISABLEINDEBUG ; /*!< Disable erase and write protection mechanism in debug mode. */ 00269 __IO uint32_t PROTBLOCKSIZE ; /*!< Erase and write protection block size. */ 00270 } NRF_MPU_Type; 00271 00272 00273 /* ================================================================================ */ 00274 /* ================ AMLI ================ */ 00275 /* ================================================================================ */ 00276 00277 00278 /** 00279 * @brief AHB Multi-Layer Interface. (AMLI) 00280 */ 00281 00282 typedef struct { /*!< AMLI Structure */ 00283 __I uint32_t RESERVED0[896]; 00284 AMLI_RAMPRI_Type RAMPRI ; /*!< RAM configurable priority configuration structure. */ 00285 } NRF_AMLI_Type; 00286 00287 00288 /* ================================================================================ */ 00289 /* ================ RADIO ================ */ 00290 /* ================================================================================ */ 00291 00292 00293 /** 00294 * @brief The radio. (RADIO) 00295 */ 00296 00297 typedef struct { /*!< RADIO Structure */ 00298 __O uint32_t TASKS_TXEN ; /*!< Enable radio in TX mode. */ 00299 __O uint32_t TASKS_RXEN ; /*!< Enable radio in RX mode. */ 00300 __O uint32_t TASKS_START ; /*!< Start radio. */ 00301 __O uint32_t TASKS_STOP ; /*!< Stop radio. */ 00302 __O uint32_t TASKS_DISABLE ; /*!< Disable radio. */ 00303 __O uint32_t TASKS_RSSISTART ; /*!< Start the RSSI and take one sample of the receive signal strength. */ 00304 __O uint32_t TASKS_RSSISTOP ; /*!< Stop the RSSI measurement. */ 00305 __O uint32_t TASKS_BCSTART ; /*!< Start the bit counter. */ 00306 __O uint32_t TASKS_BCSTOP ; /*!< Stop the bit counter. */ 00307 __I uint32_t RESERVED0[55]; 00308 __IO uint32_t EVENTS_READY ; /*!< Ready event. */ 00309 __IO uint32_t EVENTS_ADDRESS ; /*!< Address event. */ 00310 __IO uint32_t EVENTS_PAYLOAD ; /*!< Payload event. */ 00311 __IO uint32_t EVENTS_END ; /*!< End event. */ 00312 __IO uint32_t EVENTS_DISABLED ; /*!< Disable event. */ 00313 __IO uint32_t EVENTS_DEVMATCH ; /*!< A device address match occurred on the last received packet. */ 00314 __IO uint32_t EVENTS_DEVMISS ; /*!< No device address match occurred on the last received packet. */ 00315 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI 00316 sample is ready for readout at the RSSISAMPLE register. */ 00317 __I uint32_t RESERVED1[2]; 00318 __IO uint32_t EVENTS_BCMATCH ; /*!< Bit counter reached bit count value specified in BCC register. */ 00319 __I uint32_t RESERVED2[53]; 00320 __IO uint32_t SHORTS ; /*!< Shortcuts for the radio. */ 00321 __I uint32_t RESERVED3[64]; 00322 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00323 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00324 __I uint32_t RESERVED4[61]; 00325 __I uint32_t CRCSTATUS ; /*!< CRC status of received packet. */ 00326 __I uint32_t RESERVED5; 00327 __I uint32_t RXMATCH ; /*!< Received address. */ 00328 __I uint32_t RXCRC ; /*!< Received CRC. */ 00329 __I uint32_t DAI ; /*!< Device address match index. */ 00330 __I uint32_t RESERVED6[60]; 00331 __IO uint32_t PACKETPTR ; /*!< Packet pointer. Decision point: START task. */ 00332 __IO uint32_t FREQUENCY ; /*!< Frequency. */ 00333 __IO uint32_t TXPOWER ; /*!< Output power. */ 00334 __IO uint32_t MODE ; /*!< Data rate and modulation. */ 00335 __IO uint32_t PCNF0 ; /*!< Packet configuration 0. */ 00336 __IO uint32_t PCNF1 ; /*!< Packet configuration 1. */ 00337 __IO uint32_t BASE0 ; /*!< Radio base address 0. Decision point: START task. */ 00338 __IO uint32_t BASE1 ; /*!< Radio base address 1. Decision point: START task. */ 00339 __IO uint32_t PREFIX0 ; /*!< Prefixes bytes for logical addresses 0 to 3. */ 00340 __IO uint32_t PREFIX1 ; /*!< Prefixes bytes for logical addresses 4 to 7. */ 00341 __IO uint32_t TXADDRESS ; /*!< Transmit address select. */ 00342 __IO uint32_t RXADDRESSES ; /*!< Receive address select. */ 00343 __IO uint32_t CRCCNF ; /*!< CRC configuration. */ 00344 __IO uint32_t CRCPOLY ; /*!< CRC polynomial. */ 00345 __IO uint32_t CRCINIT ; /*!< CRC initial value. */ 00346 __IO uint32_t TEST ; /*!< Test features enable register. */ 00347 __IO uint32_t TIFS ; /*!< Inter Frame Spacing in microseconds. */ 00348 __I uint32_t RSSISAMPLE ; /*!< RSSI sample. */ 00349 __I uint32_t RESERVED7; 00350 __I uint32_t STATE ; /*!< Current radio state. */ 00351 __IO uint32_t DATAWHITEIV ; /*!< Data whitening initial value. */ 00352 __I uint32_t RESERVED8[2]; 00353 __IO uint32_t BCC ; /*!< Bit counter compare. */ 00354 __I uint32_t RESERVED9[39]; 00355 __IO uint32_t DAB[8]; /*!< Device address base segment. */ 00356 __IO uint32_t DAP[8]; /*!< Device address prefix. */ 00357 __IO uint32_t DACNF ; /*!< Device address match configuration. */ 00358 __I uint32_t RESERVED10[56]; 00359 __IO uint32_t OVERRIDE0 ; /*!< Trim value override register 0. */ 00360 __IO uint32_t OVERRIDE1 ; /*!< Trim value override register 1. */ 00361 __IO uint32_t OVERRIDE2 ; /*!< Trim value override register 2. */ 00362 __IO uint32_t OVERRIDE3 ; /*!< Trim value override register 3. */ 00363 __IO uint32_t OVERRIDE4 ; /*!< Trim value override register 4. */ 00364 __I uint32_t RESERVED11[561]; 00365 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00366 } NRF_RADIO_Type; 00367 00368 00369 /* ================================================================================ */ 00370 /* ================ UART ================ */ 00371 /* ================================================================================ */ 00372 00373 00374 /** 00375 * @brief Universal Asynchronous Receiver/Transmitter. (UART) 00376 */ 00377 00378 typedef struct { /*!< UART Structure */ 00379 __O uint32_t TASKS_STARTRX ; /*!< Start UART receiver. */ 00380 __O uint32_t TASKS_STOPRX ; /*!< Stop UART receiver. */ 00381 __O uint32_t TASKS_STARTTX ; /*!< Start UART transmitter. */ 00382 __O uint32_t TASKS_STOPTX ; /*!< Stop UART transmitter. */ 00383 __I uint32_t RESERVED0[3]; 00384 __O uint32_t TASKS_SUSPEND ; /*!< Suspend UART. */ 00385 __I uint32_t RESERVED1[56]; 00386 __IO uint32_t EVENTS_CTS ; /*!< CTS activated. */ 00387 __IO uint32_t EVENTS_NCTS ; /*!< CTS deactivated. */ 00388 __IO uint32_t EVENTS_RXDRDY ; /*!< Data received in RXD. */ 00389 __I uint32_t RESERVED2[4]; 00390 __IO uint32_t EVENTS_TXDRDY ; /*!< Data sent from TXD. */ 00391 __I uint32_t RESERVED3; 00392 __IO uint32_t EVENTS_ERROR ; /*!< Error detected. */ 00393 __I uint32_t RESERVED4[7]; 00394 __IO uint32_t EVENTS_RXTO ; /*!< Receiver timeout. */ 00395 __I uint32_t RESERVED5[46]; 00396 __IO uint32_t SHORTS ; /*!< Shortcuts for UART. */ 00397 __I uint32_t RESERVED6[64]; 00398 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00399 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00400 __I uint32_t RESERVED7[93]; 00401 __IO uint32_t ERRORSRC ; /*!< Error source. Write error field to 1 to clear error. */ 00402 __I uint32_t RESERVED8[31]; 00403 __IO uint32_t ENABLE ; /*!< Enable UART and acquire IOs. */ 00404 __I uint32_t RESERVED9; 00405 __IO uint32_t PSELRTS ; /*!< Pin select for RTS. */ 00406 __IO uint32_t PSELTXD ; /*!< Pin select for TXD. */ 00407 __IO uint32_t PSELCTS ; /*!< Pin select for CTS. */ 00408 __IO uint32_t PSELRXD ; /*!< Pin select for RXD. */ 00409 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced. 00410 Once read the character is consumed. If read when no character 00411 available, the UART will stop working. */ 00412 __O uint32_t TXD ; /*!< TXD register. */ 00413 __I uint32_t RESERVED10; 00414 __IO uint32_t BAUDRATE ; /*!< UART Baudrate. */ 00415 __I uint32_t RESERVED11[17]; 00416 __IO uint32_t CONFIG ; /*!< Configuration of parity and hardware flow control register. */ 00417 __I uint32_t RESERVED12[675]; 00418 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00419 } NRF_UART_Type; 00420 00421 00422 /* ================================================================================ */ 00423 /* ================ SPI ================ */ 00424 /* ================================================================================ */ 00425 00426 00427 /** 00428 * @brief SPI master 0. (SPI) 00429 */ 00430 00431 typedef struct { /*!< SPI Structure */ 00432 __I uint32_t RESERVED0[66]; 00433 __IO uint32_t EVENTS_READY ; /*!< TXD byte sent and RXD byte received. */ 00434 __I uint32_t RESERVED1[126]; 00435 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00436 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00437 __I uint32_t RESERVED2[125]; 00438 __IO uint32_t ENABLE ; /*!< Enable SPI. */ 00439 __I uint32_t RESERVED3; 00440 __IO uint32_t PSELSCK ; /*!< Pin select for SCK. */ 00441 __IO uint32_t PSELMOSI ; /*!< Pin select for MOSI. */ 00442 __IO uint32_t PSELMISO ; /*!< Pin select for MISO. */ 00443 __I uint32_t RESERVED4; 00444 __I uint32_t RXD ; /*!< RX data. */ 00445 __IO uint32_t TXD ; /*!< TX data. */ 00446 __I uint32_t RESERVED5; 00447 __IO uint32_t FREQUENCY ; /*!< SPI frequency */ 00448 __I uint32_t RESERVED6[11]; 00449 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00450 __I uint32_t RESERVED7[681]; 00451 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00452 } NRF_SPI_Type; 00453 00454 00455 /* ================================================================================ */ 00456 /* ================ TWI ================ */ 00457 /* ================================================================================ */ 00458 00459 00460 /** 00461 * @brief Two-wire interface master 0. (TWI) 00462 */ 00463 00464 typedef struct { /*!< TWI Structure */ 00465 __O uint32_t TASKS_STARTRX ; /*!< Start 2-Wire master receive sequence. */ 00466 __I uint32_t RESERVED0; 00467 __O uint32_t TASKS_STARTTX ; /*!< Start 2-Wire master transmit sequence. */ 00468 __I uint32_t RESERVED1[2]; 00469 __O uint32_t TASKS_STOP ; /*!< Stop 2-Wire transaction. */ 00470 __I uint32_t RESERVED2; 00471 __O uint32_t TASKS_SUSPEND ; /*!< Suspend 2-Wire transaction. */ 00472 __O uint32_t TASKS_RESUME ; /*!< Resume 2-Wire transaction. */ 00473 __I uint32_t RESERVED3[56]; 00474 __IO uint32_t EVENTS_STOPPED ; /*!< Two-wire stopped. */ 00475 __IO uint32_t EVENTS_RXDREADY ; /*!< Two-wire ready to deliver new RXD byte received. */ 00476 __I uint32_t RESERVED4[4]; 00477 __IO uint32_t EVENTS_TXDSENT ; /*!< Two-wire finished sending last TXD byte. */ 00478 __I uint32_t RESERVED5; 00479 __IO uint32_t EVENTS_ERROR ; /*!< Two-wire error detected. */ 00480 __I uint32_t RESERVED6[4]; 00481 __IO uint32_t EVENTS_BB ; /*!< Two-wire byte boundary. */ 00482 __I uint32_t RESERVED7[3]; 00483 __IO uint32_t EVENTS_SUSPENDED ; /*!< Two-wire suspended. */ 00484 __I uint32_t RESERVED8[45]; 00485 __IO uint32_t SHORTS ; /*!< Shortcuts for TWI. */ 00486 __I uint32_t RESERVED9[64]; 00487 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00488 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00489 __I uint32_t RESERVED10[110]; 00490 __IO uint32_t ERRORSRC ; /*!< Two-wire error source. Write error field to 1 to clear error. */ 00491 __I uint32_t RESERVED11[14]; 00492 __IO uint32_t ENABLE ; /*!< Enable two-wire master. */ 00493 __I uint32_t RESERVED12; 00494 __IO uint32_t PSELSCL ; /*!< Pin select for SCL. */ 00495 __IO uint32_t PSELSDA ; /*!< Pin select for SDA. */ 00496 __I uint32_t RESERVED13[2]; 00497 __I uint32_t RXD ; /*!< RX data register. */ 00498 __IO uint32_t TXD ; /*!< TX data register. */ 00499 __I uint32_t RESERVED14; 00500 __IO uint32_t FREQUENCY ; /*!< Two-wire frequency. */ 00501 __I uint32_t RESERVED15[24]; 00502 __IO uint32_t ADDRESS ; /*!< Address used in the two-wire transfer. */ 00503 __I uint32_t RESERVED16[668]; 00504 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00505 } NRF_TWI_Type; 00506 00507 00508 /* ================================================================================ */ 00509 /* ================ SPIS ================ */ 00510 /* ================================================================================ */ 00511 00512 00513 /** 00514 * @brief SPI slave 1. (SPIS) 00515 */ 00516 00517 typedef struct { /*!< SPIS Structure */ 00518 __I uint32_t RESERVED0[9]; 00519 __O uint32_t TASKS_ACQUIRE ; /*!< Acquire SPI semaphore. */ 00520 __O uint32_t TASKS_RELEASE ; /*!< Release SPI semaphore. */ 00521 __I uint32_t RESERVED1[54]; 00522 __IO uint32_t EVENTS_END ; /*!< Granted transaction completed. */ 00523 __I uint32_t RESERVED2[2]; 00524 __IO uint32_t EVENTS_ENDRX ; /*!< End of RXD buffer reached */ 00525 __I uint32_t RESERVED3[5]; 00526 __IO uint32_t EVENTS_ACQUIRED ; /*!< Semaphore acquired. */ 00527 __I uint32_t RESERVED4[53]; 00528 __IO uint32_t SHORTS ; /*!< Shortcuts for SPIS. */ 00529 __I uint32_t RESERVED5[64]; 00530 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00531 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00532 __I uint32_t RESERVED6[61]; 00533 __I uint32_t SEMSTAT ; /*!< Semaphore status. */ 00534 __I uint32_t RESERVED7[15]; 00535 __IO uint32_t STATUS ; /*!< Status from last transaction. */ 00536 __I uint32_t RESERVED8[47]; 00537 __IO uint32_t ENABLE ; /*!< Enable SPIS. */ 00538 __I uint32_t RESERVED9; 00539 __IO uint32_t PSELSCK ; /*!< Pin select for SCK. */ 00540 __IO uint32_t PSELMISO ; /*!< Pin select for MISO. */ 00541 __IO uint32_t PSELMOSI ; /*!< Pin select for MOSI. */ 00542 __IO uint32_t PSELCSN ; /*!< Pin select for CSN. */ 00543 __I uint32_t RESERVED10[7]; 00544 __IO uint32_t RXDPTR ; /*!< RX data pointer. */ 00545 __IO uint32_t MAXRX ; /*!< Maximum number of bytes in the receive buffer. */ 00546 __I uint32_t AMOUNTRX ; /*!< Number of bytes received in last granted transaction. */ 00547 __I uint32_t RESERVED11; 00548 __IO uint32_t TXDPTR ; /*!< TX data pointer. */ 00549 __IO uint32_t MAXTX ; /*!< Maximum number of bytes in the transmit buffer. */ 00550 __I uint32_t AMOUNTTX ; /*!< Number of bytes transmitted in last granted transaction. */ 00551 __I uint32_t RESERVED12; 00552 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00553 __I uint32_t RESERVED13; 00554 __IO uint32_t DEF ; /*!< Default character. */ 00555 __I uint32_t RESERVED14[24]; 00556 __IO uint32_t ORC ; /*!< Over-read character. */ 00557 __I uint32_t RESERVED15[654]; 00558 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00559 } NRF_SPIS_Type; 00560 00561 00562 /* ================================================================================ */ 00563 /* ================ SPIM ================ */ 00564 /* ================================================================================ */ 00565 00566 00567 /** 00568 * @brief SPI master with easyDMA 1. (SPIM) 00569 */ 00570 00571 typedef struct { /*!< SPIM Structure */ 00572 __I uint32_t RESERVED0[4]; 00573 __O uint32_t TASKS_START ; /*!< Start SPI transaction. */ 00574 __O uint32_t TASKS_STOP ; /*!< Stop SPI transaction. */ 00575 __I uint32_t RESERVED1; 00576 __O uint32_t TASKS_SUSPEND ; /*!< Suspend SPI transaction. */ 00577 __O uint32_t TASKS_RESUME ; /*!< Resume SPI transaction. */ 00578 __I uint32_t RESERVED2[56]; 00579 __IO uint32_t EVENTS_STOPPED ; /*!< SPI transaction has stopped. */ 00580 __I uint32_t RESERVED3[2]; 00581 __IO uint32_t EVENTS_ENDRX ; /*!< End of RXD buffer reached. */ 00582 __I uint32_t RESERVED4[3]; 00583 __IO uint32_t EVENTS_ENDTX ; /*!< End of TXD buffer reached. */ 00584 __I uint32_t RESERVED5[10]; 00585 __IO uint32_t EVENTS_STARTED ; /*!< Transaction started. */ 00586 __I uint32_t RESERVED6[109]; 00587 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00588 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00589 __I uint32_t RESERVED7[125]; 00590 __IO uint32_t ENABLE ; /*!< Enable SPIM. */ 00591 __I uint32_t RESERVED8; 00592 SPIM_PSEL_Type PSEL ; /*!< Pin select configuration. */ 00593 __I uint32_t RESERVED9[4]; 00594 __IO uint32_t FREQUENCY ; /*!< SPI frequency. */ 00595 __I uint32_t RESERVED10[3]; 00596 SPIM_RXD_Type RXD ; /*!< RXD EasyDMA configuration and status. */ 00597 __I uint32_t RESERVED11; 00598 SPIM_TXD_Type TXD ; /*!< TXD EasyDMA configuration and status. */ 00599 __I uint32_t RESERVED12; 00600 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00601 __I uint32_t RESERVED13[26]; 00602 __IO uint32_t ORC ; /*!< Over-read character. */ 00603 __I uint32_t RESERVED14[654]; 00604 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00605 } NRF_SPIM_Type; 00606 00607 00608 /* ================================================================================ */ 00609 /* ================ GPIOTE ================ */ 00610 /* ================================================================================ */ 00611 00612 00613 /** 00614 * @brief GPIO tasks and events. (GPIOTE) 00615 */ 00616 00617 typedef struct { /*!< GPIOTE Structure */ 00618 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */ 00619 __I uint32_t RESERVED0[60]; 00620 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */ 00621 __I uint32_t RESERVED1[27]; 00622 __IO uint32_t EVENTS_PORT ; /*!< Event generated from multiple pins. */ 00623 __I uint32_t RESERVED2[97]; 00624 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00625 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00626 __I uint32_t RESERVED3[129]; 00627 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */ 00628 __I uint32_t RESERVED4[695]; 00629 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00630 } NRF_GPIOTE_Type; 00631 00632 00633 /* ================================================================================ */ 00634 /* ================ ADC ================ */ 00635 /* ================================================================================ */ 00636 00637 00638 /** 00639 * @brief Analog to digital converter. (ADC) 00640 */ 00641 00642 typedef struct { /*!< ADC Structure */ 00643 __O uint32_t TASKS_START ; /*!< Start an ADC conversion. */ 00644 __O uint32_t TASKS_STOP ; /*!< Stop ADC. */ 00645 __I uint32_t RESERVED0[62]; 00646 __IO uint32_t EVENTS_END ; /*!< ADC conversion complete. */ 00647 __I uint32_t RESERVED1[128]; 00648 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00649 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00650 __I uint32_t RESERVED2[61]; 00651 __I uint32_t BUSY ; /*!< ADC busy register. */ 00652 __I uint32_t RESERVED3[63]; 00653 __IO uint32_t ENABLE ; /*!< ADC enable. */ 00654 __IO uint32_t CONFIG ; /*!< ADC configuration register. */ 00655 __I uint32_t RESULT ; /*!< Result of ADC conversion. */ 00656 __I uint32_t RESERVED4[700]; 00657 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00658 } NRF_ADC_Type; 00659 00660 00661 /* ================================================================================ */ 00662 /* ================ TIMER ================ */ 00663 /* ================================================================================ */ 00664 00665 00666 /** 00667 * @brief Timer 0. (TIMER) 00668 */ 00669 00670 typedef struct { /*!< TIMER Structure */ 00671 __O uint32_t TASKS_START ; /*!< Start Timer. */ 00672 __O uint32_t TASKS_STOP ; /*!< Stop Timer. */ 00673 __O uint32_t TASKS_COUNT ; /*!< Increment Timer (In counter mode). */ 00674 __O uint32_t TASKS_CLEAR ; /*!< Clear timer. */ 00675 __O uint32_t TASKS_SHUTDOWN ; /*!< Shutdown timer. */ 00676 __I uint32_t RESERVED0[11]; 00677 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */ 00678 __I uint32_t RESERVED1[60]; 00679 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ 00680 __I uint32_t RESERVED2[44]; 00681 __IO uint32_t SHORTS ; /*!< Shortcuts for Timer. */ 00682 __I uint32_t RESERVED3[64]; 00683 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00684 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00685 __I uint32_t RESERVED4[126]; 00686 __IO uint32_t MODE ; /*!< Timer Mode selection. */ 00687 __IO uint32_t BITMODE ; /*!< Sets timer behaviour. */ 00688 __I uint32_t RESERVED5; 00689 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source 00690 clock frequency is divided by 2^SCALE. */ 00691 __I uint32_t RESERVED6[11]; 00692 __IO uint32_t CC[4]; /*!< Capture/compare registers. */ 00693 __I uint32_t RESERVED7[683]; 00694 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00695 } NRF_TIMER_Type; 00696 00697 00698 /* ================================================================================ */ 00699 /* ================ RTC ================ */ 00700 /* ================================================================================ */ 00701 00702 00703 /** 00704 * @brief Real time counter 0. (RTC) 00705 */ 00706 00707 typedef struct { /*!< RTC Structure */ 00708 __O uint32_t TASKS_START ; /*!< Start RTC Counter. */ 00709 __O uint32_t TASKS_STOP ; /*!< Stop RTC Counter. */ 00710 __O uint32_t TASKS_CLEAR ; /*!< Clear RTC Counter. */ 00711 __O uint32_t TASKS_TRIGOVRFLW ; /*!< Set COUNTER to 0xFFFFFFF0. */ 00712 __I uint32_t RESERVED0[60]; 00713 __IO uint32_t EVENTS_TICK ; /*!< Event on COUNTER increment. */ 00714 __IO uint32_t EVENTS_OVRFLW ; /*!< Event on COUNTER overflow. */ 00715 __I uint32_t RESERVED1[14]; 00716 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ 00717 __I uint32_t RESERVED2[109]; 00718 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00719 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00720 __I uint32_t RESERVED3[13]; 00721 __IO uint32_t EVTEN ; /*!< Configures event enable routing to PPI for each RTC event. */ 00722 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives 00723 the value of EVTEN. */ 00724 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register 00725 gives the value of EVTEN. */ 00726 __I uint32_t RESERVED4[110]; 00727 __I uint32_t COUNTER ; /*!< Current COUNTER value. */ 00728 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). 00729 Must be written when RTC is STOPed. */ 00730 __I uint32_t RESERVED5[13]; 00731 __IO uint32_t CC[4]; /*!< Capture/compare registers. */ 00732 __I uint32_t RESERVED6[683]; 00733 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00734 } NRF_RTC_Type; 00735 00736 00737 /* ================================================================================ */ 00738 /* ================ TEMP ================ */ 00739 /* ================================================================================ */ 00740 00741 00742 /** 00743 * @brief Temperature Sensor. (TEMP) 00744 */ 00745 00746 typedef struct { /*!< TEMP Structure */ 00747 __O uint32_t TASKS_START ; /*!< Start temperature measurement. */ 00748 __O uint32_t TASKS_STOP ; /*!< Stop temperature measurement. */ 00749 __I uint32_t RESERVED0[62]; 00750 __IO uint32_t EVENTS_DATARDY ; /*!< Temperature measurement complete, data ready event. */ 00751 __I uint32_t RESERVED1[128]; 00752 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00753 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00754 __I uint32_t RESERVED2[127]; 00755 __I int32_t TEMP ; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */ 00756 __I uint32_t RESERVED3[700]; 00757 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00758 } NRF_TEMP_Type; 00759 00760 00761 /* ================================================================================ */ 00762 /* ================ RNG ================ */ 00763 /* ================================================================================ */ 00764 00765 00766 /** 00767 * @brief Random Number Generator. (RNG) 00768 */ 00769 00770 typedef struct { /*!< RNG Structure */ 00771 __O uint32_t TASKS_START ; /*!< Start the random number generator. */ 00772 __O uint32_t TASKS_STOP ; /*!< Stop the random number generator. */ 00773 __I uint32_t RESERVED0[62]; 00774 __IO uint32_t EVENTS_VALRDY ; /*!< New random number generated and written to VALUE register. */ 00775 __I uint32_t RESERVED1[63]; 00776 __IO uint32_t SHORTS ; /*!< Shortcuts for the RNG. */ 00777 __I uint32_t RESERVED2[64]; 00778 __IO uint32_t INTENSET ; /*!< Interrupt enable set register */ 00779 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register */ 00780 __I uint32_t RESERVED3[126]; 00781 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00782 __I uint32_t VALUE ; /*!< RNG random number. */ 00783 __I uint32_t RESERVED4[700]; 00784 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00785 } NRF_RNG_Type; 00786 00787 00788 /* ================================================================================ */ 00789 /* ================ ECB ================ */ 00790 /* ================================================================================ */ 00791 00792 00793 /** 00794 * @brief AES ECB Mode Encryption. (ECB) 00795 */ 00796 00797 typedef struct { /*!< ECB Structure */ 00798 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this 00799 will not initiate a new encryption and the ERRORECB event will 00800 be triggered. */ 00801 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running, 00802 this will will trigger the ERRORECB event. */ 00803 __I uint32_t RESERVED0[62]; 00804 __IO uint32_t EVENTS_ENDECB ; /*!< ECB block encrypt complete. */ 00805 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an 00806 error. */ 00807 __I uint32_t RESERVED1[127]; 00808 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00809 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00810 __I uint32_t RESERVED2[126]; 00811 __IO uint32_t ECBDATAPTR ; /*!< ECB block encrypt memory pointer. */ 00812 __I uint32_t RESERVED3[701]; 00813 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00814 } NRF_ECB_Type; 00815 00816 00817 /* ================================================================================ */ 00818 /* ================ AAR ================ */ 00819 /* ================================================================================ */ 00820 00821 00822 /** 00823 * @brief Accelerated Address Resolver. (AAR) 00824 */ 00825 00826 typedef struct { /*!< AAR Structure */ 00827 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK 00828 data structure. */ 00829 __I uint32_t RESERVED0; 00830 __O uint32_t TASKS_STOP ; /*!< Stop resolving addresses. */ 00831 __I uint32_t RESERVED1[61]; 00832 __IO uint32_t EVENTS_END ; /*!< Address resolution procedure completed. */ 00833 __IO uint32_t EVENTS_RESOLVED ; /*!< Address resolved. */ 00834 __IO uint32_t EVENTS_NOTRESOLVED ; /*!< Address not resolved. */ 00835 __I uint32_t RESERVED2[126]; 00836 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00837 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00838 __I uint32_t RESERVED3[61]; 00839 __I uint32_t STATUS ; /*!< Resolution status. */ 00840 __I uint32_t RESERVED4[63]; 00841 __IO uint32_t ENABLE ; /*!< Enable AAR. */ 00842 __IO uint32_t NIRK ; /*!< Number of Identity root Keys in the IRK data structure. */ 00843 __IO uint32_t IRKPTR ; /*!< Pointer to the IRK data structure. */ 00844 __I uint32_t RESERVED5; 00845 __IO uint32_t ADDRPTR ; /*!< Pointer to the resolvable address (6 bytes). */ 00846 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage 00847 during resolution. A minimum of 3 bytes must be reserved. */ 00848 __I uint32_t RESERVED6[697]; 00849 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00850 } NRF_AAR_Type; 00851 00852 00853 /* ================================================================================ */ 00854 /* ================ CCM ================ */ 00855 /* ================================================================================ */ 00856 00857 00858 /** 00859 * @brief AES CCM Mode Encryption. (CCM) 00860 */ 00861 00862 typedef struct { /*!< CCM Structure */ 00863 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by 00864 itself when completed. */ 00865 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when 00866 completed. */ 00867 __O uint32_t TASKS_STOP ; /*!< Stop encrypt/decrypt. */ 00868 __I uint32_t RESERVED0[61]; 00869 __IO uint32_t EVENTS_ENDKSGEN ; /*!< Keystream generation completed. */ 00870 __IO uint32_t EVENTS_ENDCRYPT ; /*!< Encrypt/decrypt completed. */ 00871 __IO uint32_t EVENTS_ERROR ; /*!< Error happened. */ 00872 __I uint32_t RESERVED1[61]; 00873 __IO uint32_t SHORTS ; /*!< Shortcuts for the CCM. */ 00874 __I uint32_t RESERVED2[64]; 00875 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00876 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00877 __I uint32_t RESERVED3[61]; 00878 __I uint32_t MICSTATUS ; /*!< CCM RX MIC check result. */ 00879 __I uint32_t RESERVED4[63]; 00880 __IO uint32_t ENABLE ; /*!< CCM enable. */ 00881 __IO uint32_t MODE ; /*!< Operation mode. */ 00882 __IO uint32_t CNFPTR ; /*!< Pointer to a data structure holding AES key and NONCE vector. */ 00883 __IO uint32_t INPTR ; /*!< Pointer to the input packet. */ 00884 __IO uint32_t OUTPTR ; /*!< Pointer to the output packet. */ 00885 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage 00886 during resolution. A minimum of 43 bytes must be reserved. */ 00887 __I uint32_t RESERVED5[697]; 00888 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00889 } NRF_CCM_Type; 00890 00891 00892 /* ================================================================================ */ 00893 /* ================ WDT ================ */ 00894 /* ================================================================================ */ 00895 00896 00897 /** 00898 * @brief Watchdog Timer. (WDT) 00899 */ 00900 00901 typedef struct { /*!< WDT Structure */ 00902 __O uint32_t TASKS_START ; /*!< Start the watchdog. */ 00903 __I uint32_t RESERVED0[63]; 00904 __IO uint32_t EVENTS_TIMEOUT ; /*!< Watchdog timeout. */ 00905 __I uint32_t RESERVED1[128]; 00906 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00907 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00908 __I uint32_t RESERVED2[61]; 00909 __I uint32_t RUNSTATUS ; /*!< Watchdog running status. */ 00910 __I uint32_t REQSTATUS ; /*!< Request status. */ 00911 __I uint32_t RESERVED3[63]; 00912 __IO uint32_t CRV ; /*!< Counter reload value in number of 32kiHz clock cycles. */ 00913 __IO uint32_t RREN ; /*!< Reload request enable. */ 00914 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00915 __I uint32_t RESERVED4[60]; 00916 __O uint32_t RR[8]; /*!< Reload requests registers. */ 00917 __I uint32_t RESERVED5[631]; 00918 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00919 } NRF_WDT_Type; 00920 00921 00922 /* ================================================================================ */ 00923 /* ================ QDEC ================ */ 00924 /* ================================================================================ */ 00925 00926 00927 /** 00928 * @brief Rotary decoder. (QDEC) 00929 */ 00930 00931 typedef struct { /*!< QDEC Structure */ 00932 __O uint32_t TASKS_START ; /*!< Start the quadrature decoder. */ 00933 __O uint32_t TASKS_STOP ; /*!< Stop the quadrature decoder. */ 00934 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers, 00935 and clears the ACC registers. */ 00936 __I uint32_t RESERVED0[61]; 00937 __IO uint32_t EVENTS_SAMPLERDY ; /*!< A new sample is written to the sample register. */ 00938 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and 00939 ACC register different than zero. */ 00940 __IO uint32_t EVENTS_ACCOF ; /*!< ACC or ACCDBL register overflow. */ 00941 __I uint32_t RESERVED1[61]; 00942 __IO uint32_t SHORTS ; /*!< Shortcuts for the QDEC. */ 00943 __I uint32_t RESERVED2[64]; 00944 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00945 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00946 __I uint32_t RESERVED3[125]; 00947 __IO uint32_t ENABLE ; /*!< Enable the QDEC. */ 00948 __IO uint32_t LEDPOL ; /*!< LED output pin polarity. */ 00949 __IO uint32_t SAMPLEPER ; /*!< Sample period. */ 00950 __I int32_t SAMPLE ; /*!< Motion sample value. */ 00951 __IO uint32_t REPORTPER ; /*!< Number of samples to generate an EVENT_REPORTRDY. */ 00952 __I int32_t ACC ; /*!< Accumulated valid transitions register. */ 00953 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC 00954 task. */ 00955 __IO uint32_t PSELLED ; /*!< Pin select for LED output. */ 00956 __IO uint32_t PSELA ; /*!< Pin select for phase A input. */ 00957 __IO uint32_t PSELB ; /*!< Pin select for phase B input. */ 00958 __IO uint32_t DBFEN ; /*!< Enable debouncer input filters. */ 00959 __I uint32_t RESERVED4[5]; 00960 __IO uint32_t LEDPRE ; /*!< Time LED is switched ON before the sample. */ 00961 __I uint32_t ACCDBL ; /*!< Accumulated double (error) transitions register. */ 00962 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC 00963 task. */ 00964 __I uint32_t RESERVED5[684]; 00965 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00966 } NRF_QDEC_Type; 00967 00968 00969 /* ================================================================================ */ 00970 /* ================ LPCOMP ================ */ 00971 /* ================================================================================ */ 00972 00973 00974 /** 00975 * @brief Low power comparator. (LPCOMP) 00976 */ 00977 00978 typedef struct { /*!< LPCOMP Structure */ 00979 __O uint32_t TASKS_START ; /*!< Start the comparator. */ 00980 __O uint32_t TASKS_STOP ; /*!< Stop the comparator. */ 00981 __O uint32_t TASKS_SAMPLE ; /*!< Sample comparator value. */ 00982 __I uint32_t RESERVED0[61]; 00983 __IO uint32_t EVENTS_READY ; /*!< LPCOMP is ready and output is valid. */ 00984 __IO uint32_t EVENTS_DOWN ; /*!< Input voltage crossed the threshold going down. */ 00985 __IO uint32_t EVENTS_UP ; /*!< Input voltage crossed the threshold going up. */ 00986 __IO uint32_t EVENTS_CROSS ; /*!< Input voltage crossed the threshold in any direction. */ 00987 __I uint32_t RESERVED1[60]; 00988 __IO uint32_t SHORTS ; /*!< Shortcuts for the LPCOMP. */ 00989 __I uint32_t RESERVED2[64]; 00990 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00991 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00992 __I uint32_t RESERVED3[61]; 00993 __I uint32_t RESULT ; /*!< Result of last compare. */ 00994 __I uint32_t RESERVED4[63]; 00995 __IO uint32_t ENABLE ; /*!< Enable the LPCOMP. */ 00996 __IO uint32_t PSEL ; /*!< Input pin select. */ 00997 __IO uint32_t REFSEL ; /*!< Reference select. */ 00998 __IO uint32_t EXTREFSEL ; /*!< External reference select. */ 00999 __I uint32_t RESERVED5[4]; 01000 __IO uint32_t ANADETECT ; /*!< Analog detect configuration. */ 01001 __I uint32_t RESERVED6[694]; 01002 __IO uint32_t POWER ; /*!< Peripheral power control. */ 01003 } NRF_LPCOMP_Type; 01004 01005 01006 /* ================================================================================ */ 01007 /* ================ SWI ================ */ 01008 /* ================================================================================ */ 01009 01010 01011 /** 01012 * @brief SW Interrupts. (SWI) 01013 */ 01014 01015 typedef struct { /*!< SWI Structure */ 01016 __I uint32_t UNUSED ; /*!< Unused. */ 01017 } NRF_SWI_Type; 01018 01019 01020 /* ================================================================================ */ 01021 /* ================ NVMC ================ */ 01022 /* ================================================================================ */ 01023 01024 01025 /** 01026 * @brief Non Volatile Memory Controller. (NVMC) 01027 */ 01028 01029 typedef struct { /*!< NVMC Structure */ 01030 __I uint32_t RESERVED0[256]; 01031 __I uint32_t READY ; /*!< Ready flag. */ 01032 __I uint32_t RESERVED1[64]; 01033 __IO uint32_t CONFIG ; /*!< Configuration register. */ 01034 01035 union { 01036 __IO uint32_t ERASEPCR1 ; /*!< Register for erasing a non-protected non-volatile memory page. */ 01037 __IO uint32_t ERASEPAGE ; /*!< Register for erasing a non-protected non-volatile memory page. */ 01038 }; 01039 __IO uint32_t ERASEALL ; /*!< Register for erasing all non-volatile user memory. */ 01040 __IO uint32_t ERASEPCR0 ; /*!< Register for erasing a protected non-volatile memory page. */ 01041 __IO uint32_t ERASEUICR ; /*!< Register for start erasing User Information Congfiguration Registers. */ 01042 } NRF_NVMC_Type; 01043 01044 01045 /* ================================================================================ */ 01046 /* ================ PPI ================ */ 01047 /* ================================================================================ */ 01048 01049 01050 /** 01051 * @brief PPI controller. (PPI) 01052 */ 01053 01054 typedef struct { /*!< PPI Structure */ 01055 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */ 01056 __I uint32_t RESERVED0[312]; 01057 __IO uint32_t CHEN ; /*!< Channel enable. */ 01058 __IO uint32_t CHENSET ; /*!< Channel enable set. */ 01059 __IO uint32_t CHENCLR ; /*!< Channel enable clear. */ 01060 __I uint32_t RESERVED1; 01061 PPI_CH_Type CH[16]; /*!< PPI Channel. */ 01062 __I uint32_t RESERVED2[156]; 01063 __IO uint32_t CHG[4]; /*!< Channel group configuration. */ 01064 } NRF_PPI_Type; 01065 01066 01067 /* ================================================================================ */ 01068 /* ================ FICR ================ */ 01069 /* ================================================================================ */ 01070 01071 01072 /** 01073 * @brief Factory Information Configuration. (FICR) 01074 */ 01075 01076 typedef struct { /*!< FICR Structure */ 01077 __I uint32_t RESERVED0[4]; 01078 __I uint32_t CODEPAGESIZE ; /*!< Code memory page size in bytes. */ 01079 __I uint32_t CODESIZE ; /*!< Code memory size in pages. */ 01080 __I uint32_t RESERVED1[4]; 01081 __I uint32_t CLENR0 ; /*!< Length of code region 0 in bytes. */ 01082 __I uint32_t PPFC ; /*!< Pre-programmed factory code present. */ 01083 __I uint32_t RESERVED2; 01084 __I uint32_t NUMRAMBLOCK ; /*!< Number of individualy controllable RAM blocks. */ 01085 01086 union { 01087 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is 01088 kept for backward compatinility purposes. Use SIZERAMBLOCKS 01089 instead. */ 01090 __I uint32_t SIZERAMBLOCKS ; /*!< Size of RAM blocks in bytes. */ 01091 }; 01092 __I uint32_t RESERVED3[5]; 01093 __I uint32_t CONFIGID ; /*!< Configuration identifier. */ 01094 __I uint32_t DEVICEID[2]; /*!< Device identifier. */ 01095 __I uint32_t RESERVED4[6]; 01096 __I uint32_t ER[4]; /*!< Encryption root. */ 01097 __I uint32_t IR[4]; /*!< Identity root. */ 01098 __I uint32_t DEVICEADDRTYPE ; /*!< Device address type. */ 01099 __I uint32_t DEVICEADDR[2]; /*!< Device address. */ 01100 __I uint32_t OVERRIDEEN ; /*!< Radio calibration override enable. */ 01101 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit 01102 mode. */ 01103 __I uint32_t RESERVED5[10]; 01104 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit 01105 mode. */ 01106 } NRF_FICR_Type; 01107 01108 01109 /* ================================================================================ */ 01110 /* ================ UICR ================ */ 01111 /* ================================================================================ */ 01112 01113 01114 /** 01115 * @brief User Information Configuration. (UICR) 01116 */ 01117 01118 typedef struct { /*!< UICR Structure */ 01119 __IO uint32_t CLENR0 ; /*!< Length of code region 0. */ 01120 __IO uint32_t RBPCONF ; /*!< Readback protection configuration. */ 01121 __IO uint32_t XTALFREQ ; /*!< Reset value for CLOCK XTALFREQ register. */ 01122 __I uint32_t RESERVED0; 01123 __I uint32_t FWID ; /*!< Firmware ID. */ 01124 01125 union { 01126 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */ 01127 __IO uint32_t BOOTLOADERADDR ; /*!< Bootloader start address. */ 01128 }; 01129 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */ 01130 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */ 01131 } NRF_UICR_Type; 01132 01133 01134 /* ================================================================================ */ 01135 /* ================ GPIO ================ */ 01136 /* ================================================================================ */ 01137 01138 01139 /** 01140 * @brief General purpose input and output. (GPIO) 01141 */ 01142 01143 typedef struct { /*!< GPIO Structure */ 01144 __I uint32_t RESERVED0[321]; 01145 __IO uint32_t OUT ; /*!< Write GPIO port. */ 01146 __IO uint32_t OUTSET ; /*!< Set individual bits in GPIO port. */ 01147 __IO uint32_t OUTCLR ; /*!< Clear individual bits in GPIO port. */ 01148 __I uint32_t IN ; /*!< Read GPIO port. */ 01149 __IO uint32_t DIR ; /*!< Direction of GPIO pins. */ 01150 __IO uint32_t DIRSET ; /*!< DIR set register. */ 01151 __IO uint32_t DIRCLR ; /*!< DIR clear register. */ 01152 __I uint32_t RESERVED1[120]; 01153 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */ 01154 } NRF_GPIO_Type; 01155 01156 01157 /* -------------------- End of section using anonymous unions ------------------- */ 01158 #if defined(__CC_ARM) 01159 #pragma pop 01160 #elif defined(__ICCARM__) 01161 /* leave anonymous unions enabled */ 01162 #elif defined(__GNUC__) 01163 /* anonymous unions are enabled by default */ 01164 #elif defined(__TMS470__) 01165 /* anonymous unions are enabled by default */ 01166 #elif defined(__TASKING__) 01167 #pragma warning restore 01168 #else 01169 #warning Not supported compiler type 01170 #endif 01171 01172 01173 01174 01175 /* ================================================================================ */ 01176 /* ================ Peripheral memory map ================ */ 01177 /* ================================================================================ */ 01178 01179 #define NRF_POWER_BASE 0x40000000UL 01180 #define NRF_CLOCK_BASE 0x40000000UL 01181 #define NRF_MPU_BASE 0x40000000UL 01182 #define NRF_AMLI_BASE 0x40000000UL 01183 #define NRF_RADIO_BASE 0x40001000UL 01184 #define NRF_UART0_BASE 0x40002000UL 01185 #define NRF_SPI0_BASE 0x40003000UL 01186 #define NRF_TWI0_BASE 0x40003000UL 01187 #define NRF_SPI1_BASE 0x40004000UL 01188 #define NRF_TWI1_BASE 0x40004000UL 01189 #define NRF_SPIS1_BASE 0x40004000UL 01190 #define NRF_SPIM1_BASE 0x40004000UL 01191 #define NRF_GPIOTE_BASE 0x40006000UL 01192 #define NRF_ADC_BASE 0x40007000UL 01193 #define NRF_TIMER0_BASE 0x40008000UL 01194 #define NRF_TIMER1_BASE 0x40009000UL 01195 #define NRF_TIMER2_BASE 0x4000A000UL 01196 #define NRF_RTC0_BASE 0x4000B000UL 01197 #define NRF_TEMP_BASE 0x4000C000UL 01198 #define NRF_RNG_BASE 0x4000D000UL 01199 #define NRF_ECB_BASE 0x4000E000UL 01200 #define NRF_AAR_BASE 0x4000F000UL 01201 #define NRF_CCM_BASE 0x4000F000UL 01202 #define NRF_WDT_BASE 0x40010000UL 01203 #define NRF_RTC1_BASE 0x40011000UL 01204 #define NRF_QDEC_BASE 0x40012000UL 01205 #define NRF_LPCOMP_BASE 0x40013000UL 01206 #define NRF_SWI_BASE 0x40014000UL 01207 #define NRF_NVMC_BASE 0x4001E000UL 01208 #define NRF_PPI_BASE 0x4001F000UL 01209 #define NRF_FICR_BASE 0x10000000UL 01210 #define NRF_UICR_BASE 0x10001000UL 01211 #define NRF_GPIO_BASE 0x50000000UL 01212 01213 01214 /* ================================================================================ */ 01215 /* ================ Peripheral declaration ================ */ 01216 /* ================================================================================ */ 01217 01218 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) 01219 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) 01220 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE) 01221 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE) 01222 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) 01223 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) 01224 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) 01225 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) 01226 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) 01227 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) 01228 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) 01229 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) 01230 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) 01231 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE) 01232 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) 01233 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) 01234 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) 01235 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) 01236 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) 01237 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) 01238 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) 01239 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) 01240 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) 01241 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) 01242 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) 01243 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) 01244 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) 01245 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE) 01246 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) 01247 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) 01248 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) 01249 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) 01250 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE) 01251 01252 01253 /** @} */ /* End of group Device_Peripheral_Registers */ 01254 /** @} */ /* End of group nrf51 */ 01255 /** @} */ /* End of group Nordic Semiconductor */ 01256 01257 #ifdef __cplusplus 01258 } 01259 #endif 01260 01261 01262 #endif /* nrf51_H */ 01263
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