Yann Garcia / Mbed 2 deprecated DS130x_I2CApp

This short program illustrates how to use the DS130x_I2C library. My objective is to share the same RTC with Microchip 18F MCU.

Dependencies:   mbed DebugLibrary

NetServices/drv/usb/UsbInc.h@0:f30e2135b0db, 2011-02-09 (annotated)

Committer:
Yann
Date:
Wed Feb 09 13:57:49 2011 +0000
Revision:
0:f30e2135b0db
V0.0.0.1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Yann 0:f30e2135b0db 1
Yann 0:f30e2135b0db 2 /*
Yann 0:f30e2135b0db 3 Copyright (c) 2010 Donatien Garnier (donatiengar [at] gmail [dot] com)
Yann 0:f30e2135b0db 4
Yann 0:f30e2135b0db 5 Permission is hereby granted, free of charge, to any person obtaining a copy
Yann 0:f30e2135b0db 6 of this software and associated documentation files (the "Software"), to deal
Yann 0:f30e2135b0db 7 in the Software without restriction, including without limitation the rights
Yann 0:f30e2135b0db 8 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
Yann 0:f30e2135b0db 9 copies of the Software, and to permit persons to whom the Software is
Yann 0:f30e2135b0db 10 furnished to do so, subject to the following conditions:
Yann 0:f30e2135b0db 11
Yann 0:f30e2135b0db 12 The above copyright notice and this permission notice shall be included in
Yann 0:f30e2135b0db 13 all copies or substantial portions of the Software.
Yann 0:f30e2135b0db 14
Yann 0:f30e2135b0db 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
Yann 0:f30e2135b0db 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
Yann 0:f30e2135b0db 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
Yann 0:f30e2135b0db 18 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
Yann 0:f30e2135b0db 19 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Yann 0:f30e2135b0db 20 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
Yann 0:f30e2135b0db 21 THE SOFTWARE.
Yann 0:f30e2135b0db 22 */
Yann 0:f30e2135b0db 23
Yann 0:f30e2135b0db 24 #ifndef USB_INC_H
Yann 0:f30e2135b0db 25 #define USB_INC_H
Yann 0:f30e2135b0db 26
Yann 0:f30e2135b0db 27 #include "mbed.h"
Yann 0:f30e2135b0db 28
Yann 0:f30e2135b0db 29 #define MIN(a,b) ((a)<(b)?(a):(b))
Yann 0:f30e2135b0db 30 #define MAX(a,b) ((a)>(b)?(a):(b))
Yann 0:f30e2135b0db 31
Yann 0:f30e2135b0db 32 //typedef int32_t RC;
Yann 0:f30e2135b0db 33
Yann 0:f30e2135b0db 34 typedef uint8_t byte;
Yann 0:f30e2135b0db 35 typedef uint16_t word;
Yann 0:f30e2135b0db 36
Yann 0:f30e2135b0db 37 enum UsbErr
Yann 0:f30e2135b0db 38 {
Yann 0:f30e2135b0db 39 __USBERR_MIN = -0xFFFF,
Yann 0:f30e2135b0db 40 USBERR_DISCONNECTED,
Yann 0:f30e2135b0db 41 USBERR_NOTFOUND,
Yann 0:f30e2135b0db 42 USBERR_BADCONFIG,
Yann 0:f30e2135b0db 43 USBERR_PROCESSING,
Yann 0:f30e2135b0db 44 USBERR_HALTED, //Transfer on an ep is stalled
Yann 0:f30e2135b0db 45 USBERR_BUSY,
Yann 0:f30e2135b0db 46 USBERR_TDFAIL,
Yann 0:f30e2135b0db 47 USBERR_ERROR,
Yann 0:f30e2135b0db 48 USBERR_OK = 0
Yann 0:f30e2135b0db 49 };
Yann 0:f30e2135b0db 50
Yann 0:f30e2135b0db 51
Yann 0:f30e2135b0db 52 /* From NXP's USBHostLite stack's usbhost_lpc17xx.h */
Yann 0:f30e2135b0db 53 /* Only the types names have been changed to avoid unecessary typedefs */
Yann 0:f30e2135b0db 54
Yann 0:f30e2135b0db 55
Yann 0:f30e2135b0db 56 /*
Yann 0:f30e2135b0db 57 **************************************************************************************************************
Yann 0:f30e2135b0db 58 * NXP USB Host Stack
Yann 0:f30e2135b0db 59 *
Yann 0:f30e2135b0db 60 * (c) Copyright 2008, NXP SemiConductors
Yann 0:f30e2135b0db 61 * (c) Copyright 2008, OnChip Technologies LLC
Yann 0:f30e2135b0db 62 * All Rights Reserved
Yann 0:f30e2135b0db 63 *
Yann 0:f30e2135b0db 64 * www.nxp.com
Yann 0:f30e2135b0db 65 * www.onchiptech.com
Yann 0:f30e2135b0db 66 *
Yann 0:f30e2135b0db 67 * File : usbhost_lpc17xx.h
Yann 0:f30e2135b0db 68 * Programmer(s) : Ravikanth.P
Yann 0:f30e2135b0db 69 * Version :
Yann 0:f30e2135b0db 70 *
Yann 0:f30e2135b0db 71 **************************************************************************************************************
Yann 0:f30e2135b0db 72 */
Yann 0:f30e2135b0db 73
Yann 0:f30e2135b0db 74
Yann 0:f30e2135b0db 75
Yann 0:f30e2135b0db 76 /*
Yann 0:f30e2135b0db 77 **************************************************************************************************************
Yann 0:f30e2135b0db 78 * OHCI OPERATIONAL REGISTER FIELD DEFINITIONS
Yann 0:f30e2135b0db 79 **************************************************************************************************************
Yann 0:f30e2135b0db 80 */
Yann 0:f30e2135b0db 81
Yann 0:f30e2135b0db 82 /* ------------------ HcControl Register --------------------- */
Yann 0:f30e2135b0db 83 #define OR_CONTROL_CLE 0x00000010
Yann 0:f30e2135b0db 84 #define OR_CONTROL_BLE 0x00000020
Yann 0:f30e2135b0db 85 #define OR_CONTROL_HCFS 0x000000C0
Yann 0:f30e2135b0db 86 #define OR_CONTROL_HC_OPER 0x00000080
Yann 0:f30e2135b0db 87 /* ----------------- HcCommandStatus Register ----------------- */
Yann 0:f30e2135b0db 88 #define OR_CMD_STATUS_HCR 0x00000001
Yann 0:f30e2135b0db 89 #define OR_CMD_STATUS_CLF 0x00000002
Yann 0:f30e2135b0db 90 #define OR_CMD_STATUS_BLF 0x00000004
Yann 0:f30e2135b0db 91 /* --------------- HcInterruptStatus Register ----------------- */
Yann 0:f30e2135b0db 92 #define OR_INTR_STATUS_WDH 0x00000002
Yann 0:f30e2135b0db 93 #define OR_INTR_STATUS_RHSC 0x00000040
Yann 0:f30e2135b0db 94 #define OR_INTR_STATUS_UE 0x00000010
Yann 0:f30e2135b0db 95 /* --------------- HcInterruptEnable Register ----------------- */
Yann 0:f30e2135b0db 96 #define OR_INTR_ENABLE_WDH 0x00000002
Yann 0:f30e2135b0db 97 #define OR_INTR_ENABLE_RHSC 0x00000040
Yann 0:f30e2135b0db 98 #define OR_INTR_ENABLE_MIE 0x80000000
Yann 0:f30e2135b0db 99 /* ---------------- HcRhDescriptorA Register ------------------ */
Yann 0:f30e2135b0db 100 #define OR_RH_STATUS_LPSC 0x00010000
Yann 0:f30e2135b0db 101 #define OR_RH_STATUS_DRWE 0x00008000
Yann 0:f30e2135b0db 102 /* -------------- HcRhPortStatus[1:NDP] Register -------------- */
Yann 0:f30e2135b0db 103 #define OR_RH_PORT_CCS 0x00000001
Yann 0:f30e2135b0db 104 #define OR_RH_PORT_PRS 0x00000010
Yann 0:f30e2135b0db 105 #define OR_RH_PORT_CSC 0x00010000
Yann 0:f30e2135b0db 106 #define OR_RH_PORT_PRSC 0x00100000
Yann 0:f30e2135b0db 107
Yann 0:f30e2135b0db 108
Yann 0:f30e2135b0db 109 /*
Yann 0:f30e2135b0db 110 **************************************************************************************************************
Yann 0:f30e2135b0db 111 * FRAME INTERVAL
Yann 0:f30e2135b0db 112 **************************************************************************************************************
Yann 0:f30e2135b0db 113 */
Yann 0:f30e2135b0db 114
Yann 0:f30e2135b0db 115 #define FI 0x2EDF /* 12000 bits per frame (-1) */
Yann 0:f30e2135b0db 116 #define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
Yann 0:f30e2135b0db 117
Yann 0:f30e2135b0db 118 /*
Yann 0:f30e2135b0db 119 **************************************************************************************************************
Yann 0:f30e2135b0db 120 * ENDPOINT DESCRIPTOR CONTROL FIELDS
Yann 0:f30e2135b0db 121 **************************************************************************************************************
Yann 0:f30e2135b0db 122 */
Yann 0:f30e2135b0db 123
Yann 0:f30e2135b0db 124 #define ED_SKIP (uint32_t) (0x00001000) /* Skip this ep in queue */
Yann 0:f30e2135b0db 125
Yann 0:f30e2135b0db 126 /*
Yann 0:f30e2135b0db 127 **************************************************************************************************************
Yann 0:f30e2135b0db 128 * TRANSFER DESCRIPTOR CONTROL FIELDS
Yann 0:f30e2135b0db 129 **************************************************************************************************************
Yann 0:f30e2135b0db 130 */
Yann 0:f30e2135b0db 131
Yann 0:f30e2135b0db 132 #define TD_ROUNDING (uint32_t) (0x00040000) /* Buffer Rounding */
Yann 0:f30e2135b0db 133 #define TD_SETUP (uint32_t)(0) /* Direction of Setup Packet */
Yann 0:f30e2135b0db 134 #define TD_IN (uint32_t)(0x00100000) /* Direction In */
Yann 0:f30e2135b0db 135 #define TD_OUT (uint32_t)(0x00080000) /* Direction Out */
Yann 0:f30e2135b0db 136 #define TD_DELAY_INT(x) (uint32_t)((x) << 21) /* Delay Interrupt */
Yann 0:f30e2135b0db 137 #define TD_TOGGLE_0 (uint32_t)(0x02000000) /* Toggle 0 */
Yann 0:f30e2135b0db 138 #define TD_TOGGLE_1 (uint32_t)(0x03000000) /* Toggle 1 */
Yann 0:f30e2135b0db 139 #define TD_CC (uint32_t)(0xF0000000) /* Completion Code */
Yann 0:f30e2135b0db 140
Yann 0:f30e2135b0db 141 /*
Yann 0:f30e2135b0db 142 **************************************************************************************************************
Yann 0:f30e2135b0db 143 * USB STANDARD REQUEST DEFINITIONS
Yann 0:f30e2135b0db 144 **************************************************************************************************************
Yann 0:f30e2135b0db 145 */
Yann 0:f30e2135b0db 146
Yann 0:f30e2135b0db 147 #define USB_DESCRIPTOR_TYPE_DEVICE 1
Yann 0:f30e2135b0db 148 #define USB_DESCRIPTOR_TYPE_CONFIGURATION 2
Yann 0:f30e2135b0db 149 #define USB_DESCRIPTOR_TYPE_INTERFACE 4
Yann 0:f30e2135b0db 150 #define USB_DESCRIPTOR_TYPE_ENDPOINT 5
Yann 0:f30e2135b0db 151 /* ----------- Control RequestType Fields ----------- */
Yann 0:f30e2135b0db 152 #define USB_DEVICE_TO_HOST 0x80
Yann 0:f30e2135b0db 153 #define USB_HOST_TO_DEVICE 0x00
Yann 0:f30e2135b0db 154 #define USB_REQUEST_TYPE_CLASS 0x20
Yann 0:f30e2135b0db 155 #define USB_RECIPIENT_DEVICE 0x00
Yann 0:f30e2135b0db 156 #define USB_RECIPIENT_INTERFACE 0x01
Yann 0:f30e2135b0db 157 /* -------------- USB Standard Requests -------------- */
Yann 0:f30e2135b0db 158 #define SET_ADDRESS 5
Yann 0:f30e2135b0db 159 #define GET_DESCRIPTOR 6
Yann 0:f30e2135b0db 160 #define SET_CONFIGURATION 9
Yann 0:f30e2135b0db 161 #define SET_INTERFACE 11
Yann 0:f30e2135b0db 162
Yann 0:f30e2135b0db 163 /*
Yann 0:f30e2135b0db 164 **************************************************************************************************************
Yann 0:f30e2135b0db 165 * TYPE DEFINITIONS
Yann 0:f30e2135b0db 166 **************************************************************************************************************
Yann 0:f30e2135b0db 167 */
Yann 0:f30e2135b0db 168
Yann 0:f30e2135b0db 169 typedef struct hcEd { /* ----------- HostController EndPoint Descriptor ------------- */
Yann 0:f30e2135b0db 170 volatile uint32_t Control; /* Endpoint descriptor control */
Yann 0:f30e2135b0db 171 volatile uint32_t TailTd; /* Physical address of tail in Transfer descriptor list */
Yann 0:f30e2135b0db 172 volatile uint32_t HeadTd; /* Physcial address of head in Transfer descriptor list */
Yann 0:f30e2135b0db 173 volatile uint32_t Next; /* Physical address of next Endpoint descriptor */
Yann 0:f30e2135b0db 174 } HCED;
Yann 0:f30e2135b0db 175
Yann 0:f30e2135b0db 176 typedef struct hcTd { /* ------------ HostController Transfer Descriptor ------------ */
Yann 0:f30e2135b0db 177 volatile uint32_t Control; /* Transfer descriptor control */
Yann 0:f30e2135b0db 178 volatile uint32_t CurrBufPtr; /* Physical address of current buffer pointer */
Yann 0:f30e2135b0db 179 volatile uint32_t Next; /* Physical pointer to next Transfer Descriptor */
Yann 0:f30e2135b0db 180 volatile uint32_t BufEnd; /* Physical address of end of buffer */
Yann 0:f30e2135b0db 181 } HCTD;
Yann 0:f30e2135b0db 182
Yann 0:f30e2135b0db 183 typedef struct hcca { /* ----------- Host Controller Communication Area ------------ */
Yann 0:f30e2135b0db 184 volatile uint32_t IntTable[32]; /* Interrupt Table */
Yann 0:f30e2135b0db 185 volatile uint32_t FrameNumber; /* Frame Number */
Yann 0:f30e2135b0db 186 volatile uint32_t DoneHead; /* Done Head */
Yann 0:f30e2135b0db 187 volatile uint8_t Reserved[116]; /* Reserved for future use */
Yann 0:f30e2135b0db 188 volatile uint8_t Unknown[4]; /* Unused */
Yann 0:f30e2135b0db 189 } HCCA;
Yann 0:f30e2135b0db 190
Yann 0:f30e2135b0db 191
Yann 0:f30e2135b0db 192
Yann 0:f30e2135b0db 193 #endif