Y SI / lib_ClockCounter

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

lib_ClockCounter.cpp@0:d3c997729db1, 2019-11-21 (annotated)

Committer:
YSI
Date:
Thu Nov 21 09:17:25 2019 +0000
Revision:
0:d3c997729db1
Child:
1:bdbac277828a
lib_ClockCounter

Who changed what in which revision?

UserRevisionLine numberNew contents of line
YSI 0:d3c997729db1 1 /** Mbed Library Clock Counter
YSI 0:d3c997729db1 2 * Hardware pulse counter with TIMER2 (CAP2.0 or CAP2.1) on Mbed LPC1768
YSI 0:d3c997729db1 3 *
YSI 0:d3c997729db1 4 * Counts signal transitions on p30(CAP2.0) or p29(CAP2.1).
YSI 0:d3c997729db1 5 * Can detecte rising, falling or both signal edge.
YSI 0:d3c997729db1 6 * Return the signal edge count during a periode in seconds.
YSI 0:d3c997729db1 7 * Shannon's theorem say with an input signal frequency up to 48 MHz with 96 MHz CCLK.
YSI 0:d3c997729db1 8 * Only tested with frequencys up to 20 MHz and it work.
YSI 0:d3c997729db1 9 *
YSI 0:d3c997729db1 10 * Example :
YSI 0:d3c997729db1 11 * @code
YSI 0:d3c997729db1 12 * #include "mbed.h"
YSI 0:d3c997729db1 13 * #include "lib_ClockCounter.h"
YSI 0:d3c997729db1 14 *
YSI 0:d3c997729db1 15 * Serial pc(USBTX, USBRX);
YSI 0:d3c997729db1 16 * ClockCounter Frequency;
YSI 0:d3c997729db1 17 *
YSI 0:d3c997729db1 18 * int main()
YSI 0:d3c997729db1 19 * {
YSI 0:d3c997729db1 20 * while(1) pc.printf("Frequency = %d Hz\r\n", Frequency.getCount());
YSI 0:d3c997729db1 21 * }
YSI 0:d3c997729db1 22 * @endcode
YSI 0:d3c997729db1 23 */
YSI 0:d3c997729db1 24
YSI 0:d3c997729db1 25 #include "lib_ClockCounter.h"
YSI 0:d3c997729db1 26
YSI 0:d3c997729db1 27 ClockCounter::ClockCounter(PinName PIN_CAP2, edgeDetection EDGE)
YSI 0:d3c997729db1 28 {
YSI 0:d3c997729db1 29 switch(PIN_CAP2)
YSI 0:d3c997729db1 30 {
YSI 0:d3c997729db1 31 case p30: case p29:
YSI 0:d3c997729db1 32 // PCONP => Power Mode Control register
YSI 0:d3c997729db1 33 LPC_SC->PCONP |= (0x1<<22); // Bit(22) 1 => Timer2 power on
YSI 0:d3c997729db1 34 // PCLKSEL1 => Peripheral Clock Selection register 1
YSI 0:d3c997729db1 35 LPC_SC->PCLKSEL1 |= (0x1<<12); // Bits(13,12) 01 => PCLK_TIMER2 = CCLK(96 MHz)
YSI 0:d3c997729db1 36 // TCR => Timer Control Register
YSI 0:d3c997729db1 37 LPC_TIM2->TCR = 0x0; // Bits(1,0) 00 => Timer2 disabled
YSI 0:d3c997729db1 38 // PINSEL0 => Pin Function Select register 0
YSI 0:d3c997729db1 39 LPC_PINCON->PINSEL0 |= (0x3<<((PIN_CAP2==p30)?8:10)); // Bits(9,8) 11 => pin function CAP2.0 (p30), Bits(11,10) 11 => pin function CAP2.1 (p29)
YSI 0:d3c997729db1 40 // CTCR => Count Control Register
YSI 0:d3c997729db1 41 LPC_TIM2->CTCR = ((PIN_CAP2==p30)?0:4)+EDGE; // Bits(3,2) 00 => CAP2.0 (p30 signal is counter clock) or 11 => CAP2.1 (p29 signal is counter clock), Bits(1,0) XX => timer is incremented on edge
YSI 0:d3c997729db1 42 // CCR => Capture Control Register
YSI 0:d3c997729db1 43 LPC_TIM2->CCR = 0x0; // Bits(5,4,3,2,1,0) 000000 => capture and interrupt on event disabled
YSI 0:d3c997729db1 44 break;
YSI 0:d3c997729db1 45 }
YSI 0:d3c997729db1 46 }
YSI 0:d3c997729db1 47
YSI 0:d3c997729db1 48 int ClockCounter::getCount(float period)
YSI 0:d3c997729db1 49 {
YSI 0:d3c997729db1 50 // TCR => Timer Control Register
YSI 0:d3c997729db1 51 LPC_TIM2->TCR = 0x2; // Bits(1,0) 10 => Timer2 count reset
YSI 0:d3c997729db1 52 LPC_TIM2->TCR = 0x1; // Bits(1,0) 01 => Timer2 enabled
YSI 0:d3c997729db1 53 wait(period);
YSI 0:d3c997729db1 54 LPC_TIM2->TCR = 0x0; // Bits(1,0) 00 => Timer2 disabled
YSI 0:d3c997729db1 55 return LPC_TIM2->TC; // TC => Timer Counter
YSI 0:d3c997729db1 56 }