Library to control a Graphics TFT connected to 4-wire SPI - revised for the Raio RA8875 Display Controller.
Dependents: FRDM_RA8875_mPaint RA8875_Demo RA8875_KeyPadDemo SignalGenerator ... more
Fork of SPI_TFT by
See Components - RA8875 Based Display
Enhanced touch-screen support - where it previous supported both the Resistive Touch and Capacitive Touch based on the FT5206 Touch Controller, now it also has support for the GSL1680 Touch Controller.
Offline Help Manual (Windows chm)
/media/uploads/WiredHome/ra8875.zip.bin (download, rename to .zip and unzip)
Diff: RA8875.cpp
- Revision:
- 134:f028ed71a0af
- Parent:
- 133:e36dcfc2d756
- Child:
- 135:af519fe4ba91
--- a/RA8875.cpp Mon Oct 17 00:42:47 2016 +0000 +++ b/RA8875.cpp Sun Nov 06 16:46:52 2016 +0000 @@ -4,9 +4,13 @@ /// which is 480 x 272 using a 4-wire SPI interface. Support is provided for /// both a keypad and a resistive touch-screen. /// -/// This dirver has been fully tested with an 800 x 480 variant (also using +/// This driver has been fully tested with an 800 x 480 variant (also using /// 4-wire SPI). /// +/// 20161106: Updated the initialization to set the various registers based on +/// the BuyDisplay.com example code. This altered several registers +/// for the 800x480 display driver. +/// #include "RA8875.h" //#define DEBUG "RAIO" @@ -147,7 +151,12 @@ _select(false); // deselect the display frequency(RA8875_DEFAULT_SPI_FREQ); // data rate Reset(); - WriteCommand(0x88, 0x0B); // PLLC1 - Phase Lock Loop registers + // Set PLL based on display size from buy-display.com sample code + if (width == 800) { + WriteCommand(0x88, 0x0C); // PLLC1 - Phase Lock Loop registers + } else { + WriteCommand(0x88, 0x0B); // PLLC1 - Phase Lock Loop registers + } wait_ms(1); WriteCommand(0x89, 0x02); wait_ms(1); @@ -159,27 +168,51 @@ } else { // color_bpp == 8 WriteCommand(0x10, 0x00); // 8-bpp (256 colors) } - // Pixel Clock Setting Register (PCSR) - WriteCommand(0x04, 0x82); // PDAT on PCLK falling edge, PCLK = 4 x System Clock - wait_ms(1); - - // Horizontal Settings - screenwidth = width; - WriteCommand(0x14, width/8 - 1); //HDWR//Horizontal Display Width Setting Bit[6:0] - WriteCommand(0x15, 0x02); //HNDFCR//Horizontal Non-Display Period fine tune Bit[3:0] - WriteCommand(0x16, 0x03); //HNDR//Horizontal Non-Display Period Bit[4:0] - WriteCommand(0x17, 0x01); //HSTR//HSYNC Start Position[4:0] - WriteCommand(0x18, 0x03); //HPWR//HSYNC Polarity ,The period width of HSYNC. - - // Vertical Settings - screenheight = height; - WriteCommand(0x19, (height-1)&0xFF); //VDHR0 //Vertical Display Height Bit [7:0] - WriteCommand(0x1a, (height-1)>>8); //VDHR1 //Vertical Display Height Bit [8] - WriteCommand(0x1b, 0x0F); //VNDR0 //Vertical Non-Display Period Bit [7:0] - WriteCommand(0x1c, 0x00); //VNDR1 //Vertical Non-Display Period Bit [8] - WriteCommand(0x1d, 0x0e); //VSTR0 //VSYNC Start Position[7:0] - WriteCommand(0x1e, 0x06); //VSTR1 //VSYNC Start Position[8] - WriteCommand(0x1f, 0x01); //VPWR //VSYNC Polarity ,VSYNC Pulse Width[6:0] + + // Set Pixel Clock Setting Register (PCSR) based on display size from buy-display.com sample code + if (width == 800) { + WriteCommand(0x04, 0x81); // PDAT on PCLK falling edge, PCLK = 4 x System Clock + wait_ms(1); + + // Horizontal Settings + screenwidth = width; + WriteCommand(0x14, width/8 - 1); //HDWR//Horizontal Display Width Setting Bit[6:0] + WriteCommand(0x15, 0x00); //HNDFCR//Horizontal Non-Display Period fine tune Bit[3:0] + WriteCommand(0x16, 0x03); //HNDR//Horizontal Non-Display Period Bit[4:0] + WriteCommand(0x17, 0x03); //HSTR//HSYNC Start Position[4:0] + WriteCommand(0x18, 0x0B); //HPWR//HSYNC Polarity ,The period width of HSYNC. + + // Vertical Settings + screenheight = height; + WriteCommand(0x19, (height-1)&0xFF); //VDHR0 //Vertical Display Height Bit [7:0] + WriteCommand(0x1a, (height-1)>>8); //VDHR1 //Vertical Display Height Bit [8] + WriteCommand(0x1b, 0x20); //VNDR0 //Vertical Non-Display Period Bit [7:0] + WriteCommand(0x1c, 0x00); //VNDR1 //Vertical Non-Display Period Bit [8] + WriteCommand(0x1d, 0x16); //VSTR0 //VSYNC Start Position[7:0] + WriteCommand(0x1e, 0x00); //VSTR1 //VSYNC Start Position[8] + WriteCommand(0x1f, 0x01); //VPWR //VSYNC Polarity ,VSYNC Pulse Width[6:0] + } else { + WriteCommand(0x04, 0x82); // PDAT on PCLK falling edge, PCLK = 4 x System Clock + wait_ms(1); + + // Horizontal Settings + screenwidth = width; + WriteCommand(0x14, width/8 - 1); //HDWR//Horizontal Display Width Setting Bit[6:0] + WriteCommand(0x15, 0x02); //HNDFCR//Horizontal Non-Display Period fine tune Bit[3:0] + WriteCommand(0x16, 0x03); //HNDR//Horizontal Non-Display Period Bit[4:0] + WriteCommand(0x17, 0x01); //HSTR//HSYNC Start Position[4:0] + WriteCommand(0x18, 0x03); //HPWR//HSYNC Polarity ,The period width of HSYNC. + + // Vertical Settings + screenheight = height; + WriteCommand(0x19, (height-1)&0xFF); //VDHR0 //Vertical Display Height Bit [7:0] + WriteCommand(0x1a, (height-1)>>8); //VDHR1 //Vertical Display Height Bit [8] + WriteCommand(0x1b, 0x0F); //VNDR0 //Vertical Non-Display Period Bit [7:0] + WriteCommand(0x1c, 0x00); //VNDR1 //Vertical Non-Display Period Bit [8] + WriteCommand(0x1d, 0x0e); //VSTR0 //VSYNC Start Position[7:0] + WriteCommand(0x1e, 0x06); //VSTR1 //VSYNC Start Position[8] + WriteCommand(0x1f, 0x01); //VPWR //VSYNC Polarity ,VSYNC Pulse Width[6:0] + } portraitmode = false;