Vybhav Kadaba
Minor changes to support ADMW FWv1.17.75
Diff: inc/admw1001/ADMW1001_REGISTERS_typedefs.h
- Revision:
- 50:d84305e5e1c0
- Parent:
- 44:94bdfaefddac
- Child:
- 58:aa9cd5072f66
--- a/inc/admw1001/ADMW1001_REGISTERS_typedefs.h Thu Feb 06 11:04:31 2020 +0000
+++ b/inc/admw1001/ADMW1001_REGISTERS_typedefs.h Mon Feb 17 11:23:39 2020 +0000
@@ -1,9 +1,7 @@
/* ================================================================================
Created by :
- Created on : 2020 Jan 08, 12:45 GMT Standard Time
-
- Created on : 2020 Jan 08, 12:45 GMT Standard Time
+ Created on : 2020 Jan 15, 14:45 GMT Standard Time
Project : ADMW1001_REGISTERS
File : ADMW1001_REGISTERS_typedefs.h
@@ -18,7 +16,6 @@
This file was auto-generated. Do not make local changes to this file.
-
Auto generation script information:
Script: C:\Program Files (x86)\Yoda-19.05.01\generators\inc\genHeaders
Last modified: 26-SEP-2017
@@ -74,38 +71,6 @@
/*@}*/
-/** @defgroup Interface_Config_B Interface Configuration B (Interface_Config_B) Register
- * Interface Configuration B (Interface_Config_B) Register.
- * @{
- */
-
-/* =========================================================================
- *! \enum ADMW_SPI_Interface_Config_B_Single_Inst
- *! \brief Select Streaming or Single Instruction Mode (Single_Inst) Enumerations
- * ========================================================================= */
-typedef enum
-{
- SPI_INTERFACE_CONFIG_B_STREAMING_MODE = 0, /**< Streaming mode is enabled */
- SPI_INTERFACE_CONFIG_B_SINGLE_INSTRUCTION_MODE = 1 /**< Single Instruction mode is enabled */
-} ADMW_SPI_Interface_Config_B_Single_Inst;
-
-
-/* ==========================================================================
- *! \struct ADMW_SPI_Interface_Config_B_Struct
- *! \brief Interface Configuration B Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_SPI_Interface_Config_B_t {
- union {
- struct {
- uint8_t reserved0 : 7;
- uint8_t Single_Inst : 1; /**< Select Streaming or Single Instruction Mode */
- };
- uint8_t VALUE8;
- };
-} ADMW_SPI_Interface_Config_B_t;
-
-/*@}*/
-
/** @defgroup Chip_Type Chip Type (Chip_Type) Register
* Chip Type (Chip_Type) Register.
* @{
@@ -139,8 +104,7 @@
typedef struct _ADMW_SPI_Product_ID_L_t {
union {
struct {
- uint8_t Product_ID_Trim_Bits : 4; /**< These Bits Vary on Die Configured for Multiple Generics */
- uint8_t Product_ID_Fixed_Bits : 4; /**< Product_ID_Fixed_Bits[3:0] These Bits are Fixed on Die Configured for Multiple Generics */
+ uint8_t Product_ID : 8; /**< Product_ID[7:0] The Device Chip Type and Family */
};
uint8_t VALUE8;
};
@@ -160,7 +124,7 @@
typedef struct _ADMW_SPI_Product_ID_H_t {
union {
struct {
- uint8_t Product_ID_Fixed_Bits : 8; /**< Product_ID_Fixed_Bits[11:4] These Bits are Fixed on Die Configured for Multiple Generics */
+ uint8_t Product_ID : 8; /**< Product_ID[15:8] The Device Chip Type and Family */
};
uint8_t VALUE8;
};
@@ -168,27 +132,6 @@
/*@}*/
-/** @defgroup Chip_Grade Chip Grade (Chip_Grade) Register
- * Chip Grade (Chip_Grade) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_SPI_Chip_Grade_Struct
- *! \brief Chip Grade Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_SPI_Chip_Grade_t {
- union {
- struct {
- uint8_t Device_Revision : 4; /**< Device Hardware Revision */
- uint8_t Grade : 4; /**< Device Performance Grade */
- };
- uint8_t VALUE8;
- };
-} ADMW_SPI_Chip_Grade_t;
-
-/*@}*/
-
/** @defgroup Scratch_Pad Scratch Pad (Scratch_Pad) Register
* Scratch Pad (Scratch_Pad) Register.
* @{
@@ -311,85 +254,6 @@
/*@}*/
-/** @defgroup Transfer_Config Transfer Config (Transfer_Config) Register
- * Transfer Config (Transfer_Config) Register.
- * @{
- */
-
-/* =========================================================================
- *! \enum ADMW_SPI_Transfer_Config_Stream_Mode
- *! \brief When Streaming, Control Master to Slave Transfer (Stream_Mode) Enumerations
- * ========================================================================= */
-typedef enum
-{
- SPI_TRANSFER_CONFIG_UPDATE_ON_WRITE = 0, /**< Transfers after each byte/mulit-byte register */
- SPI_TRANSFER_CONFIG_UPDATE_ON_ADDRESS_LOOP = 1 /**< Transfers when address loops */
-} ADMW_SPI_Transfer_Config_Stream_Mode;
-
-
-/* ==========================================================================
- *! \struct ADMW_SPI_Transfer_Config_Struct
- *! \brief Transfer Config Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_SPI_Transfer_Config_t {
- union {
- struct {
- uint8_t reserved0 : 1;
- uint8_t Stream_Mode : 1; /**< When Streaming, Control Master to Slave Transfer */
- uint8_t reserved2 : 6;
- };
- uint8_t VALUE8;
- };
-} ADMW_SPI_Transfer_Config_t;
-
-/*@}*/
-
-/** @defgroup Interface_Config_C Interface Configuration C (Interface_Config_C) Register
- * Interface Configuration C (Interface_Config_C) Register.
- * @{
- */
-
-/* =========================================================================
- *! \enum ADMW_SPI_Interface_Config_C_Strict_Register_Access
- *! \brief Multibyte Registers Must Be Read or Written in Full (Strict_Register_Access) Enumerations
- * ========================================================================= */
-typedef enum
-{
- SPI_INTERFACE_CONFIG_C_NORMAL_ACCESS = 0, /**< Normal mode, no access restrictions */
- SPI_INTERFACE_CONFIG_C_STRICT_ACCESS = 1 /**< Strict mode, multi-byte registers require all bytes read/written */
-} ADMW_SPI_Interface_Config_C_Strict_Register_Access;
-
-
-/* =========================================================================
- *! \enum ADMW_SPI_Interface_Config_C_CRC_Enable
- *! \brief CRC Enable (CRC_Enable) Enumerations
- * ========================================================================= */
-typedef enum
-{
- SPI_INTERFACE_CONFIG_C_DISABLED = 0, /**< CRC Disabled */
- SPI_INTERFACE_CONFIG_C_ENABLED = 1 /**< CRC Enabled */
-} ADMW_SPI_Interface_Config_C_CRC_Enable;
-
-
-/* ==========================================================================
- *! \struct ADMW_SPI_Interface_Config_C_Struct
- *! \brief Interface Configuration C Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_SPI_Interface_Config_C_t {
- union {
- struct {
- uint8_t CRC_EnableB : 2; /**< Inverted CRC Enable */
- uint8_t reserved2 : 2;
- uint8_t Send_Status : 1; /**< Sends Status in 4-Wire Mode When Enabled */
- uint8_t Strict_Register_Access : 1; /**< Multibyte Registers Must Be Read or Written in Full */
- uint8_t CRC_Enable : 2; /**< CRC Enable */
- };
- uint8_t VALUE8;
- };
-} ADMW_SPI_Interface_Config_C_t;
-
-/*@}*/
-
/** @defgroup Interface_Status_A Interface Status A (Interface_Status_A) Register
* Interface Status A (Interface_Status_A) Register.
* @{
@@ -433,7 +297,6 @@
CORE_COMMAND_LATCH_CONFIG = 7, /**< Latch configuration. */
CORE_COMMAND_LOAD_LUT = 8, /**< Load LUT from flash */
CORE_COMMAND_SAVE_LUT = 9, /**< Save LUT to flash */
- CORE_COMMAND_POWER_DOWN = 20, /**< Enter Low Power State */
CORE_COMMAND_LOAD_CONFIG_1 = 24, /**< Load registers with configuration from flash */
CORE_COMMAND_SAVE_CONFIG_1 = 25 /**< Store current registers to flash configuration */
} ADMW_CORE_Command_Special_Command;
@@ -478,7 +341,8 @@
typedef enum
{
CORE_MODE_DRDY_PER_CONVERSION = 0, /**< Data ready per conversion */
- CORE_MODE_DRDY_PER_CYCLE = 1 /**< Data ready per cycle */
+ CORE_MODE_DRDY_PER_CYCLE = 1, /**< Data ready per cycle */
+ CORE_MODE_DRDY_PER_FIFO_FILL = 2
} ADMW_CORE_Mode_Drdy_Mode;
@@ -542,9 +406,8 @@
* ========================================================================= */
typedef enum
{
-
- CORE_CYCLE_CONTROL_CYCLE_SW = 0, /**< Ground Switch Opens outside of measurement cycle to conserve power */
- CORE_CYCLE_CONTROL_CLOSE_SW = 1, /**< Ground Switch Closed */
+ CORE_CYCLE_CONTROL_OPEN_SW = 0, /**< Ground Switch Opens outside of measurement cycle to conserve power */
+ CORE_CYCLE_CONTROL_CLOSE_SW = 1 /**< Ground Switch Closed */
} ADMW_CORE_Cycle_Control_GND_SW_CTRL;
@@ -698,9 +561,10 @@
uint16_t Sensor_OverRange : 1; /**< Indicates If the Sensor is Overrange */
uint16_t CJ_Soft_Fault : 1; /**< Cold Junction Soft Fault */
uint16_t CJ_Hard_Fault : 1; /**< Cold Junction Hard Fault */
- uint16_t ADC_Input_OverRange : 1; /**< Indicates the ADC Input is Overrange */
- uint16_t Sensor_HardFault : 1; /**< Indicates Sensor Hard Fault */
- uint16_t reserved8 : 8;
+ uint16_t ADC_Input_OverRange : 1; /**< Indicates the ADC Input is Overrange */
+ uint16_t Sensor_HardFault : 1; /**< Indicates Sensor Hard Fault */
+ uint16_t Threshold_Exceeded : 1;
+ uint16_t reserved7 : 7;
};
uint16_t VALUE16;
};
@@ -913,7 +777,6 @@
typedef struct _ADMW_CORE_LUT_Offset_t {
union {
struct {
-
uint16_t LUT_Offset : 11; /**< Offset into the Lookup Table */
uint16_t reserved11 : 5;
};
@@ -1076,9 +939,9 @@
* ========================================================================= */
typedef enum
{
- CORE_SENSOR_DETAILS_LUT_DEFAULT = 0, /**< Default lookup table for selected sensor type */
- CORE_SENSOR_DETAILS_LUT_CUSTOM = 1, /**< User defined custom lookup table. */
- CORE_SENSOR_DETAILS_LUT_RESERVED = 2 /**< Reserved */
+ CORE_SENSOR_DETAILS_LUT_DEFAULT = 0, /**< Default lookup table for selected sensor type */
+ CORE_SENSOR_DETAILS_LUT_CUSTOM = 1, /**< User defined custom lookup table. */
+ CORE_SENSOR_DETAILS_LUT_RESERVED = 2 /**< Reserved */
} ADMW_CORE_Sensor_Details_LUT_Select;
@@ -1213,20 +1076,6 @@
* @{
*/
-/* =========================================================================
- *! \enum ADMW_CORE_Settling_Time_Settling_Time_Units
- *! \brief Units for Settling Time (Settling_Time_Units) Enumerations
- * ========================================================================= */
-typedef enum
-{
-
- CORE_SETTLING_TIME_MILLISECONDS = 0, /**< Micro-seconds */
- CORE_SETTLING_TIME_SECONDS = 1, /**< Milli-seconds */
- CORE_SETTLING_TIME_RESERVED = 2, /**< Seconds */
- CORE_SETTLING_TIME_UNDEFINED = 3 /**< Undefined */
-} ADMW_CORE_Settling_Time_Settling_Time_Units;
-
-
/* ==========================================================================
*! \struct ADMW_CORE_Settling_Time_Struct
*! \brief Settling Time Register bit field structure
@@ -1234,8 +1083,8 @@
typedef struct _ADMW_CORE_Settling_Time_t {
union {
struct {
- uint16_t Settling_Time : 14; /**< Settling Time to Allow When Switching to Channel */
- uint16_t Settling_Time_Units : 2; /**< Units for Settling Time */
+ uint16_t Settling_Time : 8; /**< Additional Settling Time in Milliseconds. Max 255ms */
+ uint16_t reserved8 : 8;
};
uint16_t VALUE16;
};
@@ -1522,17 +1371,6 @@
*/
/* =========================================================================
- *! \enum ADMW_CORE_Digital_Sensor_Comms_Digital_Sensor_Comms_En
- *! \brief Enable Digital Sensor Communications Register Parameters (Digital_Sensor_Comms_En) Enumerations
- * ========================================================================= */
-typedef enum
-{
- CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_DEFAULT = 0, /**< Default parameters used for digital sensor communications */
- CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_USER = 1 /**< User supplied parameters used for digital sensor communications */
-} ADMW_CORE_Digital_Sensor_Comms_Digital_Sensor_Comms_En;
-
-
-/* =========================================================================
*! \enum ADMW_CORE_Digital_Sensor_Comms_SPI_Clock
*! \brief Controls Clock Frequency for SPI Sensors (SPI_Clock) Enumerations
* ========================================================================= */
@@ -1590,12 +1428,12 @@
typedef struct _ADMW_CORE_Digital_Sensor_Comms_t {
union {
struct {
- uint16_t Digital_Sensor_Comms_En : 1; /**< Enable Digital Sensor Communications Register Parameters */
- uint16_t SPI_Clock : 4; /**< Controls Clock Frequency for SPI Sensors */
- uint16_t I2C_Clock : 2; /**< Controls SCLK Frequency for I2C Sensors */
- uint16_t reserved7 : 3;
- uint16_t SPI_Mode : 2; /**< Configuration for Sensor SPI Protocol */
- uint16_t reserved12 : 4;
+ uint16_t reserved0 : 1;
+ uint16_t SPI_Clock : 4; /**< Controls Clock Frequency for SPI Sensors */
+ uint16_t I2C_Clock : 2; /**< Controls SCLK Frequency for I2C Sensors */
+ uint16_t reserved7 : 3;
+ uint16_t SPI_Mode : 2; /**< Configuration for Sensor SPI Protocol */
+ uint16_t reserved12 : 4;
};
uint16_t VALUE16;
};
@@ -1606,7 +1444,6 @@
#if defined (__CC_ARM)
#pragma pop
+#endif
#endif
-
-#endif