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Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register

Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register

Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register. More...

Enumerations

enum  ADMW_CORE_Digital_Sensor_Comms_SPI_Clock {
  CORE_DIGITAL_SENSOR_COMMS_SPI_8MHZ = 0, CORE_DIGITAL_SENSOR_COMMS_SPI_4MHZ = 1, CORE_DIGITAL_SENSOR_COMMS_SPI_2MHZ = 2, CORE_DIGITAL_SENSOR_COMMS_SPI_1MHZ = 3,
  CORE_DIGITAL_SENSOR_COMMS_SPI_500KHZ = 4, CORE_DIGITAL_SENSOR_COMMS_SPI_250KHZ = 5, CORE_DIGITAL_SENSOR_COMMS_SPI_125KHZ = 6, CORE_DIGITAL_SENSOR_COMMS_SPI_62P5KHZ = 7,
  CORE_DIGITAL_SENSOR_COMMS_SPI_31P3KHZ = 8, CORE_DIGITAL_SENSOR_COMMS_SPI_15P6KHZ = 9, CORE_DIGITAL_SENSOR_COMMS_SPI_7P8KHZ = 10, CORE_DIGITAL_SENSOR_COMMS_SPI_3P9KHZ = 11,
  CORE_DIGITAL_SENSOR_COMMS_SPI_1P9KHZ = 12, CORE_DIGITAL_SENSOR_COMMS_SPI_977HZ = 13, CORE_DIGITAL_SENSOR_COMMS_SPI_488HZ = 14, CORE_DIGITAL_SENSOR_COMMS_SPI_244HZ = 15
}
enum  ADMW_CORE_Digital_Sensor_Comms_I2C_Clock { CORE_DIGITAL_SENSOR_COMMS_I2C_100K = 0, CORE_DIGITAL_SENSOR_COMMS_I2C_400K = 1, CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED1 = 2, CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED2 = 3 }
enum  ADMW_CORE_Digital_Sensor_Comms_SPI_Mode { CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 = 0, CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 = 1, CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 = 2, CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_3 = 3 }

Detailed Description

Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register.


Enumeration Type Documentation

Enumerator:
CORE_DIGITAL_SENSOR_COMMS_I2C_100K 

100kHz SCL

CORE_DIGITAL_SENSOR_COMMS_I2C_400K 

400kHz SCL

CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED1 

Reserved.

CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED2 

Reserved.

Definition at line 1473 of file ADMW1001_REGISTERS_typedefs.h.

Enumerator:
CORE_DIGITAL_SENSOR_COMMS_SPI_8MHZ 

8MHz

CORE_DIGITAL_SENSOR_COMMS_SPI_4MHZ 

4MHz

CORE_DIGITAL_SENSOR_COMMS_SPI_2MHZ 

2MHz

CORE_DIGITAL_SENSOR_COMMS_SPI_1MHZ 

1MHz

CORE_DIGITAL_SENSOR_COMMS_SPI_500KHZ 

500kHz

CORE_DIGITAL_SENSOR_COMMS_SPI_250KHZ 

250kHz

CORE_DIGITAL_SENSOR_COMMS_SPI_125KHZ 

125kHz

CORE_DIGITAL_SENSOR_COMMS_SPI_62P5KHZ 

62.5kHz

CORE_DIGITAL_SENSOR_COMMS_SPI_31P3KHZ 

31.25kHz

CORE_DIGITAL_SENSOR_COMMS_SPI_15P6KHZ 

15.625kHz

CORE_DIGITAL_SENSOR_COMMS_SPI_7P8KHZ 

7.8kHz

CORE_DIGITAL_SENSOR_COMMS_SPI_3P9KHZ 

3.9kHz

CORE_DIGITAL_SENSOR_COMMS_SPI_1P9KHZ 

1.95kHz

CORE_DIGITAL_SENSOR_COMMS_SPI_977HZ 

977Hz

CORE_DIGITAL_SENSOR_COMMS_SPI_488HZ 

488Hz

CORE_DIGITAL_SENSOR_COMMS_SPI_244HZ 

244Hz

Definition at line 1448 of file ADMW1001_REGISTERS_typedefs.h.

Enumerator:
CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 

Clock polarity = 0 Clock phase = 0.

CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 

Clock polarity = 0 Clock phase = 1.

CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 

Clock polarity = 1 Clock phase = 0.

CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_3 

Clock polarity = 1 Clock phase = 1.

Definition at line 1486 of file ADMW1001_REGISTERS_typedefs.h.