Vitaly Badeev / Mbed 2 deprecated Radar1

Dependencies:   FT800_2 mbed Encoder

DSP/src/arm_cmplx_mag_f32.c@0:fda1a80ff1ac, 2019-04-25 (annotated)

Committer:
Vitan
Date:
Thu Apr 25 11:19:28 2019 +0000
Revision:
0:fda1a80ff1ac
Radar1

Who changed what in which revision?

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Vitan 0:fda1a80ff1ac 1 /* ----------------------------------------------------------------------
Vitan 0:fda1a80ff1ac 2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
Vitan 0:fda1a80ff1ac 3 *
Vitan 0:fda1a80ff1ac 4 * $Date: 19. March 2015
Vitan 0:fda1a80ff1ac 5 * $Revision: V.1.4.5
Vitan 0:fda1a80ff1ac 6 *
Vitan 0:fda1a80ff1ac 7 * Project: CMSIS DSP Library
Vitan 0:fda1a80ff1ac 8 * Title: arm_cmplx_mag_f32.c
Vitan 0:fda1a80ff1ac 9 *
Vitan 0:fda1a80ff1ac 10 * Description: Floating-point complex magnitude.
Vitan 0:fda1a80ff1ac 11 *
Vitan 0:fda1a80ff1ac 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
Vitan 0:fda1a80ff1ac 13 *
Vitan 0:fda1a80ff1ac 14 * Redistribution and use in source and binary forms, with or without
Vitan 0:fda1a80ff1ac 15 * modification, are permitted provided that the following conditions
Vitan 0:fda1a80ff1ac 16 * are met:
Vitan 0:fda1a80ff1ac 17 * - Redistributions of source code must retain the above copyright
Vitan 0:fda1a80ff1ac 18 * notice, this list of conditions and the following disclaimer.
Vitan 0:fda1a80ff1ac 19 * - Redistributions in binary form must reproduce the above copyright
Vitan 0:fda1a80ff1ac 20 * notice, this list of conditions and the following disclaimer in
Vitan 0:fda1a80ff1ac 21 * the documentation and/or other materials provided with the
Vitan 0:fda1a80ff1ac 22 * distribution.
Vitan 0:fda1a80ff1ac 23 * - Neither the name of ARM LIMITED nor the names of its contributors
Vitan 0:fda1a80ff1ac 24 * may be used to endorse or promote products derived from this
Vitan 0:fda1a80ff1ac 25 * software without specific prior written permission.
Vitan 0:fda1a80ff1ac 26 *
Vitan 0:fda1a80ff1ac 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
Vitan 0:fda1a80ff1ac 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
Vitan 0:fda1a80ff1ac 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
Vitan 0:fda1a80ff1ac 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
Vitan 0:fda1a80ff1ac 31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
Vitan 0:fda1a80ff1ac 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
Vitan 0:fda1a80ff1ac 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Vitan 0:fda1a80ff1ac 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Vitan 0:fda1a80ff1ac 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
Vitan 0:fda1a80ff1ac 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Vitan 0:fda1a80ff1ac 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Vitan 0:fda1a80ff1ac 38 * POSSIBILITY OF SUCH DAMAGE.
Vitan 0:fda1a80ff1ac 39 * ---------------------------------------------------------------------------- */
Vitan 0:fda1a80ff1ac 40
Vitan 0:fda1a80ff1ac 41 #include "arm_math.h"
Vitan 0:fda1a80ff1ac 42
Vitan 0:fda1a80ff1ac 43 /**
Vitan 0:fda1a80ff1ac 44 * @ingroup groupCmplxMath
Vitan 0:fda1a80ff1ac 45 */
Vitan 0:fda1a80ff1ac 46
Vitan 0:fda1a80ff1ac 47 /**
Vitan 0:fda1a80ff1ac 48 * @defgroup cmplx_mag Complex Magnitude
Vitan 0:fda1a80ff1ac 49 *
Vitan 0:fda1a80ff1ac 50 * Computes the magnitude of the elements of a complex data vector.
Vitan 0:fda1a80ff1ac 51 *
Vitan 0:fda1a80ff1ac 52 * The <code>pSrc</code> points to the source data and
Vitan 0:fda1a80ff1ac 53 * <code>pDst</code> points to the where the result should be written.
Vitan 0:fda1a80ff1ac 54 * <code>numSamples</code> specifies the number of complex samples
Vitan 0:fda1a80ff1ac 55 * in the input array and the data is stored in an interleaved fashion
Vitan 0:fda1a80ff1ac 56 * (real, imag, real, imag, ...).
Vitan 0:fda1a80ff1ac 57 * The input array has a total of <code>2*numSamples</code> values;
Vitan 0:fda1a80ff1ac 58 * the output array has a total of <code>numSamples</code> values.
Vitan 0:fda1a80ff1ac 59 * The underlying algorithm is used:
Vitan 0:fda1a80ff1ac 60 *
Vitan 0:fda1a80ff1ac 61 * <pre>
Vitan 0:fda1a80ff1ac 62 * for(n=0; n<numSamples; n++) {
Vitan 0:fda1a80ff1ac 63 * pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
Vitan 0:fda1a80ff1ac 64 * }
Vitan 0:fda1a80ff1ac 65 * </pre>
Vitan 0:fda1a80ff1ac 66 *
Vitan 0:fda1a80ff1ac 67 * There are separate functions for floating-point, Q15, and Q31 data types.
Vitan 0:fda1a80ff1ac 68 */
Vitan 0:fda1a80ff1ac 69
Vitan 0:fda1a80ff1ac 70 /**
Vitan 0:fda1a80ff1ac 71 * @addtogroup cmplx_mag
Vitan 0:fda1a80ff1ac 72 * @{
Vitan 0:fda1a80ff1ac 73 */
Vitan 0:fda1a80ff1ac 74 /**
Vitan 0:fda1a80ff1ac 75 * @brief Floating-point complex magnitude.
Vitan 0:fda1a80ff1ac 76 * @param[in] *pSrc points to complex input buffer
Vitan 0:fda1a80ff1ac 77 * @param[out] *pDst points to real output buffer
Vitan 0:fda1a80ff1ac 78 * @param[in] numSamples number of complex samples in the input vector
Vitan 0:fda1a80ff1ac 79 * @return none.
Vitan 0:fda1a80ff1ac 80 *
Vitan 0:fda1a80ff1ac 81 */
Vitan 0:fda1a80ff1ac 82
Vitan 0:fda1a80ff1ac 83
Vitan 0:fda1a80ff1ac 84 void arm_cmplx_mag_f32(
Vitan 0:fda1a80ff1ac 85 float32_t * pSrc,
Vitan 0:fda1a80ff1ac 86 float32_t * pDst,
Vitan 0:fda1a80ff1ac 87 uint32_t numSamples)
Vitan 0:fda1a80ff1ac 88 {
Vitan 0:fda1a80ff1ac 89 float32_t realIn, imagIn; /* Temporary variables to hold input values */
Vitan 0:fda1a80ff1ac 90
Vitan 0:fda1a80ff1ac 91 #ifndef ARM_MATH_CM0_FAMILY
Vitan 0:fda1a80ff1ac 92
Vitan 0:fda1a80ff1ac 93 /* Run the below code for Cortex-M4 and Cortex-M3 */
Vitan 0:fda1a80ff1ac 94 uint32_t blkCnt; /* loop counter */
Vitan 0:fda1a80ff1ac 95
Vitan 0:fda1a80ff1ac 96 /*loop Unrolling */
Vitan 0:fda1a80ff1ac 97 blkCnt = numSamples >> 2u;
Vitan 0:fda1a80ff1ac 98
Vitan 0:fda1a80ff1ac 99 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
Vitan 0:fda1a80ff1ac 100 ** a second loop below computes the remaining 1 to 3 samples. */
Vitan 0:fda1a80ff1ac 101 while(blkCnt > 0u)
Vitan 0:fda1a80ff1ac 102 {
Vitan 0:fda1a80ff1ac 103
Vitan 0:fda1a80ff1ac 104 /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
Vitan 0:fda1a80ff1ac 105 realIn = *pSrc++;
Vitan 0:fda1a80ff1ac 106 imagIn = *pSrc++;
Vitan 0:fda1a80ff1ac 107 /* store the result in the destination buffer. */
Vitan 0:fda1a80ff1ac 108 arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
Vitan 0:fda1a80ff1ac 109
Vitan 0:fda1a80ff1ac 110 realIn = *pSrc++;
Vitan 0:fda1a80ff1ac 111 imagIn = *pSrc++;
Vitan 0:fda1a80ff1ac 112 arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
Vitan 0:fda1a80ff1ac 113
Vitan 0:fda1a80ff1ac 114 realIn = *pSrc++;
Vitan 0:fda1a80ff1ac 115 imagIn = *pSrc++;
Vitan 0:fda1a80ff1ac 116 arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
Vitan 0:fda1a80ff1ac 117
Vitan 0:fda1a80ff1ac 118 realIn = *pSrc++;
Vitan 0:fda1a80ff1ac 119 imagIn = *pSrc++;
Vitan 0:fda1a80ff1ac 120 arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
Vitan 0:fda1a80ff1ac 121
Vitan 0:fda1a80ff1ac 122
Vitan 0:fda1a80ff1ac 123 /* Decrement the loop counter */
Vitan 0:fda1a80ff1ac 124 blkCnt--;
Vitan 0:fda1a80ff1ac 125 }
Vitan 0:fda1a80ff1ac 126
Vitan 0:fda1a80ff1ac 127 /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
Vitan 0:fda1a80ff1ac 128 ** No loop unrolling is used. */
Vitan 0:fda1a80ff1ac 129 blkCnt = numSamples % 0x4u;
Vitan 0:fda1a80ff1ac 130
Vitan 0:fda1a80ff1ac 131 while(blkCnt > 0u)
Vitan 0:fda1a80ff1ac 132 {
Vitan 0:fda1a80ff1ac 133 /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
Vitan 0:fda1a80ff1ac 134 realIn = *pSrc++;
Vitan 0:fda1a80ff1ac 135 imagIn = *pSrc++;
Vitan 0:fda1a80ff1ac 136 /* store the result in the destination buffer. */
Vitan 0:fda1a80ff1ac 137 arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
Vitan 0:fda1a80ff1ac 138
Vitan 0:fda1a80ff1ac 139 /* Decrement the loop counter */
Vitan 0:fda1a80ff1ac 140 blkCnt--;
Vitan 0:fda1a80ff1ac 141 }
Vitan 0:fda1a80ff1ac 142
Vitan 0:fda1a80ff1ac 143 #else
Vitan 0:fda1a80ff1ac 144
Vitan 0:fda1a80ff1ac 145 /* Run the below code for Cortex-M0 */
Vitan 0:fda1a80ff1ac 146
Vitan 0:fda1a80ff1ac 147 while(numSamples > 0u)
Vitan 0:fda1a80ff1ac 148 {
Vitan 0:fda1a80ff1ac 149 /* out = sqrt((real * real) + (imag * imag)) */
Vitan 0:fda1a80ff1ac 150 realIn = *pSrc++;
Vitan 0:fda1a80ff1ac 151 imagIn = *pSrc++;
Vitan 0:fda1a80ff1ac 152 /* store the result in the destination buffer. */
Vitan 0:fda1a80ff1ac 153 arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
Vitan 0:fda1a80ff1ac 154
Vitan 0:fda1a80ff1ac 155 /* Decrement the loop counter */
Vitan 0:fda1a80ff1ac 156 numSamples--;
Vitan 0:fda1a80ff1ac 157 }
Vitan 0:fda1a80ff1ac 158
Vitan 0:fda1a80ff1ac 159 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
Vitan 0:fda1a80ff1ac 160
Vitan 0:fda1a80ff1ac 161 }
Vitan 0:fda1a80ff1ac 162
Vitan 0:fda1a80ff1ac 163 /**
Vitan 0:fda1a80ff1ac 164 * @} end of cmplx_mag group
Vitan 0:fda1a80ff1ac 165 */