Songw Jiang / Mbed 2 deprecated Quad-Rotor

Flight control with nRF and MPU6050

Dependencies:   mbed

mpu6050.h@2:cef800934402, 2018-09-26 (annotated)

Committer:
Ucial
Date:
Wed Sep 26 02:45:14 2018 +0000
Revision:
2:cef800934402
Parent:
1:23afaebeed15 
Flight control of drone

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Ucial 0:7365f8db1bac 1 #ifndef __MPU6050_H
Ucial 0:7365f8db1bac 2 #define __MPU6050_H
Ucial 0:7365f8db1bac 3 //#include "mpuiic.h"
Ucial 0:7365f8db1bac 4 #include "mbed.h"
Ucial 0:7365f8db1bac 5
Ucial 0:7365f8db1bac 6 //////////////////////////////////////////////////////////////////////////////////
Ucial 0:7365f8db1bac 7 //MPU6050驱动程序 C.H.
Ucial 0:7365f8db1bac 8 //////////////////////////////////////////////////////////////////////////////////
Ucial 0:7365f8db1bac 9
Ucial 0:7365f8db1bac 10 //用来选择驱动程序用于哪个项目的电路板
Ucial 0:7365f8db1bac 11 #define DRIVER_MODE_ROTOR //四旋翼
Ucial 0:7365f8db1bac 12 //#define DRIVER_MODE_BALANCE //平衡车
Ucial 0:7365f8db1bac 13
Ucial 0:7365f8db1bac 14 //兼容宏定义
Ucial 0:7365f8db1bac 15 #define delay_us wait_us
Ucial 0:7365f8db1bac 16 #define delay_ms wait_ms
Ucial 0:7365f8db1bac 17
Ucial 0:7365f8db1bac 18
Ucial 0:7365f8db1bac 19 //IO口操作宏定义
Ucial 0:7365f8db1bac 20 #define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2))
Ucial 0:7365f8db1bac 21 #define MEM_ADDR(addr) *((volatile unsigned long *)(addr))
Ucial 0:7365f8db1bac 22 #define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum))
Ucial 0:7365f8db1bac 23 //IO口地址映射
Ucial 0:7365f8db1bac 24 #define GPIOA_ODR_Addr (GPIOA_BASE+12) //0x4001080C
Ucial 0:7365f8db1bac 25 #define GPIOB_ODR_Addr (GPIOB_BASE+12) //0x40010C0C
Ucial 0:7365f8db1bac 26 #define GPIOC_ODR_Addr (GPIOC_BASE+12) //0x4001100C
Ucial 0:7365f8db1bac 27 #define GPIOD_ODR_Addr (GPIOD_BASE+12) //0x4001140C
Ucial 0:7365f8db1bac 28 #define GPIOE_ODR_Addr (GPIOE_BASE+12) //0x4001180C
Ucial 0:7365f8db1bac 29 #define GPIOF_ODR_Addr (GPIOF_BASE+12) //0x40011A0C
Ucial 0:7365f8db1bac 30 #define GPIOG_ODR_Addr (GPIOG_BASE+12) //0x40011E0C
Ucial 0:7365f8db1bac 31
Ucial 0:7365f8db1bac 32 #define GPIOA_IDR_Addr (GPIOA_BASE+8) //0x40010808
Ucial 0:7365f8db1bac 33 #define GPIOB_IDR_Addr (GPIOB_BASE+8) //0x40010C08
Ucial 0:7365f8db1bac 34 #define GPIOC_IDR_Addr (GPIOC_BASE+8) //0x40011008
Ucial 0:7365f8db1bac 35 #define GPIOD_IDR_Addr (GPIOD_BASE+8) //0x40011408
Ucial 0:7365f8db1bac 36 #define GPIOE_IDR_Addr (GPIOE_BASE+8) //0x40011808
Ucial 0:7365f8db1bac 37 #define GPIOF_IDR_Addr (GPIOF_BASE+8) //0x40011A08
Ucial 0:7365f8db1bac 38 #define GPIOG_IDR_Addr (GPIOG_BASE+8) //0x40011E08
Ucial 0:7365f8db1bac 39
Ucial 0:7365f8db1bac 40 //IO口操作,只对单一的IO口!
Ucial 0:7365f8db1bac 41 //确保n的值小于16!
Ucial 0:7365f8db1bac 42 #define PAout(n) BIT_ADDR(GPIOA_ODR_Addr,n) //输出
Ucial 0:7365f8db1bac 43 #define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //输入
Ucial 0:7365f8db1bac 44
Ucial 0:7365f8db1bac 45 #define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //输出
Ucial 0:7365f8db1bac 46 #define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //输入
Ucial 0:7365f8db1bac 47
Ucial 0:7365f8db1bac 48 #define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //输出
Ucial 0:7365f8db1bac 49 #define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //输入
Ucial 0:7365f8db1bac 50
Ucial 0:7365f8db1bac 51 #define PDout(n) BIT_ADDR(GPIOD_ODR_Addr,n) //输出
Ucial 0:7365f8db1bac 52 #define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //输入
Ucial 0:7365f8db1bac 53
Ucial 0:7365f8db1bac 54 #define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //输出
Ucial 0:7365f8db1bac 55 #define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //输入
Ucial 0:7365f8db1bac 56
Ucial 0:7365f8db1bac 57 #define PFout(n) BIT_ADDR(GPIOF_ODR_Addr,n) //输出
Ucial 0:7365f8db1bac 58 #define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //输入
Ucial 0:7365f8db1bac 59
Ucial 0:7365f8db1bac 60 #define PGout(n) BIT_ADDR(GPIOG_ODR_Addr,n) //输出
Ucial 0:7365f8db1bac 61 #define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //输入
Ucial 0:7365f8db1bac 62 /////////////////////////////////////////////////////////////////
Ucial 0:7365f8db1bac 63
Ucial 0:7365f8db1bac 64
Ucial 0:7365f8db1bac 65
Ucial 0:7365f8db1bac 66
Ucial 0:7365f8db1bac 67 //#define MPU_ACCEL_OFFS_REG 0X06 //accel_offs寄存器,可读取版本号,寄存器手册未提到
Ucial 0:7365f8db1bac 68 //#define MPU_PROD_ID_REG 0X0C //prod id寄存器,在寄存器手册未提到
Ucial 0:7365f8db1bac 69 #define MPU_SELF_TESTX_REG 0X0D //自检寄存器X
Ucial 0:7365f8db1bac 70 #define MPU_SELF_TESTY_REG 0X0E //自检寄存器Y
Ucial 0:7365f8db1bac 71 #define MPU_SELF_TESTZ_REG 0X0F //自检寄存器Z
Ucial 0:7365f8db1bac 72 #define MPU_SELF_TESTA_REG 0X10 //自检寄存器A
Ucial 0:7365f8db1bac 73 #define MPU_SAMPLE_RATE_REG 0X19 //采样频率分频器
Ucial 0:7365f8db1bac 74 #define MPU_CFG_REG 0X1A //配置寄存器
Ucial 0:7365f8db1bac 75 #define MPU_GYRO_CFG_REG 0X1B //陀螺仪配置寄存器
Ucial 0:7365f8db1bac 76 #define MPU_ACCEL_CFG_REG 0X1C //加速度计配置寄存器
Ucial 0:7365f8db1bac 77 #define MPU_MOTION_DET_REG 0X1F //运动检测阀值设置寄存器
Ucial 0:7365f8db1bac 78 #define MPU_FIFO_EN_REG 0X23 //FIFO使能寄存器
Ucial 0:7365f8db1bac 79 #define MPU_I2CMST_CTRL_REG 0X24 //IIC主机控制寄存器
Ucial 0:7365f8db1bac 80 #define MPU_I2CSLV0_ADDR_REG 0X25 //IIC从机0器件地址寄存器
Ucial 0:7365f8db1bac 81 #define MPU_I2CSLV0_REG 0X26 //IIC从机0数据地址寄存器
Ucial 0:7365f8db1bac 82 #define MPU_I2CSLV0_CTRL_REG 0X27 //IIC从机0控制寄存器
Ucial 0:7365f8db1bac 83 #define MPU_I2CSLV1_ADDR_REG 0X28 //IIC从机1器件地址寄存器
Ucial 0:7365f8db1bac 84 #define MPU_I2CSLV1_REG 0X29 //IIC从机1数据地址寄存器
Ucial 0:7365f8db1bac 85 #define MPU_I2CSLV1_CTRL_REG 0X2A //IIC从机1控制寄存器
Ucial 0:7365f8db1bac 86 #define MPU_I2CSLV2_ADDR_REG 0X2B //IIC从机2器件地址寄存器
Ucial 0:7365f8db1bac 87 #define MPU_I2CSLV2_REG 0X2C //IIC从机2数据地址寄存器
Ucial 0:7365f8db1bac 88 #define MPU_I2CSLV2_CTRL_REG 0X2D //IIC从机2控制寄存器
Ucial 0:7365f8db1bac 89 #define MPU_I2CSLV3_ADDR_REG 0X2E //IIC从机3器件地址寄存器
Ucial 0:7365f8db1bac 90 #define MPU_I2CSLV3_REG 0X2F //IIC从机3数据地址寄存器
Ucial 0:7365f8db1bac 91 #define MPU_I2CSLV3_CTRL_REG 0X30 //IIC从机3控制寄存器
Ucial 0:7365f8db1bac 92 #define MPU_I2CSLV4_ADDR_REG 0X31 //IIC从机4器件地址寄存器
Ucial 0:7365f8db1bac 93 #define MPU_I2CSLV4_REG 0X32 //IIC从机4数据地址寄存器
Ucial 0:7365f8db1bac 94 #define MPU_I2CSLV4_DO_REG 0X33 //IIC从机4写数据寄存器
Ucial 0:7365f8db1bac 95 #define MPU_I2CSLV4_CTRL_REG 0X34 //IIC从机4控制寄存器
Ucial 0:7365f8db1bac 96 #define MPU_I2CSLV4_DI_REG 0X35 //IIC从机4读数据寄存器
Ucial 0:7365f8db1bac 97
Ucial 0:7365f8db1bac 98 #define MPU_I2CMST_STA_REG 0X36 //IIC主机状态寄存器
Ucial 0:7365f8db1bac 99 #define MPU_INTBP_CFG_REG 0X37 //中断/旁路设置寄存器
Ucial 0:7365f8db1bac 100 #define MPU_INT_EN_REG 0X38 //中断使能寄存器
Ucial 0:7365f8db1bac 101 #define MPU_INT_STA_REG 0X3A //中断状态寄存器
Ucial 0:7365f8db1bac 102
Ucial 0:7365f8db1bac 103 #define MPU_ACCEL_XOUTH_REG 0X3B //加速度值,X轴高8位寄存器
Ucial 0:7365f8db1bac 104 #define MPU_ACCEL_XOUTL_REG 0X3C //加速度值,X轴低8位寄存器
Ucial 0:7365f8db1bac 105 #define MPU_ACCEL_YOUTH_REG 0X3D //加速度值,Y轴高8位寄存器
Ucial 0:7365f8db1bac 106 #define MPU_ACCEL_YOUTL_REG 0X3E //加速度值,Y轴低8位寄存器
Ucial 0:7365f8db1bac 107 #define MPU_ACCEL_ZOUTH_REG 0X3F //加速度值,Z轴高8位寄存器
Ucial 0:7365f8db1bac 108 #define MPU_ACCEL_ZOUTL_REG 0X40 //加速度值,Z轴低8位寄存器
Ucial 0:7365f8db1bac 109
Ucial 0:7365f8db1bac 110 #define MPU_TEMP_OUTH_REG 0X41 //温度值高八位寄存器
Ucial 0:7365f8db1bac 111 #define MPU_TEMP_OUTL_REG 0X42 //温度值低8位寄存器
Ucial 0:7365f8db1bac 112
Ucial 0:7365f8db1bac 113 #define MPU_GYRO_XOUTH_REG 0X43 //陀螺仪值,X轴高8位寄存器
Ucial 0:7365f8db1bac 114 #define MPU_GYRO_XOUTL_REG 0X44 //陀螺仪值,X轴低8位寄存器
Ucial 0:7365f8db1bac 115 #define MPU_GYRO_YOUTH_REG 0X45 //陀螺仪值,Y轴高8位寄存器
Ucial 0:7365f8db1bac 116 #define MPU_GYRO_YOUTL_REG 0X46 //陀螺仪值,Y轴低8位寄存器
Ucial 0:7365f8db1bac 117 #define MPU_GYRO_ZOUTH_REG 0X47 //陀螺仪值,Z轴高8位寄存器
Ucial 0:7365f8db1bac 118 #define MPU_GYRO_ZOUTL_REG 0X48 //陀螺仪值,Z轴低8位寄存器
Ucial 0:7365f8db1bac 119
Ucial 0:7365f8db1bac 120 #define MPU_I2CSLV0_DO_REG 0X63 //IIC从机0数据寄存器
Ucial 0:7365f8db1bac 121 #define MPU_I2CSLV1_DO_REG 0X64 //IIC从机1数据寄存器
Ucial 0:7365f8db1bac 122 #define MPU_I2CSLV2_DO_REG 0X65 //IIC从机2数据寄存器
Ucial 0:7365f8db1bac 123 #define MPU_I2CSLV3_DO_REG 0X66 //IIC从机3数据寄存器
Ucial 0:7365f8db1bac 124
Ucial 0:7365f8db1bac 125 #define MPU_I2CMST_DELAY_REG 0X67 //IIC主机延时管理寄存器
Ucial 0:7365f8db1bac 126 #define MPU_SIGPATH_RST_REG 0X68 //信号通道复位寄存器
Ucial 0:7365f8db1bac 127 #define MPU_MDETECT_CTRL_REG 0X69 //运动检测控制寄存器
Ucial 0:7365f8db1bac 128 #define MPU_USER_CTRL_REG 0X6A //用户控制寄存器
Ucial 0:7365f8db1bac 129 #define MPU_PWR_MGMT1_REG 0X6B //电源管理寄存器1
Ucial 0:7365f8db1bac 130 #define MPU_PWR_MGMT2_REG 0X6C //电源管理寄存器2
Ucial 0:7365f8db1bac 131 #define MPU_FIFO_CNTH_REG 0X72 //FIFO计数寄存器高八位
Ucial 0:7365f8db1bac 132 #define MPU_FIFO_CNTL_REG 0X73 //FIFO计数寄存器低八位
Ucial 0:7365f8db1bac 133 #define MPU_FIFO_RW_REG 0X74 //FIFO读写寄存器
Ucial 0:7365f8db1bac 134 #define MPU_DEVICE_ID_REG 0X75 //器件ID寄存器
Ucial 0:7365f8db1bac 135
Ucial 0:7365f8db1bac 136 //如果AD0脚(9脚)接地,IIC地址为0X68(不包含最低位).
Ucial 0:7365f8db1bac 137 //如果接V3.3,则IIC地址为0X69(不包含最低位).
Ucial 0:7365f8db1bac 138 #define MPU_ADDR 0X68
Ucial 0:7365f8db1bac 139
Ucial 0:7365f8db1bac 140
Ucial 0:7365f8db1bac 141 ////因为模块AD0默认接GND,所以转为读写地址后,为0XD1和0XD0(如果接VCC,则为0XD3和0XD2)
Ucial 0:7365f8db1bac 142 //#define MPU_READ 0XD1
Ucial 0:7365f8db1bac 143 //#define MPU_WRITE 0XD0
Ucial 0:7365f8db1bac 144
Ucial 0:7365f8db1bac 145 unsigned char MPU_Init(void); //初始化MPU6050
Ucial 0:7365f8db1bac 146 unsigned char MPU_Write_Len(unsigned char addr,unsigned char reg,unsigned char len,unsigned char *buf);//IIC连续写
Ucial 0:7365f8db1bac 147 unsigned char MPU_Read_Len(unsigned char addr,unsigned char reg,unsigned char len,unsigned char *buf); //IIC连续读
Ucial 0:7365f8db1bac 148 unsigned char MPU_Write_Byte(unsigned char reg,unsigned char data); //IIC写一个字节
Ucial 0:7365f8db1bac 149 unsigned char MPU_Read_Byte(unsigned char reg); //IIC读一个字节
Ucial 0:7365f8db1bac 150
Ucial 0:7365f8db1bac 151 unsigned char MPU_Set_Gyro_Fsr(unsigned char fsr);
Ucial 0:7365f8db1bac 152 unsigned char MPU_Set_Accel_Fsr(unsigned char fsr);
Ucial 0:7365f8db1bac 153 unsigned char MPU_Set_LPF(unsigned short lpf);
Ucial 0:7365f8db1bac 154 unsigned char MPU_Set_Rate(unsigned short rate);
Ucial 0:7365f8db1bac 155 unsigned char MPU_Set_Fifo(unsigned char sens);
Ucial 0:7365f8db1bac 156
Ucial 0:7365f8db1bac 157
Ucial 0:7365f8db1bac 158 short MPU_Get_Temperature(void);
Ucial 0:7365f8db1bac 159 unsigned char MPU_Get_Gyroscope(short *gx,short *gy,short *gz);
Ucial 0:7365f8db1bac 160 unsigned char MPU_Get_Accelerometer(short *ax,short *ay,short *az);
Ucial 0:7365f8db1bac 161
Ucial 0:7365f8db1bac 162 #if defined DRIVER_MODE_BALANCE
Ucial 0:7365f8db1bac 163 //IO方向设置
Ucial 0:7365f8db1bac 164 #define MPU_SDA_IN() {GPIOB->CRL&=0X0FFFFFFF;GPIOB->CRL|=8<<28;}
Ucial 0:7365f8db1bac 165 #define MPU_SDA_OUT() {GPIOB->CRL&=0X0FFFFFFF;GPIOB->CRL|=3<<28;}
Ucial 0:7365f8db1bac 166
Ucial 0:7365f8db1bac 167 //IO操作函数
Ucial 0:7365f8db1bac 168 #define MPU_IIC_SCL PBout(6) //SCL
Ucial 0:7365f8db1bac 169 #define MPU_IIC_SDA PBout(7) //SDA
Ucial 0:7365f8db1bac 170 #define MPU_READ_SDA PBin(7) //输入SDA
Ucial 0:7365f8db1bac 171 #elif defined DRIVER_MODE_ROTOR
Ucial 0:7365f8db1bac 172
Ucial 0:7365f8db1bac 173 #define MPU_SDA_IN() {GPIOB->CRH&=0XFFFF0FFF;GPIOB->CRH|=8<<12;}
Ucial 0:7365f8db1bac 174 #define MPU_SDA_OUT() {GPIOB->CRH&=0XFFFF0FFF;GPIOB->CRH|=3<<12;}
Ucial 0:7365f8db1bac 175
Ucial 0:7365f8db1bac 176 #define MPU_IIC_SCL PBout(10) //SCL
Ucial 0:7365f8db1bac 177 #define MPU_IIC_SDA PBout(11) //SDA
Ucial 0:7365f8db1bac 178 #define MPU_READ_SDA PBin(11) //输入SDA
Ucial 0:7365f8db1bac 179 #else
Ucial 0:7365f8db1bac 180 #error Target Board is not specified.
Ucial 0:7365f8db1bac 181 #endif
Ucial 0:7365f8db1bac 182
Ucial 0:7365f8db1bac 183
Ucial 0:7365f8db1bac 184 //IIC所有操作函数
Ucial 0:7365f8db1bac 185 void MPU_IIC_Delay(void); //MPU IIC延时函数
Ucial 0:7365f8db1bac 186 void MPU_IIC_Init(void); //初始化IIC的IO口
Ucial 0:7365f8db1bac 187 void MPU_IIC_Start(void); //发送IIC开始信号
Ucial 0:7365f8db1bac 188 void MPU_IIC_Stop(void); //发送IIC停止信号
Ucial 0:7365f8db1bac 189 void MPU_IIC_Send_Byte(unsigned char txd); //IIC发送一个字节
Ucial 0:7365f8db1bac 190 unsigned char MPU_IIC_Read_Byte(unsigned char ack);//IIC读取一个字节
Ucial 0:7365f8db1bac 191 unsigned char MPU_IIC_Wait_Ack(void); //IIC等待ACK信号
Ucial 0:7365f8db1bac 192 void MPU_IIC_Ack(void); //IIC发送ACK信号
Ucial 0:7365f8db1bac 193 void MPU_IIC_NAck(void); //IIC不发送ACK信号
Ucial 0:7365f8db1bac 194
Ucial 0:7365f8db1bac 195 void IMPU_IC_Write_One_Byte(unsigned char daddr,unsigned char addr,unsigned char data);
Ucial 0:7365f8db1bac 196 unsigned char MPU_IIC_Read_One_Byte(unsigned char daddr,unsigned char addr);
Ucial 0:7365f8db1bac 197
Ucial 0:7365f8db1bac 198 #define KEY_CFG_25 (0)
Ucial 0:7365f8db1bac 199 #define KEY_CFG_24 (KEY_CFG_25 + 1)
Ucial 0:7365f8db1bac 200 #define KEY_CFG_26 (KEY_CFG_24 + 1)
Ucial 0:7365f8db1bac 201 #define KEY_CFG_27 (KEY_CFG_26 + 1)
Ucial 0:7365f8db1bac 202 #define KEY_CFG_21 (KEY_CFG_27 + 1)
Ucial 0:7365f8db1bac 203 #define KEY_CFG_20 (KEY_CFG_21 + 1)
Ucial 0:7365f8db1bac 204 #define KEY_CFG_TAP4 (KEY_CFG_20 + 1)
Ucial 0:7365f8db1bac 205 #define KEY_CFG_TAP5 (KEY_CFG_TAP4 + 1)
Ucial 0:7365f8db1bac 206 #define KEY_CFG_TAP6 (KEY_CFG_TAP5 + 1)
Ucial 0:7365f8db1bac 207 #define KEY_CFG_TAP7 (KEY_CFG_TAP6 + 1)
Ucial 0:7365f8db1bac 208 #define KEY_CFG_TAP0 (KEY_CFG_TAP7 + 1)
Ucial 0:7365f8db1bac 209 #define KEY_CFG_TAP1 (KEY_CFG_TAP0 + 1)
Ucial 0:7365f8db1bac 210 #define KEY_CFG_TAP2 (KEY_CFG_TAP1 + 1)
Ucial 0:7365f8db1bac 211 #define KEY_CFG_TAP3 (KEY_CFG_TAP2 + 1)
Ucial 0:7365f8db1bac 212 #define KEY_CFG_TAP_QUANTIZE (KEY_CFG_TAP3 + 1)
Ucial 0:7365f8db1bac 213 #define KEY_CFG_TAP_JERK (KEY_CFG_TAP_QUANTIZE + 1)
Ucial 0:7365f8db1bac 214 #define KEY_CFG_DR_INT (KEY_CFG_TAP_JERK + 1)
Ucial 0:7365f8db1bac 215 #define KEY_CFG_AUTH (KEY_CFG_DR_INT + 1)
Ucial 0:7365f8db1bac 216 #define KEY_CFG_TAP_SAVE_ACCB (KEY_CFG_AUTH + 1)
Ucial 0:7365f8db1bac 217 #define KEY_CFG_TAP_CLEAR_STICKY (KEY_CFG_TAP_SAVE_ACCB + 1)
Ucial 0:7365f8db1bac 218 #define KEY_CFG_FIFO_ON_EVENT (KEY_CFG_TAP_CLEAR_STICKY + 1)
Ucial 0:7365f8db1bac 219 #define KEY_FCFG_ACCEL_INPUT (KEY_CFG_FIFO_ON_EVENT + 1)
Ucial 0:7365f8db1bac 220 #define KEY_FCFG_ACCEL_INIT (KEY_FCFG_ACCEL_INPUT + 1)
Ucial 0:7365f8db1bac 221 #define KEY_CFG_23 (KEY_FCFG_ACCEL_INIT + 1)
Ucial 0:7365f8db1bac 222 #define KEY_FCFG_1 (KEY_CFG_23 + 1)
Ucial 0:7365f8db1bac 223 #define KEY_FCFG_3 (KEY_FCFG_1 + 1)
Ucial 0:7365f8db1bac 224 #define KEY_FCFG_2 (KEY_FCFG_3 + 1)
Ucial 0:7365f8db1bac 225 #define KEY_CFG_3D (KEY_FCFG_2 + 1)
Ucial 0:7365f8db1bac 226 #define KEY_CFG_3B (KEY_CFG_3D + 1)
Ucial 0:7365f8db1bac 227 #define KEY_CFG_3C (KEY_CFG_3B + 1)
Ucial 0:7365f8db1bac 228 #define KEY_FCFG_5 (KEY_CFG_3C + 1)
Ucial 0:7365f8db1bac 229 #define KEY_FCFG_4 (KEY_FCFG_5 + 1)
Ucial 0:7365f8db1bac 230 #define KEY_FCFG_7 (KEY_FCFG_4 + 1)
Ucial 0:7365f8db1bac 231 #define KEY_FCFG_FSCALE (KEY_FCFG_7 + 1)
Ucial 0:7365f8db1bac 232 #define KEY_FCFG_AZ (KEY_FCFG_FSCALE + 1)
Ucial 0:7365f8db1bac 233 #define KEY_FCFG_6 (KEY_FCFG_AZ + 1)
Ucial 0:7365f8db1bac 234 #define KEY_FCFG_LSB4 (KEY_FCFG_6 + 1)
Ucial 0:7365f8db1bac 235 #define KEY_CFG_12 (KEY_FCFG_LSB4 + 1)
Ucial 0:7365f8db1bac 236 #define KEY_CFG_14 (KEY_CFG_12 + 1)
Ucial 0:7365f8db1bac 237 #define KEY_CFG_15 (KEY_CFG_14 + 1)
Ucial 0:7365f8db1bac 238 #define KEY_CFG_16 (KEY_CFG_15 + 1)
Ucial 0:7365f8db1bac 239 #define KEY_CFG_18 (KEY_CFG_16 + 1)
Ucial 0:7365f8db1bac 240 #define KEY_CFG_6 (KEY_CFG_18 + 1)
Ucial 0:7365f8db1bac 241 #define KEY_CFG_7 (KEY_CFG_6 + 1)
Ucial 0:7365f8db1bac 242 #define KEY_CFG_4 (KEY_CFG_7 + 1)
Ucial 0:7365f8db1bac 243 #define KEY_CFG_5 (KEY_CFG_4 + 1)
Ucial 0:7365f8db1bac 244 #define KEY_CFG_2 (KEY_CFG_5 + 1)
Ucial 0:7365f8db1bac 245 #define KEY_CFG_3 (KEY_CFG_2 + 1)
Ucial 0:7365f8db1bac 246 #define KEY_CFG_1 (KEY_CFG_3 + 1)
Ucial 0:7365f8db1bac 247 #define KEY_CFG_EXTERNAL (KEY_CFG_1 + 1)
Ucial 0:7365f8db1bac 248 #define KEY_CFG_8 (KEY_CFG_EXTERNAL + 1)
Ucial 0:7365f8db1bac 249 #define KEY_CFG_9 (KEY_CFG_8 + 1)
Ucial 0:7365f8db1bac 250 #define KEY_CFG_ORIENT_3 (KEY_CFG_9 + 1)
Ucial 0:7365f8db1bac 251 #define KEY_CFG_ORIENT_2 (KEY_CFG_ORIENT_3 + 1)
Ucial 0:7365f8db1bac 252 #define KEY_CFG_ORIENT_1 (KEY_CFG_ORIENT_2 + 1)
Ucial 0:7365f8db1bac 253 #define KEY_CFG_GYRO_SOURCE (KEY_CFG_ORIENT_1 + 1)
Ucial 0:7365f8db1bac 254 #define KEY_CFG_ORIENT_IRQ_1 (KEY_CFG_GYRO_SOURCE + 1)
Ucial 0:7365f8db1bac 255 #define KEY_CFG_ORIENT_IRQ_2 (KEY_CFG_ORIENT_IRQ_1 + 1)
Ucial 0:7365f8db1bac 256 #define KEY_CFG_ORIENT_IRQ_3 (KEY_CFG_ORIENT_IRQ_2 + 1)
Ucial 0:7365f8db1bac 257 #define KEY_FCFG_MAG_VAL (KEY_CFG_ORIENT_IRQ_3 + 1)
Ucial 0:7365f8db1bac 258 #define KEY_FCFG_MAG_MOV (KEY_FCFG_MAG_VAL + 1)
Ucial 0:7365f8db1bac 259 #define KEY_CFG_LP_QUAT (KEY_FCFG_MAG_MOV + 1)
Ucial 0:7365f8db1bac 260
Ucial 0:7365f8db1bac 261 /* MPU6050 keys */
Ucial 0:7365f8db1bac 262 #define KEY_CFG_ACCEL_FILTER (KEY_CFG_LP_QUAT + 1)
Ucial 0:7365f8db1bac 263 #define KEY_CFG_MOTION_BIAS (KEY_CFG_ACCEL_FILTER + 1)
Ucial 0:7365f8db1bac 264 #define KEY_TEMPLABEL (KEY_CFG_MOTION_BIAS + 1)
Ucial 0:7365f8db1bac 265
Ucial 0:7365f8db1bac 266 #define KEY_D_0_22 (KEY_TEMPLABEL + 1)
Ucial 0:7365f8db1bac 267 #define KEY_D_0_24 (KEY_D_0_22 + 1)
Ucial 0:7365f8db1bac 268 #define KEY_D_0_36 (KEY_D_0_24 + 1)
Ucial 0:7365f8db1bac 269 #define KEY_D_0_52 (KEY_D_0_36 + 1)
Ucial 0:7365f8db1bac 270 #define KEY_D_0_96 (KEY_D_0_52 + 1)
Ucial 0:7365f8db1bac 271 #define KEY_D_0_104 (KEY_D_0_96 + 1)
Ucial 0:7365f8db1bac 272 #define KEY_D_0_108 (KEY_D_0_104 + 1)
Ucial 0:7365f8db1bac 273 #define KEY_D_0_163 (KEY_D_0_108 + 1)
Ucial 0:7365f8db1bac 274 #define KEY_D_0_188 (KEY_D_0_163 + 1)
Ucial 0:7365f8db1bac 275 #define KEY_D_0_192 (KEY_D_0_188 + 1)
Ucial 0:7365f8db1bac 276 #define KEY_D_0_224 (KEY_D_0_192 + 1)
Ucial 0:7365f8db1bac 277 #define KEY_D_0_228 (KEY_D_0_224 + 1)
Ucial 0:7365f8db1bac 278 #define KEY_D_0_232 (KEY_D_0_228 + 1)
Ucial 0:7365f8db1bac 279 #define KEY_D_0_236 (KEY_D_0_232 + 1)
Ucial 0:7365f8db1bac 280
Ucial 0:7365f8db1bac 281 #define KEY_DMP_PREVPTAT (KEY_D_0_236 + 1)
Ucial 0:7365f8db1bac 282 #define KEY_D_1_2 (KEY_DMP_PREVPTAT + 1)
Ucial 0:7365f8db1bac 283 #define KEY_D_1_4 (KEY_D_1_2 + 1)
Ucial 0:7365f8db1bac 284 #define KEY_D_1_8 (KEY_D_1_4 + 1)
Ucial 0:7365f8db1bac 285 #define KEY_D_1_10 (KEY_D_1_8 + 1)
Ucial 0:7365f8db1bac 286 #define KEY_D_1_24 (KEY_D_1_10 + 1)
Ucial 0:7365f8db1bac 287 #define KEY_D_1_28 (KEY_D_1_24 + 1)
Ucial 0:7365f8db1bac 288 #define KEY_D_1_36 (KEY_D_1_28 + 1)
Ucial 0:7365f8db1bac 289 #define KEY_D_1_40 (KEY_D_1_36 + 1)
Ucial 0:7365f8db1bac 290 #define KEY_D_1_44 (KEY_D_1_40 + 1)
Ucial 0:7365f8db1bac 291 #define KEY_D_1_72 (KEY_D_1_44 + 1)
Ucial 0:7365f8db1bac 292 #define KEY_D_1_74 (KEY_D_1_72 + 1)
Ucial 0:7365f8db1bac 293 #define KEY_D_1_79 (KEY_D_1_74 + 1)
Ucial 0:7365f8db1bac 294 #define KEY_D_1_88 (KEY_D_1_79 + 1)
Ucial 0:7365f8db1bac 295 #define KEY_D_1_90 (KEY_D_1_88 + 1)
Ucial 0:7365f8db1bac 296 #define KEY_D_1_92 (KEY_D_1_90 + 1)
Ucial 0:7365f8db1bac 297 #define KEY_D_1_96 (KEY_D_1_92 + 1)
Ucial 0:7365f8db1bac 298 #define KEY_D_1_98 (KEY_D_1_96 + 1)
Ucial 0:7365f8db1bac 299 #define KEY_D_1_100 (KEY_D_1_98 + 1)
Ucial 0:7365f8db1bac 300 #define KEY_D_1_106 (KEY_D_1_100 + 1)
Ucial 0:7365f8db1bac 301 #define KEY_D_1_108 (KEY_D_1_106 + 1)
Ucial 0:7365f8db1bac 302 #define KEY_D_1_112 (KEY_D_1_108 + 1)
Ucial 0:7365f8db1bac 303 #define KEY_D_1_128 (KEY_D_1_112 + 1)
Ucial 0:7365f8db1bac 304 #define KEY_D_1_152 (KEY_D_1_128 + 1)
Ucial 0:7365f8db1bac 305 #define KEY_D_1_160 (KEY_D_1_152 + 1)
Ucial 0:7365f8db1bac 306 #define KEY_D_1_168 (KEY_D_1_160 + 1)
Ucial 0:7365f8db1bac 307 #define KEY_D_1_175 (KEY_D_1_168 + 1)
Ucial 0:7365f8db1bac 308 #define KEY_D_1_176 (KEY_D_1_175 + 1)
Ucial 0:7365f8db1bac 309 #define KEY_D_1_178 (KEY_D_1_176 + 1)
Ucial 0:7365f8db1bac 310 #define KEY_D_1_179 (KEY_D_1_178 + 1)
Ucial 0:7365f8db1bac 311 #define KEY_D_1_218 (KEY_D_1_179 + 1)
Ucial 0:7365f8db1bac 312 #define KEY_D_1_232 (KEY_D_1_218 + 1)
Ucial 0:7365f8db1bac 313 #define KEY_D_1_236 (KEY_D_1_232 + 1)
Ucial 0:7365f8db1bac 314 #define KEY_D_1_240 (KEY_D_1_236 + 1)
Ucial 0:7365f8db1bac 315 #define KEY_D_1_244 (KEY_D_1_240 + 1)
Ucial 0:7365f8db1bac 316 #define KEY_D_1_250 (KEY_D_1_244 + 1)
Ucial 0:7365f8db1bac 317 #define KEY_D_1_252 (KEY_D_1_250 + 1)
Ucial 0:7365f8db1bac 318 #define KEY_D_2_12 (KEY_D_1_252 + 1)
Ucial 0:7365f8db1bac 319 #define KEY_D_2_96 (KEY_D_2_12 + 1)
Ucial 0:7365f8db1bac 320 #define KEY_D_2_108 (KEY_D_2_96 + 1)
Ucial 0:7365f8db1bac 321 #define KEY_D_2_208 (KEY_D_2_108 + 1)
Ucial 0:7365f8db1bac 322 #define KEY_FLICK_MSG (KEY_D_2_208 + 1)
Ucial 0:7365f8db1bac 323 #define KEY_FLICK_COUNTER (KEY_FLICK_MSG + 1)
Ucial 0:7365f8db1bac 324 #define KEY_FLICK_LOWER (KEY_FLICK_COUNTER + 1)
Ucial 0:7365f8db1bac 325 #define KEY_CFG_FLICK_IN (KEY_FLICK_LOWER + 1)
Ucial 0:7365f8db1bac 326 #define KEY_FLICK_UPPER (KEY_CFG_FLICK_IN + 1)
Ucial 0:7365f8db1bac 327 #define KEY_CGNOTICE_INTR (KEY_FLICK_UPPER + 1)
Ucial 0:7365f8db1bac 328 #define KEY_D_2_224 (KEY_CGNOTICE_INTR + 1)
Ucial 0:7365f8db1bac 329 #define KEY_D_2_244 (KEY_D_2_224 + 1)
Ucial 0:7365f8db1bac 330 #define KEY_D_2_248 (KEY_D_2_244 + 1)
Ucial 0:7365f8db1bac 331 #define KEY_D_2_252 (KEY_D_2_248 + 1)
Ucial 0:7365f8db1bac 332
Ucial 0:7365f8db1bac 333 #define KEY_D_GYRO_BIAS_X (KEY_D_2_252 + 1)
Ucial 0:7365f8db1bac 334 #define KEY_D_GYRO_BIAS_Y (KEY_D_GYRO_BIAS_X + 1)
Ucial 0:7365f8db1bac 335 #define KEY_D_GYRO_BIAS_Z (KEY_D_GYRO_BIAS_Y + 1)
Ucial 0:7365f8db1bac 336 #define KEY_D_ACC_BIAS_X (KEY_D_GYRO_BIAS_Z + 1)
Ucial 0:7365f8db1bac 337 #define KEY_D_ACC_BIAS_Y (KEY_D_ACC_BIAS_X + 1)
Ucial 0:7365f8db1bac 338 #define KEY_D_ACC_BIAS_Z (KEY_D_ACC_BIAS_Y + 1)
Ucial 0:7365f8db1bac 339 #define KEY_D_GYRO_ENABLE (KEY_D_ACC_BIAS_Z + 1)
Ucial 0:7365f8db1bac 340 #define KEY_D_ACCEL_ENABLE (KEY_D_GYRO_ENABLE + 1)
Ucial 0:7365f8db1bac 341 #define KEY_D_QUAT_ENABLE (KEY_D_ACCEL_ENABLE +1)
Ucial 0:7365f8db1bac 342 #define KEY_D_OUTPUT_ENABLE (KEY_D_QUAT_ENABLE + 1)
Ucial 0:7365f8db1bac 343 #define KEY_D_CR_TIME_G (KEY_D_OUTPUT_ENABLE + 1)
Ucial 0:7365f8db1bac 344 #define KEY_D_CR_TIME_A (KEY_D_CR_TIME_G + 1)
Ucial 0:7365f8db1bac 345 #define KEY_D_CR_TIME_Q (KEY_D_CR_TIME_A + 1)
Ucial 0:7365f8db1bac 346 #define KEY_D_CS_TAX (KEY_D_CR_TIME_Q + 1)
Ucial 0:7365f8db1bac 347 #define KEY_D_CS_TAY (KEY_D_CS_TAX + 1)
Ucial 0:7365f8db1bac 348 #define KEY_D_CS_TAZ (KEY_D_CS_TAY + 1)
Ucial 0:7365f8db1bac 349 #define KEY_D_CS_TGX (KEY_D_CS_TAZ + 1)
Ucial 0:7365f8db1bac 350 #define KEY_D_CS_TGY (KEY_D_CS_TGX + 1)
Ucial 0:7365f8db1bac 351 #define KEY_D_CS_TGZ (KEY_D_CS_TGY + 1)
Ucial 0:7365f8db1bac 352 #define KEY_D_CS_TQ0 (KEY_D_CS_TGZ + 1)
Ucial 0:7365f8db1bac 353 #define KEY_D_CS_TQ1 (KEY_D_CS_TQ0 + 1)
Ucial 0:7365f8db1bac 354 #define KEY_D_CS_TQ2 (KEY_D_CS_TQ1 + 1)
Ucial 0:7365f8db1bac 355 #define KEY_D_CS_TQ3 (KEY_D_CS_TQ2 + 1)
Ucial 0:7365f8db1bac 356
Ucial 0:7365f8db1bac 357 /* Compass keys */
Ucial 0:7365f8db1bac 358 #define KEY_CPASS_BIAS_X (KEY_D_CS_TQ3 + 1)
Ucial 0:7365f8db1bac 359 #define KEY_CPASS_BIAS_Y (KEY_CPASS_BIAS_X + 1)
Ucial 0:7365f8db1bac 360 #define KEY_CPASS_BIAS_Z (KEY_CPASS_BIAS_Y + 1)
Ucial 0:7365f8db1bac 361 #define KEY_CPASS_MTX_00 (KEY_CPASS_BIAS_Z + 1)
Ucial 0:7365f8db1bac 362 #define KEY_CPASS_MTX_01 (KEY_CPASS_MTX_00 + 1)
Ucial 0:7365f8db1bac 363 #define KEY_CPASS_MTX_02 (KEY_CPASS_MTX_01 + 1)
Ucial 0:7365f8db1bac 364 #define KEY_CPASS_MTX_10 (KEY_CPASS_MTX_02 + 1)
Ucial 0:7365f8db1bac 365 #define KEY_CPASS_MTX_11 (KEY_CPASS_MTX_10 + 1)
Ucial 0:7365f8db1bac 366 #define KEY_CPASS_MTX_12 (KEY_CPASS_MTX_11 + 1)
Ucial 0:7365f8db1bac 367 #define KEY_CPASS_MTX_20 (KEY_CPASS_MTX_12 + 1)
Ucial 0:7365f8db1bac 368 #define KEY_CPASS_MTX_21 (KEY_CPASS_MTX_20 + 1)
Ucial 0:7365f8db1bac 369 #define KEY_CPASS_MTX_22 (KEY_CPASS_MTX_21 + 1)
Ucial 0:7365f8db1bac 370
Ucial 0:7365f8db1bac 371 /* Gesture Keys */
Ucial 0:7365f8db1bac 372 #define KEY_DMP_TAPW_MIN (KEY_CPASS_MTX_22 + 1)
Ucial 0:7365f8db1bac 373 #define KEY_DMP_TAP_THR_X (KEY_DMP_TAPW_MIN + 1)
Ucial 0:7365f8db1bac 374 #define KEY_DMP_TAP_THR_Y (KEY_DMP_TAP_THR_X + 1)
Ucial 0:7365f8db1bac 375 #define KEY_DMP_TAP_THR_Z (KEY_DMP_TAP_THR_Y + 1)
Ucial 0:7365f8db1bac 376 #define KEY_DMP_SH_TH_Y (KEY_DMP_TAP_THR_Z + 1)
Ucial 0:7365f8db1bac 377 #define KEY_DMP_SH_TH_X (KEY_DMP_SH_TH_Y + 1)
Ucial 0:7365f8db1bac 378 #define KEY_DMP_SH_TH_Z (KEY_DMP_SH_TH_X + 1)
Ucial 0:7365f8db1bac 379 #define KEY_DMP_ORIENT (KEY_DMP_SH_TH_Z + 1)
Ucial 0:7365f8db1bac 380 #define KEY_D_ACT0 (KEY_DMP_ORIENT + 1)
Ucial 0:7365f8db1bac 381 #define KEY_D_ACSX (KEY_D_ACT0 + 1)
Ucial 0:7365f8db1bac 382 #define KEY_D_ACSY (KEY_D_ACSX + 1)
Ucial 0:7365f8db1bac 383 #define KEY_D_ACSZ (KEY_D_ACSY + 1)
Ucial 0:7365f8db1bac 384
Ucial 0:7365f8db1bac 385 #define KEY_X_GRT_Y_TMP (KEY_D_ACSZ + 1)
Ucial 0:7365f8db1bac 386 #define KEY_SKIP_X_GRT_Y_TMP (KEY_X_GRT_Y_TMP + 1)
Ucial 0:7365f8db1bac 387 #define KEY_SKIP_END_COMPARE (KEY_SKIP_X_GRT_Y_TMP + 1)
Ucial 0:7365f8db1bac 388 #define KEY_END_COMPARE_Y_X_TMP2 (KEY_SKIP_END_COMPARE + 1)
Ucial 0:7365f8db1bac 389 #define KEY_CFG_ANDROID_ORIENT_INT (KEY_END_COMPARE_Y_X_TMP2 + 1)
Ucial 0:7365f8db1bac 390 #define KEY_NO_ORIENT_INTERRUPT (KEY_CFG_ANDROID_ORIENT_INT + 1)
Ucial 0:7365f8db1bac 391 #define KEY_END_COMPARE_Y_X_TMP (KEY_NO_ORIENT_INTERRUPT + 1)
Ucial 0:7365f8db1bac 392 #define KEY_END_ORIENT_1 (KEY_END_COMPARE_Y_X_TMP + 1)
Ucial 0:7365f8db1bac 393 #define KEY_END_COMPARE_Y_X (KEY_END_ORIENT_1 + 1)
Ucial 0:7365f8db1bac 394 #define KEY_END_ORIENT (KEY_END_COMPARE_Y_X + 1)
Ucial 0:7365f8db1bac 395 #define KEY_X_GRT_Y (KEY_END_ORIENT + 1)
Ucial 0:7365f8db1bac 396 #define KEY_NOT_TIME_MINUS_1 (KEY_X_GRT_Y + 1)
Ucial 0:7365f8db1bac 397 #define KEY_END_COMPARE_Y_X_TMP3 (KEY_NOT_TIME_MINUS_1 + 1)
Ucial 0:7365f8db1bac 398 #define KEY_X_GRT_Y_TMP2 (KEY_END_COMPARE_Y_X_TMP3 + 1)
Ucial 0:7365f8db1bac 399
Ucial 0:7365f8db1bac 400 /* Authenticate Keys */
Ucial 0:7365f8db1bac 401 #define KEY_D_AUTH_OUT (KEY_X_GRT_Y_TMP2 + 1)
Ucial 0:7365f8db1bac 402 #define KEY_D_AUTH_IN (KEY_D_AUTH_OUT + 1)
Ucial 0:7365f8db1bac 403 #define KEY_D_AUTH_A (KEY_D_AUTH_IN + 1)
Ucial 0:7365f8db1bac 404 #define KEY_D_AUTH_B (KEY_D_AUTH_A + 1)
Ucial 0:7365f8db1bac 405
Ucial 0:7365f8db1bac 406 /* Pedometer standalone only keys */
Ucial 0:7365f8db1bac 407 #define KEY_D_PEDSTD_BP_B (KEY_D_AUTH_B + 1)
Ucial 0:7365f8db1bac 408 #define KEY_D_PEDSTD_HP_A (KEY_D_PEDSTD_BP_B + 1)
Ucial 0:7365f8db1bac 409 #define KEY_D_PEDSTD_HP_B (KEY_D_PEDSTD_HP_A + 1)
Ucial 0:7365f8db1bac 410 #define KEY_D_PEDSTD_BP_A4 (KEY_D_PEDSTD_HP_B + 1)
Ucial 0:7365f8db1bac 411 #define KEY_D_PEDSTD_BP_A3 (KEY_D_PEDSTD_BP_A4 + 1)
Ucial 0:7365f8db1bac 412 #define KEY_D_PEDSTD_BP_A2 (KEY_D_PEDSTD_BP_A3 + 1)
Ucial 0:7365f8db1bac 413 #define KEY_D_PEDSTD_BP_A1 (KEY_D_PEDSTD_BP_A2 + 1)
Ucial 0:7365f8db1bac 414 #define KEY_D_PEDSTD_INT_THRSH (KEY_D_PEDSTD_BP_A1 + 1)
Ucial 0:7365f8db1bac 415 #define KEY_D_PEDSTD_CLIP (KEY_D_PEDSTD_INT_THRSH + 1)
Ucial 0:7365f8db1bac 416 #define KEY_D_PEDSTD_SB (KEY_D_PEDSTD_CLIP + 1)
Ucial 0:7365f8db1bac 417 #define KEY_D_PEDSTD_SB_TIME (KEY_D_PEDSTD_SB + 1)
Ucial 0:7365f8db1bac 418 #define KEY_D_PEDSTD_PEAKTHRSH (KEY_D_PEDSTD_SB_TIME + 1)
Ucial 0:7365f8db1bac 419 #define KEY_D_PEDSTD_TIML (KEY_D_PEDSTD_PEAKTHRSH + 1)
Ucial 0:7365f8db1bac 420 #define KEY_D_PEDSTD_TIMH (KEY_D_PEDSTD_TIML + 1)
Ucial 0:7365f8db1bac 421 #define KEY_D_PEDSTD_PEAK (KEY_D_PEDSTD_TIMH + 1)
Ucial 0:7365f8db1bac 422 #define KEY_D_PEDSTD_TIMECTR (KEY_D_PEDSTD_PEAK + 1)
Ucial 0:7365f8db1bac 423 #define KEY_D_PEDSTD_STEPCTR (KEY_D_PEDSTD_TIMECTR + 1)
Ucial 0:7365f8db1bac 424 #define KEY_D_PEDSTD_WALKTIME (KEY_D_PEDSTD_STEPCTR + 1)
Ucial 0:7365f8db1bac 425 #define KEY_D_PEDSTD_DECI (KEY_D_PEDSTD_WALKTIME + 1)
Ucial 0:7365f8db1bac 426
Ucial 0:7365f8db1bac 427 /*Host Based No Motion*/
Ucial 0:7365f8db1bac 428 #define KEY_D_HOST_NO_MOT (KEY_D_PEDSTD_DECI + 1)
Ucial 0:7365f8db1bac 429
Ucial 0:7365f8db1bac 430 /* EIS keys */
Ucial 0:7365f8db1bac 431 #define KEY_P_EIS_FIFO_FOOTER (KEY_D_HOST_NO_MOT + 1)
Ucial 0:7365f8db1bac 432 #define KEY_P_EIS_FIFO_YSHIFT (KEY_P_EIS_FIFO_FOOTER + 1)
Ucial 0:7365f8db1bac 433 #define KEY_P_EIS_DATA_RATE (KEY_P_EIS_FIFO_YSHIFT + 1)
Ucial 0:7365f8db1bac 434 #define KEY_P_EIS_FIFO_XSHIFT (KEY_P_EIS_DATA_RATE + 1)
Ucial 0:7365f8db1bac 435 #define KEY_P_EIS_FIFO_SYNC (KEY_P_EIS_FIFO_XSHIFT + 1)
Ucial 0:7365f8db1bac 436 #define KEY_P_EIS_FIFO_ZSHIFT (KEY_P_EIS_FIFO_SYNC + 1)
Ucial 0:7365f8db1bac 437 #define KEY_P_EIS_FIFO_READY (KEY_P_EIS_FIFO_ZSHIFT + 1)
Ucial 0:7365f8db1bac 438 #define KEY_DMP_FOOTER (KEY_P_EIS_FIFO_READY + 1)
Ucial 0:7365f8db1bac 439 #define KEY_DMP_INTX_HC (KEY_DMP_FOOTER + 1)
Ucial 0:7365f8db1bac 440 #define KEY_DMP_INTX_PH (KEY_DMP_INTX_HC + 1)
Ucial 0:7365f8db1bac 441 #define KEY_DMP_INTX_SH (KEY_DMP_INTX_PH + 1)
Ucial 0:7365f8db1bac 442 #define KEY_DMP_AINV_SH (KEY_DMP_INTX_SH + 1)
Ucial 0:7365f8db1bac 443 #define KEY_DMP_A_INV_XH (KEY_DMP_AINV_SH + 1)
Ucial 0:7365f8db1bac 444 #define KEY_DMP_AINV_PH (KEY_DMP_A_INV_XH + 1)
Ucial 0:7365f8db1bac 445 #define KEY_DMP_CTHX_H (KEY_DMP_AINV_PH + 1)
Ucial 0:7365f8db1bac 446 #define KEY_DMP_CTHY_H (KEY_DMP_CTHX_H + 1)
Ucial 0:7365f8db1bac 447 #define KEY_DMP_CTHZ_H (KEY_DMP_CTHY_H + 1)
Ucial 0:7365f8db1bac 448 #define KEY_DMP_NCTHX_H (KEY_DMP_CTHZ_H + 1)
Ucial 0:7365f8db1bac 449 #define KEY_DMP_NCTHY_H (KEY_DMP_NCTHX_H + 1)
Ucial 0:7365f8db1bac 450 #define KEY_DMP_NCTHZ_H (KEY_DMP_NCTHY_H + 1)
Ucial 0:7365f8db1bac 451 #define KEY_DMP_CTSQ_XH (KEY_DMP_NCTHZ_H + 1)
Ucial 0:7365f8db1bac 452 #define KEY_DMP_CTSQ_YH (KEY_DMP_CTSQ_XH + 1)
Ucial 0:7365f8db1bac 453 #define KEY_DMP_CTSQ_ZH (KEY_DMP_CTSQ_YH + 1)
Ucial 0:7365f8db1bac 454 #define KEY_DMP_INTX_H (KEY_DMP_CTSQ_ZH + 1)
Ucial 0:7365f8db1bac 455 #define KEY_DMP_INTY_H (KEY_DMP_INTX_H + 1)
Ucial 0:7365f8db1bac 456 #define KEY_DMP_INTZ_H (KEY_DMP_INTY_H + 1)
Ucial 0:7365f8db1bac 457 //#define KEY_DMP_HPX_H (KEY_DMP_INTZ_H + 1)
Ucial 0:7365f8db1bac 458 //#define KEY_DMP_HPY_H (KEY_DMP_HPX_H + 1)
Ucial 0:7365f8db1bac 459 //#define KEY_DMP_HPZ_H (KEY_DMP_HPY_H + 1)
Ucial 0:7365f8db1bac 460
Ucial 0:7365f8db1bac 461 /* Stream keys */
Ucial 0:7365f8db1bac 462 #define KEY_STREAM_P_GYRO_Z (KEY_DMP_INTZ_H + 1)
Ucial 0:7365f8db1bac 463 #define KEY_STREAM_P_GYRO_Y (KEY_STREAM_P_GYRO_Z + 1)
Ucial 0:7365f8db1bac 464 #define KEY_STREAM_P_GYRO_X (KEY_STREAM_P_GYRO_Y + 1)
Ucial 0:7365f8db1bac 465 #define KEY_STREAM_P_TEMP (KEY_STREAM_P_GYRO_X + 1)
Ucial 0:7365f8db1bac 466 #define KEY_STREAM_P_AUX_Y (KEY_STREAM_P_TEMP + 1)
Ucial 0:7365f8db1bac 467 #define KEY_STREAM_P_AUX_X (KEY_STREAM_P_AUX_Y + 1)
Ucial 0:7365f8db1bac 468 #define KEY_STREAM_P_AUX_Z (KEY_STREAM_P_AUX_X + 1)
Ucial 0:7365f8db1bac 469 #define KEY_STREAM_P_ACCEL_Y (KEY_STREAM_P_AUX_Z + 1)
Ucial 0:7365f8db1bac 470 #define KEY_STREAM_P_ACCEL_X (KEY_STREAM_P_ACCEL_Y + 1)
Ucial 0:7365f8db1bac 471 #define KEY_STREAM_P_FOOTER (KEY_STREAM_P_ACCEL_X + 1)
Ucial 0:7365f8db1bac 472 #define KEY_STREAM_P_ACCEL_Z (KEY_STREAM_P_FOOTER + 1)
Ucial 0:7365f8db1bac 473
Ucial 0:7365f8db1bac 474 #define NUM_KEYS (KEY_STREAM_P_ACCEL_Z + 1)
Ucial 0:7365f8db1bac 475
Ucial 0:7365f8db1bac 476 typedef struct {
Ucial 0:7365f8db1bac 477 unsigned short key;
Ucial 0:7365f8db1bac 478 unsigned short addr;
Ucial 0:7365f8db1bac 479 } tKeyLabel;
Ucial 0:7365f8db1bac 480
Ucial 0:7365f8db1bac 481 #define DINA0A 0x0a
Ucial 0:7365f8db1bac 482 #define DINA22 0x22
Ucial 0:7365f8db1bac 483 #define DINA42 0x42
Ucial 0:7365f8db1bac 484 #define DINA5A 0x5a
Ucial 0:7365f8db1bac 485
Ucial 0:7365f8db1bac 486 #define DINA06 0x06
Ucial 0:7365f8db1bac 487 #define DINA0E 0x0e
Ucial 0:7365f8db1bac 488 #define DINA16 0x16
Ucial 0:7365f8db1bac 489 #define DINA1E 0x1e
Ucial 0:7365f8db1bac 490 #define DINA26 0x26
Ucial 0:7365f8db1bac 491 #define DINA2E 0x2e
Ucial 0:7365f8db1bac 492 #define DINA36 0x36
Ucial 0:7365f8db1bac 493 #define DINA3E 0x3e
Ucial 0:7365f8db1bac 494 #define DINA46 0x46
Ucial 0:7365f8db1bac 495 #define DINA4E 0x4e
Ucial 0:7365f8db1bac 496 #define DINA56 0x56
Ucial 0:7365f8db1bac 497 #define DINA5E 0x5e
Ucial 0:7365f8db1bac 498 #define DINA66 0x66
Ucial 0:7365f8db1bac 499 #define DINA6E 0x6e
Ucial 0:7365f8db1bac 500 #define DINA76 0x76
Ucial 0:7365f8db1bac 501 #define DINA7E 0x7e
Ucial 0:7365f8db1bac 502
Ucial 0:7365f8db1bac 503 #define DINA00 0x00
Ucial 0:7365f8db1bac 504 #define DINA08 0x08
Ucial 0:7365f8db1bac 505 #define DINA10 0x10
Ucial 0:7365f8db1bac 506 #define DINA18 0x18
Ucial 0:7365f8db1bac 507 #define DINA20 0x20
Ucial 0:7365f8db1bac 508 #define DINA28 0x28
Ucial 0:7365f8db1bac 509 #define DINA30 0x30
Ucial 0:7365f8db1bac 510 #define DINA38 0x38
Ucial 0:7365f8db1bac 511 #define DINA40 0x40
Ucial 0:7365f8db1bac 512 #define DINA48 0x48
Ucial 0:7365f8db1bac 513 #define DINA50 0x50
Ucial 0:7365f8db1bac 514 #define DINA58 0x58
Ucial 0:7365f8db1bac 515 #define DINA60 0x60
Ucial 0:7365f8db1bac 516 #define DINA68 0x68
Ucial 0:7365f8db1bac 517 #define DINA70 0x70
Ucial 0:7365f8db1bac 518 #define DINA78 0x78
Ucial 0:7365f8db1bac 519
Ucial 0:7365f8db1bac 520 #define DINA04 0x04
Ucial 0:7365f8db1bac 521 #define DINA0C 0x0c
Ucial 0:7365f8db1bac 522 #define DINA14 0x14
Ucial 0:7365f8db1bac 523 #define DINA1C 0x1C
Ucial 0:7365f8db1bac 524 #define DINA24 0x24
Ucial 0:7365f8db1bac 525 #define DINA2C 0x2c
Ucial 0:7365f8db1bac 526 #define DINA34 0x34
Ucial 0:7365f8db1bac 527 #define DINA3C 0x3c
Ucial 0:7365f8db1bac 528 #define DINA44 0x44
Ucial 0:7365f8db1bac 529 #define DINA4C 0x4c
Ucial 0:7365f8db1bac 530 #define DINA54 0x54
Ucial 0:7365f8db1bac 531 #define DINA5C 0x5c
Ucial 0:7365f8db1bac 532 #define DINA64 0x64
Ucial 0:7365f8db1bac 533 #define DINA6C 0x6c
Ucial 0:7365f8db1bac 534 #define DINA74 0x74
Ucial 0:7365f8db1bac 535 #define DINA7C 0x7c
Ucial 0:7365f8db1bac 536
Ucial 0:7365f8db1bac 537 #define DINA01 0x01
Ucial 0:7365f8db1bac 538 #define DINA09 0x09
Ucial 0:7365f8db1bac 539 #define DINA11 0x11
Ucial 0:7365f8db1bac 540 #define DINA19 0x19
Ucial 0:7365f8db1bac 541 #define DINA21 0x21
Ucial 0:7365f8db1bac 542 #define DINA29 0x29
Ucial 0:7365f8db1bac 543 #define DINA31 0x31
Ucial 0:7365f8db1bac 544 #define DINA39 0x39
Ucial 0:7365f8db1bac 545 #define DINA41 0x41
Ucial 0:7365f8db1bac 546 #define DINA49 0x49
Ucial 0:7365f8db1bac 547 #define DINA51 0x51
Ucial 0:7365f8db1bac 548 #define DINA59 0x59
Ucial 0:7365f8db1bac 549 #define DINA61 0x61
Ucial 0:7365f8db1bac 550 #define DINA69 0x69
Ucial 0:7365f8db1bac 551 #define DINA71 0x71
Ucial 0:7365f8db1bac 552 #define DINA79 0x79
Ucial 0:7365f8db1bac 553
Ucial 0:7365f8db1bac 554 #define DINA25 0x25
Ucial 0:7365f8db1bac 555 #define DINA2D 0x2d
Ucial 0:7365f8db1bac 556 #define DINA35 0x35
Ucial 0:7365f8db1bac 557 #define DINA3D 0x3d
Ucial 0:7365f8db1bac 558 #define DINA4D 0x4d
Ucial 0:7365f8db1bac 559 #define DINA55 0x55
Ucial 0:7365f8db1bac 560 #define DINA5D 0x5D
Ucial 0:7365f8db1bac 561 #define DINA6D 0x6d
Ucial 0:7365f8db1bac 562 #define DINA75 0x75
Ucial 0:7365f8db1bac 563 #define DINA7D 0x7d
Ucial 0:7365f8db1bac 564
Ucial 0:7365f8db1bac 565 #define DINADC 0xdc
Ucial 0:7365f8db1bac 566 #define DINAF2 0xf2
Ucial 0:7365f8db1bac 567 #define DINAAB 0xab
Ucial 0:7365f8db1bac 568 #define DINAAA 0xaa
Ucial 0:7365f8db1bac 569 #define DINAF1 0xf1
Ucial 0:7365f8db1bac 570 #define DINADF 0xdf
Ucial 0:7365f8db1bac 571 #define DINADA 0xda
Ucial 0:7365f8db1bac 572 #define DINAB1 0xb1
Ucial 0:7365f8db1bac 573 #define DINAB9 0xb9
Ucial 0:7365f8db1bac 574 #define DINAF3 0xf3
Ucial 0:7365f8db1bac 575 #define DINA8B 0x8b
Ucial 0:7365f8db1bac 576 #define DINAA3 0xa3
Ucial 0:7365f8db1bac 577 #define DINA91 0x91
Ucial 0:7365f8db1bac 578 #define DINAB6 0xb6
Ucial 0:7365f8db1bac 579 #define DINAB4 0xb4
Ucial 0:7365f8db1bac 580
Ucial 0:7365f8db1bac 581
Ucial 0:7365f8db1bac 582 #define DINC00 0x00
Ucial 0:7365f8db1bac 583 #define DINC01 0x01
Ucial 0:7365f8db1bac 584 #define DINC02 0x02
Ucial 0:7365f8db1bac 585 #define DINC03 0x03
Ucial 0:7365f8db1bac 586 #define DINC08 0x08
Ucial 0:7365f8db1bac 587 #define DINC09 0x09
Ucial 0:7365f8db1bac 588 #define DINC0A 0x0a
Ucial 0:7365f8db1bac 589 #define DINC0B 0x0b
Ucial 0:7365f8db1bac 590 #define DINC10 0x10
Ucial 0:7365f8db1bac 591 #define DINC11 0x11
Ucial 0:7365f8db1bac 592 #define DINC12 0x12
Ucial 0:7365f8db1bac 593 #define DINC13 0x13
Ucial 0:7365f8db1bac 594 #define DINC18 0x18
Ucial 0:7365f8db1bac 595 #define DINC19 0x19
Ucial 0:7365f8db1bac 596 #define DINC1A 0x1a
Ucial 0:7365f8db1bac 597 #define DINC1B 0x1b
Ucial 0:7365f8db1bac 598
Ucial 0:7365f8db1bac 599 #define DINC20 0x20
Ucial 0:7365f8db1bac 600 #define DINC21 0x21
Ucial 0:7365f8db1bac 601 #define DINC22 0x22
Ucial 0:7365f8db1bac 602 #define DINC23 0x23
Ucial 0:7365f8db1bac 603 #define DINC28 0x28
Ucial 0:7365f8db1bac 604 #define DINC29 0x29
Ucial 0:7365f8db1bac 605 #define DINC2A 0x2a
Ucial 0:7365f8db1bac 606 #define DINC2B 0x2b
Ucial 0:7365f8db1bac 607 #define DINC30 0x30
Ucial 0:7365f8db1bac 608 #define DINC31 0x31
Ucial 0:7365f8db1bac 609 #define DINC32 0x32
Ucial 0:7365f8db1bac 610 #define DINC33 0x33
Ucial 0:7365f8db1bac 611 #define DINC38 0x38
Ucial 0:7365f8db1bac 612 #define DINC39 0x39
Ucial 0:7365f8db1bac 613 #define DINC3A 0x3a
Ucial 0:7365f8db1bac 614 #define DINC3B 0x3b
Ucial 0:7365f8db1bac 615
Ucial 0:7365f8db1bac 616 #define DINC40 0x40
Ucial 0:7365f8db1bac 617 #define DINC41 0x41
Ucial 0:7365f8db1bac 618 #define DINC42 0x42
Ucial 0:7365f8db1bac 619 #define DINC43 0x43
Ucial 0:7365f8db1bac 620 #define DINC48 0x48
Ucial 0:7365f8db1bac 621 #define DINC49 0x49
Ucial 0:7365f8db1bac 622 #define DINC4A 0x4a
Ucial 0:7365f8db1bac 623 #define DINC4B 0x4b
Ucial 0:7365f8db1bac 624 #define DINC50 0x50
Ucial 0:7365f8db1bac 625 #define DINC51 0x51
Ucial 0:7365f8db1bac 626 #define DINC52 0x52
Ucial 0:7365f8db1bac 627 #define DINC53 0x53
Ucial 0:7365f8db1bac 628 #define DINC58 0x58
Ucial 0:7365f8db1bac 629 #define DINC59 0x59
Ucial 0:7365f8db1bac 630 #define DINC5A 0x5a
Ucial 0:7365f8db1bac 631 #define DINC5B 0x5b
Ucial 0:7365f8db1bac 632
Ucial 0:7365f8db1bac 633 #define DINC60 0x60
Ucial 0:7365f8db1bac 634 #define DINC61 0x61
Ucial 0:7365f8db1bac 635 #define DINC62 0x62
Ucial 0:7365f8db1bac 636 #define DINC63 0x63
Ucial 0:7365f8db1bac 637 #define DINC68 0x68
Ucial 0:7365f8db1bac 638 #define DINC69 0x69
Ucial 0:7365f8db1bac 639 #define DINC6A 0x6a
Ucial 0:7365f8db1bac 640 #define DINC6B 0x6b
Ucial 0:7365f8db1bac 641 #define DINC70 0x70
Ucial 0:7365f8db1bac 642 #define DINC71 0x71
Ucial 0:7365f8db1bac 643 #define DINC72 0x72
Ucial 0:7365f8db1bac 644 #define DINC73 0x73
Ucial 0:7365f8db1bac 645 #define DINC78 0x78
Ucial 0:7365f8db1bac 646 #define DINC79 0x79
Ucial 0:7365f8db1bac 647 #define DINC7A 0x7a
Ucial 0:7365f8db1bac 648 #define DINC7B 0x7b
Ucial 0:7365f8db1bac 649
Ucial 0:7365f8db1bac 650 #define DIND40 0x40
Ucial 0:7365f8db1bac 651
Ucial 0:7365f8db1bac 652
Ucial 0:7365f8db1bac 653 #define DINA80 0x80
Ucial 0:7365f8db1bac 654 #define DINA90 0x90
Ucial 0:7365f8db1bac 655 #define DINAA0 0xa0
Ucial 0:7365f8db1bac 656 #define DINAC9 0xc9
Ucial 0:7365f8db1bac 657 #define DINACB 0xcb
Ucial 0:7365f8db1bac 658 #define DINACD 0xcd
Ucial 0:7365f8db1bac 659 #define DINACF 0xcf
Ucial 0:7365f8db1bac 660 #define DINAC8 0xc8
Ucial 0:7365f8db1bac 661 #define DINACA 0xca
Ucial 0:7365f8db1bac 662 #define DINACC 0xcc
Ucial 0:7365f8db1bac 663 #define DINACE 0xce
Ucial 0:7365f8db1bac 664 #define DINAD8 0xd8
Ucial 0:7365f8db1bac 665 #define DINADD 0xdd
Ucial 0:7365f8db1bac 666 #define DINAF8 0xf0
Ucial 0:7365f8db1bac 667 #define DINAFE 0xfe
Ucial 0:7365f8db1bac 668
Ucial 0:7365f8db1bac 669 #define DINBF8 0xf8
Ucial 0:7365f8db1bac 670 #define DINAC0 0xb0
Ucial 0:7365f8db1bac 671 #define DINAC1 0xb1
Ucial 0:7365f8db1bac 672 #define DINAC2 0xb4
Ucial 0:7365f8db1bac 673 #define DINAC3 0xb5
Ucial 0:7365f8db1bac 674 #define DINAC4 0xb8
Ucial 0:7365f8db1bac 675 #define DINAC5 0xb9
Ucial 0:7365f8db1bac 676 #define DINBC0 0xc0
Ucial 0:7365f8db1bac 677 #define DINBC2 0xc2
Ucial 0:7365f8db1bac 678 #define DINBC4 0xc4
Ucial 0:7365f8db1bac 679 #define DINBC6 0xc6
Ucial 0:7365f8db1bac 680
Ucial 0:7365f8db1bac 681 #ifdef __cplusplus
Ucial 0:7365f8db1bac 682 extern "C"
Ucial 0:7365f8db1bac 683 {
Ucial 0:7365f8db1bac 684 #endif
Ucial 0:7365f8db1bac 685
Ucial 0:7365f8db1bac 686 #define DMP_PTAT 0
Ucial 0:7365f8db1bac 687 #define DMP_XGYR 2
Ucial 0:7365f8db1bac 688 #define DMP_YGYR 4
Ucial 0:7365f8db1bac 689 #define DMP_ZGYR 6
Ucial 0:7365f8db1bac 690 #define DMP_XACC 8
Ucial 0:7365f8db1bac 691 #define DMP_YACC 10
Ucial 0:7365f8db1bac 692 #define DMP_ZACC 12
Ucial 0:7365f8db1bac 693 #define DMP_ADC1 14
Ucial 0:7365f8db1bac 694 #define DMP_ADC2 16
Ucial 0:7365f8db1bac 695 #define DMP_ADC3 18
Ucial 0:7365f8db1bac 696 #define DMP_BIASUNC 20
Ucial 0:7365f8db1bac 697 #define DMP_FIFORT 22
Ucial 0:7365f8db1bac 698 #define DMP_INVGSFH 24
Ucial 0:7365f8db1bac 699 #define DMP_INVGSFL 26
Ucial 0:7365f8db1bac 700 #define DMP_1H 28
Ucial 0:7365f8db1bac 701 #define DMP_1L 30
Ucial 0:7365f8db1bac 702 #define DMP_BLPFSTCH 32
Ucial 0:7365f8db1bac 703 #define DMP_BLPFSTCL 34
Ucial 0:7365f8db1bac 704 #define DMP_BLPFSXH 36
Ucial 0:7365f8db1bac 705 #define DMP_BLPFSXL 38
Ucial 0:7365f8db1bac 706 #define DMP_BLPFSYH 40
Ucial 0:7365f8db1bac 707 #define DMP_BLPFSYL 42
Ucial 0:7365f8db1bac 708 #define DMP_BLPFSZH 44
Ucial 0:7365f8db1bac 709 #define DMP_BLPFSZL 46
Ucial 0:7365f8db1bac 710 #define DMP_BLPFMTC 48
Ucial 0:7365f8db1bac 711 #define DMP_SMC 50
Ucial 0:7365f8db1bac 712 #define DMP_BLPFMXH 52
Ucial 0:7365f8db1bac 713 #define DMP_BLPFMXL 54
Ucial 0:7365f8db1bac 714 #define DMP_BLPFMYH 56
Ucial 0:7365f8db1bac 715 #define DMP_BLPFMYL 58
Ucial 0:7365f8db1bac 716 #define DMP_BLPFMZH 60
Ucial 0:7365f8db1bac 717 #define DMP_BLPFMZL 62
Ucial 0:7365f8db1bac 718 #define DMP_BLPFC 64
Ucial 0:7365f8db1bac 719 #define DMP_SMCTH 66
Ucial 0:7365f8db1bac 720 #define DMP_0H2 68
Ucial 0:7365f8db1bac 721 #define DMP_0L2 70
Ucial 0:7365f8db1bac 722 #define DMP_BERR2H 72
Ucial 0:7365f8db1bac 723 #define DMP_BERR2L 74
Ucial 0:7365f8db1bac 724 #define DMP_BERR2NH 76
Ucial 0:7365f8db1bac 725 #define DMP_SMCINC 78
Ucial 0:7365f8db1bac 726 #define DMP_ANGVBXH 80
Ucial 0:7365f8db1bac 727 #define DMP_ANGVBXL 82
Ucial 0:7365f8db1bac 728 #define DMP_ANGVBYH 84
Ucial 0:7365f8db1bac 729 #define DMP_ANGVBYL 86
Ucial 0:7365f8db1bac 730 #define DMP_ANGVBZH 88
Ucial 0:7365f8db1bac 731 #define DMP_ANGVBZL 90
Ucial 0:7365f8db1bac 732 #define DMP_BERR1H 92
Ucial 0:7365f8db1bac 733 #define DMP_BERR1L 94
Ucial 0:7365f8db1bac 734 #define DMP_ATCH 96
Ucial 0:7365f8db1bac 735 #define DMP_BIASUNCSF 98
Ucial 0:7365f8db1bac 736 #define DMP_ACT2H 100
Ucial 0:7365f8db1bac 737 #define DMP_ACT2L 102
Ucial 0:7365f8db1bac 738 #define DMP_GSFH 104
Ucial 0:7365f8db1bac 739 #define DMP_GSFL 106
Ucial 0:7365f8db1bac 740 #define DMP_GH 108
Ucial 0:7365f8db1bac 741 #define DMP_GL 110
Ucial 0:7365f8db1bac 742 #define DMP_0_5H 112
Ucial 0:7365f8db1bac 743 #define DMP_0_5L 114
Ucial 0:7365f8db1bac 744 #define DMP_0_0H 116
Ucial 0:7365f8db1bac 745 #define DMP_0_0L 118
Ucial 0:7365f8db1bac 746 #define DMP_1_0H 120
Ucial 0:7365f8db1bac 747 #define DMP_1_0L 122
Ucial 0:7365f8db1bac 748 #define DMP_1_5H 124
Ucial 0:7365f8db1bac 749 #define DMP_1_5L 126
Ucial 0:7365f8db1bac 750 #define DMP_TMP1AH 128
Ucial 0:7365f8db1bac 751 #define DMP_TMP1AL 130
Ucial 0:7365f8db1bac 752 #define DMP_TMP2AH 132
Ucial 0:7365f8db1bac 753 #define DMP_TMP2AL 134
Ucial 0:7365f8db1bac 754 #define DMP_TMP3AH 136
Ucial 0:7365f8db1bac 755 #define DMP_TMP3AL 138
Ucial 0:7365f8db1bac 756 #define DMP_TMP4AH 140
Ucial 0:7365f8db1bac 757 #define DMP_TMP4AL 142
Ucial 0:7365f8db1bac 758 #define DMP_XACCW 144
Ucial 0:7365f8db1bac 759 #define DMP_TMP5 146
Ucial 0:7365f8db1bac 760 #define DMP_XACCB 148
Ucial 0:7365f8db1bac 761 #define DMP_TMP8 150
Ucial 0:7365f8db1bac 762 #define DMP_YACCB 152
Ucial 0:7365f8db1bac 763 #define DMP_TMP9 154
Ucial 0:7365f8db1bac 764 #define DMP_ZACCB 156
Ucial 0:7365f8db1bac 765 #define DMP_TMP10 158
Ucial 0:7365f8db1bac 766 #define DMP_DZH 160
Ucial 0:7365f8db1bac 767 #define DMP_DZL 162
Ucial 0:7365f8db1bac 768 #define DMP_XGCH 164
Ucial 0:7365f8db1bac 769 #define DMP_XGCL 166
Ucial 0:7365f8db1bac 770 #define DMP_YGCH 168
Ucial 0:7365f8db1bac 771 #define DMP_YGCL 170
Ucial 0:7365f8db1bac 772 #define DMP_ZGCH 172
Ucial 0:7365f8db1bac 773 #define DMP_ZGCL 174
Ucial 0:7365f8db1bac 774 #define DMP_YACCW 176
Ucial 0:7365f8db1bac 775 #define DMP_TMP7 178
Ucial 0:7365f8db1bac 776 #define DMP_AFB1H 180
Ucial 0:7365f8db1bac 777 #define DMP_AFB1L 182
Ucial 0:7365f8db1bac 778 #define DMP_AFB2H 184
Ucial 0:7365f8db1bac 779 #define DMP_AFB2L 186
Ucial 0:7365f8db1bac 780 #define DMP_MAGFBH 188
Ucial 0:7365f8db1bac 781 #define DMP_MAGFBL 190
Ucial 0:7365f8db1bac 782 #define DMP_QT1H 192
Ucial 0:7365f8db1bac 783 #define DMP_QT1L 194
Ucial 0:7365f8db1bac 784 #define DMP_QT2H 196
Ucial 0:7365f8db1bac 785 #define DMP_QT2L 198
Ucial 0:7365f8db1bac 786 #define DMP_QT3H 200
Ucial 0:7365f8db1bac 787 #define DMP_QT3L 202
Ucial 0:7365f8db1bac 788 #define DMP_QT4H 204
Ucial 0:7365f8db1bac 789 #define DMP_QT4L 206
Ucial 0:7365f8db1bac 790 #define DMP_CTRL1H 208
Ucial 0:7365f8db1bac 791 #define DMP_CTRL1L 210
Ucial 0:7365f8db1bac 792 #define DMP_CTRL2H 212
Ucial 0:7365f8db1bac 793 #define DMP_CTRL2L 214
Ucial 0:7365f8db1bac 794 #define DMP_CTRL3H 216
Ucial 0:7365f8db1bac 795 #define DMP_CTRL3L 218
Ucial 0:7365f8db1bac 796 #define DMP_CTRL4H 220
Ucial 0:7365f8db1bac 797 #define DMP_CTRL4L 222
Ucial 0:7365f8db1bac 798 #define DMP_CTRLS1 224
Ucial 0:7365f8db1bac 799 #define DMP_CTRLSF1 226
Ucial 0:7365f8db1bac 800 #define DMP_CTRLS2 228
Ucial 0:7365f8db1bac 801 #define DMP_CTRLSF2 230
Ucial 0:7365f8db1bac 802 #define DMP_CTRLS3 232
Ucial 0:7365f8db1bac 803 #define DMP_CTRLSFNLL 234
Ucial 0:7365f8db1bac 804 #define DMP_CTRLS4 236
Ucial 0:7365f8db1bac 805 #define DMP_CTRLSFNL2 238
Ucial 0:7365f8db1bac 806 #define DMP_CTRLSFNL 240
Ucial 0:7365f8db1bac 807 #define DMP_TMP30 242
Ucial 0:7365f8db1bac 808 #define DMP_CTRLSFJT 244
Ucial 0:7365f8db1bac 809 #define DMP_TMP31 246
Ucial 0:7365f8db1bac 810 #define DMP_TMP11 248
Ucial 0:7365f8db1bac 811 #define DMP_CTRLSF2_2 250
Ucial 0:7365f8db1bac 812 #define DMP_TMP12 252
Ucial 0:7365f8db1bac 813 #define DMP_CTRLSF1_2 254
Ucial 0:7365f8db1bac 814 #define DMP_PREVPTAT 256
Ucial 0:7365f8db1bac 815 #define DMP_ACCZB 258
Ucial 0:7365f8db1bac 816 #define DMP_ACCXB 264
Ucial 0:7365f8db1bac 817 #define DMP_ACCYB 266
Ucial 0:7365f8db1bac 818 #define DMP_1HB 272
Ucial 0:7365f8db1bac 819 #define DMP_1LB 274
Ucial 0:7365f8db1bac 820 #define DMP_0H 276
Ucial 0:7365f8db1bac 821 #define DMP_0L 278
Ucial 0:7365f8db1bac 822 #define DMP_ASR22H 280
Ucial 0:7365f8db1bac 823 #define DMP_ASR22L 282
Ucial 0:7365f8db1bac 824 #define DMP_ASR6H 284
Ucial 0:7365f8db1bac 825 #define DMP_ASR6L 286
Ucial 0:7365f8db1bac 826 #define DMP_TMP13 288
Ucial 0:7365f8db1bac 827 #define DMP_TMP14 290
Ucial 0:7365f8db1bac 828 #define DMP_FINTXH 292
Ucial 0:7365f8db1bac 829 #define DMP_FINTXL 294
Ucial 0:7365f8db1bac 830 #define DMP_FINTYH 296
Ucial 0:7365f8db1bac 831 #define DMP_FINTYL 298
Ucial 0:7365f8db1bac 832 #define DMP_FINTZH 300
Ucial 0:7365f8db1bac 833 #define DMP_FINTZL 302
Ucial 0:7365f8db1bac 834 #define DMP_TMP1BH 304
Ucial 0:7365f8db1bac 835 #define DMP_TMP1BL 306
Ucial 0:7365f8db1bac 836 #define DMP_TMP2BH 308
Ucial 0:7365f8db1bac 837 #define DMP_TMP2BL 310
Ucial 0:7365f8db1bac 838 #define DMP_TMP3BH 312
Ucial 0:7365f8db1bac 839 #define DMP_TMP3BL 314
Ucial 0:7365f8db1bac 840 #define DMP_TMP4BH 316
Ucial 0:7365f8db1bac 841 #define DMP_TMP4BL 318
Ucial 0:7365f8db1bac 842 #define DMP_STXG 320
Ucial 0:7365f8db1bac 843 #define DMP_ZCTXG 322
Ucial 0:7365f8db1bac 844 #define DMP_STYG 324
Ucial 0:7365f8db1bac 845 #define DMP_ZCTYG 326
Ucial 0:7365f8db1bac 846 #define DMP_STZG 328
Ucial 0:7365f8db1bac 847 #define DMP_ZCTZG 330
Ucial 0:7365f8db1bac 848 #define DMP_CTRLSFJT2 332
Ucial 0:7365f8db1bac 849 #define DMP_CTRLSFJTCNT 334
Ucial 0:7365f8db1bac 850 #define DMP_PVXG 336
Ucial 0:7365f8db1bac 851 #define DMP_TMP15 338
Ucial 0:7365f8db1bac 852 #define DMP_PVYG 340
Ucial 0:7365f8db1bac 853 #define DMP_TMP16 342
Ucial 0:7365f8db1bac 854 #define DMP_PVZG 344
Ucial 0:7365f8db1bac 855 #define DMP_TMP17 346
Ucial 0:7365f8db1bac 856 #define DMP_MNMFLAGH 352
Ucial 0:7365f8db1bac 857 #define DMP_MNMFLAGL 354
Ucial 0:7365f8db1bac 858 #define DMP_MNMTMH 356
Ucial 0:7365f8db1bac 859 #define DMP_MNMTML 358
Ucial 0:7365f8db1bac 860 #define DMP_MNMTMTHRH 360
Ucial 0:7365f8db1bac 861 #define DMP_MNMTMTHRL 362
Ucial 0:7365f8db1bac 862 #define DMP_MNMTHRH 364
Ucial 0:7365f8db1bac 863 #define DMP_MNMTHRL 366
Ucial 0:7365f8db1bac 864 #define DMP_ACCQD4H 368
Ucial 0:7365f8db1bac 865 #define DMP_ACCQD4L 370
Ucial 0:7365f8db1bac 866 #define DMP_ACCQD5H 372
Ucial 0:7365f8db1bac 867 #define DMP_ACCQD5L 374
Ucial 0:7365f8db1bac 868 #define DMP_ACCQD6H 376
Ucial 0:7365f8db1bac 869 #define DMP_ACCQD6L 378
Ucial 0:7365f8db1bac 870 #define DMP_ACCQD7H 380
Ucial 0:7365f8db1bac 871 #define DMP_ACCQD7L 382
Ucial 0:7365f8db1bac 872 #define DMP_ACCQD0H 384
Ucial 0:7365f8db1bac 873 #define DMP_ACCQD0L 386
Ucial 0:7365f8db1bac 874 #define DMP_ACCQD1H 388
Ucial 0:7365f8db1bac 875 #define DMP_ACCQD1L 390
Ucial 0:7365f8db1bac 876 #define DMP_ACCQD2H 392
Ucial 0:7365f8db1bac 877 #define DMP_ACCQD2L 394
Ucial 0:7365f8db1bac 878 #define DMP_ACCQD3H 396
Ucial 0:7365f8db1bac 879 #define DMP_ACCQD3L 398
Ucial 0:7365f8db1bac 880 #define DMP_XN2H 400
Ucial 0:7365f8db1bac 881 #define DMP_XN2L 402
Ucial 0:7365f8db1bac 882 #define DMP_XN1H 404
Ucial 0:7365f8db1bac 883 #define DMP_XN1L 406
Ucial 0:7365f8db1bac 884 #define DMP_YN2H 408
Ucial 0:7365f8db1bac 885 #define DMP_YN2L 410
Ucial 0:7365f8db1bac 886 #define DMP_YN1H 412
Ucial 0:7365f8db1bac 887 #define DMP_YN1L 414
Ucial 0:7365f8db1bac 888 #define DMP_YH 416
Ucial 0:7365f8db1bac 889 #define DMP_YL 418
Ucial 0:7365f8db1bac 890 #define DMP_B0H 420
Ucial 0:7365f8db1bac 891 #define DMP_B0L 422
Ucial 0:7365f8db1bac 892 #define DMP_A1H 424
Ucial 0:7365f8db1bac 893 #define DMP_A1L 426
Ucial 0:7365f8db1bac 894 #define DMP_A2H 428
Ucial 0:7365f8db1bac 895 #define DMP_A2L 430
Ucial 0:7365f8db1bac 896 #define DMP_SEM1 432
Ucial 0:7365f8db1bac 897 #define DMP_FIFOCNT 434
Ucial 0:7365f8db1bac 898 #define DMP_SH_TH_X 436
Ucial 0:7365f8db1bac 899 #define DMP_PACKET 438
Ucial 0:7365f8db1bac 900 #define DMP_SH_TH_Y 440
Ucial 0:7365f8db1bac 901 #define DMP_FOOTER 442
Ucial 0:7365f8db1bac 902 #define DMP_SH_TH_Z 444
Ucial 0:7365f8db1bac 903 #define DMP_TEMP29 448
Ucial 0:7365f8db1bac 904 #define DMP_TEMP30 450
Ucial 0:7365f8db1bac 905 #define DMP_XACCB_PRE 452
Ucial 0:7365f8db1bac 906 #define DMP_XACCB_PREL 454
Ucial 0:7365f8db1bac 907 #define DMP_YACCB_PRE 456
Ucial 0:7365f8db1bac 908 #define DMP_YACCB_PREL 458
Ucial 0:7365f8db1bac 909 #define DMP_ZACCB_PRE 460
Ucial 0:7365f8db1bac 910 #define DMP_ZACCB_PREL 462
Ucial 0:7365f8db1bac 911 #define DMP_TMP22 464
Ucial 0:7365f8db1bac 912 #define DMP_TAP_TIMER 466
Ucial 0:7365f8db1bac 913 #define DMP_TAP_THX 468
Ucial 0:7365f8db1bac 914 #define DMP_TAP_THY 472
Ucial 0:7365f8db1bac 915 #define DMP_TAP_THZ 476
Ucial 0:7365f8db1bac 916 #define DMP_TAPW_MIN 478
Ucial 0:7365f8db1bac 917 #define DMP_TMP25 480
Ucial 0:7365f8db1bac 918 #define DMP_TMP26 482
Ucial 0:7365f8db1bac 919 #define DMP_TMP27 484
Ucial 0:7365f8db1bac 920 #define DMP_TMP28 486
Ucial 0:7365f8db1bac 921 #define DMP_ORIENT 488
Ucial 0:7365f8db1bac 922 #define DMP_THRSH 490
Ucial 0:7365f8db1bac 923 #define DMP_ENDIANH 492
Ucial 0:7365f8db1bac 924 #define DMP_ENDIANL 494
Ucial 0:7365f8db1bac 925 #define DMP_BLPFNMTCH 496
Ucial 0:7365f8db1bac 926 #define DMP_BLPFNMTCL 498
Ucial 0:7365f8db1bac 927 #define DMP_BLPFNMXH 500
Ucial 0:7365f8db1bac 928 #define DMP_BLPFNMXL 502
Ucial 0:7365f8db1bac 929 #define DMP_BLPFNMYH 504
Ucial 0:7365f8db1bac 930 #define DMP_BLPFNMYL 506
Ucial 0:7365f8db1bac 931 #define DMP_BLPFNMZH 508
Ucial 0:7365f8db1bac 932 #define DMP_BLPFNMZL 510
Ucial 0:7365f8db1bac 933 #ifdef __cplusplus
Ucial 0:7365f8db1bac 934 }
Ucial 0:7365f8db1bac 935 #endif
Ucial 0:7365f8db1bac 936
Ucial 0:7365f8db1bac 937 //定义输出速度
Ucial 0:7365f8db1bac 938 #define DEFAULT_MPU_HZ (100) //100Hz
Ucial 0:7365f8db1bac 939
Ucial 0:7365f8db1bac 940 #define INV_X_GYRO (0x40)
Ucial 0:7365f8db1bac 941 #define INV_Y_GYRO (0x20)
Ucial 0:7365f8db1bac 942 #define INV_Z_GYRO (0x10)
Ucial 0:7365f8db1bac 943 #define INV_XYZ_GYRO (INV_X_GYRO | INV_Y_GYRO | INV_Z_GYRO)
Ucial 0:7365f8db1bac 944 #define INV_XYZ_ACCEL (0x08)
Ucial 0:7365f8db1bac 945 #define INV_XYZ_COMPASS (0x01)
Ucial 0:7365f8db1bac 946
Ucial 0:7365f8db1bac 947 //移植官方MSP430 DMP驱动过来
Ucial 0:7365f8db1bac 948 struct int_param_s {
Ucial 0:7365f8db1bac 949 //#if defined EMPL_TARGET_MSP430 || defined MOTION_DRIVER_TARGET_MSP430
Ucial 0:7365f8db1bac 950 void (*cb)(void);
Ucial 0:7365f8db1bac 951 unsigned short pin;
Ucial 0:7365f8db1bac 952 unsigned char lp_exit;
Ucial 0:7365f8db1bac 953 unsigned char active_low;
Ucial 0:7365f8db1bac 954 //#elif defined EMPL_TARGET_UC3L0
Ucial 0:7365f8db1bac 955 // unsigned long pin;
Ucial 0:7365f8db1bac 956 // void (*cb)(volatile void*);
Ucial 0:7365f8db1bac 957 // void *arg;
Ucial 0:7365f8db1bac 958 //#endif
Ucial 0:7365f8db1bac 959 };
Ucial 0:7365f8db1bac 960
Ucial 0:7365f8db1bac 961 #define MPU_INT_STATUS_DATA_READY (0x0001)
Ucial 0:7365f8db1bac 962 #define MPU_INT_STATUS_DMP (0x0002)
Ucial 0:7365f8db1bac 963 #define MPU_INT_STATUS_PLL_READY (0x0004)
Ucial 0:7365f8db1bac 964 #define MPU_INT_STATUS_I2C_MST (0x0008)
Ucial 0:7365f8db1bac 965 #define MPU_INT_STATUS_FIFO_OVERFLOW (0x0010)
Ucial 0:7365f8db1bac 966 #define MPU_INT_STATUS_ZMOT (0x0020)
Ucial 0:7365f8db1bac 967 #define MPU_INT_STATUS_MOT (0x0040)
Ucial 0:7365f8db1bac 968 #define MPU_INT_STATUS_FREE_FALL (0x0080)
Ucial 0:7365f8db1bac 969 #define MPU_INT_STATUS_DMP_0 (0x0100)
Ucial 0:7365f8db1bac 970 #define MPU_INT_STATUS_DMP_1 (0x0200)
Ucial 0:7365f8db1bac 971 #define MPU_INT_STATUS_DMP_2 (0x0400)
Ucial 0:7365f8db1bac 972 #define MPU_INT_STATUS_DMP_3 (0x0800)
Ucial 0:7365f8db1bac 973 #define MPU_INT_STATUS_DMP_4 (0x1000)
Ucial 0:7365f8db1bac 974 #define MPU_INT_STATUS_DMP_5 (0x2000)
Ucial 0:7365f8db1bac 975
Ucial 0:7365f8db1bac 976 /* Set up APIs */
Ucial 0:7365f8db1bac 977 int mpu_init(void);
Ucial 0:7365f8db1bac 978 int mpu_init_slave(void);
Ucial 0:7365f8db1bac 979 int mpu_set_bypass(unsigned char bypass_on);
Ucial 0:7365f8db1bac 980
Ucial 0:7365f8db1bac 981 /* Configuration APIs */
Ucial 0:7365f8db1bac 982 int mpu_lp_accel_mode(unsigned char rate);
Ucial 0:7365f8db1bac 983 int mpu_lp_motion_interrupt(unsigned short thresh, unsigned char time,
Ucial 0:7365f8db1bac 984 unsigned char lpa_freq);
Ucial 0:7365f8db1bac 985 int mpu_set_int_level(unsigned char active_low);
Ucial 0:7365f8db1bac 986 int mpu_set_int_latched(unsigned char enable);
Ucial 0:7365f8db1bac 987
Ucial 0:7365f8db1bac 988 int mpu_set_dmp_state(unsigned char enable);
Ucial 0:7365f8db1bac 989 int mpu_get_dmp_state(unsigned char *enabled);
Ucial 0:7365f8db1bac 990
Ucial 0:7365f8db1bac 991 int mpu_get_lpf(unsigned short *lpf);
Ucial 0:7365f8db1bac 992 int mpu_set_lpf(unsigned short lpf);
Ucial 0:7365f8db1bac 993
Ucial 0:7365f8db1bac 994 int mpu_get_gyro_fsr(unsigned short *fsr);
Ucial 0:7365f8db1bac 995 int mpu_set_gyro_fsr(unsigned short fsr);
Ucial 0:7365f8db1bac 996
Ucial 0:7365f8db1bac 997 int mpu_get_accel_fsr(unsigned char *fsr);
Ucial 0:7365f8db1bac 998 int mpu_set_accel_fsr(unsigned char fsr);
Ucial 0:7365f8db1bac 999
Ucial 0:7365f8db1bac 1000 int mpu_get_compass_fsr(unsigned short *fsr);
Ucial 0:7365f8db1bac 1001
Ucial 0:7365f8db1bac 1002 int mpu_get_gyro_sens(float *sens);
Ucial 0:7365f8db1bac 1003 int mpu_get_accel_sens(unsigned short *sens);
Ucial 0:7365f8db1bac 1004
Ucial 0:7365f8db1bac 1005 int mpu_get_sample_rate(unsigned short *rate);
Ucial 0:7365f8db1bac 1006 int mpu_set_sample_rate(unsigned short rate);
Ucial 0:7365f8db1bac 1007 int mpu_get_compass_sample_rate(unsigned short *rate);
Ucial 0:7365f8db1bac 1008 int mpu_set_compass_sample_rate(unsigned short rate);
Ucial 0:7365f8db1bac 1009
Ucial 0:7365f8db1bac 1010 int mpu_get_fifo_config(unsigned char *sensors);
Ucial 0:7365f8db1bac 1011 int mpu_configure_fifo(unsigned char sensors);
Ucial 0:7365f8db1bac 1012
Ucial 0:7365f8db1bac 1013 int mpu_get_power_state(unsigned char *power_on);
Ucial 0:7365f8db1bac 1014 int mpu_set_sensors(unsigned char sensors);
Ucial 0:7365f8db1bac 1015
Ucial 0:7365f8db1bac 1016 int mpu_set_accel_bias(const long *accel_bias);
Ucial 0:7365f8db1bac 1017
Ucial 0:7365f8db1bac 1018 /* Data getter/setter APIs */
Ucial 0:7365f8db1bac 1019 int mpu_get_gyro_reg(short *data, unsigned long *timestamp);
Ucial 0:7365f8db1bac 1020 int mpu_get_accel_reg(short *data, unsigned long *timestamp);
Ucial 0:7365f8db1bac 1021 int mpu_get_compass_reg(short *data, unsigned long *timestamp);
Ucial 0:7365f8db1bac 1022 int mpu_get_temperature(long *data, unsigned long *timestamp);
Ucial 0:7365f8db1bac 1023
Ucial 0:7365f8db1bac 1024 int mpu_get_int_status(short *status);
Ucial 0:7365f8db1bac 1025 int mpu_read_fifo(short *gyro, short *accel, unsigned long *timestamp,
Ucial 0:7365f8db1bac 1026 unsigned char *sensors, unsigned char *more);
Ucial 0:7365f8db1bac 1027 int mpu_read_fifo_stream(unsigned short length, unsigned char *data,
Ucial 0:7365f8db1bac 1028 unsigned char *more);
Ucial 0:7365f8db1bac 1029 int mpu_reset_fifo(void);
Ucial 0:7365f8db1bac 1030
Ucial 0:7365f8db1bac 1031 int mpu_write_mem(unsigned short mem_addr, unsigned short length,
Ucial 0:7365f8db1bac 1032 unsigned char *data);
Ucial 0:7365f8db1bac 1033 int mpu_read_mem(unsigned short mem_addr, unsigned short length,
Ucial 0:7365f8db1bac 1034 unsigned char *data);
Ucial 0:7365f8db1bac 1035 int mpu_load_firmware(unsigned short length, const unsigned char *firmware,
Ucial 0:7365f8db1bac 1036 unsigned short start_addr, unsigned short sample_rate);
Ucial 0:7365f8db1bac 1037
Ucial 0:7365f8db1bac 1038 int mpu_reg_dump(void);
Ucial 0:7365f8db1bac 1039 int mpu_read_reg(unsigned char reg, unsigned char *data);
Ucial 0:7365f8db1bac 1040 int mpu_run_self_test(long *gyro, long *accel);
Ucial 0:7365f8db1bac 1041 int mpu_register_tap_cb(void (*func)(unsigned char, unsigned char));
Ucial 0:7365f8db1bac 1042 //自行添加的一些函数
Ucial 0:7365f8db1bac 1043 void mget_ms(unsigned long *time);
Ucial 0:7365f8db1bac 1044 unsigned short inv_row_2_scale(const signed char *row);
Ucial 0:7365f8db1bac 1045 unsigned short inv_orientation_matrix_to_scalar(const signed char *mtx);
Ucial 0:7365f8db1bac 1046 unsigned char run_self_test(void);
Ucial 0:7365f8db1bac 1047 unsigned char mpu_dmp_init(void);
Ucial 0:7365f8db1bac 1048 unsigned char mpu_dmp_get_data(float *pitch,float *roll,float *yaw);
Ucial 0:7365f8db1bac 1049
Ucial 0:7365f8db1bac 1050 #define TAP_X (0x01)
Ucial 0:7365f8db1bac 1051 #define TAP_Y (0x02)
Ucial 0:7365f8db1bac 1052 #define TAP_Z (0x04)
Ucial 0:7365f8db1bac 1053 #define TAP_XYZ (0x07)
Ucial 0:7365f8db1bac 1054
Ucial 0:7365f8db1bac 1055 #define TAP_X_UP (0x01)
Ucial 0:7365f8db1bac 1056 #define TAP_X_DOWN (0x02)
Ucial 0:7365f8db1bac 1057 #define TAP_Y_UP (0x03)
Ucial 0:7365f8db1bac 1058 #define TAP_Y_DOWN (0x04)
Ucial 0:7365f8db1bac 1059 #define TAP_Z_UP (0x05)
Ucial 0:7365f8db1bac 1060 #define TAP_Z_DOWN (0x06)
Ucial 0:7365f8db1bac 1061
Ucial 0:7365f8db1bac 1062 #define ANDROID_ORIENT_PORTRAIT (0x00)
Ucial 0:7365f8db1bac 1063 #define ANDROID_ORIENT_LANDSCAPE (0x01)
Ucial 0:7365f8db1bac 1064 #define ANDROID_ORIENT_REVERSE_PORTRAIT (0x02)
Ucial 0:7365f8db1bac 1065 #define ANDROID_ORIENT_REVERSE_LANDSCAPE (0x03)
Ucial 0:7365f8db1bac 1066
Ucial 0:7365f8db1bac 1067 #define DMP_INT_GESTURE (0x01)
Ucial 0:7365f8db1bac 1068 #define DMP_INT_CONTINUOUS (0x02)
Ucial 0:7365f8db1bac 1069
Ucial 0:7365f8db1bac 1070 #define DMP_FEATURE_TAP (0x001)
Ucial 0:7365f8db1bac 1071 #define DMP_FEATURE_ANDROID_ORIENT (0x002)
Ucial 0:7365f8db1bac 1072 #define DMP_FEATURE_LP_QUAT (0x004)
Ucial 0:7365f8db1bac 1073 #define DMP_FEATURE_PEDOMETER (0x008)
Ucial 0:7365f8db1bac 1074 #define DMP_FEATURE_6X_LP_QUAT (0x010)
Ucial 0:7365f8db1bac 1075 #define DMP_FEATURE_GYRO_CAL (0x020)
Ucial 0:7365f8db1bac 1076 #define DMP_FEATURE_SEND_RAW_ACCEL (0x040)
Ucial 0:7365f8db1bac 1077 #define DMP_FEATURE_SEND_RAW_GYRO (0x080)
Ucial 0:7365f8db1bac 1078 #define DMP_FEATURE_SEND_CAL_GYRO (0x100)
Ucial 0:7365f8db1bac 1079
Ucial 0:7365f8db1bac 1080 #define INV_WXYZ_QUAT (0x100)
Ucial 0:7365f8db1bac 1081
Ucial 0:7365f8db1bac 1082 /* Set up functions. */
Ucial 0:7365f8db1bac 1083 int dmp_load_motion_driver_firmware(void);
Ucial 0:7365f8db1bac 1084 int dmp_set_fifo_rate(unsigned short rate);
Ucial 0:7365f8db1bac 1085 int dmp_get_fifo_rate(unsigned short *rate);
Ucial 0:7365f8db1bac 1086 int dmp_enable_feature(unsigned short mask);
Ucial 0:7365f8db1bac 1087 int dmp_get_enabled_features(unsigned short *mask);
Ucial 0:7365f8db1bac 1088 int dmp_set_interrupt_mode(unsigned char mode);
Ucial 0:7365f8db1bac 1089 int dmp_set_orientation(unsigned short orient);
Ucial 0:7365f8db1bac 1090 int dmp_set_gyro_bias(long *bias);
Ucial 0:7365f8db1bac 1091 int dmp_set_accel_bias(long *bias);
Ucial 0:7365f8db1bac 1092
Ucial 0:7365f8db1bac 1093 /* Tap functions. */
Ucial 0:7365f8db1bac 1094 int dmp_register_tap_cb(void (*func)(unsigned char, unsigned char));
Ucial 0:7365f8db1bac 1095 int dmp_set_tap_thresh(unsigned char axis, unsigned short thresh);
Ucial 0:7365f8db1bac 1096 int dmp_set_tap_axes(unsigned char axis);
Ucial 0:7365f8db1bac 1097 int dmp_set_tap_count(unsigned char min_taps);
Ucial 0:7365f8db1bac 1098 int dmp_set_tap_time(unsigned short time);
Ucial 0:7365f8db1bac 1099 int dmp_set_tap_time_multi(unsigned short time);
Ucial 0:7365f8db1bac 1100 int dmp_set_shake_reject_thresh(long sf, unsigned short thresh);
Ucial 0:7365f8db1bac 1101 int dmp_set_shake_reject_time(unsigned short time);
Ucial 0:7365f8db1bac 1102 int dmp_set_shake_reject_timeout(unsigned short time);
Ucial 0:7365f8db1bac 1103
Ucial 0:7365f8db1bac 1104 /* Android orientation functions. */
Ucial 0:7365f8db1bac 1105 int dmp_register_android_orient_cb(void (*func)(unsigned char));
Ucial 0:7365f8db1bac 1106
Ucial 0:7365f8db1bac 1107 /* LP quaternion functions. */
Ucial 0:7365f8db1bac 1108 int dmp_enable_lp_quat(unsigned char enable);
Ucial 0:7365f8db1bac 1109 int dmp_enable_6x_lp_quat(unsigned char enable);
Ucial 0:7365f8db1bac 1110
Ucial 0:7365f8db1bac 1111 /* Pedometer functions. */
Ucial 0:7365f8db1bac 1112 int dmp_get_pedometer_step_count(unsigned long *count);
Ucial 0:7365f8db1bac 1113 int dmp_set_pedometer_step_count(unsigned long count);
Ucial 0:7365f8db1bac 1114 int dmp_get_pedometer_walk_time(unsigned long *time);
Ucial 0:7365f8db1bac 1115 int dmp_set_pedometer_walk_time(unsigned long time);
Ucial 0:7365f8db1bac 1116
Ucial 0:7365f8db1bac 1117 /* DMP gyro calibration functions. */
Ucial 0:7365f8db1bac 1118 int dmp_enable_gyro_cal(unsigned char enable);
Ucial 0:7365f8db1bac 1119
Ucial 0:7365f8db1bac 1120 /* Read function. This function should be called whenever the MPU interrupt is
Ucial 0:7365f8db1bac 1121 * detected.
Ucial 0:7365f8db1bac 1122 */
Ucial 0:7365f8db1bac 1123 int dmp_read_fifo(short *gyro, short *accel, long *quat,
Ucial 0:7365f8db1bac 1124 unsigned long *timestamp, short *sensors, unsigned char *more);
Ucial 0:7365f8db1bac 1125
Ucial 0:7365f8db1bac 1126 #endif
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