Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c@153:fa9ff456f731, 2016-12-20 (annotated)

Committer:
<>
Date:
Tue Dec 20 17:27:56 2016 +0000
Revision:
153:fa9ff456f731
Parent:
149:156823d33999
Child:
160:d5399cc887bb
This updates the lib to the mbed lib v132

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 * Copyright (c) 2015-2016 Nuvoton
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 149:156823d33999 5 * you may not use this file except in compliance with the License.
<> 149:156823d33999 6 * You may obtain a copy of the License at
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 9 *
<> 149:156823d33999 10 * Unless required by applicable law or agreed to in writing, software
<> 149:156823d33999 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 149:156823d33999 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 149:156823d33999 13 * See the License for the specific language governing permissions and
<> 149:156823d33999 14 * limitations under the License.
<> 149:156823d33999 15 */
<> 149:156823d33999 16
<> 149:156823d33999 17 #include "i2c_api.h"
<> 149:156823d33999 18
<> 149:156823d33999 19 #if DEVICE_I2C
<> 149:156823d33999 20
<> 149:156823d33999 21 #include "cmsis.h"
<> 149:156823d33999 22 #include "pinmap.h"
<> 149:156823d33999 23 #include "PeripheralPins.h"
<> 149:156823d33999 24 #include "nu_modutil.h"
<> 149:156823d33999 25 #include "nu_miscutil.h"
<> 149:156823d33999 26 #include "nu_bitutil.h"
<> 149:156823d33999 27 #include "critical.h"
<> 149:156823d33999 28
<> 149:156823d33999 29 #define NU_I2C_DEBUG 0
<> 149:156823d33999 30
<> 149:156823d33999 31 #if NU_I2C_DEBUG
<> 149:156823d33999 32 struct i2c_s MY_I2C;
<> 149:156823d33999 33 struct i2c_s MY_I2C_2;
<> 149:156823d33999 34 char MY_I2C_STATUS[64];
<> 149:156823d33999 35 int MY_I2C_STATUS_POS = 0;
<> 149:156823d33999 36 uint32_t MY_I2C_TIMEOUT;
<> 149:156823d33999 37 uint32_t MY_I2C_ELAPSED;
<> 149:156823d33999 38 uint32_t MY_I2C_T1;
<> 149:156823d33999 39 uint32_t MY_I2C_T2;
<> 149:156823d33999 40 #endif
<> 149:156823d33999 41
<> 149:156823d33999 42 struct nu_i2c_var {
<> 149:156823d33999 43 i2c_t * obj;
<> 149:156823d33999 44 void (*vec)(void);
<> 149:156823d33999 45 };
<> 149:156823d33999 46
<> 149:156823d33999 47 static void i2c0_vec(void);
<> 149:156823d33999 48 static void i2c1_vec(void);
<> 149:156823d33999 49 static void i2c_irq(i2c_t *obj);
<> 149:156823d33999 50 static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl);
<> 153:fa9ff456f731 51 static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked);
<> 149:156823d33999 52
<> 149:156823d33999 53 static struct nu_i2c_var i2c0_var = {
<> 149:156823d33999 54 .obj = NULL,
<> 149:156823d33999 55 .vec = i2c0_vec,
<> 149:156823d33999 56 };
<> 149:156823d33999 57 static struct nu_i2c_var i2c1_var = {
<> 149:156823d33999 58 .obj = NULL,
<> 149:156823d33999 59 .vec = i2c1_vec,
<> 149:156823d33999 60 };
<> 149:156823d33999 61
<> 149:156823d33999 62 static uint32_t i2c_modinit_mask = 0;
<> 149:156823d33999 63
<> 149:156823d33999 64 static const struct nu_modinit_s i2c_modinit_tab[] = {
<> 149:156823d33999 65 {I2C_0, I2C0_MODULE, 0, 0, I2C0_RST, I2C0_IRQn, &i2c0_var},
<> 149:156823d33999 66 {I2C_1, I2C1_MODULE, 0, 0, I2C1_RST, I2C1_IRQn, &i2c1_var},
<> 149:156823d33999 67
<> 149:156823d33999 68 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
<> 149:156823d33999 69 };
<> 149:156823d33999 70
<> 149:156823d33999 71 static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata);
<> 149:156823d33999 72 static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
<> 149:156823d33999 73 #define NU_I2C_TIMEOUT_STAT_INT 500000
<> 149:156823d33999 74 #define NU_I2C_TIMEOUT_STOP 500000
<> 149:156823d33999 75 static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout);
<> 149:156823d33999 76 static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout);
<> 149:156823d33999 77 //static int i2c_is_stat_int(i2c_t *obj);
<> 149:156823d33999 78 //static int i2c_is_stop_det(i2c_t *obj);
<> 149:156823d33999 79 static int i2c_is_trsn_done(i2c_t *obj);
<> 149:156823d33999 80 static int i2c_is_tran_started(i2c_t *obj);
<> 149:156823d33999 81 static int i2c_addr2data(int address, int read);
<> 149:156823d33999 82 #if DEVICE_I2CSLAVE
<> 149:156823d33999 83 // Convert mbed address to BSP address.
<> 149:156823d33999 84 static int i2c_addr2bspaddr(int address);
<> 149:156823d33999 85 #endif // #if DEVICE_I2CSLAVE
<> 149:156823d33999 86 static void i2c_enable_int(i2c_t *obj);
<> 149:156823d33999 87 static void i2c_disable_int(i2c_t *obj);
<> 149:156823d33999 88 static int i2c_set_int(i2c_t *obj, int inten);
<> 149:156823d33999 89
<> 149:156823d33999 90
<> 149:156823d33999 91 #if DEVICE_I2C_ASYNCH
<> 149:156823d33999 92 static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
<> 149:156823d33999 93 static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable);
<> 149:156823d33999 94 static void i2c_rollback_vector_interrupt(i2c_t *obj);
<> 149:156823d33999 95 #endif
<> 149:156823d33999 96
<> 149:156823d33999 97 #define TRANCTRL_STARTED (1)
<> 149:156823d33999 98 #define TRANCTRL_NAKLASTDATA (1 << 1)
<> 153:fa9ff456f731 99 #define TRANCTRL_LASTDATANAKED (1 << 2)
<> 149:156823d33999 100
<> 149:156823d33999 101 uint32_t us_ticker_read(void);
<> 149:156823d33999 102
<> 149:156823d33999 103 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
<> 149:156823d33999 104 {
<> 149:156823d33999 105 uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
<> 149:156823d33999 106 uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
<> 149:156823d33999 107 obj->i2c.i2c = (I2CName) pinmap_merge(i2c_sda, i2c_scl);
<> 149:156823d33999 108 MBED_ASSERT((int)obj->i2c.i2c != NC);
<> 149:156823d33999 109
<> 149:156823d33999 110 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
<> 149:156823d33999 111 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 112 MBED_ASSERT(modinit->modname == obj->i2c.i2c);
<> 149:156823d33999 113
<> 149:156823d33999 114 // Reset this module
<> 149:156823d33999 115 SYS_ResetModule(modinit->rsetidx);
<> 149:156823d33999 116
<> 149:156823d33999 117 // Enable IP clock
<> 149:156823d33999 118 CLK_EnableModuleClock(modinit->clkidx);
<> 149:156823d33999 119
<> 149:156823d33999 120 pinmap_pinout(sda, PinMap_I2C_SDA);
<> 149:156823d33999 121 pinmap_pinout(scl, PinMap_I2C_SCL);
<> 149:156823d33999 122
<> 149:156823d33999 123 #if DEVICE_I2C_ASYNCH
<> 149:156823d33999 124 obj->i2c.dma_usage = DMA_USAGE_NEVER;
<> 149:156823d33999 125 obj->i2c.event = 0;
<> 149:156823d33999 126 obj->i2c.stop = 0;
<> 149:156823d33999 127 obj->i2c.address = 0;
<> 149:156823d33999 128 #endif
<> 149:156823d33999 129
<> 149:156823d33999 130 // NOTE: Setting I2C bus clock to 100 KHz is required. See I2C::I2C in common/I2C.cpp.
<> 149:156823d33999 131 I2C_Open((I2C_T *) NU_MODBASE(obj->i2c.i2c), 100000);
<> 149:156823d33999 132 // NOTE: INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL. We cannot control interrupt through
<> 149:156823d33999 133 // INTEN bit without impacting FSM control bits. Use NVIC_EnableIRQ/NVIC_DisableIRQ instead for interrupt control.
<> 149:156823d33999 134 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
<> 149:156823d33999 135 i2c_base->CTL |= (I2C_CTL_INTEN_Msk | I2C_CTL_I2CEN_Msk);
<> 149:156823d33999 136
<> 149:156823d33999 137 // Enable sync-moce vector interrupt.
<> 149:156823d33999 138 struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
<> 149:156823d33999 139 var->obj = obj;
<> 149:156823d33999 140 obj->i2c.tran_ctrl = 0;
<> 149:156823d33999 141 obj->i2c.stop = 0;
<> 149:156823d33999 142 i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
<> 149:156823d33999 143
<> 149:156823d33999 144 // Mark this module to be inited.
<> 149:156823d33999 145 int i = modinit - i2c_modinit_tab;
<> 149:156823d33999 146 i2c_modinit_mask |= 1 << i;
<> 149:156823d33999 147 }
<> 149:156823d33999 148
<> 149:156823d33999 149 int i2c_start(i2c_t *obj)
<> 149:156823d33999 150 {
<> 149:156823d33999 151 return i2c_do_trsn(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk, 1);
<> 149:156823d33999 152 }
<> 149:156823d33999 153
<> 149:156823d33999 154 int i2c_stop(i2c_t *obj)
<> 149:156823d33999 155 {
<> 149:156823d33999 156 return i2c_do_trsn(obj, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk, 1);
<> 149:156823d33999 157 }
<> 149:156823d33999 158
<> 149:156823d33999 159 void i2c_frequency(i2c_t *obj, int hz)
<> 149:156823d33999 160 {
<> 149:156823d33999 161 I2C_SetBusClockFreq((I2C_T *) NU_MODBASE(obj->i2c.i2c), hz);
<> 149:156823d33999 162 }
<> 149:156823d33999 163
<> 149:156823d33999 164 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
<> 149:156823d33999 165 {
<> 149:156823d33999 166 if (i2c_start(obj)) {
<> 149:156823d33999 167 i2c_stop(obj);
<> 149:156823d33999 168 return I2C_ERROR_BUS_BUSY;
<> 149:156823d33999 169 }
<> 149:156823d33999 170
<> 153:fa9ff456f731 171 if (i2c_byte_write(obj, i2c_addr2data(address, 1)) != 1) {
<> 149:156823d33999 172 i2c_stop(obj);
<> 149:156823d33999 173 return I2C_ERROR_NO_SLAVE;
<> 149:156823d33999 174 }
<> 149:156823d33999 175
<> 149:156823d33999 176 // Read in bytes
<> 149:156823d33999 177 length = i2c_do_tran(obj, data, length, 1, 1);
<> 149:156823d33999 178
<> 149:156823d33999 179 // If not repeated start, send stop.
<> 149:156823d33999 180 if (stop) {
<> 149:156823d33999 181 i2c_stop(obj);
<> 149:156823d33999 182 }
<> 149:156823d33999 183
<> 149:156823d33999 184 return length;
<> 149:156823d33999 185 }
<> 149:156823d33999 186
<> 149:156823d33999 187 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
<> 149:156823d33999 188 {
<> 149:156823d33999 189 if (i2c_start(obj)) {
<> 149:156823d33999 190 i2c_stop(obj);
<> 149:156823d33999 191 return I2C_ERROR_BUS_BUSY;
<> 149:156823d33999 192 }
<> 149:156823d33999 193
<> 153:fa9ff456f731 194 if (i2c_byte_write(obj, i2c_addr2data(address, 0)) != 1) {
<> 149:156823d33999 195 i2c_stop(obj);
<> 149:156823d33999 196 return I2C_ERROR_NO_SLAVE;
<> 149:156823d33999 197 }
<> 149:156823d33999 198
<> 149:156823d33999 199 // Write out bytes
<> 149:156823d33999 200 length = i2c_do_tran(obj, (char *) data, length, 0, 1);
<> 149:156823d33999 201
<> 149:156823d33999 202 if (stop) {
<> 149:156823d33999 203 i2c_stop(obj);
<> 149:156823d33999 204 }
<> 149:156823d33999 205
<> 149:156823d33999 206 return length;
<> 149:156823d33999 207 }
<> 149:156823d33999 208
<> 149:156823d33999 209 void i2c_reset(i2c_t *obj)
<> 149:156823d33999 210 {
<> 149:156823d33999 211 i2c_stop(obj);
<> 149:156823d33999 212 }
<> 149:156823d33999 213
<> 149:156823d33999 214 int i2c_byte_read(i2c_t *obj, int last)
<> 149:156823d33999 215 {
<> 149:156823d33999 216 char data = 0;
<> 153:fa9ff456f731 217 i2c_do_tran(obj, &data, 1, 1, last);
<> 149:156823d33999 218 return data;
<> 149:156823d33999 219 }
<> 149:156823d33999 220
<> 149:156823d33999 221 int i2c_byte_write(i2c_t *obj, int data)
<> 149:156823d33999 222 {
<> 153:fa9ff456f731 223 char data_[1];
<> 153:fa9ff456f731 224 data_[0] = data & 0xFF;
<> 153:fa9ff456f731 225
<> 153:fa9ff456f731 226 if (i2c_do_tran(obj, data_, 1, 0, 0) == 1 &&
<> 153:fa9ff456f731 227 ! (obj->i2c.tran_ctrl & TRANCTRL_LASTDATANAKED)) {
<> 153:fa9ff456f731 228 return 1;
<> 153:fa9ff456f731 229 }
<> 153:fa9ff456f731 230 else {
<> 153:fa9ff456f731 231 return 0;
<> 153:fa9ff456f731 232 }
<> 149:156823d33999 233 }
<> 149:156823d33999 234
<> 149:156823d33999 235 #if DEVICE_I2CSLAVE
<> 149:156823d33999 236
<> 149:156823d33999 237 // See I2CSlave.h
<> 149:156823d33999 238 #define NoData 0 // the slave has not been addressed
<> 149:156823d33999 239 #define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
<> 149:156823d33999 240 #define WriteGeneral 2 // the master is writing to all slave
<> 149:156823d33999 241 #define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
<> 149:156823d33999 242
<> 149:156823d33999 243 void i2c_slave_mode(i2c_t *obj, int enable_slave)
<> 149:156823d33999 244 {
<> 149:156823d33999 245 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
<> 149:156823d33999 246
<> 149:156823d33999 247 i2c_disable_int(obj);
<> 149:156823d33999 248
<> 149:156823d33999 249 obj->i2c.slaveaddr_state = NoData;
<> 149:156823d33999 250
<> 149:156823d33999 251 // Switch to not addressed mode
<> 149:156823d33999 252 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
<> 149:156823d33999 253
<> 149:156823d33999 254 i2c_enable_int(obj);
<> 149:156823d33999 255 }
<> 149:156823d33999 256
<> 149:156823d33999 257 int i2c_slave_receive(i2c_t *obj)
<> 149:156823d33999 258 {
<> 149:156823d33999 259 int slaveaddr_state;
<> 149:156823d33999 260
<> 149:156823d33999 261 i2c_disable_int(obj);
<> 149:156823d33999 262 slaveaddr_state = obj->i2c.slaveaddr_state;
<> 149:156823d33999 263 i2c_enable_int(obj);
<> 149:156823d33999 264
<> 149:156823d33999 265 return slaveaddr_state;
<> 149:156823d33999 266 }
<> 149:156823d33999 267
<> 149:156823d33999 268 int i2c_slave_read(i2c_t *obj, char *data, int length)
<> 149:156823d33999 269 {
<> 149:156823d33999 270 return i2c_do_tran(obj, data, length, 1, 1);
<> 149:156823d33999 271 }
<> 149:156823d33999 272
<> 149:156823d33999 273 int i2c_slave_write(i2c_t *obj, const char *data, int length)
<> 149:156823d33999 274 {
<> 149:156823d33999 275 return i2c_do_tran(obj, (char *) data, length, 0, 1);
<> 149:156823d33999 276 }
<> 149:156823d33999 277
<> 149:156823d33999 278 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
<> 149:156823d33999 279 {
<> 149:156823d33999 280 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
<> 149:156823d33999 281
<> 149:156823d33999 282 i2c_disable_int(obj);
<> 149:156823d33999 283
<> 149:156823d33999 284 I2C_SetSlaveAddr(i2c_base, 0, i2c_addr2bspaddr(address), I2C_GCMODE_ENABLE);
<> 149:156823d33999 285
<> 149:156823d33999 286 i2c_enable_int(obj);
<> 149:156823d33999 287 }
<> 149:156823d33999 288
<> 149:156823d33999 289 static int i2c_addr2bspaddr(int address)
<> 149:156823d33999 290 {
<> 149:156823d33999 291 return (address >> 1);
<> 149:156823d33999 292 }
<> 149:156823d33999 293
<> 149:156823d33999 294 #endif // #if DEVICE_I2CSLAVE
<> 149:156823d33999 295
<> 149:156823d33999 296 static void i2c_enable_int(i2c_t *obj)
<> 149:156823d33999 297 {
<> 149:156823d33999 298 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
<> 149:156823d33999 299
<> 149:156823d33999 300 core_util_critical_section_enter();
<> 149:156823d33999 301
<> 149:156823d33999 302 // Enable I2C interrupt
<> 149:156823d33999 303 NVIC_EnableIRQ(modinit->irq_n);
<> 149:156823d33999 304 obj->i2c.inten = 1;
<> 149:156823d33999 305
<> 149:156823d33999 306 core_util_critical_section_exit();
<> 149:156823d33999 307 }
<> 149:156823d33999 308
<> 149:156823d33999 309 static void i2c_disable_int(i2c_t *obj)
<> 149:156823d33999 310 {
<> 149:156823d33999 311 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
<> 149:156823d33999 312
<> 149:156823d33999 313 core_util_critical_section_enter();
<> 149:156823d33999 314
<> 149:156823d33999 315 // Disable I2C interrupt
<> 149:156823d33999 316 NVIC_DisableIRQ(modinit->irq_n);
<> 149:156823d33999 317 obj->i2c.inten = 0;
<> 149:156823d33999 318
<> 149:156823d33999 319 core_util_critical_section_exit();
<> 149:156823d33999 320 }
<> 149:156823d33999 321
<> 149:156823d33999 322 static int i2c_set_int(i2c_t *obj, int inten)
<> 149:156823d33999 323 {
<> 149:156823d33999 324 int inten_back;
<> 149:156823d33999 325
<> 149:156823d33999 326 core_util_critical_section_enter();
<> 149:156823d33999 327
<> 149:156823d33999 328 inten_back = obj->i2c.inten;
<> 149:156823d33999 329
<> 149:156823d33999 330 core_util_critical_section_exit();
<> 149:156823d33999 331
<> 149:156823d33999 332 if (inten) {
<> 149:156823d33999 333 i2c_enable_int(obj);
<> 149:156823d33999 334 }
<> 149:156823d33999 335 else {
<> 149:156823d33999 336 i2c_disable_int(obj);
<> 149:156823d33999 337 }
<> 149:156823d33999 338
<> 149:156823d33999 339 return inten_back;
<> 149:156823d33999 340 }
<> 149:156823d33999 341
<> 149:156823d33999 342 int i2c_allow_powerdown(void)
<> 149:156823d33999 343 {
<> 149:156823d33999 344 uint32_t modinit_mask = i2c_modinit_mask;
<> 149:156823d33999 345 while (modinit_mask) {
<> 149:156823d33999 346 int i2c_idx = nu_ctz(modinit_mask);
<> 149:156823d33999 347 const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx;
<> 149:156823d33999 348 struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
<> 149:156823d33999 349 if (var->obj) {
<> 149:156823d33999 350 // Disallow entering power-down mode if I2C transfer is enabled.
<> 149:156823d33999 351 if (i2c_active(var->obj)) {
<> 149:156823d33999 352 return 0;
<> 149:156823d33999 353 }
<> 149:156823d33999 354 }
<> 149:156823d33999 355 modinit_mask &= ~(1 << i2c_idx);
<> 149:156823d33999 356 }
<> 149:156823d33999 357
<> 149:156823d33999 358 return 1;
<> 149:156823d33999 359 }
<> 149:156823d33999 360
<> 149:156823d33999 361 static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
<> 149:156823d33999 362 {
<> 153:fa9ff456f731 363 if (! buf || ! length) {
<> 153:fa9ff456f731 364 return 0;
<> 153:fa9ff456f731 365 }
<> 153:fa9ff456f731 366
<> 149:156823d33999 367 int tran_len = 0;
<> 149:156823d33999 368
<> 149:156823d33999 369 i2c_disable_int(obj);
<> 149:156823d33999 370 obj->i2c.tran_ctrl = naklastdata ? (TRANCTRL_STARTED | TRANCTRL_NAKLASTDATA) : TRANCTRL_STARTED;
<> 149:156823d33999 371 obj->i2c.tran_beg = buf;
<> 149:156823d33999 372 obj->i2c.tran_pos = buf;
<> 149:156823d33999 373 obj->i2c.tran_end = buf + length;
<> 149:156823d33999 374 i2c_enable_int(obj);
<> 149:156823d33999 375
<> 149:156823d33999 376 if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) {
<> 149:156823d33999 377 #if NU_I2C_DEBUG
<> 149:156823d33999 378 MY_I2C_2 = obj->i2c;
<> 149:156823d33999 379 while (1);
<> 149:156823d33999 380 #endif
<> 149:156823d33999 381 }
<> 149:156823d33999 382 else {
<> 149:156823d33999 383 i2c_disable_int(obj);
<> 149:156823d33999 384 tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg;
<> 149:156823d33999 385 obj->i2c.tran_beg = NULL;
<> 149:156823d33999 386 obj->i2c.tran_pos = NULL;
<> 149:156823d33999 387 obj->i2c.tran_end = NULL;
<> 149:156823d33999 388 i2c_enable_int(obj);
<> 149:156823d33999 389 }
<> 149:156823d33999 390
<> 149:156823d33999 391 return tran_len;
<> 149:156823d33999 392 }
<> 149:156823d33999 393
<> 149:156823d33999 394 static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
<> 149:156823d33999 395 {
<> 149:156823d33999 396 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
<> 149:156823d33999 397 int err = 0;
<> 149:156823d33999 398
<> 149:156823d33999 399 i2c_disable_int(obj);
<> 149:156823d33999 400
<> 149:156823d33999 401 if (i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
<> 149:156823d33999 402 err = I2C_ERROR_BUS_BUSY;
<> 149:156823d33999 403 #if NU_I2C_DEBUG
<> 149:156823d33999 404 MY_I2C_2 = obj->i2c;
<> 149:156823d33999 405 while (1);
<> 149:156823d33999 406 #endif
<> 149:156823d33999 407 }
<> 149:156823d33999 408 else {
<> 149:156823d33999 409 #if 1
<> 149:156823d33999 410 // NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error.
<> 149:156823d33999 411 uint32_t status = I2C_GET_STATUS(i2c_base);
<> 149:156823d33999 412
<> 149:156823d33999 413 switch (status) {
<> 149:156823d33999 414 case 0x08: // Start
<> 149:156823d33999 415 case 0x10: // Master Repeat Start
<> 149:156823d33999 416 if (i2c_ctl & I2C_CTL_STA_Msk) {
<> 149:156823d33999 417 return 0;
<> 149:156823d33999 418 }
<> 149:156823d33999 419 else {
<> 149:156823d33999 420 break;
<> 149:156823d33999 421 }
<> 149:156823d33999 422 case 0xF8: // Bus Released
<> 149:156823d33999 423 if (i2c_ctl & (I2C_CTL_STA_Msk | I2C_CTL_STO_Msk) == I2C_CTL_STO_Msk) {
<> 149:156823d33999 424 return 0;
<> 149:156823d33999 425 }
<> 149:156823d33999 426 else {
<> 149:156823d33999 427 break;
<> 149:156823d33999 428 }
<> 149:156823d33999 429 }
<> 149:156823d33999 430 #endif
<> 149:156823d33999 431 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
<> 149:156823d33999 432 if (sync && i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
<> 149:156823d33999 433 err = I2C_ERROR_BUS_BUSY;
<> 149:156823d33999 434 #if NU_I2C_DEBUG
<> 149:156823d33999 435 MY_I2C_2 = obj->i2c;
<> 149:156823d33999 436 while (1);
<> 149:156823d33999 437 #endif
<> 149:156823d33999 438 }
<> 149:156823d33999 439 }
<> 149:156823d33999 440
<> 149:156823d33999 441 i2c_enable_int(obj);
<> 149:156823d33999 442
<> 149:156823d33999 443 return err;
<> 149:156823d33999 444 }
<> 149:156823d33999 445
<> 149:156823d33999 446 static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout)
<> 149:156823d33999 447 {
<> 149:156823d33999 448 uint32_t t1, t2, elapsed = 0;
<> 149:156823d33999 449 int status_assert = 0;
<> 149:156823d33999 450
<> 149:156823d33999 451 t1 = us_ticker_read();
<> 149:156823d33999 452 while (1) {
<> 149:156823d33999 453 status_assert = is_status(obj);
<> 149:156823d33999 454 if (status_assert) {
<> 149:156823d33999 455 break;
<> 149:156823d33999 456 }
<> 149:156823d33999 457
<> 149:156823d33999 458 t2 = us_ticker_read();
<> 149:156823d33999 459 elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
<> 149:156823d33999 460 if (elapsed >= timeout) {
<> 149:156823d33999 461 #if NU_I2C_DEBUG
<> 149:156823d33999 462 MY_I2C_T1 = t1;
<> 149:156823d33999 463 MY_I2C_T2 = t2;
<> 149:156823d33999 464 MY_I2C_ELAPSED = elapsed;
<> 149:156823d33999 465 MY_I2C_TIMEOUT = timeout;
<> 149:156823d33999 466 MY_I2C_2 = obj->i2c;
<> 149:156823d33999 467 while (1);
<> 149:156823d33999 468 #endif
<> 149:156823d33999 469 break;
<> 149:156823d33999 470 }
<> 149:156823d33999 471 }
<> 149:156823d33999 472
<> 149:156823d33999 473 return (elapsed >= timeout);
<> 149:156823d33999 474 }
<> 149:156823d33999 475
<> 149:156823d33999 476 static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
<> 149:156823d33999 477 {
<> 149:156823d33999 478 uint32_t t1, t2, elapsed = 0;
<> 149:156823d33999 479 int tran_started;
<> 149:156823d33999 480 char *tran_pos = NULL;
<> 149:156823d33999 481 char *tran_pos2 = NULL;
<> 149:156823d33999 482
<> 149:156823d33999 483 i2c_disable_int(obj);
<> 149:156823d33999 484 tran_pos = obj->i2c.tran_pos;
<> 149:156823d33999 485 i2c_enable_int(obj);
<> 149:156823d33999 486 t1 = us_ticker_read();
<> 149:156823d33999 487 while (1) {
<> 149:156823d33999 488 i2c_disable_int(obj);
<> 149:156823d33999 489 tran_started = i2c_is_tran_started(obj);
<> 149:156823d33999 490 i2c_enable_int(obj);
<> 149:156823d33999 491 if (! tran_started) { // Transfer completed or stopped
<> 149:156823d33999 492 break;
<> 149:156823d33999 493 }
<> 149:156823d33999 494
<> 149:156823d33999 495 i2c_disable_int(obj);
<> 149:156823d33999 496 tran_pos2 = obj->i2c.tran_pos;
<> 149:156823d33999 497 i2c_enable_int(obj);
<> 149:156823d33999 498 t2 = us_ticker_read();
<> 149:156823d33999 499 if (tran_pos2 != tran_pos) { // Transfer on-going
<> 149:156823d33999 500 t1 = t2;
<> 149:156823d33999 501 tran_pos = tran_pos2;
<> 149:156823d33999 502 continue;
<> 149:156823d33999 503 }
<> 149:156823d33999 504
<> 149:156823d33999 505 elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
<> 149:156823d33999 506 if (elapsed >= timeout) { // Transfer idle
<> 149:156823d33999 507 #if NU_I2C_DEBUG
<> 149:156823d33999 508 MY_I2C = obj->i2c;
<> 149:156823d33999 509 MY_I2C_T1 = t1;
<> 149:156823d33999 510 MY_I2C_T2 = t2;
<> 149:156823d33999 511 MY_I2C_ELAPSED = elapsed;
<> 149:156823d33999 512 MY_I2C_TIMEOUT = timeout;
<> 149:156823d33999 513 MY_I2C_2 = obj->i2c;
<> 149:156823d33999 514 while (1);
<> 149:156823d33999 515 #endif
<> 149:156823d33999 516 break;
<> 149:156823d33999 517 }
<> 149:156823d33999 518 }
<> 149:156823d33999 519
<> 149:156823d33999 520 return (elapsed >= timeout);
<> 149:156823d33999 521 }
<> 149:156823d33999 522
<> 149:156823d33999 523 #if 0
<> 149:156823d33999 524 static int i2c_is_stat_int(i2c_t *obj)
<> 149:156823d33999 525 {
<> 149:156823d33999 526 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
<> 149:156823d33999 527
<> 149:156823d33999 528 return !! (i2c_base->CTL & I2C_CTL_SI_Msk);
<> 149:156823d33999 529 }
<> 149:156823d33999 530
<> 149:156823d33999 531 static int i2c_is_stop_det(i2c_t *obj)
<> 149:156823d33999 532 {
<> 149:156823d33999 533 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
<> 149:156823d33999 534
<> 149:156823d33999 535 return ! (i2c_base->CTL & I2C_CTL_STO_Msk);
<> 149:156823d33999 536 }
<> 149:156823d33999 537 #endif
<> 149:156823d33999 538
<> 149:156823d33999 539 static int i2c_is_trsn_done(i2c_t *obj)
<> 149:156823d33999 540 {
<> 149:156823d33999 541 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
<> 149:156823d33999 542 int i2c_int;
<> 149:156823d33999 543 uint32_t status;
<> 149:156823d33999 544 int inten_back;
<> 149:156823d33999 545
<> 149:156823d33999 546 inten_back = i2c_set_int(obj, 0);
<> 149:156823d33999 547 i2c_int = !! (i2c_base->CTL & I2C_CTL_SI_Msk);
<> 149:156823d33999 548 status = I2C_GET_STATUS(i2c_base);
<> 149:156823d33999 549 i2c_set_int(obj, inten_back);
<> 149:156823d33999 550
<> 149:156823d33999 551 return (i2c_int || status == 0xF8);
<> 149:156823d33999 552 }
<> 149:156823d33999 553
<> 149:156823d33999 554 static int i2c_is_tran_started(i2c_t *obj)
<> 149:156823d33999 555 {
<> 149:156823d33999 556 int started;
<> 149:156823d33999 557 int inten_back;
<> 149:156823d33999 558
<> 149:156823d33999 559 inten_back = i2c_set_int(obj, 0);
<> 149:156823d33999 560 started = !! (obj->i2c.tran_ctrl & TRANCTRL_STARTED);
<> 149:156823d33999 561 i2c_set_int(obj, inten_back);
<> 149:156823d33999 562
<> 149:156823d33999 563 return started;
<> 149:156823d33999 564 }
<> 149:156823d33999 565
<> 149:156823d33999 566 static int i2c_addr2data(int address, int read)
<> 149:156823d33999 567 {
<> 149:156823d33999 568 return read ? (address | 1) : (address & 0xFE);
<> 149:156823d33999 569 }
<> 149:156823d33999 570
<> 149:156823d33999 571 static void i2c0_vec(void)
<> 149:156823d33999 572 {
<> 149:156823d33999 573 i2c_irq(i2c0_var.obj);
<> 149:156823d33999 574 }
<> 149:156823d33999 575 static void i2c1_vec(void)
<> 149:156823d33999 576 {
<> 149:156823d33999 577 i2c_irq(i2c1_var.obj);
<> 149:156823d33999 578 }
<> 149:156823d33999 579
<> 149:156823d33999 580 static void i2c_irq(i2c_t *obj)
<> 149:156823d33999 581 {
<> 149:156823d33999 582 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
<> 149:156823d33999 583 uint32_t status;
<> 149:156823d33999 584
<> 149:156823d33999 585 if (I2C_GET_TIMEOUT_FLAG(i2c_base)) {
<> 149:156823d33999 586 I2C_ClearTimeoutFlag(i2c_base);
<> 149:156823d33999 587 return;
<> 149:156823d33999 588 }
<> 149:156823d33999 589
<> 149:156823d33999 590 status = I2C_GET_STATUS(i2c_base);
<> 149:156823d33999 591 #if NU_I2C_DEBUG
<> 149:156823d33999 592 if (MY_I2C_STATUS_POS < (sizeof (MY_I2C_STATUS) / sizeof (MY_I2C_STATUS[0]))) {
<> 149:156823d33999 593 MY_I2C_STATUS[MY_I2C_STATUS_POS ++] = status;
<> 149:156823d33999 594 }
<> 149:156823d33999 595 else {
<> 149:156823d33999 596 memset(MY_I2C_STATUS, 0x00, sizeof (MY_I2C_STATUS));
<> 149:156823d33999 597 MY_I2C_STATUS_POS = 0;
<> 149:156823d33999 598 }
<> 149:156823d33999 599 #endif
<> 149:156823d33999 600
<> 149:156823d33999 601 switch (status) {
<> 149:156823d33999 602 // Master Transmit
<> 149:156823d33999 603 case 0x28: // Master Transmit Data ACK
<> 149:156823d33999 604 case 0x18: // Master Transmit Address ACK
<> 149:156823d33999 605 case 0x08: // Start
<> 149:156823d33999 606 case 0x10: // Master Repeat Start
<> 149:156823d33999 607 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
<> 149:156823d33999 608 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
<> 149:156823d33999 609 I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
<> 149:156823d33999 610 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
<> 149:156823d33999 611 }
<> 149:156823d33999 612 else {
<> 153:fa9ff456f731 613 i2c_fsm_tranfini(obj, 0);
<> 149:156823d33999 614 }
<> 149:156823d33999 615 }
<> 149:156823d33999 616 else {
<> 149:156823d33999 617 i2c_disable_int(obj);
<> 149:156823d33999 618 }
<> 149:156823d33999 619 break;
<> 153:fa9ff456f731 620
<> 149:156823d33999 621 case 0x30: // Master Transmit Data NACK
<> 153:fa9ff456f731 622 i2c_fsm_tranfini(obj, 1);
<> 153:fa9ff456f731 623 break;
<> 153:fa9ff456f731 624
<> 149:156823d33999 625 case 0x20: // Master Transmit Address NACK
<> 153:fa9ff456f731 626 i2c_fsm_tranfini(obj, 1);
<> 149:156823d33999 627 break;
<> 153:fa9ff456f731 628
<> 149:156823d33999 629 case 0x38: // Master Arbitration Lost
<> 149:156823d33999 630 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
<> 149:156823d33999 631 break;
<> 149:156823d33999 632
<> 149:156823d33999 633 case 0x48: // Master Receive Address NACK
<> 153:fa9ff456f731 634 i2c_fsm_tranfini(obj, 1);
<> 149:156823d33999 635 break;
<> 153:fa9ff456f731 636
<> 149:156823d33999 637 case 0x40: // Master Receive Address ACK
<> 149:156823d33999 638 case 0x50: // Master Receive Data ACK
<> 149:156823d33999 639 case 0x58: // Master Receive Data NACK
<> 149:156823d33999 640 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
<> 149:156823d33999 641 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
<> 149:156823d33999 642 if (status == 0x50 || status == 0x58) {
<> 149:156823d33999 643 *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
<> 149:156823d33999 644 }
<> 149:156823d33999 645
<> 149:156823d33999 646 if (status == 0x58) {
<> 149:156823d33999 647 #if NU_I2C_DEBUG
<> 149:156823d33999 648 if (obj->i2c.tran_pos != obj->i2c.tran_end) {
<> 149:156823d33999 649 MY_I2C = obj->i2c;
<> 149:156823d33999 650 while (1);
<> 149:156823d33999 651 }
<> 149:156823d33999 652 #endif
<> 153:fa9ff456f731 653 i2c_fsm_tranfini(obj, 1);
<> 149:156823d33999 654 }
<> 149:156823d33999 655 else {
<> 149:156823d33999 656 uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
<> 149:156823d33999 657 if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
<> 149:156823d33999 658 obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
<> 149:156823d33999 659 // Last data
<> 149:156823d33999 660 i2c_ctl &= ~I2C_CTL_AA_Msk;
<> 149:156823d33999 661 }
<> 149:156823d33999 662 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
<> 149:156823d33999 663 }
<> 149:156823d33999 664 }
<> 149:156823d33999 665 else {
<> 149:156823d33999 666 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
<> 149:156823d33999 667 i2c_disable_int(obj);
<> 149:156823d33999 668 break;
<> 149:156823d33999 669 }
<> 149:156823d33999 670 }
<> 149:156823d33999 671 else {
<> 149:156823d33999 672 i2c_disable_int(obj);
<> 149:156823d33999 673 }
<> 149:156823d33999 674 break;
<> 149:156823d33999 675
<> 149:156823d33999 676 //case 0x00: // Bus error
<> 149:156823d33999 677
<> 149:156823d33999 678 // Slave Transmit
<> 149:156823d33999 679 case 0xB8: // Slave Transmit Data ACK
<> 149:156823d33999 680 case 0xA8: // Slave Transmit Address ACK
<> 149:156823d33999 681 case 0xB0: // Slave Transmit Arbitration Lost
<> 149:156823d33999 682 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
<> 149:156823d33999 683 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
<> 149:156823d33999 684 uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
<> 149:156823d33999 685
<> 149:156823d33999 686 I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
<> 149:156823d33999 687 if (obj->i2c.tran_pos == obj->i2c.tran_end &&
<> 149:156823d33999 688 obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
<> 149:156823d33999 689 // Last data
<> 149:156823d33999 690 i2c_ctl &= ~I2C_CTL_AA_Msk;
<> 149:156823d33999 691 }
<> 149:156823d33999 692 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
<> 149:156823d33999 693 }
<> 149:156823d33999 694 else {
<> 149:156823d33999 695 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
<> 149:156823d33999 696 i2c_disable_int(obj);
<> 149:156823d33999 697 break;
<> 149:156823d33999 698 }
<> 149:156823d33999 699 }
<> 149:156823d33999 700 else {
<> 149:156823d33999 701 i2c_disable_int(obj);
<> 149:156823d33999 702 }
<> 149:156823d33999 703 obj->i2c.slaveaddr_state = ReadAddressed;
<> 149:156823d33999 704 break;
<> 149:156823d33999 705 //case 0xA0: // Slave Transmit Repeat Start or Stop
<> 149:156823d33999 706 case 0xC0: // Slave Transmit Data NACK
<> 149:156823d33999 707 case 0xC8: // Slave Transmit Last Data ACK
<> 149:156823d33999 708 obj->i2c.slaveaddr_state = NoData;
<> 149:156823d33999 709 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
<> 149:156823d33999 710 break;
<> 149:156823d33999 711
<> 149:156823d33999 712 // Slave Receive
<> 149:156823d33999 713 case 0x80: // Slave Receive Data ACK
<> 149:156823d33999 714 case 0x88: // Slave Receive Data NACK
<> 149:156823d33999 715 case 0x60: // Slave Receive Address ACK
<> 149:156823d33999 716 case 0x68: // Slave Receive Arbitration Lost
<> 149:156823d33999 717 obj->i2c.slaveaddr_state = WriteAddressed;
<> 149:156823d33999 718 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
<> 149:156823d33999 719 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
<> 149:156823d33999 720 if (status == 0x80 || status == 0x88) {
<> 149:156823d33999 721 *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
<> 149:156823d33999 722 }
<> 149:156823d33999 723
<> 149:156823d33999 724 if (status == 0x88) {
<> 149:156823d33999 725 #if NU_I2C_DEBUG
<> 149:156823d33999 726 if (obj->i2c.tran_pos != obj->i2c.tran_end) {
<> 149:156823d33999 727 MY_I2C = obj->i2c;
<> 149:156823d33999 728 while (1);
<> 149:156823d33999 729 }
<> 149:156823d33999 730 #endif
<> 149:156823d33999 731 obj->i2c.slaveaddr_state = NoData;
<> 149:156823d33999 732 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
<> 149:156823d33999 733 }
<> 149:156823d33999 734 else {
<> 149:156823d33999 735 uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
<> 149:156823d33999 736 if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
<> 149:156823d33999 737 obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
<> 149:156823d33999 738 // Last data
<> 149:156823d33999 739 i2c_ctl &= ~I2C_CTL_AA_Msk;
<> 149:156823d33999 740 }
<> 149:156823d33999 741 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
<> 149:156823d33999 742 }
<> 149:156823d33999 743 }
<> 149:156823d33999 744 else {
<> 149:156823d33999 745 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
<> 149:156823d33999 746 i2c_disable_int(obj);
<> 149:156823d33999 747 break;
<> 149:156823d33999 748 }
<> 149:156823d33999 749 }
<> 149:156823d33999 750 else {
<> 149:156823d33999 751 i2c_disable_int(obj);
<> 149:156823d33999 752 }
<> 149:156823d33999 753 break;
<> 149:156823d33999 754 //case 0xA0: // Slave Receive Repeat Start or Stop
<> 149:156823d33999 755
<> 149:156823d33999 756 // GC mode
<> 149:156823d33999 757 //case 0xA0: // GC mode Repeat Start or Stop
<> 149:156823d33999 758 case 0x90: // GC mode Data ACK
<> 149:156823d33999 759 case 0x98: // GC mode Data NACK
<> 149:156823d33999 760 case 0x70: // GC mode Address ACK
<> 149:156823d33999 761 case 0x78: // GC mode Arbitration Lost
<> 149:156823d33999 762 obj->i2c.slaveaddr_state = WriteAddressed;
<> 149:156823d33999 763 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
<> 149:156823d33999 764 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
<> 149:156823d33999 765 if (status == 0x90 || status == 0x98) {
<> 149:156823d33999 766 *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
<> 149:156823d33999 767 }
<> 149:156823d33999 768
<> 149:156823d33999 769 if (status == 0x98) {
<> 149:156823d33999 770 #if NU_I2C_DEBUG
<> 149:156823d33999 771 if (obj->i2c.tran_pos != obj->i2c.tran_end) {
<> 149:156823d33999 772 MY_I2C = obj->i2c;
<> 149:156823d33999 773 while (1);
<> 149:156823d33999 774 }
<> 149:156823d33999 775 #endif
<> 149:156823d33999 776 obj->i2c.slaveaddr_state = NoData;
<> 149:156823d33999 777 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
<> 149:156823d33999 778 }
<> 149:156823d33999 779 else {
<> 149:156823d33999 780 uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
<> 149:156823d33999 781 if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
<> 149:156823d33999 782 obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
<> 149:156823d33999 783 // Last data
<> 149:156823d33999 784 i2c_ctl &= ~I2C_CTL_AA_Msk;
<> 149:156823d33999 785 }
<> 149:156823d33999 786 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
<> 149:156823d33999 787 }
<> 149:156823d33999 788 }
<> 149:156823d33999 789 else {
<> 149:156823d33999 790 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
<> 149:156823d33999 791 i2c_disable_int(obj);
<> 149:156823d33999 792 break;
<> 149:156823d33999 793 }
<> 149:156823d33999 794 }
<> 149:156823d33999 795 else {
<> 149:156823d33999 796 i2c_disable_int(obj);
<> 149:156823d33999 797 }
<> 149:156823d33999 798 break;
<> 149:156823d33999 799
<> 149:156823d33999 800 case 0xF8: // Bus Released
<> 149:156823d33999 801 break;
<> 149:156823d33999 802
<> 149:156823d33999 803 default:
<> 149:156823d33999 804 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
<> 149:156823d33999 805 }
<> 149:156823d33999 806 }
<> 149:156823d33999 807
<> 149:156823d33999 808 static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl)
<> 149:156823d33999 809 {
<> 149:156823d33999 810 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
<> 149:156823d33999 811
<> 149:156823d33999 812 obj->i2c.stop = 0;
<> 149:156823d33999 813
<> 149:156823d33999 814 obj->i2c.tran_ctrl = 0;
<> 149:156823d33999 815
<> 149:156823d33999 816 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
<> 149:156823d33999 817 obj->i2c.slaveaddr_state = NoData;
<> 149:156823d33999 818 }
<> 149:156823d33999 819
<> 153:fa9ff456f731 820 static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked)
<> 153:fa9ff456f731 821 {
<> 153:fa9ff456f731 822 if (lastdatanaked) {
<> 153:fa9ff456f731 823 obj->i2c.tran_ctrl |= TRANCTRL_LASTDATANAKED;
<> 153:fa9ff456f731 824 }
<> 153:fa9ff456f731 825
<> 153:fa9ff456f731 826 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
<> 153:fa9ff456f731 827 i2c_disable_int(obj);
<> 153:fa9ff456f731 828 }
<> 153:fa9ff456f731 829
<> 149:156823d33999 830 #if DEVICE_I2C_ASYNCH
<> 149:156823d33999 831
<> 149:156823d33999 832 void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
<> 149:156823d33999 833 {
<> 149:156823d33999 834 // NOTE: M451 I2C only supports 7-bit slave address. The mbed I2C address passed in is shifted left by 1 bit (7-bit addr << 1).
<> 149:156823d33999 835 MBED_ASSERT((address & 0xFFFFFF00) == 0);
<> 149:156823d33999 836
<> 149:156823d33999 837 // NOTE: First transmit and then receive.
<> 149:156823d33999 838
<> 149:156823d33999 839 (void) hint;
<> 149:156823d33999 840 obj->i2c.dma_usage = DMA_USAGE_NEVER;
<> 149:156823d33999 841 obj->i2c.stop = stop;
<> 149:156823d33999 842 obj->i2c.address = address;
<> 149:156823d33999 843 obj->i2c.event = event;
<> 149:156823d33999 844 i2c_buffer_set(obj, tx, tx_length, rx, rx_length);
<> 149:156823d33999 845
<> 149:156823d33999 846 //I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
<> 149:156823d33999 847
<> 149:156823d33999 848 i2c_enable_vector_interrupt(obj, handler, 1);
<> 149:156823d33999 849 i2c_start(obj);
<> 149:156823d33999 850 }
<> 149:156823d33999 851
<> 149:156823d33999 852 uint32_t i2c_irq_handler_asynch(i2c_t *obj)
<> 149:156823d33999 853 {
<> 149:156823d33999 854 int event = 0;
<> 149:156823d33999 855
<> 149:156823d33999 856 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
<> 149:156823d33999 857 uint32_t status = I2C_GET_STATUS(i2c_base);
<> 149:156823d33999 858 switch (status) {
<> 149:156823d33999 859 case 0x08: // Start
<> 149:156823d33999 860 case 0x10: {// Master Repeat Start
<> 149:156823d33999 861 if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
<> 149:156823d33999 862 I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0)));
<> 149:156823d33999 863 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
<> 149:156823d33999 864 }
<> 149:156823d33999 865 else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
<> 149:156823d33999 866 I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1)));
<> 149:156823d33999 867 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
<> 149:156823d33999 868 }
<> 149:156823d33999 869 else {
<> 149:156823d33999 870 event = I2C_EVENT_TRANSFER_COMPLETE;
<> 149:156823d33999 871 if (obj->i2c.stop) {
<> 149:156823d33999 872 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
<> 149:156823d33999 873 }
<> 149:156823d33999 874 }
<> 149:156823d33999 875 break;
<> 149:156823d33999 876 }
<> 149:156823d33999 877
<> 149:156823d33999 878 case 0x18: // Master Transmit Address ACK
<> 149:156823d33999 879 case 0x28: // Master Transmit Data ACK
<> 149:156823d33999 880 if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
<> 149:156823d33999 881 uint8_t *tx = (uint8_t *)obj->tx_buff.buffer;
<> 149:156823d33999 882 I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]);
<> 149:156823d33999 883 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
<> 149:156823d33999 884 }
<> 149:156823d33999 885 else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
<> 149:156823d33999 886 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
<> 149:156823d33999 887 }
<> 149:156823d33999 888 else {
<> 149:156823d33999 889 event = I2C_EVENT_TRANSFER_COMPLETE;
<> 149:156823d33999 890 if (obj->i2c.stop) {
<> 149:156823d33999 891 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
<> 149:156823d33999 892 }
<> 149:156823d33999 893 }
<> 149:156823d33999 894 break;
<> 149:156823d33999 895
<> 149:156823d33999 896 case 0x20: // Master Transmit Address NACK
<> 149:156823d33999 897 event = I2C_EVENT_ERROR_NO_SLAVE;
<> 149:156823d33999 898 if (obj->i2c.stop) {
<> 149:156823d33999 899 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
<> 149:156823d33999 900 }
<> 149:156823d33999 901 break;
<> 149:156823d33999 902
<> 149:156823d33999 903 case 0x30: // Master Transmit Data NACK
<> 149:156823d33999 904 if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
<> 149:156823d33999 905 event = I2C_EVENT_TRANSFER_EARLY_NACK;
<> 149:156823d33999 906 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
<> 149:156823d33999 907 }
<> 149:156823d33999 908 else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
<> 149:156823d33999 909 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
<> 149:156823d33999 910 }
<> 149:156823d33999 911 else {
<> 149:156823d33999 912 event = I2C_EVENT_TRANSFER_COMPLETE;
<> 149:156823d33999 913 if (obj->i2c.stop) {
<> 149:156823d33999 914 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
<> 149:156823d33999 915 }
<> 149:156823d33999 916 }
<> 149:156823d33999 917 break;
<> 149:156823d33999 918
<> 149:156823d33999 919 case 0x38: // Master Arbitration Lost
<> 149:156823d33999 920 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk); // Enter not addressed SLV mode
<> 149:156823d33999 921 event = I2C_EVENT_ERROR;
<> 149:156823d33999 922 break;
<> 149:156823d33999 923
<> 149:156823d33999 924 case 0x50: // Master Receive Data ACK
<> 149:156823d33999 925 if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
<> 149:156823d33999 926 uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
<> 149:156823d33999 927 rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
<> 149:156823d33999 928 }
<> 149:156823d33999 929 case 0x40: // Master Receive Address ACK
<> 149:156823d33999 930 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | ((obj->rx_buff.pos != obj->rx_buff.length - 1) ? I2C_CTL_AA_Msk : 0));
<> 149:156823d33999 931 break;
<> 149:156823d33999 932
<> 149:156823d33999 933 case 0x48: // Master Receive Address NACK
<> 149:156823d33999 934 event = I2C_EVENT_ERROR_NO_SLAVE;
<> 149:156823d33999 935 if (obj->i2c.stop) {
<> 149:156823d33999 936 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
<> 149:156823d33999 937 }
<> 149:156823d33999 938 break;
<> 149:156823d33999 939
<> 149:156823d33999 940 case 0x58: // Master Receive Data NACK
<> 149:156823d33999 941 if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
<> 149:156823d33999 942 uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
<> 149:156823d33999 943 rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
<> 149:156823d33999 944 }
<> 149:156823d33999 945 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
<> 149:156823d33999 946 break;
<> 149:156823d33999 947
<> 149:156823d33999 948 case 0x00: // Bus error
<> 149:156823d33999 949 event = I2C_EVENT_ERROR;
<> 149:156823d33999 950 i2c_reset(obj);
<> 149:156823d33999 951 break;
<> 149:156823d33999 952
<> 149:156823d33999 953 default:
<> 149:156823d33999 954 event = I2C_EVENT_ERROR;
<> 149:156823d33999 955 if (obj->i2c.stop) {
<> 149:156823d33999 956 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
<> 149:156823d33999 957 }
<> 149:156823d33999 958 }
<> 149:156823d33999 959
<> 149:156823d33999 960 if (event) {
<> 149:156823d33999 961 i2c_rollback_vector_interrupt(obj);
<> 149:156823d33999 962 }
<> 149:156823d33999 963
<> 149:156823d33999 964 return (event & obj->i2c.event);
<> 149:156823d33999 965 }
<> 149:156823d33999 966
<> 149:156823d33999 967 uint8_t i2c_active(i2c_t *obj)
<> 149:156823d33999 968 {
<> 149:156823d33999 969 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
<> 149:156823d33999 970 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 971 MBED_ASSERT(modinit->modname == obj->i2c.i2c);
<> 149:156823d33999 972
<> 149:156823d33999 973 // Vector will be changed for async transfer. Use it to judge if async transfer is on-going.
<> 149:156823d33999 974 uint32_t vec = NVIC_GetVector(modinit->irq_n);
<> 149:156823d33999 975 struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
<> 149:156823d33999 976 return (vec && vec != (uint32_t) var->vec);
<> 149:156823d33999 977 }
<> 149:156823d33999 978
<> 149:156823d33999 979 void i2c_abort_asynch(i2c_t *obj)
<> 149:156823d33999 980 {
<> 149:156823d33999 981 i2c_rollback_vector_interrupt(obj);
<> 149:156823d33999 982 i2c_stop(obj);
<> 149:156823d33999 983 }
<> 149:156823d33999 984
<> 149:156823d33999 985 static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
<> 149:156823d33999 986 {
<> 149:156823d33999 987 obj->tx_buff.buffer = (void *) tx;
<> 149:156823d33999 988 obj->tx_buff.length = tx_length;
<> 149:156823d33999 989 obj->tx_buff.pos = 0;
<> 149:156823d33999 990 obj->rx_buff.buffer = rx;
<> 149:156823d33999 991 obj->rx_buff.length = rx_length;
<> 149:156823d33999 992 obj->rx_buff.pos = 0;
<> 149:156823d33999 993 }
<> 149:156823d33999 994
<> 149:156823d33999 995 static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable)
<> 149:156823d33999 996 {
<> 149:156823d33999 997 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
<> 149:156823d33999 998 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 999 MBED_ASSERT(modinit->modname == obj->i2c.i2c);
<> 149:156823d33999 1000
<> 149:156823d33999 1001 if (enable) {
<> 149:156823d33999 1002 NVIC_SetVector(modinit->irq_n, handler);
<> 149:156823d33999 1003 i2c_enable_int(obj);
<> 149:156823d33999 1004 }
<> 149:156823d33999 1005 else {
<> 149:156823d33999 1006 i2c_disable_int(obj);
<> 149:156823d33999 1007 }
<> 149:156823d33999 1008
<> 149:156823d33999 1009 }
<> 149:156823d33999 1010
<> 149:156823d33999 1011 static void i2c_rollback_vector_interrupt(i2c_t *obj)
<> 149:156823d33999 1012 {
<> 149:156823d33999 1013 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
<> 149:156823d33999 1014 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 1015 MBED_ASSERT(modinit->modname == obj->i2c.i2c);
<> 149:156823d33999 1016
<> 149:156823d33999 1017 struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
<> 149:156823d33999 1018 i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
<> 149:156823d33999 1019 }
<> 149:156823d33999 1020
<> 149:156823d33999 1021 #endif
<> 149:156823d33999 1022
<> 149:156823d33999 1023 #endif