Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
149:156823d33999 
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_tim_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Timer Extended peripheral:
<> 144:ef7eb2e8f9f7 10 * + Time Hall Sensor Interface Initialization
<> 144:ef7eb2e8f9f7 11 * + Time Hall Sensor Interface Start
<> 144:ef7eb2e8f9f7 12 * + Time Complementary signal break and dead time configuration
<> 144:ef7eb2e8f9f7 13 * + Time Master and Slave synchronization configuration
<> 144:ef7eb2e8f9f7 14 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
<> 144:ef7eb2e8f9f7 15 * + Time OCRef clear configuration
<> 144:ef7eb2e8f9f7 16 * + Timer remapping capabilities configuration
<> 144:ef7eb2e8f9f7 17 @verbatim
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 ##### TIMER Extended features #####
<> 144:ef7eb2e8f9f7 20 ==============================================================================
<> 144:ef7eb2e8f9f7 21 [..]
<> 144:ef7eb2e8f9f7 22 The Timer Extended features include:
<> 144:ef7eb2e8f9f7 23 (#) Complementary outputs with programmable dead-time for :
<> 144:ef7eb2e8f9f7 24 (++) Output Compare
<> 144:ef7eb2e8f9f7 25 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 26 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 27 (#) Synchronization circuit to control the timer with external signals and to
<> 144:ef7eb2e8f9f7 28 interconnect several timers together.
<> 144:ef7eb2e8f9f7 29 (#) Break input to put the timer output signals in reset state or in a known state.
<> 144:ef7eb2e8f9f7 30 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
<> 144:ef7eb2e8f9f7 31 positioning purposes
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 34 ==============================================================================
<> 144:ef7eb2e8f9f7 35 [..]
<> 144:ef7eb2e8f9f7 36 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 37 depending on the selected feature:
<> 144:ef7eb2e8f9f7 38 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 41 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 42 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 43 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 44 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 45 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 48 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 49 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 50 any start function.
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 53 initialization function of this driver:
<> 144:ef7eb2e8f9f7 54 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutationEvent(): to use the
<> 144:ef7eb2e8f9f7 55 Timer Hall Sensor Interface and the commutation event with the corresponding
<> 144:ef7eb2e8f9f7 56 Interrupt and DMA request if needed (Note that One Timer is used to interface
<> 144:ef7eb2e8f9f7 57 with the Hall sensor Interface and another Timer should be used to use
<> 144:ef7eb2e8f9f7 58 the commutation event).
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (#) Activate the TIM peripheral using one of the start functions:
<> 144:ef7eb2e8f9f7 61 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
<> 144:ef7eb2e8f9f7 62 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
<> 144:ef7eb2e8f9f7 63 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
<> 144:ef7eb2e8f9f7 64 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 @endverbatim
<> 144:ef7eb2e8f9f7 68 ******************************************************************************
<> 144:ef7eb2e8f9f7 69 * @attention
<> 144:ef7eb2e8f9f7 70 *
AnnaBridge 167:e84263d55307 71 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 74 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 75 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 76 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 78 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 79 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 81 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 82 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 83 *
<> 144:ef7eb2e8f9f7 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 ******************************************************************************
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @defgroup TIMEx TIMEx
<> 144:ef7eb2e8f9f7 106 * @brief TIM Extended HAL module driver
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 113 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 #define BDTR_BKF_SHIFT (16)
<> 144:ef7eb2e8f9f7 115 #define BDTR_BK2F_SHIFT (20)
<> 144:ef7eb2e8f9f7 116 #define TIMx_ETRSEL_MASK ((uint32_t)0x0001C000)
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 120 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 121 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 126 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
<> 144:ef7eb2e8f9f7 127 * @{
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 131 * @brief Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 132 *
<> 144:ef7eb2e8f9f7 133 @verbatim
<> 144:ef7eb2e8f9f7 134 ==============================================================================
<> 144:ef7eb2e8f9f7 135 ##### Timer Hall Sensor functions #####
<> 144:ef7eb2e8f9f7 136 ==============================================================================
<> 144:ef7eb2e8f9f7 137 [..]
<> 144:ef7eb2e8f9f7 138 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 139 (+) Initialize and configure TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 140 (+) De-initialize TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 141 (+) Start the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 142 (+) Stop the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 143 (+) Start the Hall Sensor Interface and enable interrupts.
<> 144:ef7eb2e8f9f7 144 (+) Stop the Hall Sensor Interface and disable interrupts.
<> 144:ef7eb2e8f9f7 145 (+) Start the Hall Sensor Interface and enable DMA transfers.
<> 144:ef7eb2e8f9f7 146 (+) Stop the Hall Sensor Interface and disable DMA transfers.
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 @endverbatim
<> 144:ef7eb2e8f9f7 149 * @{
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 /**
<> 144:ef7eb2e8f9f7 152 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
<> 144:ef7eb2e8f9f7 153 * @param htim: TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 154 * @param sConfig: TIM Hall Sensor configuration structure
<> 144:ef7eb2e8f9f7 155 * @retval HAL status
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 TIM_OC_InitTypeDef OC_Config;
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 162 if(htim == NULL)
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 168 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 169 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 170 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 171 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 172 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 177 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 180 HAL_TIMEx_HallSensor_MspInit(htim);
<> 144:ef7eb2e8f9f7 181 }
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 184 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 187 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
<> 144:ef7eb2e8f9f7 190 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 193 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 194 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 195 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Enable the Hall sensor interface (XOR function of the three inputs) */
<> 144:ef7eb2e8f9f7 198 htim->Instance->CR2 |= TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
<> 144:ef7eb2e8f9f7 201 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 202 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
<> 144:ef7eb2e8f9f7 205 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 206 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
<> 144:ef7eb2e8f9f7 209 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
<> 144:ef7eb2e8f9f7 210 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 211 OC_Config.OCMode = TIM_OCMODE_PWM2;
<> 144:ef7eb2e8f9f7 212 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 213 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 214 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 215 OC_Config.Pulse = sConfig->Commutation_Delay;
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
<> 144:ef7eb2e8f9f7 220 register to 101 */
<> 144:ef7eb2e8f9f7 221 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 222 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 225 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 return HAL_OK;
<> 144:ef7eb2e8f9f7 228 }
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @brief DeInitialize the TIM Hall Sensor interface
<> 144:ef7eb2e8f9f7 232 * @param htim: TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 233 * @retval HAL status
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 236 {
<> 144:ef7eb2e8f9f7 237 /* Check the parameters */
<> 144:ef7eb2e8f9f7 238 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 243 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 246 HAL_TIMEx_HallSensor_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Change TIM state */
<> 144:ef7eb2e8f9f7 249 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Release Lock */
<> 144:ef7eb2e8f9f7 252 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 return HAL_OK;
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @brief Initializes the TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 259 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 260 * @retval None
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 263 {
<> 144:ef7eb2e8f9f7 264 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 265 UNUSED(htim);
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 268 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /**
<> 144:ef7eb2e8f9f7 273 * @brief DeInitialize TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 274 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 275 * @retval None
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 280 UNUSED(htim);
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 283 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 }
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @brief Starts the TIM Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 289 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 290 * @retval HAL status
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 293 {
<> 144:ef7eb2e8f9f7 294 /* Check the parameters */
<> 144:ef7eb2e8f9f7 295 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 298 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 299 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 302 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* Return function status */
<> 144:ef7eb2e8f9f7 305 return HAL_OK;
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /**
<> 144:ef7eb2e8f9f7 309 * @brief Stops the TIM Hall sensor Interface.
<> 144:ef7eb2e8f9f7 310 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 311 * @retval HAL status
<> 144:ef7eb2e8f9f7 312 */
<> 144:ef7eb2e8f9f7 313 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 314 {
<> 144:ef7eb2e8f9f7 315 /* Check the parameters */
<> 144:ef7eb2e8f9f7 316 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /* Disable the Input Capture channels 1, 2 and 3
<> 144:ef7eb2e8f9f7 319 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 320 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 323 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Return function status */
<> 144:ef7eb2e8f9f7 326 return HAL_OK;
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 331 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 332 * @retval HAL status
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 /* Check the parameters */
<> 144:ef7eb2e8f9f7 337 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Enable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 340 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 343 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 344 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 347 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Return function status */
<> 144:ef7eb2e8f9f7 350 return HAL_OK;
<> 144:ef7eb2e8f9f7 351 }
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /**
<> 144:ef7eb2e8f9f7 354 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 355 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 356 * @retval HAL status
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 /* Check the parameters */
<> 144:ef7eb2e8f9f7 361 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Disable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 364 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 365 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Disable the capture compare Interrupts event */
<> 144:ef7eb2e8f9f7 368 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 371 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* Return function status */
<> 144:ef7eb2e8f9f7 374 return HAL_OK;
<> 144:ef7eb2e8f9f7 375 }
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /**
<> 144:ef7eb2e8f9f7 378 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 379 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 380 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 381 * @param Length: The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 382 * @retval HAL status
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 385 {
<> 144:ef7eb2e8f9f7 386 /* Check the parameters */
<> 144:ef7eb2e8f9f7 387 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 390 {
<> 144:ef7eb2e8f9f7 391 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 392 }
<> 144:ef7eb2e8f9f7 393 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 394 {
<> 144:ef7eb2e8f9f7 395 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 398 }
<> 144:ef7eb2e8f9f7 399 else
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 405 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 406 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /* Set the DMA Input Capture 1 Callback */
<> 144:ef7eb2e8f9f7 409 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 410 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 411 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Enable the DMA channel for Capture 1*/
<> 144:ef7eb2e8f9f7 414 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Enable the capture compare 1 Interrupt */
<> 144:ef7eb2e8f9f7 417 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 420 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Return function status */
<> 144:ef7eb2e8f9f7 423 return HAL_OK;
<> 144:ef7eb2e8f9f7 424 }
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /**
<> 144:ef7eb2e8f9f7 427 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 428 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 429 * @retval HAL status
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 /* Check the parameters */
<> 144:ef7eb2e8f9f7 434 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /* Disable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 437 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 438 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* Disable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 442 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 445 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Return function status */
<> 144:ef7eb2e8f9f7 448 return HAL_OK;
<> 144:ef7eb2e8f9f7 449 }
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /**
<> 144:ef7eb2e8f9f7 452 * @}
<> 144:ef7eb2e8f9f7 453 */
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 456 * @brief Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 457 *
<> 144:ef7eb2e8f9f7 458 @verbatim
<> 144:ef7eb2e8f9f7 459 ==============================================================================
<> 144:ef7eb2e8f9f7 460 ##### Timer Complementary Output Compare functions #####
<> 144:ef7eb2e8f9f7 461 ==============================================================================
<> 144:ef7eb2e8f9f7 462 [..]
<> 144:ef7eb2e8f9f7 463 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 464 (+) Start the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 465 (+) Stop the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 466 (+) Start the Complementary Output Compare/PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 467 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 468 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 469 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 @endverbatim
<> 144:ef7eb2e8f9f7 472 * @{
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /**
<> 144:ef7eb2e8f9f7 476 * @brief Starts the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 477 * output.
<> 144:ef7eb2e8f9f7 478 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 479 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 480 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 481 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 482 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 483 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 484 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 485 * @retval HAL status
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 488 {
<> 144:ef7eb2e8f9f7 489 /* Check the parameters */
<> 144:ef7eb2e8f9f7 490 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 493 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 496 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 499 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* Return function status */
<> 144:ef7eb2e8f9f7 502 return HAL_OK;
<> 144:ef7eb2e8f9f7 503 }
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /**
<> 144:ef7eb2e8f9f7 506 * @brief Stops the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 507 * output.
<> 144:ef7eb2e8f9f7 508 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 509 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 510 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 511 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 512 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 513 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 514 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 515 * @retval HAL status
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 518 {
<> 144:ef7eb2e8f9f7 519 /* Check the parameters */
<> 144:ef7eb2e8f9f7 520 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 523 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 526 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 529 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Return function status */
<> 144:ef7eb2e8f9f7 532 return HAL_OK;
<> 144:ef7eb2e8f9f7 533 }
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /**
<> 144:ef7eb2e8f9f7 536 * @brief Starts the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 537 * on the complementary output.
<> 144:ef7eb2e8f9f7 538 * @param htim : TIM OC handle
<> 144:ef7eb2e8f9f7 539 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 540 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 541 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 542 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 543 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 544 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 545 * @retval HAL status
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 548 {
<> 144:ef7eb2e8f9f7 549 /* Check the parameters */
<> 144:ef7eb2e8f9f7 550 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 switch (Channel)
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 557 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 558 }
<> 144:ef7eb2e8f9f7 559 break;
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 562 {
<> 144:ef7eb2e8f9f7 563 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 564 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 565 }
<> 144:ef7eb2e8f9f7 566 break;
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 569 {
<> 144:ef7eb2e8f9f7 570 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 571 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573 break;
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 578 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580 break;
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 default:
<> 144:ef7eb2e8f9f7 583 break;
<> 144:ef7eb2e8f9f7 584 }
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 587 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 590 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 593 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 596 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Return function status */
<> 144:ef7eb2e8f9f7 599 return HAL_OK;
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /**
<> 144:ef7eb2e8f9f7 603 * @brief Stops the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 604 * on the complementary output.
<> 144:ef7eb2e8f9f7 605 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 606 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 607 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 608 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 609 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 610 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 611 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 612 * @retval HAL status
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Check the parameters */
<> 144:ef7eb2e8f9f7 619 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 switch (Channel)
<> 144:ef7eb2e8f9f7 622 {
<> 144:ef7eb2e8f9f7 623 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 626 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628 break;
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 633 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635 break;
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 640 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 641 }
<> 144:ef7eb2e8f9f7 642 break;
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 647 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 648 }
<> 144:ef7eb2e8f9f7 649 break;
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 default:
<> 144:ef7eb2e8f9f7 652 break;
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 656 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 659 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 660 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 663 }
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 666 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 669 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Return function status */
<> 144:ef7eb2e8f9f7 672 return HAL_OK;
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /**
<> 144:ef7eb2e8f9f7 676 * @brief Starts the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 677 * on the complementary output.
<> 144:ef7eb2e8f9f7 678 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 679 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 680 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 681 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 682 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 683 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 684 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 685 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 686 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 687 * @retval HAL status
<> 144:ef7eb2e8f9f7 688 */
<> 144:ef7eb2e8f9f7 689 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 690 {
<> 144:ef7eb2e8f9f7 691 /* Check the parameters */
<> 144:ef7eb2e8f9f7 692 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 695 {
<> 144:ef7eb2e8f9f7 696 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 699 {
<> 144:ef7eb2e8f9f7 700 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 701 {
<> 144:ef7eb2e8f9f7 702 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704 else
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709 switch (Channel)
<> 144:ef7eb2e8f9f7 710 {
<> 144:ef7eb2e8f9f7 711 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 714 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 717 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 720 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 723 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 724 }
<> 144:ef7eb2e8f9f7 725 break;
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 728 {
<> 144:ef7eb2e8f9f7 729 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 730 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 733 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 736 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 739 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 740 }
<> 144:ef7eb2e8f9f7 741 break;
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 744 {
<> 144:ef7eb2e8f9f7 745 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 746 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 749 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 752 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 755 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 756 }
<> 144:ef7eb2e8f9f7 757 break;
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 760 {
<> 144:ef7eb2e8f9f7 761 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 762 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 765 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 768 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 771 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 772 }
<> 144:ef7eb2e8f9f7 773 break;
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 default:
<> 144:ef7eb2e8f9f7 776 break;
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 780 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 783 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 786 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /* Return function status */
<> 144:ef7eb2e8f9f7 789 return HAL_OK;
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /**
<> 144:ef7eb2e8f9f7 793 * @brief Stops the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 794 * on the complementary output.
<> 144:ef7eb2e8f9f7 795 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 796 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 797 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 798 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 799 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 800 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 801 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 802 * @retval HAL status
<> 144:ef7eb2e8f9f7 803 */
<> 144:ef7eb2e8f9f7 804 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 /* Check the parameters */
<> 144:ef7eb2e8f9f7 807 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 switch (Channel)
<> 144:ef7eb2e8f9f7 810 {
<> 144:ef7eb2e8f9f7 811 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 814 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 815 }
<> 144:ef7eb2e8f9f7 816 break;
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 819 {
<> 144:ef7eb2e8f9f7 820 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 821 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 822 }
<> 144:ef7eb2e8f9f7 823 break;
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 826 {
<> 144:ef7eb2e8f9f7 827 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 828 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 829 }
<> 144:ef7eb2e8f9f7 830 break;
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 833 {
<> 144:ef7eb2e8f9f7 834 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 835 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 836 }
<> 144:ef7eb2e8f9f7 837 break;
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 default:
<> 144:ef7eb2e8f9f7 840 break;
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 844 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 847 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 850 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /* Change the htim state */
<> 144:ef7eb2e8f9f7 853 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /* Return function status */
<> 144:ef7eb2e8f9f7 856 return HAL_OK;
<> 144:ef7eb2e8f9f7 857 }
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 /**
<> 144:ef7eb2e8f9f7 860 * @}
<> 144:ef7eb2e8f9f7 861 */
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 864 * @brief Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 865 *
<> 144:ef7eb2e8f9f7 866 @verbatim
<> 144:ef7eb2e8f9f7 867 ==============================================================================
<> 144:ef7eb2e8f9f7 868 ##### Timer Complementary PWM functions #####
<> 144:ef7eb2e8f9f7 869 ==============================================================================
<> 144:ef7eb2e8f9f7 870 [..]
<> 144:ef7eb2e8f9f7 871 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 872 (+) Start the Complementary PWM.
<> 144:ef7eb2e8f9f7 873 (+) Stop the Complementary PWM.
<> 144:ef7eb2e8f9f7 874 (+) Start the Complementary PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 875 (+) Stop the Complementary PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 876 (+) Start the Complementary PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 877 (+) Stop the Complementary PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 878 (+) Start the Complementary Input Capture measurement.
<> 144:ef7eb2e8f9f7 879 (+) Stop the Complementary Input Capture.
<> 144:ef7eb2e8f9f7 880 (+) Start the Complementary Input Capture and enable interrupts.
<> 144:ef7eb2e8f9f7 881 (+) Stop the Complementary Input Capture and disable interrupts.
<> 144:ef7eb2e8f9f7 882 (+) Start the Complementary Input Capture and enable DMA transfers.
<> 144:ef7eb2e8f9f7 883 (+) Stop the Complementary Input Capture and disable DMA transfers.
<> 144:ef7eb2e8f9f7 884 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 885 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 886 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 887 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 @endverbatim
<> 144:ef7eb2e8f9f7 890 * @{
<> 144:ef7eb2e8f9f7 891 */
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /**
<> 144:ef7eb2e8f9f7 894 * @brief Starts the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 895 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 896 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 897 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 898 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 899 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 900 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 901 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 902 * @retval HAL status
<> 144:ef7eb2e8f9f7 903 */
<> 144:ef7eb2e8f9f7 904 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 905 {
<> 144:ef7eb2e8f9f7 906 /* Check the parameters */
<> 144:ef7eb2e8f9f7 907 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 910 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 913 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 916 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /* Return function status */
<> 144:ef7eb2e8f9f7 919 return HAL_OK;
<> 144:ef7eb2e8f9f7 920 }
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /**
<> 144:ef7eb2e8f9f7 923 * @brief Stops the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 924 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 925 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 926 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 927 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 928 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 929 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 930 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 931 * @retval HAL status
<> 144:ef7eb2e8f9f7 932 */
<> 144:ef7eb2e8f9f7 933 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 934 {
<> 144:ef7eb2e8f9f7 935 /* Check the parameters */
<> 144:ef7eb2e8f9f7 936 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 939 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 942 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 945 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /* Return function status */
<> 144:ef7eb2e8f9f7 948 return HAL_OK;
<> 144:ef7eb2e8f9f7 949 }
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /**
<> 144:ef7eb2e8f9f7 952 * @brief Starts the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 953 * complementary output.
<> 144:ef7eb2e8f9f7 954 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 955 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 956 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 957 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 958 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 959 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 960 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 961 * @retval HAL status
<> 144:ef7eb2e8f9f7 962 */
<> 144:ef7eb2e8f9f7 963 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 964 {
<> 144:ef7eb2e8f9f7 965 /* Check the parameters */
<> 144:ef7eb2e8f9f7 966 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 switch (Channel)
<> 144:ef7eb2e8f9f7 969 {
<> 144:ef7eb2e8f9f7 970 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 971 {
<> 144:ef7eb2e8f9f7 972 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 973 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 974 }
<> 144:ef7eb2e8f9f7 975 break;
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 978 {
<> 144:ef7eb2e8f9f7 979 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 980 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 981 }
<> 144:ef7eb2e8f9f7 982 break;
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 985 {
<> 144:ef7eb2e8f9f7 986 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 987 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 988 }
<> 144:ef7eb2e8f9f7 989 break;
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 992 {
<> 144:ef7eb2e8f9f7 993 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 994 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996 break;
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 default:
<> 144:ef7eb2e8f9f7 999 break;
<> 144:ef7eb2e8f9f7 1000 }
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 1003 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1006 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1009 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1012 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 /* Return function status */
<> 144:ef7eb2e8f9f7 1015 return HAL_OK;
<> 144:ef7eb2e8f9f7 1016 }
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /**
<> 144:ef7eb2e8f9f7 1019 * @brief Stops the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1020 * complementary output.
<> 144:ef7eb2e8f9f7 1021 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1022 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1023 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1024 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1025 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1026 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1027 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1028 * @retval HAL status
<> 144:ef7eb2e8f9f7 1029 */
<> 144:ef7eb2e8f9f7 1030 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1031 {
<> 144:ef7eb2e8f9f7 1032 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1035 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 switch (Channel)
<> 144:ef7eb2e8f9f7 1038 {
<> 144:ef7eb2e8f9f7 1039 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1040 {
<> 144:ef7eb2e8f9f7 1041 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1042 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1043 }
<> 144:ef7eb2e8f9f7 1044 break;
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1047 {
<> 144:ef7eb2e8f9f7 1048 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1049 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1050 }
<> 144:ef7eb2e8f9f7 1051 break;
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1054 {
<> 144:ef7eb2e8f9f7 1055 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1056 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1057 }
<> 144:ef7eb2e8f9f7 1058 break;
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1061 {
<> 144:ef7eb2e8f9f7 1062 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1063 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1064 }
<> 144:ef7eb2e8f9f7 1065 break;
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 default:
<> 144:ef7eb2e8f9f7 1068 break;
<> 144:ef7eb2e8f9f7 1069 }
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1072 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 1076 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 1077 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 1078 {
<> 144:ef7eb2e8f9f7 1079 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1080 }
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1083 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1084
<> 144:ef7eb2e8f9f7 1085 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1086 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 /* Return function status */
<> 144:ef7eb2e8f9f7 1089 return HAL_OK;
<> 144:ef7eb2e8f9f7 1090 }
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 /**
<> 144:ef7eb2e8f9f7 1093 * @brief Starts the TIM PWM signal generation in DMA mode on the
<> 144:ef7eb2e8f9f7 1094 * complementary output
<> 144:ef7eb2e8f9f7 1095 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1096 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1097 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1098 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1099 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1100 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1101 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1102 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 1103 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1104 * @retval HAL status
<> 144:ef7eb2e8f9f7 1105 */
<> 144:ef7eb2e8f9f7 1106 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1107 {
<> 144:ef7eb2e8f9f7 1108 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1109 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1112 {
<> 144:ef7eb2e8f9f7 1113 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1114 }
<> 144:ef7eb2e8f9f7 1115 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1116 {
<> 144:ef7eb2e8f9f7 1117 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 1118 {
<> 144:ef7eb2e8f9f7 1119 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121 else
<> 144:ef7eb2e8f9f7 1122 {
<> 144:ef7eb2e8f9f7 1123 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1124 }
<> 144:ef7eb2e8f9f7 1125 }
<> 144:ef7eb2e8f9f7 1126 switch (Channel)
<> 144:ef7eb2e8f9f7 1127 {
<> 144:ef7eb2e8f9f7 1128 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1129 {
<> 144:ef7eb2e8f9f7 1130 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1131 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1134 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1135
<> 144:ef7eb2e8f9f7 1136 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1137 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1140 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1141 }
<> 144:ef7eb2e8f9f7 1142 break;
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1145 {
<> 144:ef7eb2e8f9f7 1146 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1147 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1150 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1153 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1156 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1157 }
<> 144:ef7eb2e8f9f7 1158 break;
<> 144:ef7eb2e8f9f7 1159
<> 144:ef7eb2e8f9f7 1160 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1161 {
<> 144:ef7eb2e8f9f7 1162 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1163 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1166 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1167
<> 144:ef7eb2e8f9f7 1168 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1169 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1172 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1173 }
<> 144:ef7eb2e8f9f7 1174 break;
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1177 {
<> 144:ef7eb2e8f9f7 1178 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1179 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1182 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1185 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1188 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1189 }
<> 144:ef7eb2e8f9f7 1190 break;
<> 144:ef7eb2e8f9f7 1191
<> 144:ef7eb2e8f9f7 1192 default:
<> 144:ef7eb2e8f9f7 1193 break;
<> 144:ef7eb2e8f9f7 1194 }
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1197 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1200 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1203 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 /* Return function status */
<> 144:ef7eb2e8f9f7 1206 return HAL_OK;
<> 144:ef7eb2e8f9f7 1207 }
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /**
<> 144:ef7eb2e8f9f7 1210 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
<> 144:ef7eb2e8f9f7 1211 * output
<> 144:ef7eb2e8f9f7 1212 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1213 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1214 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1215 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1216 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1217 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1218 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1219 * @retval HAL status
<> 144:ef7eb2e8f9f7 1220 */
<> 144:ef7eb2e8f9f7 1221 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1222 {
<> 144:ef7eb2e8f9f7 1223 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1224 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1225
<> 144:ef7eb2e8f9f7 1226 switch (Channel)
<> 144:ef7eb2e8f9f7 1227 {
<> 144:ef7eb2e8f9f7 1228 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1229 {
<> 144:ef7eb2e8f9f7 1230 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1231 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1232 }
<> 144:ef7eb2e8f9f7 1233 break;
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1236 {
<> 144:ef7eb2e8f9f7 1237 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1238 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1239 }
<> 144:ef7eb2e8f9f7 1240 break;
<> 144:ef7eb2e8f9f7 1241
<> 144:ef7eb2e8f9f7 1242 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1243 {
<> 144:ef7eb2e8f9f7 1244 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1245 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1246 }
<> 144:ef7eb2e8f9f7 1247 break;
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1250 {
<> 144:ef7eb2e8f9f7 1251 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1252 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1253 }
<> 144:ef7eb2e8f9f7 1254 break;
<> 144:ef7eb2e8f9f7 1255
<> 144:ef7eb2e8f9f7 1256 default:
<> 144:ef7eb2e8f9f7 1257 break;
<> 144:ef7eb2e8f9f7 1258 }
<> 144:ef7eb2e8f9f7 1259
<> 144:ef7eb2e8f9f7 1260 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1261 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1264 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1265
<> 144:ef7eb2e8f9f7 1266 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1267 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1268
<> 144:ef7eb2e8f9f7 1269 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1270 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Return function status */
<> 144:ef7eb2e8f9f7 1273 return HAL_OK;
<> 144:ef7eb2e8f9f7 1274 }
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 /**
<> 144:ef7eb2e8f9f7 1277 * @}
<> 144:ef7eb2e8f9f7 1278 */
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1281 * @brief Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1282 *
<> 144:ef7eb2e8f9f7 1283 @verbatim
<> 144:ef7eb2e8f9f7 1284 ==============================================================================
<> 144:ef7eb2e8f9f7 1285 ##### Timer Complementary One Pulse functions #####
<> 144:ef7eb2e8f9f7 1286 ==============================================================================
<> 144:ef7eb2e8f9f7 1287 [..]
<> 144:ef7eb2e8f9f7 1288 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1289 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 1290 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 1291 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 1292 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 1293
<> 144:ef7eb2e8f9f7 1294 @endverbatim
<> 144:ef7eb2e8f9f7 1295 * @{
<> 144:ef7eb2e8f9f7 1296 */
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 /**
<> 144:ef7eb2e8f9f7 1299 * @brief Starts the TIM One Pulse signal generation on the complementary
<> 144:ef7eb2e8f9f7 1300 * output.
<> 144:ef7eb2e8f9f7 1301 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1302 * @param OutputChannel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1303 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1304 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1305 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1306 * @retval HAL status
<> 144:ef7eb2e8f9f7 1307 */
<> 144:ef7eb2e8f9f7 1308 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1309 {
<> 144:ef7eb2e8f9f7 1310 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1311 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1314 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1317 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1318
<> 144:ef7eb2e8f9f7 1319 /* Return function status */
<> 144:ef7eb2e8f9f7 1320 return HAL_OK;
<> 144:ef7eb2e8f9f7 1321 }
<> 144:ef7eb2e8f9f7 1322
<> 144:ef7eb2e8f9f7 1323 /**
<> 144:ef7eb2e8f9f7 1324 * @brief Stops the TIM One Pulse signal generation on the complementary
<> 144:ef7eb2e8f9f7 1325 * output.
<> 144:ef7eb2e8f9f7 1326 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1327 * @param OutputChannel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1328 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1329 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1330 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1331 * @retval HAL status
<> 144:ef7eb2e8f9f7 1332 */
<> 144:ef7eb2e8f9f7 1333 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1334 {
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1337 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1340 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1341
<> 144:ef7eb2e8f9f7 1342 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1343 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1344
<> 144:ef7eb2e8f9f7 1345 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1346 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348 /* Return function status */
<> 144:ef7eb2e8f9f7 1349 return HAL_OK;
<> 144:ef7eb2e8f9f7 1350 }
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 /**
<> 144:ef7eb2e8f9f7 1353 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1354 * complementary channel.
<> 144:ef7eb2e8f9f7 1355 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1356 * @param OutputChannel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1357 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1358 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1359 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1360 * @retval HAL status
<> 144:ef7eb2e8f9f7 1361 */
<> 144:ef7eb2e8f9f7 1362 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1363 {
<> 144:ef7eb2e8f9f7 1364 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1365 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1368 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1371 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1372
<> 144:ef7eb2e8f9f7 1373 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1374 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1375
<> 144:ef7eb2e8f9f7 1376 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1377 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1378
<> 144:ef7eb2e8f9f7 1379 /* Return function status */
<> 144:ef7eb2e8f9f7 1380 return HAL_OK;
<> 144:ef7eb2e8f9f7 1381 }
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 /**
<> 144:ef7eb2e8f9f7 1384 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1385 * complementary channel.
<> 144:ef7eb2e8f9f7 1386 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1387 * @param OutputChannel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1388 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1389 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1390 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1391 * @retval HAL status
<> 144:ef7eb2e8f9f7 1392 */
<> 144:ef7eb2e8f9f7 1393 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1394 {
<> 144:ef7eb2e8f9f7 1395 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1396 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1399 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1400
<> 144:ef7eb2e8f9f7 1401 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1402 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1403
<> 144:ef7eb2e8f9f7 1404 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1405 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1406
<> 144:ef7eb2e8f9f7 1407 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1408 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1409
<> 144:ef7eb2e8f9f7 1410 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1411 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1412
<> 144:ef7eb2e8f9f7 1413 /* Return function status */
<> 144:ef7eb2e8f9f7 1414 return HAL_OK;
<> 144:ef7eb2e8f9f7 1415 }
<> 144:ef7eb2e8f9f7 1416
<> 144:ef7eb2e8f9f7 1417 /**
<> 144:ef7eb2e8f9f7 1418 * @}
<> 144:ef7eb2e8f9f7 1419 */
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 1422 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1423 *
<> 144:ef7eb2e8f9f7 1424 @verbatim
<> 144:ef7eb2e8f9f7 1425 ==============================================================================
<> 144:ef7eb2e8f9f7 1426 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1427 ==============================================================================
<> 144:ef7eb2e8f9f7 1428 [..]
<> 144:ef7eb2e8f9f7 1429 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1430 (+) Configure the commutation event in case of use of the Hall sensor interface.
<> 144:ef7eb2e8f9f7 1431 (+) Configure Output channels for OC and PWM mode.
<> 144:ef7eb2e8f9f7 1432
<> 144:ef7eb2e8f9f7 1433 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 1434 (+) Configure Master synchronization.
<> 144:ef7eb2e8f9f7 1435 (+) Configure timer remapping capabilities.
<> 144:ef7eb2e8f9f7 1436 (+) Enable or disable channel grouping
<> 144:ef7eb2e8f9f7 1437
<> 144:ef7eb2e8f9f7 1438 @endverbatim
<> 144:ef7eb2e8f9f7 1439 * @{
<> 144:ef7eb2e8f9f7 1440 */
<> 144:ef7eb2e8f9f7 1441
<> 144:ef7eb2e8f9f7 1442 /**
<> 144:ef7eb2e8f9f7 1443 * @brief Configure the TIM commutation event sequence.
<> 144:ef7eb2e8f9f7 1444 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1445 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1446 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1447 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1448 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1449 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1450 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1451 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1452 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1453 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1454 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1455 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1456 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1457 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1458 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1459 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1460 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1461 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1462 * @retval HAL status
<> 144:ef7eb2e8f9f7 1463 */
<> 144:ef7eb2e8f9f7 1464 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1465 {
<> 144:ef7eb2e8f9f7 1466 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1467 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1468 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1469
<> 144:ef7eb2e8f9f7 1470 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1471
<> 144:ef7eb2e8f9f7 1472 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1473 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1474 {
<> 144:ef7eb2e8f9f7 1475 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1476 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1477 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1478 }
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1481 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1482 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1483 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1484 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1485
<> 144:ef7eb2e8f9f7 1486 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1487
<> 144:ef7eb2e8f9f7 1488 return HAL_OK;
<> 144:ef7eb2e8f9f7 1489 }
<> 144:ef7eb2e8f9f7 1490
<> 144:ef7eb2e8f9f7 1491 /**
<> 144:ef7eb2e8f9f7 1492 * @brief Configure the TIM commutation event sequence with interrupt.
<> 144:ef7eb2e8f9f7 1493 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1494 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1495 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1496 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1497 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1498 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1499 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1500 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1501 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1502 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1503 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1504 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1505 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1506 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1507 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1508 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1509 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1510 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1511 * @retval HAL status
<> 144:ef7eb2e8f9f7 1512 */
<> 144:ef7eb2e8f9f7 1513 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1514 {
<> 144:ef7eb2e8f9f7 1515 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1516 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1517 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1518
<> 144:ef7eb2e8f9f7 1519 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1520
<> 144:ef7eb2e8f9f7 1521 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1522 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1523 {
<> 144:ef7eb2e8f9f7 1524 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1525 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1526 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1527 }
<> 144:ef7eb2e8f9f7 1528
<> 144:ef7eb2e8f9f7 1529 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1530 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1531 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1532 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1533 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1534
<> 144:ef7eb2e8f9f7 1535 /* Enable the Commutation Interrupt Request */
<> 144:ef7eb2e8f9f7 1536 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
<> 144:ef7eb2e8f9f7 1537
<> 144:ef7eb2e8f9f7 1538 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1539
<> 144:ef7eb2e8f9f7 1540 return HAL_OK;
<> 144:ef7eb2e8f9f7 1541 }
<> 144:ef7eb2e8f9f7 1542
<> 144:ef7eb2e8f9f7 1543 /**
<> 144:ef7eb2e8f9f7 1544 * @brief Configure the TIM commutation event sequence with DMA.
<> 144:ef7eb2e8f9f7 1545 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1546 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1547 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1548 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1549 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1550 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1551 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
<> 144:ef7eb2e8f9f7 1552 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1553 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1554 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1555 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1556 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1557 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1558 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1559 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1560 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1561 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1562 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1563 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1564 * @retval HAL status
<> 144:ef7eb2e8f9f7 1565 */
<> 144:ef7eb2e8f9f7 1566 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1567 {
<> 144:ef7eb2e8f9f7 1568 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1569 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1570 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1571
<> 144:ef7eb2e8f9f7 1572 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1573
<> 144:ef7eb2e8f9f7 1574 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1575 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1576 {
<> 144:ef7eb2e8f9f7 1577 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1578 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1579 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1580 }
<> 144:ef7eb2e8f9f7 1581
<> 144:ef7eb2e8f9f7 1582 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1583 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1584 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1585 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1586 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1587
<> 144:ef7eb2e8f9f7 1588 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1589 /* Set the DMA Commutation Callback */
<> 144:ef7eb2e8f9f7 1590 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 1591 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1592 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
<> 144:ef7eb2e8f9f7 1593
<> 144:ef7eb2e8f9f7 1594 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1595 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
<> 144:ef7eb2e8f9f7 1596
<> 144:ef7eb2e8f9f7 1597 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1598
<> 144:ef7eb2e8f9f7 1599 return HAL_OK;
<> 144:ef7eb2e8f9f7 1600 }
<> 144:ef7eb2e8f9f7 1601
<> 144:ef7eb2e8f9f7 1602 /**
<> 144:ef7eb2e8f9f7 1603 * @brief Configures the TIM in master mode.
<> 144:ef7eb2e8f9f7 1604 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 1605 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1606 * contains the selected trigger output (TRGO) and the Master/Slave
<> 144:ef7eb2e8f9f7 1607 * mode.
<> 144:ef7eb2e8f9f7 1608 * @retval HAL status
<> 144:ef7eb2e8f9f7 1609 */
<> 144:ef7eb2e8f9f7 1610 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1611 TIM_MasterConfigTypeDef * sMasterConfig)
<> 144:ef7eb2e8f9f7 1612 {
<> 144:ef7eb2e8f9f7 1613 uint32_t tmpcr2;
<> 144:ef7eb2e8f9f7 1614 uint32_t tmpsmcr;
<> 144:ef7eb2e8f9f7 1615
<> 144:ef7eb2e8f9f7 1616 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1617 assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1618 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
<> 144:ef7eb2e8f9f7 1619 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
<> 144:ef7eb2e8f9f7 1620
<> 144:ef7eb2e8f9f7 1621 /* Check input state */
<> 144:ef7eb2e8f9f7 1622 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1623
<> 144:ef7eb2e8f9f7 1624 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 1625 tmpcr2 = htim->Instance->CR2;
<> 144:ef7eb2e8f9f7 1626
<> 144:ef7eb2e8f9f7 1627 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 1628 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 1629
<> 144:ef7eb2e8f9f7 1630 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
<> 144:ef7eb2e8f9f7 1631 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
<> 144:ef7eb2e8f9f7 1632 {
<> 144:ef7eb2e8f9f7 1633 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1634 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
<> 144:ef7eb2e8f9f7 1635
<> 144:ef7eb2e8f9f7 1636 /* Clear the MMS2 bits */
<> 144:ef7eb2e8f9f7 1637 tmpcr2 &= ~TIM_CR2_MMS2;
<> 144:ef7eb2e8f9f7 1638 /* Select the TRGO2 source*/
<> 144:ef7eb2e8f9f7 1639 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
<> 144:ef7eb2e8f9f7 1640 }
<> 144:ef7eb2e8f9f7 1641
<> 144:ef7eb2e8f9f7 1642 /* Reset the MMS Bits */
<> 144:ef7eb2e8f9f7 1643 tmpcr2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 1644 /* Select the TRGO source */
<> 144:ef7eb2e8f9f7 1645 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
<> 144:ef7eb2e8f9f7 1646
<> 144:ef7eb2e8f9f7 1647 /* Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1648 tmpsmcr &= ~TIM_SMCR_MSM;
<> 144:ef7eb2e8f9f7 1649 /* Set master mode */
<> 144:ef7eb2e8f9f7 1650 tmpsmcr |= sMasterConfig->MasterSlaveMode;
<> 144:ef7eb2e8f9f7 1651
<> 144:ef7eb2e8f9f7 1652 /* Update TIMx CR2 */
<> 144:ef7eb2e8f9f7 1653 htim->Instance->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 1654
<> 144:ef7eb2e8f9f7 1655 /* Update TIMx SMCR */
<> 144:ef7eb2e8f9f7 1656 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 1657
<> 144:ef7eb2e8f9f7 1658 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1659
<> 144:ef7eb2e8f9f7 1660 return HAL_OK;
<> 144:ef7eb2e8f9f7 1661 }
<> 144:ef7eb2e8f9f7 1662
<> 144:ef7eb2e8f9f7 1663 /**
<> 144:ef7eb2e8f9f7 1664 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
<> 144:ef7eb2e8f9f7 1665 * and the AOE(automatic output enable).
<> 144:ef7eb2e8f9f7 1666 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1667 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1668 * contains the BDTR Register configuration information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 1669 * @retval HAL status
<> 144:ef7eb2e8f9f7 1670 */
<> 144:ef7eb2e8f9f7 1671 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1672 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
<> 144:ef7eb2e8f9f7 1673 {
<> 144:ef7eb2e8f9f7 1674 uint32_t tmpbdtr = 0;
AnnaBridge 167:e84263d55307 1675
<> 144:ef7eb2e8f9f7 1676 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1677 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1678 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
<> 144:ef7eb2e8f9f7 1679 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
<> 144:ef7eb2e8f9f7 1680 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
<> 144:ef7eb2e8f9f7 1681 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
<> 144:ef7eb2e8f9f7 1682 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
<> 144:ef7eb2e8f9f7 1683 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
<> 144:ef7eb2e8f9f7 1684 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
<> 144:ef7eb2e8f9f7 1685 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
AnnaBridge 167:e84263d55307 1686
<> 144:ef7eb2e8f9f7 1687 /* Check input state */
<> 144:ef7eb2e8f9f7 1688 __HAL_LOCK(htim);
AnnaBridge 167:e84263d55307 1689
<> 144:ef7eb2e8f9f7 1690 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
AnnaBridge 167:e84263d55307 1691 the OSSI State, the dead time value and the Automatic Output Enable Bit */
AnnaBridge 167:e84263d55307 1692
AnnaBridge 167:e84263d55307 1693 /* Set the BDTR bits */
AnnaBridge 167:e84263d55307 1694 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
AnnaBridge 167:e84263d55307 1695 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
AnnaBridge 167:e84263d55307 1696 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
AnnaBridge 167:e84263d55307 1697 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
AnnaBridge 167:e84263d55307 1698 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
AnnaBridge 167:e84263d55307 1699 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
AnnaBridge 167:e84263d55307 1700 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
AnnaBridge 167:e84263d55307 1701 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
AnnaBridge 167:e84263d55307 1702 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT));
AnnaBridge 167:e84263d55307 1703
<> 144:ef7eb2e8f9f7 1704 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
<> 144:ef7eb2e8f9f7 1705 {
<> 144:ef7eb2e8f9f7 1706 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
<> 144:ef7eb2e8f9f7 1707 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
<> 144:ef7eb2e8f9f7 1708 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
AnnaBridge 167:e84263d55307 1709
AnnaBridge 167:e84263d55307 1710 /* Set the BREAK2 input related BDTR bits */
AnnaBridge 167:e84263d55307 1711 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT));
AnnaBridge 167:e84263d55307 1712 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
AnnaBridge 167:e84263d55307 1713 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
<> 144:ef7eb2e8f9f7 1714 }
AnnaBridge 167:e84263d55307 1715
<> 144:ef7eb2e8f9f7 1716 /* Set TIMx_BDTR */
<> 144:ef7eb2e8f9f7 1717 htim->Instance->BDTR = tmpbdtr;
AnnaBridge 167:e84263d55307 1718
<> 144:ef7eb2e8f9f7 1719 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1720
<> 144:ef7eb2e8f9f7 1721 return HAL_OK;
<> 144:ef7eb2e8f9f7 1722 }
<> 144:ef7eb2e8f9f7 1723
<> 144:ef7eb2e8f9f7 1724 /**
<> 144:ef7eb2e8f9f7 1725 * @brief Configures the break input source.
<> 144:ef7eb2e8f9f7 1726 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 1727 * @param BreakInput: Break input to configure
<> 144:ef7eb2e8f9f7 1728 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1729 * @arg TIM_BREAKINPUT_BRK: Timer break input
<> 144:ef7eb2e8f9f7 1730 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
<> 144:ef7eb2e8f9f7 1731 * @param sBreakInputConfig: Break input source configuration
<> 144:ef7eb2e8f9f7 1732 * @retval HAL status
<> 144:ef7eb2e8f9f7 1733 */
<> 144:ef7eb2e8f9f7 1734 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1735 uint32_t BreakInput,
<> 144:ef7eb2e8f9f7 1736 TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
<> 144:ef7eb2e8f9f7 1737
<> 144:ef7eb2e8f9f7 1738 {
<> 144:ef7eb2e8f9f7 1739 uint32_t tmporx = 0;
<> 144:ef7eb2e8f9f7 1740 uint32_t bkin_enable_mask = 0;
<> 144:ef7eb2e8f9f7 1741 uint32_t bkin_polarity_mask = 0;
<> 144:ef7eb2e8f9f7 1742 uint32_t bkin_enable_bitpos = 0;
<> 144:ef7eb2e8f9f7 1743 uint32_t bkin_polarity_bitpos = 0;
<> 144:ef7eb2e8f9f7 1744
<> 144:ef7eb2e8f9f7 1745 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1746 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1747 assert_param(IS_TIM_BREAKINPUT(BreakInput));
<> 144:ef7eb2e8f9f7 1748 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
<> 144:ef7eb2e8f9f7 1749 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
<> 144:ef7eb2e8f9f7 1750
AnnaBridge 167:e84263d55307 1751 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \
AnnaBridge 167:e84263d55307 1752 defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
AnnaBridge 167:e84263d55307 1753 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1754 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
<> 144:ef7eb2e8f9f7 1755 {
<> 144:ef7eb2e8f9f7 1756 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
<> 144:ef7eb2e8f9f7 1757 }
<> 144:ef7eb2e8f9f7 1758 #else
<> 144:ef7eb2e8f9f7 1759 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
AnnaBridge 167:e84263d55307 1760 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */
AnnaBridge 167:e84263d55307 1761 /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
AnnaBridge 167:e84263d55307 1762 /* STM32L496xx || STM32L4A6xx */
<> 144:ef7eb2e8f9f7 1763
<> 144:ef7eb2e8f9f7 1764 /* Check input state */
<> 144:ef7eb2e8f9f7 1765 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1766
<> 144:ef7eb2e8f9f7 1767 switch(sBreakInputConfig->Source)
<> 144:ef7eb2e8f9f7 1768 {
<> 144:ef7eb2e8f9f7 1769 case TIM_BREAKINPUTSOURCE_BKIN:
<> 144:ef7eb2e8f9f7 1770 {
<> 144:ef7eb2e8f9f7 1771 bkin_enable_mask = TIM1_OR2_BKINE;
<> 144:ef7eb2e8f9f7 1772 bkin_enable_bitpos = 0;
<> 144:ef7eb2e8f9f7 1773 bkin_polarity_mask = TIM1_OR2_BKINP;
<> 144:ef7eb2e8f9f7 1774 bkin_polarity_bitpos = 9;
<> 144:ef7eb2e8f9f7 1775 }
<> 144:ef7eb2e8f9f7 1776 break;
<> 144:ef7eb2e8f9f7 1777 case TIM_BREAKINPUTSOURCE_COMP1:
<> 144:ef7eb2e8f9f7 1778 {
<> 144:ef7eb2e8f9f7 1779 bkin_enable_mask = TIM1_OR2_BKCMP1E;
<> 144:ef7eb2e8f9f7 1780 bkin_enable_bitpos = 1;
<> 144:ef7eb2e8f9f7 1781 bkin_polarity_mask = TIM1_OR2_BKCMP1P;
<> 144:ef7eb2e8f9f7 1782 bkin_polarity_bitpos = 10;
<> 144:ef7eb2e8f9f7 1783 }
<> 144:ef7eb2e8f9f7 1784 break;
<> 144:ef7eb2e8f9f7 1785 case TIM_BREAKINPUTSOURCE_COMP2:
<> 144:ef7eb2e8f9f7 1786 {
<> 144:ef7eb2e8f9f7 1787 bkin_enable_mask = TIM1_OR2_BKCMP2E;
<> 144:ef7eb2e8f9f7 1788 bkin_enable_bitpos = 2;
<> 144:ef7eb2e8f9f7 1789 bkin_polarity_mask = TIM1_OR2_BKCMP2P;
<> 144:ef7eb2e8f9f7 1790 bkin_polarity_bitpos = 11;
<> 144:ef7eb2e8f9f7 1791 }
<> 144:ef7eb2e8f9f7 1792 break;
<> 144:ef7eb2e8f9f7 1793
AnnaBridge 167:e84263d55307 1794 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \
AnnaBridge 167:e84263d55307 1795 defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
AnnaBridge 167:e84263d55307 1796 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1797 case TIM_BREAKINPUTSOURCE_DFSDM1:
<> 144:ef7eb2e8f9f7 1798 {
<> 144:ef7eb2e8f9f7 1799 bkin_enable_mask = TIM1_OR2_BKDF1BK0E;
<> 144:ef7eb2e8f9f7 1800 bkin_enable_bitpos = 8;
<> 144:ef7eb2e8f9f7 1801 }
<> 144:ef7eb2e8f9f7 1802 break;
AnnaBridge 167:e84263d55307 1803 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */
AnnaBridge 167:e84263d55307 1804 /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
AnnaBridge 167:e84263d55307 1805 /* STM32L496xx || STM32L4A6xx */
<> 144:ef7eb2e8f9f7 1806
<> 144:ef7eb2e8f9f7 1807 default:
<> 144:ef7eb2e8f9f7 1808 break;
<> 144:ef7eb2e8f9f7 1809 }
<> 144:ef7eb2e8f9f7 1810
<> 144:ef7eb2e8f9f7 1811 switch(BreakInput)
<> 144:ef7eb2e8f9f7 1812 {
<> 144:ef7eb2e8f9f7 1813 case TIM_BREAKINPUT_BRK:
<> 144:ef7eb2e8f9f7 1814 {
<> 144:ef7eb2e8f9f7 1815 /* Get the TIMx_OR2 register value */
<> 144:ef7eb2e8f9f7 1816 tmporx = htim->Instance->OR2;
<> 144:ef7eb2e8f9f7 1817
<> 144:ef7eb2e8f9f7 1818 /* Enable the break input */
<> 144:ef7eb2e8f9f7 1819 tmporx &= ~bkin_enable_mask;
<> 144:ef7eb2e8f9f7 1820 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
<> 144:ef7eb2e8f9f7 1821
<> 144:ef7eb2e8f9f7 1822 /* Set the break input polarity */
AnnaBridge 167:e84263d55307 1823 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \
AnnaBridge 167:e84263d55307 1824 defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
AnnaBridge 167:e84263d55307 1825 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1826 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
AnnaBridge 167:e84263d55307 1827 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */
AnnaBridge 167:e84263d55307 1828 /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
AnnaBridge 167:e84263d55307 1829 /* STM32L496xx || STM32L4A6xx */
<> 144:ef7eb2e8f9f7 1830 {
<> 144:ef7eb2e8f9f7 1831 tmporx &= ~bkin_polarity_mask;
<> 144:ef7eb2e8f9f7 1832 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
<> 144:ef7eb2e8f9f7 1833 }
<> 144:ef7eb2e8f9f7 1834
<> 144:ef7eb2e8f9f7 1835 /* Set TIMx_OR2 */
<> 144:ef7eb2e8f9f7 1836 htim->Instance->OR2 = tmporx;
<> 144:ef7eb2e8f9f7 1837 }
<> 144:ef7eb2e8f9f7 1838 break;
<> 144:ef7eb2e8f9f7 1839 case TIM_BREAKINPUT_BRK2:
<> 144:ef7eb2e8f9f7 1840 {
<> 144:ef7eb2e8f9f7 1841 /* Get the TIMx_OR3 register value */
<> 144:ef7eb2e8f9f7 1842 tmporx = htim->Instance->OR3;
<> 144:ef7eb2e8f9f7 1843
<> 144:ef7eb2e8f9f7 1844 /* Enable the break input */
<> 144:ef7eb2e8f9f7 1845 tmporx &= ~bkin_enable_mask;
<> 144:ef7eb2e8f9f7 1846 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
<> 144:ef7eb2e8f9f7 1847
<> 144:ef7eb2e8f9f7 1848 /* Set the break input polarity */
AnnaBridge 167:e84263d55307 1849 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \
AnnaBridge 167:e84263d55307 1850 defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
AnnaBridge 167:e84263d55307 1851 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1852 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
AnnaBridge 167:e84263d55307 1853 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */
AnnaBridge 167:e84263d55307 1854 /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
AnnaBridge 167:e84263d55307 1855 /* STM32L496xx || STM32L4A6xx */
<> 144:ef7eb2e8f9f7 1856 {
<> 144:ef7eb2e8f9f7 1857 tmporx &= ~bkin_polarity_mask;
<> 144:ef7eb2e8f9f7 1858 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
<> 144:ef7eb2e8f9f7 1859 }
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 /* Set TIMx_OR3 */
<> 144:ef7eb2e8f9f7 1862 htim->Instance->OR3 = tmporx;
<> 144:ef7eb2e8f9f7 1863 }
<> 144:ef7eb2e8f9f7 1864 break;
<> 144:ef7eb2e8f9f7 1865 default:
<> 144:ef7eb2e8f9f7 1866 break;
<> 144:ef7eb2e8f9f7 1867 }
<> 144:ef7eb2e8f9f7 1868
<> 144:ef7eb2e8f9f7 1869 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1870
<> 144:ef7eb2e8f9f7 1871 return HAL_OK;
<> 144:ef7eb2e8f9f7 1872 }
<> 144:ef7eb2e8f9f7 1873
<> 144:ef7eb2e8f9f7 1874 /**
<> 144:ef7eb2e8f9f7 1875 * @brief Configures the TIMx Remapping input capabilities.
<> 144:ef7eb2e8f9f7 1876 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 1877 * @param Remap: specifies the TIM remapping source.
<> 144:ef7eb2e8f9f7 1878 *
<> 144:ef7eb2e8f9f7 1879 @if STM32L486xx
<> 144:ef7eb2e8f9f7 1880 * For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):
<> 144:ef7eb2e8f9f7 1881 *
<> 144:ef7eb2e8f9f7 1882 * field1 can have the following values:
<> 144:ef7eb2e8f9f7 1883 * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
<> 144:ef7eb2e8f9f7 1884 * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
<> 144:ef7eb2e8f9f7 1885 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
<> 144:ef7eb2e8f9f7 1886 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
<> 144:ef7eb2e8f9f7 1887 *
<> 144:ef7eb2e8f9f7 1888 * field2 can have the following values:
<> 144:ef7eb2e8f9f7 1889 * @arg TIM_TIM1_ETR_ADC3_NONE: TIM1_ETR is not connected to any ADC3 AWD (analog watchdog)
<> 144:ef7eb2e8f9f7 1890 * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
<> 144:ef7eb2e8f9f7 1891 * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
<> 144:ef7eb2e8f9f7 1892 * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
<> 144:ef7eb2e8f9f7 1893 *
<> 144:ef7eb2e8f9f7 1894 * field3 can have the following values:
<> 144:ef7eb2e8f9f7 1895 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
<> 144:ef7eb2e8f9f7 1896 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
<> 144:ef7eb2e8f9f7 1897 *
<> 144:ef7eb2e8f9f7 1898 * field4 can have the following values:
<> 144:ef7eb2e8f9f7 1899 * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
<> 144:ef7eb2e8f9f7 1900 * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
<> 144:ef7eb2e8f9f7 1901 * @note When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant
<> 144:ef7eb2e8f9f7 1902 @endif
<> 144:ef7eb2e8f9f7 1903 @if STM32L443xx
<> 144:ef7eb2e8f9f7 1904 * For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3):
<> 144:ef7eb2e8f9f7 1905 *
<> 144:ef7eb2e8f9f7 1906 * field1 can have the following values:
<> 144:ef7eb2e8f9f7 1907 * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
<> 144:ef7eb2e8f9f7 1908 * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
<> 144:ef7eb2e8f9f7 1909 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
<> 144:ef7eb2e8f9f7 1910 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
<> 144:ef7eb2e8f9f7 1911 *
<> 144:ef7eb2e8f9f7 1912 * field2 can have the following values:
<> 144:ef7eb2e8f9f7 1913 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
<> 144:ef7eb2e8f9f7 1914 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
<> 144:ef7eb2e8f9f7 1915 *
<> 144:ef7eb2e8f9f7 1916 * field3 can have the following values:
<> 144:ef7eb2e8f9f7 1917 * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
<> 144:ef7eb2e8f9f7 1918 * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
<> 144:ef7eb2e8f9f7 1919 *
<> 144:ef7eb2e8f9f7 1920 * @note When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant
<> 144:ef7eb2e8f9f7 1921 *
<> 144:ef7eb2e8f9f7 1922 @endif
<> 144:ef7eb2e8f9f7 1923 @if STM32L486xx
<> 144:ef7eb2e8f9f7 1924 * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
<> 144:ef7eb2e8f9f7 1925 *
<> 144:ef7eb2e8f9f7 1926 * field1 can have the following values:
<> 144:ef7eb2e8f9f7 1927 * @arg TIM_TIM2_ITR1_TIM8_TRGO: TIM2_ITR1 is connected to TIM8_TRGO
<> 144:ef7eb2e8f9f7 1928 * @arg TIM_TIM2_ITR1_OTG_FS_SOF: TIM2_ITR1 is connected to OTG_FS SOF
<> 144:ef7eb2e8f9f7 1929 *
<> 144:ef7eb2e8f9f7 1930 * field2 can have the following values:
<> 144:ef7eb2e8f9f7 1931 * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
<> 144:ef7eb2e8f9f7 1932 * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
<> 144:ef7eb2e8f9f7 1933 * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
<> 144:ef7eb2e8f9f7 1934 * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output
<> 144:ef7eb2e8f9f7 1935 *
<> 144:ef7eb2e8f9f7 1936 * field3 can have the following values:
<> 144:ef7eb2e8f9f7 1937 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
<> 144:ef7eb2e8f9f7 1938 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
<> 144:ef7eb2e8f9f7 1939 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
<> 144:ef7eb2e8f9f7 1940 * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
<> 144:ef7eb2e8f9f7 1941 @endif
<> 144:ef7eb2e8f9f7 1942 @if STM32L443xx
<> 144:ef7eb2e8f9f7 1943 * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
<> 144:ef7eb2e8f9f7 1944 *
<> 144:ef7eb2e8f9f7 1945 * field1 can have the following values:
<> 144:ef7eb2e8f9f7 1946 * @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1
<> 144:ef7eb2e8f9f7 1947 * @arg TIM_TIM2_ITR1_USB_SOF: TIM2_ITR1 is connected to USB SOF
<> 144:ef7eb2e8f9f7 1948 *
<> 144:ef7eb2e8f9f7 1949 * field2 can have the following values:
<> 144:ef7eb2e8f9f7 1950 * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
<> 144:ef7eb2e8f9f7 1951 * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
<> 144:ef7eb2e8f9f7 1952 * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
<> 144:ef7eb2e8f9f7 1953 * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output
<> 144:ef7eb2e8f9f7 1954 *
<> 144:ef7eb2e8f9f7 1955 * field3 can have the following values:
<> 144:ef7eb2e8f9f7 1956 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
<> 144:ef7eb2e8f9f7 1957 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
<> 144:ef7eb2e8f9f7 1958 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
<> 144:ef7eb2e8f9f7 1959 * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
<> 144:ef7eb2e8f9f7 1960 *
<> 144:ef7eb2e8f9f7 1961 @endif
<> 144:ef7eb2e8f9f7 1962 @if STM32L486xx
<> 144:ef7eb2e8f9f7 1963 * For TIM3, the parameter is a combination 2 fields(field1 | field2):
<> 144:ef7eb2e8f9f7 1964 *
<> 144:ef7eb2e8f9f7 1965 * field1 can have the following values:
<> 144:ef7eb2e8f9f7 1966 * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
<> 144:ef7eb2e8f9f7 1967 * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
<> 144:ef7eb2e8f9f7 1968 * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
<> 144:ef7eb2e8f9f7 1969 * @arg TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
<> 144:ef7eb2e8f9f7 1970 *
<> 144:ef7eb2e8f9f7 1971 * field2 can have the following values:
<> 144:ef7eb2e8f9f7 1972 * @arg TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO
<> 144:ef7eb2e8f9f7 1973 * @arg TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output
<> 144:ef7eb2e8f9f7 1974 *
<> 144:ef7eb2e8f9f7 1975 @endif
<> 144:ef7eb2e8f9f7 1976 @if STM32L486xx
<> 144:ef7eb2e8f9f7 1977 * For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3):
<> 144:ef7eb2e8f9f7 1978 *
<> 144:ef7eb2e8f9f7 1979 * field1 can have the following values:
<> 144:ef7eb2e8f9f7 1980 * @arg TIM_TIM8_ETR_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD (analog watchdog)
<> 144:ef7eb2e8f9f7 1981 * @arg TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
<> 144:ef7eb2e8f9f7 1982 * @arg TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
<> 144:ef7eb2e8f9f7 1983 * @arg TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
<> 144:ef7eb2e8f9f7 1984 *
<> 144:ef7eb2e8f9f7 1985 * field2 can have the following values:
<> 144:ef7eb2e8f9f7 1986 * @arg TIM_TIM8_ETR_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD (analog watchdog)
<> 144:ef7eb2e8f9f7 1987 * @arg TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
<> 144:ef7eb2e8f9f7 1988 * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
<> 144:ef7eb2e8f9f7 1989 * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
<> 144:ef7eb2e8f9f7 1990 *
<> 144:ef7eb2e8f9f7 1991 * field3 can have the following values:
<> 144:ef7eb2e8f9f7 1992 * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
<> 144:ef7eb2e8f9f7 1993 * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
<> 144:ef7eb2e8f9f7 1994 *
<> 144:ef7eb2e8f9f7 1995 * field4 can have the following values:
<> 144:ef7eb2e8f9f7 1996 * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output
<> 144:ef7eb2e8f9f7 1997 * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output
<> 144:ef7eb2e8f9f7 1998 * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant
<> 144:ef7eb2e8f9f7 1999 *
<> 144:ef7eb2e8f9f7 2000 @endif
<> 144:ef7eb2e8f9f7 2001 * For TIM15, the parameter is a combination of 3 fields (field1 | field2):
<> 144:ef7eb2e8f9f7 2002 *
<> 144:ef7eb2e8f9f7 2003 * field1 can have the following values:
<> 144:ef7eb2e8f9f7 2004 * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
<> 144:ef7eb2e8f9f7 2005 * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
<> 144:ef7eb2e8f9f7 2006 *
<> 144:ef7eb2e8f9f7 2007 * field2 can have the following values:
<> 144:ef7eb2e8f9f7 2008 * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection
<> 144:ef7eb2e8f9f7 2009 * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
<> 144:ef7eb2e8f9f7 2010 * @arg TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
<> 144:ef7eb2e8f9f7 2011 * @arg TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
<> 144:ef7eb2e8f9f7 2012 *
<> 144:ef7eb2e8f9f7 2013 @if STM32L486xx
<> 144:ef7eb2e8f9f7 2014 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
<> 144:ef7eb2e8f9f7 2015 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
<> 144:ef7eb2e8f9f7 2016 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
<> 144:ef7eb2e8f9f7 2017 * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
<> 144:ef7eb2e8f9f7 2018 *
<> 144:ef7eb2e8f9f7 2019 @endif
<> 144:ef7eb2e8f9f7 2020 @if STM32L443xx
<> 144:ef7eb2e8f9f7 2021 * For TIM16, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 2022 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
<> 144:ef7eb2e8f9f7 2023 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
<> 144:ef7eb2e8f9f7 2024 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
<> 144:ef7eb2e8f9f7 2025 * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
<> 144:ef7eb2e8f9f7 2026 * @arg TIM_TIM16_TI1_MSI: TIM16 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock)
<> 144:ef7eb2e8f9f7 2027 * @arg TIM_TIM16_TI1_HSE_32: TIM16 TI1 is connected to HSE div 32 (note that HSE div 32 must be selected as RTC clock source)
<> 144:ef7eb2e8f9f7 2028 * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO
<> 144:ef7eb2e8f9f7 2029 *
<> 144:ef7eb2e8f9f7 2030 @endif
<> 144:ef7eb2e8f9f7 2031 @if STM32L486xx
<> 144:ef7eb2e8f9f7 2032 * For TIM17, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 2033 * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
<> 144:ef7eb2e8f9f7 2034 * @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock)
<> 144:ef7eb2e8f9f7 2035 * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32
<> 144:ef7eb2e8f9f7 2036 * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
<> 144:ef7eb2e8f9f7 2037 @endif
<> 144:ef7eb2e8f9f7 2038 *
<> 144:ef7eb2e8f9f7 2039 * @retval HAL status
<> 144:ef7eb2e8f9f7 2040 */
<> 144:ef7eb2e8f9f7 2041 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
<> 144:ef7eb2e8f9f7 2042 {
<> 144:ef7eb2e8f9f7 2043 uint32_t tmpor1 = 0;
<> 144:ef7eb2e8f9f7 2044 uint32_t tmpor2 = 0;
<> 144:ef7eb2e8f9f7 2045
<> 144:ef7eb2e8f9f7 2046 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2047
<> 144:ef7eb2e8f9f7 2048 /* Check parameters */
<> 144:ef7eb2e8f9f7 2049 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2050 assert_param(IS_TIM_REMAP(Remap));
<> 144:ef7eb2e8f9f7 2051
<> 144:ef7eb2e8f9f7 2052 /* Set ETR_SEL bit field (if required) */
<> 144:ef7eb2e8f9f7 2053 if (IS_TIM_ETRSEL_INSTANCE(htim->Instance))
<> 144:ef7eb2e8f9f7 2054 {
<> 144:ef7eb2e8f9f7 2055 tmpor2 = htim->Instance->OR2;
<> 144:ef7eb2e8f9f7 2056 tmpor2 &= ~TIMx_ETRSEL_MASK;
<> 144:ef7eb2e8f9f7 2057 tmpor2 |= (Remap & TIMx_ETRSEL_MASK);
<> 144:ef7eb2e8f9f7 2058
<> 144:ef7eb2e8f9f7 2059 /* Set TIMx_OR2 */
<> 144:ef7eb2e8f9f7 2060 htim->Instance->OR2 = tmpor2;
<> 144:ef7eb2e8f9f7 2061 }
<> 144:ef7eb2e8f9f7 2062
<> 144:ef7eb2e8f9f7 2063 /* Set other remapping capabilities */
<> 144:ef7eb2e8f9f7 2064 tmpor1 = Remap;
<> 144:ef7eb2e8f9f7 2065 tmpor1 &= ~TIMx_ETRSEL_MASK;
<> 144:ef7eb2e8f9f7 2066
<> 144:ef7eb2e8f9f7 2067 /* Set TIMx_OR1 */
<> 144:ef7eb2e8f9f7 2068 htim->Instance->OR1 = Remap;
<> 144:ef7eb2e8f9f7 2069
<> 144:ef7eb2e8f9f7 2070 /* Set TIMx_OR1 */
<> 144:ef7eb2e8f9f7 2071 htim->Instance->OR1 = tmpor1;
<> 144:ef7eb2e8f9f7 2072
<> 144:ef7eb2e8f9f7 2073 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2074
<> 144:ef7eb2e8f9f7 2075 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2076
<> 144:ef7eb2e8f9f7 2077 return HAL_OK;
<> 144:ef7eb2e8f9f7 2078 }
<> 144:ef7eb2e8f9f7 2079
<> 144:ef7eb2e8f9f7 2080 /**
<> 144:ef7eb2e8f9f7 2081 * @brief Group channel 5 and channel 1, 2 or 3
<> 144:ef7eb2e8f9f7 2082 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 2083 * @param Channels: specifies the reference signal(s) the OC5REF is combined with.
<> 144:ef7eb2e8f9f7 2084 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 2085 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
<> 144:ef7eb2e8f9f7 2086 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
<> 144:ef7eb2e8f9f7 2087 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
<> 144:ef7eb2e8f9f7 2088 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
<> 144:ef7eb2e8f9f7 2089 * @retval HAL status
<> 144:ef7eb2e8f9f7 2090 */
<> 144:ef7eb2e8f9f7 2091 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
<> 144:ef7eb2e8f9f7 2092 {
<> 144:ef7eb2e8f9f7 2093 /* Check parameters */
<> 144:ef7eb2e8f9f7 2094 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2095 assert_param(IS_TIM_GROUPCH5(Channels));
<> 144:ef7eb2e8f9f7 2096
<> 144:ef7eb2e8f9f7 2097 /* Process Locked */
<> 144:ef7eb2e8f9f7 2098 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2099
<> 144:ef7eb2e8f9f7 2100 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2101
<> 144:ef7eb2e8f9f7 2102 /* Clear GC5Cx bit fields */
<> 144:ef7eb2e8f9f7 2103 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
<> 144:ef7eb2e8f9f7 2104
<> 144:ef7eb2e8f9f7 2105 /* Set GC5Cx bit fields */
<> 144:ef7eb2e8f9f7 2106 htim->Instance->CCR5 |= Channels;
<> 144:ef7eb2e8f9f7 2107
<> 144:ef7eb2e8f9f7 2108 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2109
<> 144:ef7eb2e8f9f7 2110 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2111
<> 144:ef7eb2e8f9f7 2112 return HAL_OK;
<> 144:ef7eb2e8f9f7 2113 }
<> 144:ef7eb2e8f9f7 2114
<> 144:ef7eb2e8f9f7 2115 /**
<> 144:ef7eb2e8f9f7 2116 * @}
<> 144:ef7eb2e8f9f7 2117 */
<> 144:ef7eb2e8f9f7 2118
<> 144:ef7eb2e8f9f7 2119 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
<> 144:ef7eb2e8f9f7 2120 * @brief Extended Callbacks functions
<> 144:ef7eb2e8f9f7 2121 *
<> 144:ef7eb2e8f9f7 2122 @verbatim
<> 144:ef7eb2e8f9f7 2123 ==============================================================================
<> 144:ef7eb2e8f9f7 2124 ##### Extended Callbacks functions #####
<> 144:ef7eb2e8f9f7 2125 ==============================================================================
<> 144:ef7eb2e8f9f7 2126 [..]
<> 144:ef7eb2e8f9f7 2127 This section provides Extended TIM callback functions:
<> 144:ef7eb2e8f9f7 2128 (+) Timer Commutation callback
<> 144:ef7eb2e8f9f7 2129 (+) Timer Break callback
<> 144:ef7eb2e8f9f7 2130
<> 144:ef7eb2e8f9f7 2131 @endverbatim
<> 144:ef7eb2e8f9f7 2132 * @{
<> 144:ef7eb2e8f9f7 2133 */
<> 144:ef7eb2e8f9f7 2134
<> 144:ef7eb2e8f9f7 2135 /**
<> 144:ef7eb2e8f9f7 2136 * @brief Hall commutation changed callback in non-blocking mode
<> 144:ef7eb2e8f9f7 2137 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2138 * @retval None
<> 144:ef7eb2e8f9f7 2139 */
<> 144:ef7eb2e8f9f7 2140 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2141 {
<> 144:ef7eb2e8f9f7 2142 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2143 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2144
<> 144:ef7eb2e8f9f7 2145 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2146 the HAL_TIMEx_CommutationCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 2147 */
<> 144:ef7eb2e8f9f7 2148 }
<> 144:ef7eb2e8f9f7 2149
<> 144:ef7eb2e8f9f7 2150 /**
<> 144:ef7eb2e8f9f7 2151 * @brief Hall Break detection callback in non-blocking mode
<> 144:ef7eb2e8f9f7 2152 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 2153 * @retval None
<> 144:ef7eb2e8f9f7 2154 */
<> 144:ef7eb2e8f9f7 2155 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2156 {
<> 144:ef7eb2e8f9f7 2157 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2158 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2159
<> 144:ef7eb2e8f9f7 2160 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2161 the HAL_TIMEx_BreakCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 2162 */
<> 144:ef7eb2e8f9f7 2163 }
<> 144:ef7eb2e8f9f7 2164
<> 144:ef7eb2e8f9f7 2165 /**
<> 144:ef7eb2e8f9f7 2166 * @}
<> 144:ef7eb2e8f9f7 2167 */
<> 144:ef7eb2e8f9f7 2168
<> 144:ef7eb2e8f9f7 2169 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
<> 144:ef7eb2e8f9f7 2170 * @brief Extended Peripheral State functions
<> 144:ef7eb2e8f9f7 2171 *
<> 144:ef7eb2e8f9f7 2172 @verbatim
<> 144:ef7eb2e8f9f7 2173 ==============================================================================
<> 144:ef7eb2e8f9f7 2174 ##### Extended Peripheral State functions #####
<> 144:ef7eb2e8f9f7 2175 ==============================================================================
<> 144:ef7eb2e8f9f7 2176 [..]
<> 144:ef7eb2e8f9f7 2177 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 2178 and the data flow.
<> 144:ef7eb2e8f9f7 2179
<> 144:ef7eb2e8f9f7 2180 @endverbatim
<> 144:ef7eb2e8f9f7 2181 * @{
<> 144:ef7eb2e8f9f7 2182 */
<> 144:ef7eb2e8f9f7 2183
<> 144:ef7eb2e8f9f7 2184 /**
<> 144:ef7eb2e8f9f7 2185 * @brief Return the TIM Hall Sensor interface handle state.
<> 144:ef7eb2e8f9f7 2186 * @param htim: TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 2187 * @retval HAL state
<> 144:ef7eb2e8f9f7 2188 */
<> 144:ef7eb2e8f9f7 2189 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2190 {
<> 144:ef7eb2e8f9f7 2191 return htim->State;
<> 144:ef7eb2e8f9f7 2192 }
<> 144:ef7eb2e8f9f7 2193
<> 144:ef7eb2e8f9f7 2194 /**
<> 144:ef7eb2e8f9f7 2195 * @}
<> 144:ef7eb2e8f9f7 2196 */
<> 144:ef7eb2e8f9f7 2197
<> 144:ef7eb2e8f9f7 2198 /**
<> 144:ef7eb2e8f9f7 2199 * @brief TIM DMA Commutation callback.
<> 144:ef7eb2e8f9f7 2200 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 2201 * @retval None
<> 144:ef7eb2e8f9f7 2202 */
<> 144:ef7eb2e8f9f7 2203 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2204 {
<> 144:ef7eb2e8f9f7 2205 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2206
<> 144:ef7eb2e8f9f7 2207 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2208
<> 144:ef7eb2e8f9f7 2209 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 2210 }
<> 144:ef7eb2e8f9f7 2211
<> 144:ef7eb2e8f9f7 2212 /**
<> 144:ef7eb2e8f9f7 2213 * @brief Enables or disables the TIM Capture Compare Channel xN.
<> 144:ef7eb2e8f9f7 2214 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 2215 * @param Channel: specifies the TIM Channel
<> 144:ef7eb2e8f9f7 2216 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2217 * @arg TIM_Channel_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 2218 * @arg TIM_Channel_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 2219 * @arg TIM_Channel_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 2220 * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
<> 144:ef7eb2e8f9f7 2221 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
<> 144:ef7eb2e8f9f7 2222 * @retval None
<> 144:ef7eb2e8f9f7 2223 */
<> 144:ef7eb2e8f9f7 2224 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
<> 144:ef7eb2e8f9f7 2225 {
<> 144:ef7eb2e8f9f7 2226 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 2227
<> 144:ef7eb2e8f9f7 2228 tmp = TIM_CCER_CC1NE << Channel;
<> 144:ef7eb2e8f9f7 2229
<> 144:ef7eb2e8f9f7 2230 /* Reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 2231 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 2232
<> 144:ef7eb2e8f9f7 2233 /* Set or reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 2234 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
<> 144:ef7eb2e8f9f7 2235 }
<> 144:ef7eb2e8f9f7 2236
<> 144:ef7eb2e8f9f7 2237 /**
<> 144:ef7eb2e8f9f7 2238 * @}
<> 144:ef7eb2e8f9f7 2239 */
<> 144:ef7eb2e8f9f7 2240
<> 144:ef7eb2e8f9f7 2241 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2242 /**
<> 144:ef7eb2e8f9f7 2243 * @}
<> 144:ef7eb2e8f9f7 2244 */
<> 144:ef7eb2e8f9f7 2245
<> 144:ef7eb2e8f9f7 2246 /**
<> 144:ef7eb2e8f9f7 2247 * @}
<> 144:ef7eb2e8f9f7 2248 */
<> 144:ef7eb2e8f9f7 2249
<> 144:ef7eb2e8f9f7 2250 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/