mbed library sources. Supersedes mbed-src.
Fork of mbed-dev by
Diff: targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h
- Revision:
- 181:96ed750bd169
- Parent:
- 156:95d6b41a828b
--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h Thu Dec 07 14:01:42 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h Wed Jan 17 15:23:54 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -600,14 +598,14 @@ typedef struct { uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. - This parameter must be a number between 0 and 0xFFFF */ + This parameter must be a number between 0 and 0xFFFFU */ uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. - This parameter must be a number between 0 and 0x3F */ + This parameter must be a number between 0 and 0x3FU */ uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. - This parameter must be a number between 0 and 0xFFFF */ + This parameter must be a number between 0 and 0xFFFFU */ uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the frequency error counter latched in the time of the last SYNC event. @@ -839,7 +837,7 @@ /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source * @{ */ -#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */ #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ /** @@ -849,7 +847,7 @@ /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider * @{ */ -#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ @@ -864,7 +862,7 @@ /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity * @{ */ -#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ /** * @} @@ -873,7 +871,7 @@ /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value * @{ */ -#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds +#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ /** * @} @@ -882,7 +880,7 @@ /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value * @{ */ -#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */ +#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ /** * @} */ @@ -890,7 +888,7 @@ /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. +#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency */ /** @@ -900,7 +898,7 @@ /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction * @{ */ -#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ /** * @} @@ -962,7 +960,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) @@ -976,7 +974,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) @@ -993,7 +991,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) @@ -1010,7 +1008,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) @@ -1033,7 +1031,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) @@ -1054,7 +1052,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) @@ -1075,7 +1073,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) @@ -1096,14 +1094,14 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) @@ -1123,7 +1121,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) @@ -1142,7 +1140,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) @@ -1160,21 +1158,21 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) @@ -1192,7 +1190,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) @@ -1208,7 +1206,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ @@ -1222,7 +1220,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) @@ -1236,7 +1234,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) @@ -1258,7 +1256,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) @@ -1275,7 +1273,7 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) @@ -1289,14 +1287,14 @@ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART8_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) #define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) @@ -1942,7 +1940,7 @@ { \ WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ } \ - } while(0) + } while(0U) /** * @brief Check whether the specified CRS flag is set or not. @@ -1982,7 +1980,7 @@ { \ WRITE_REG(CRS->ICR, (__FLAG__)); \ } \ - } while(0) + } while(0U) /** * @}