Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
83:a036322b8637 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_eth.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief ETH HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Ethernet (ETH) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 21 ETH_HandleTypeDef heth;
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#)Fill parameters of Init structure in heth handle
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
<> 144:ef7eb2e8f9f7 28 (##) Enable the Ethernet interface clock using
<> 144:ef7eb2e8f9f7 29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 (##) Initialize the related GPIO clocks
<> 144:ef7eb2e8f9f7 34 (##) Configure Ethernet pin-out
<> 144:ef7eb2e8f9f7 35 (##) Configure Ethernet NVIC interrupt (IT mode)
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
<> 144:ef7eb2e8f9f7 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
<> 144:ef7eb2e8f9f7 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#)Enable MAC and DMA transmission and reception:
<> 144:ef7eb2e8f9f7 42 (##) HAL_ETH_Start();
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
<> 144:ef7eb2e8f9f7 45 the frame to MAC TX FIFO:
<> 144:ef7eb2e8f9f7 46 (##) HAL_ETH_TransmitFrame();
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
<> 144:ef7eb2e8f9f7 49 frame parameters
<> 144:ef7eb2e8f9f7 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 (#) Get a received frame when an ETH RX interrupt occurs:
<> 144:ef7eb2e8f9f7 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 (#) Communicate with external PHY device:
<> 144:ef7eb2e8f9f7 56 (##) Read a specific register from the PHY
<> 144:ef7eb2e8f9f7 57 HAL_ETH_ReadPHYRegister();
<> 144:ef7eb2e8f9f7 58 (##) Write data to a specific RHY register:
<> 144:ef7eb2e8f9f7 59 HAL_ETH_WritePHYRegister();
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
<> 144:ef7eb2e8f9f7 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
<> 144:ef7eb2e8f9f7 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 @endverbatim
<> 144:ef7eb2e8f9f7 68 ******************************************************************************
<> 144:ef7eb2e8f9f7 69 * @attention
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 74 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 75 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 76 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 78 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 79 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 81 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 82 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 83 *
<> 144:ef7eb2e8f9f7 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 ******************************************************************************
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @defgroup ETH ETH
<> 144:ef7eb2e8f9f7 106 * @brief ETH HAL module driver
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #ifdef HAL_ETH_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 113 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 /** @defgroup ETH_Private_Constants ETH Private Constants
<> 144:ef7eb2e8f9f7 115 * @{
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117 #define ETH_TIMEOUT_SWRESET ((uint32_t)500)
<> 144:ef7eb2e8f9f7 118 #define ETH_TIMEOUT_LINKED_STATE ((uint32_t)5000)
<> 144:ef7eb2e8f9f7 119 #define ETH_TIMEOUT_AUTONEGO_COMPLETED ((uint32_t)5000)
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /**
<> 144:ef7eb2e8f9f7 122 * @}
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 125 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 126 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 127 /** @defgroup ETH_Private_Functions ETH Private Functions
<> 144:ef7eb2e8f9f7 128 * @{
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
<> 144:ef7eb2e8f9f7 131 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
<> 144:ef7eb2e8f9f7 132 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 133 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 134 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 135 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 136 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 137 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 138 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 139 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 140 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @}
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /** @defgroup ETH_Exported_Functions ETH Exported Functions
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 152 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 153 *
<> 144:ef7eb2e8f9f7 154 @verbatim
<> 144:ef7eb2e8f9f7 155 ===============================================================================
<> 144:ef7eb2e8f9f7 156 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 157 ===============================================================================
<> 144:ef7eb2e8f9f7 158 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 159 (+) Initialize and configure the Ethernet peripheral
<> 144:ef7eb2e8f9f7 160 (+) De-initialize the Ethernet peripheral
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 @endverbatim
<> 144:ef7eb2e8f9f7 163 * @{
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @brief Initializes the Ethernet MAC and DMA according to default
<> 144:ef7eb2e8f9f7 168 * parameters.
<> 144:ef7eb2e8f9f7 169 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 170 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 171 * @retval HAL status
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 174 {
<> 144:ef7eb2e8f9f7 175 uint32_t tempreg = 0, phyreg = 0;
<> 144:ef7eb2e8f9f7 176 uint32_t hclk = 60000000;
<> 144:ef7eb2e8f9f7 177 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 178 uint32_t err = ETH_SUCCESS;
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Check the ETH peripheral state */
<> 144:ef7eb2e8f9f7 181 if(heth == NULL)
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Check parameters */
<> 144:ef7eb2e8f9f7 187 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
<> 144:ef7eb2e8f9f7 188 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
<> 144:ef7eb2e8f9f7 189 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
<> 144:ef7eb2e8f9f7 190 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 if(heth->State == HAL_ETH_STATE_RESET)
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 195 heth->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 196 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
<> 144:ef7eb2e8f9f7 197 HAL_ETH_MspInit(heth);
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* Enable SYSCFG Clock */
<> 144:ef7eb2e8f9f7 201 __HAL_RCC_SYSCFG_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Select MII or RMII Mode*/
<> 144:ef7eb2e8f9f7 204 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
<> 144:ef7eb2e8f9f7 205 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Ethernet Software reset */
<> 144:ef7eb2e8f9f7 208 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
<> 144:ef7eb2e8f9f7 209 /* After reset all the registers holds their respective reset values */
<> 144:ef7eb2e8f9f7 210 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* Get tick */
<> 144:ef7eb2e8f9f7 213 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /* Wait for software reset */
<> 144:ef7eb2e8f9f7 216 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
<> 144:ef7eb2e8f9f7 217 {
<> 144:ef7eb2e8f9f7 218 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 219 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 heth->State= HAL_ETH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 224 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
<> 144:ef7eb2e8f9f7 227 not available, please check your external PHY or the IO configuration */
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /*-------------------------------- MAC Initialization ----------------------*/
<> 144:ef7eb2e8f9f7 234 /* Get the ETHERNET MACMIIAR value */
<> 144:ef7eb2e8f9f7 235 tempreg = (heth->Instance)->MACMIIAR;
<> 144:ef7eb2e8f9f7 236 /* Clear CSR Clock Range CR[2:0] bits */
<> 144:ef7eb2e8f9f7 237 tempreg &= ETH_MACMIIAR_CR_MASK;
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Get hclk frequency value */
<> 144:ef7eb2e8f9f7 240 hclk = HAL_RCC_GetHCLKFreq();
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Set CR bits depending on hclk value */
<> 144:ef7eb2e8f9f7 243 if((hclk >= 20000000)&&(hclk < 35000000))
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 /* CSR Clock Range between 20-35 MHz */
<> 144:ef7eb2e8f9f7 246 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
<> 144:ef7eb2e8f9f7 247 }
<> 144:ef7eb2e8f9f7 248 else if((hclk >= 35000000)&&(hclk < 60000000))
<> 144:ef7eb2e8f9f7 249 {
<> 144:ef7eb2e8f9f7 250 /* CSR Clock Range between 35-60 MHz */
<> 144:ef7eb2e8f9f7 251 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253 else if((hclk >= 60000000)&&(hclk < 100000000))
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 /* CSR Clock Range between 60-100 MHz */
<> 144:ef7eb2e8f9f7 256 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258 else if((hclk >= 100000000)&&(hclk < 150000000))
<> 144:ef7eb2e8f9f7 259 {
<> 144:ef7eb2e8f9f7 260 /* CSR Clock Range between 100-150 MHz */
<> 144:ef7eb2e8f9f7 261 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263 else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */
<> 144:ef7eb2e8f9f7 264 {
<> 144:ef7eb2e8f9f7 265 /* CSR Clock Range between 150-216 MHz */
<> 144:ef7eb2e8f9f7 266 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
<> 144:ef7eb2e8f9f7 267 }
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
<> 144:ef7eb2e8f9f7 270 (heth->Instance)->MACMIIAR = (uint32_t)tempreg;
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /*-------------------- PHY initialization and configuration ----------------*/
<> 144:ef7eb2e8f9f7 273 /* Put the PHY in reset mode */
<> 144:ef7eb2e8f9f7 274 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 /* In case of write timeout */
<> 144:ef7eb2e8f9f7 277 err = ETH_ERROR;
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Config MAC and DMA */
<> 144:ef7eb2e8f9f7 280 ETH_MACDMAConfig(heth, err);
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Set the ETH peripheral state to READY */
<> 144:ef7eb2e8f9f7 283 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* Return HAL_ERROR */
<> 144:ef7eb2e8f9f7 286 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* Delay to assure PHY reset */
<> 144:ef7eb2e8f9f7 290 HAL_Delay(PHY_RESET_DELAY);
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
<> 144:ef7eb2e8f9f7 293 {
<> 144:ef7eb2e8f9f7 294 /* Get tick */
<> 144:ef7eb2e8f9f7 295 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* We wait for linked status */
<> 144:ef7eb2e8f9f7 298 do
<> 144:ef7eb2e8f9f7 299 {
<> 144:ef7eb2e8f9f7 300 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 303 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 /* In case of write timeout */
<> 144:ef7eb2e8f9f7 306 err = ETH_ERROR;
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Config MAC and DMA */
<> 144:ef7eb2e8f9f7 309 ETH_MACDMAConfig(heth, err);
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 heth->State= HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 314 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Enable Auto-Negotiation */
<> 144:ef7eb2e8f9f7 322 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 /* In case of write timeout */
<> 144:ef7eb2e8f9f7 325 err = ETH_ERROR;
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Config MAC and DMA */
<> 144:ef7eb2e8f9f7 328 ETH_MACDMAConfig(heth, err);
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* Set the ETH peripheral state to READY */
<> 144:ef7eb2e8f9f7 331 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Return HAL_ERROR */
<> 144:ef7eb2e8f9f7 334 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /* Get tick */
<> 144:ef7eb2e8f9f7 338 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Wait until the auto-negotiation will be completed */
<> 144:ef7eb2e8f9f7 341 do
<> 144:ef7eb2e8f9f7 342 {
<> 144:ef7eb2e8f9f7 343 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 346 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 /* In case of write timeout */
<> 144:ef7eb2e8f9f7 349 err = ETH_ERROR;
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Config MAC and DMA */
<> 144:ef7eb2e8f9f7 352 ETH_MACDMAConfig(heth, err);
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 heth->State= HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 357 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Read the result of the auto-negotiation */
<> 144:ef7eb2e8f9f7 365 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
<> 144:ef7eb2e8f9f7 366 {
<> 144:ef7eb2e8f9f7 367 /* In case of write timeout */
<> 144:ef7eb2e8f9f7 368 err = ETH_ERROR;
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Config MAC and DMA */
<> 144:ef7eb2e8f9f7 371 ETH_MACDMAConfig(heth, err);
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* Set the ETH peripheral state to READY */
<> 144:ef7eb2e8f9f7 374 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Return HAL_ERROR */
<> 144:ef7eb2e8f9f7 377 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
<> 144:ef7eb2e8f9f7 381 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
<> 144:ef7eb2e8f9f7 382 {
<> 144:ef7eb2e8f9f7 383 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
<> 144:ef7eb2e8f9f7 384 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
<> 144:ef7eb2e8f9f7 385 }
<> 144:ef7eb2e8f9f7 386 else
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
<> 144:ef7eb2e8f9f7 389 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
<> 144:ef7eb2e8f9f7 390 }
<> 144:ef7eb2e8f9f7 391 /* Configure the MAC with the speed fixed by the auto-negotiation process */
<> 144:ef7eb2e8f9f7 392 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
<> 144:ef7eb2e8f9f7 393 {
<> 144:ef7eb2e8f9f7 394 /* Set Ethernet speed to 10M following the auto-negotiation */
<> 144:ef7eb2e8f9f7 395 (heth->Init).Speed = ETH_SPEED_10M;
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397 else
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 /* Set Ethernet speed to 100M following the auto-negotiation */
<> 144:ef7eb2e8f9f7 400 (heth->Init).Speed = ETH_SPEED_100M;
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403 else /* AutoNegotiation Disable */
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 /* Check parameters */
<> 144:ef7eb2e8f9f7 406 assert_param(IS_ETH_SPEED(heth->Init.Speed));
<> 144:ef7eb2e8f9f7 407 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Set MAC Speed and Duplex Mode */
<> 144:ef7eb2e8f9f7 410 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
<> 144:ef7eb2e8f9f7 411 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
<> 144:ef7eb2e8f9f7 412 {
<> 144:ef7eb2e8f9f7 413 /* In case of write timeout */
<> 144:ef7eb2e8f9f7 414 err = ETH_ERROR;
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Config MAC and DMA */
<> 144:ef7eb2e8f9f7 417 ETH_MACDMAConfig(heth, err);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Set the ETH peripheral state to READY */
<> 144:ef7eb2e8f9f7 420 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Return HAL_ERROR */
<> 144:ef7eb2e8f9f7 423 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 424 }
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /* Delay to assure PHY configuration */
<> 144:ef7eb2e8f9f7 427 HAL_Delay(PHY_CONFIG_DELAY);
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Config MAC and DMA */
<> 144:ef7eb2e8f9f7 431 ETH_MACDMAConfig(heth, err);
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /* Set ETH HAL State to Ready */
<> 144:ef7eb2e8f9f7 434 heth->State= HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /* Return function status */
<> 144:ef7eb2e8f9f7 437 return HAL_OK;
<> 144:ef7eb2e8f9f7 438 }
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /**
<> 144:ef7eb2e8f9f7 441 * @brief De-Initializes the ETH peripheral.
<> 144:ef7eb2e8f9f7 442 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 443 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 444 * @retval HAL status
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 447 {
<> 144:ef7eb2e8f9f7 448 /* Set the ETH peripheral state to BUSY */
<> 144:ef7eb2e8f9f7 449 heth->State = HAL_ETH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
<> 144:ef7eb2e8f9f7 452 HAL_ETH_MspDeInit(heth);
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Set ETH HAL state to Disabled */
<> 144:ef7eb2e8f9f7 455 heth->State= HAL_ETH_STATE_RESET;
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /* Release Lock */
<> 144:ef7eb2e8f9f7 458 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* Return function status */
<> 144:ef7eb2e8f9f7 461 return HAL_OK;
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /**
<> 144:ef7eb2e8f9f7 465 * @brief Initializes the DMA Tx descriptors in chain mode.
<> 144:ef7eb2e8f9f7 466 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 467 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 468 * @param DMATxDescTab: Pointer to the first Tx desc list
<> 144:ef7eb2e8f9f7 469 * @param TxBuff: Pointer to the first TxBuffer list
<> 144:ef7eb2e8f9f7 470 * @param TxBuffCount: Number of the used Tx desc in the list
<> 144:ef7eb2e8f9f7 471 * @retval HAL status
<> 144:ef7eb2e8f9f7 472 */
<> 144:ef7eb2e8f9f7 473 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
<> 144:ef7eb2e8f9f7 474 {
<> 144:ef7eb2e8f9f7 475 uint32_t i = 0;
<> 144:ef7eb2e8f9f7 476 ETH_DMADescTypeDef *dmatxdesc;
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /* Process Locked */
<> 144:ef7eb2e8f9f7 479 __HAL_LOCK(heth);
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /* Set the ETH peripheral state to BUSY */
<> 144:ef7eb2e8f9f7 482 heth->State = HAL_ETH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
<> 144:ef7eb2e8f9f7 485 heth->TxDesc = DMATxDescTab;
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* Fill each DMATxDesc descriptor with the right values */
<> 144:ef7eb2e8f9f7 488 for(i=0; i < TxBuffCount; i++)
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 /* Get the pointer on the ith member of the Tx Desc list */
<> 144:ef7eb2e8f9f7 491 dmatxdesc = DMATxDescTab + i;
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /* Set Second Address Chained bit */
<> 144:ef7eb2e8f9f7 494 dmatxdesc->Status = ETH_DMATXDESC_TCH;
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /* Set Buffer1 address pointer */
<> 144:ef7eb2e8f9f7 497 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
<> 144:ef7eb2e8f9f7 500 {
<> 144:ef7eb2e8f9f7 501 /* Set the DMA Tx descriptors checksum insertion */
<> 144:ef7eb2e8f9f7 502 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
<> 144:ef7eb2e8f9f7 503 }
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
<> 144:ef7eb2e8f9f7 506 if(i < (TxBuffCount-1))
<> 144:ef7eb2e8f9f7 507 {
<> 144:ef7eb2e8f9f7 508 /* Set next descriptor address register with next descriptor base address */
<> 144:ef7eb2e8f9f7 509 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511 else
<> 144:ef7eb2e8f9f7 512 {
<> 144:ef7eb2e8f9f7 513 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
<> 144:ef7eb2e8f9f7 514 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516 }
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /* Set Transmit Descriptor List Address Register */
<> 144:ef7eb2e8f9f7 519 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /* Set ETH HAL State to Ready */
<> 144:ef7eb2e8f9f7 522 heth->State= HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 525 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Return function status */
<> 144:ef7eb2e8f9f7 528 return HAL_OK;
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /**
<> 144:ef7eb2e8f9f7 532 * @brief Initializes the DMA Rx descriptors in chain mode.
<> 144:ef7eb2e8f9f7 533 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 534 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 535 * @param DMARxDescTab: Pointer to the first Rx desc list
<> 144:ef7eb2e8f9f7 536 * @param RxBuff: Pointer to the first RxBuffer list
<> 144:ef7eb2e8f9f7 537 * @param RxBuffCount: Number of the used Rx desc in the list
<> 144:ef7eb2e8f9f7 538 * @retval HAL status
<> 144:ef7eb2e8f9f7 539 */
<> 144:ef7eb2e8f9f7 540 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
<> 144:ef7eb2e8f9f7 541 {
<> 144:ef7eb2e8f9f7 542 uint32_t i = 0;
<> 144:ef7eb2e8f9f7 543 ETH_DMADescTypeDef *DMARxDesc;
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /* Process Locked */
<> 144:ef7eb2e8f9f7 546 __HAL_LOCK(heth);
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /* Set the ETH peripheral state to BUSY */
<> 144:ef7eb2e8f9f7 549 heth->State = HAL_ETH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
<> 144:ef7eb2e8f9f7 552 heth->RxDesc = DMARxDescTab;
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /* Fill each DMARxDesc descriptor with the right values */
<> 144:ef7eb2e8f9f7 555 for(i=0; i < RxBuffCount; i++)
<> 144:ef7eb2e8f9f7 556 {
<> 144:ef7eb2e8f9f7 557 /* Get the pointer on the ith member of the Rx Desc list */
<> 144:ef7eb2e8f9f7 558 DMARxDesc = DMARxDescTab+i;
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* Set Own bit of the Rx descriptor Status */
<> 144:ef7eb2e8f9f7 561 DMARxDesc->Status = ETH_DMARXDESC_OWN;
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /* Set Buffer1 size and Second Address Chained bit */
<> 144:ef7eb2e8f9f7 564 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /* Set Buffer1 address pointer */
<> 144:ef7eb2e8f9f7 567 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 /* Enable Ethernet DMA Rx Descriptor interrupt */
<> 144:ef7eb2e8f9f7 572 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
<> 144:ef7eb2e8f9f7 576 if(i < (RxBuffCount-1))
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 /* Set next descriptor address register with next descriptor base address */
<> 144:ef7eb2e8f9f7 579 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
<> 144:ef7eb2e8f9f7 580 }
<> 144:ef7eb2e8f9f7 581 else
<> 144:ef7eb2e8f9f7 582 {
<> 144:ef7eb2e8f9f7 583 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
<> 144:ef7eb2e8f9f7 584 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /* Set Receive Descriptor List Address Register */
<> 144:ef7eb2e8f9f7 589 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Set ETH HAL State to Ready */
<> 144:ef7eb2e8f9f7 592 heth->State= HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 595 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /* Return function status */
<> 144:ef7eb2e8f9f7 598 return HAL_OK;
<> 144:ef7eb2e8f9f7 599 }
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /**
<> 144:ef7eb2e8f9f7 602 * @brief Initializes the ETH MSP.
<> 144:ef7eb2e8f9f7 603 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 604 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 605 * @retval None
<> 144:ef7eb2e8f9f7 606 */
<> 144:ef7eb2e8f9f7 607 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 608 {
<> 144:ef7eb2e8f9f7 609 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 610 UNUSED(heth);
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 613 the HAL_ETH_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 614 */
<> 144:ef7eb2e8f9f7 615 }
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /**
<> 144:ef7eb2e8f9f7 618 * @brief DeInitializes ETH MSP.
<> 144:ef7eb2e8f9f7 619 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 620 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 621 * @retval None
<> 144:ef7eb2e8f9f7 622 */
<> 144:ef7eb2e8f9f7 623 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 626 UNUSED(heth);
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 629 the HAL_ETH_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631 }
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /**
<> 144:ef7eb2e8f9f7 634 * @}
<> 144:ef7eb2e8f9f7 635 */
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 638 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 639 *
<> 144:ef7eb2e8f9f7 640 @verbatim
<> 144:ef7eb2e8f9f7 641 ==============================================================================
<> 144:ef7eb2e8f9f7 642 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 643 ==============================================================================
<> 144:ef7eb2e8f9f7 644 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 645 (+) Transmit a frame
<> 144:ef7eb2e8f9f7 646 HAL_ETH_TransmitFrame();
<> 144:ef7eb2e8f9f7 647 (+) Receive a frame
<> 144:ef7eb2e8f9f7 648 HAL_ETH_GetReceivedFrame();
<> 144:ef7eb2e8f9f7 649 HAL_ETH_GetReceivedFrame_IT();
<> 144:ef7eb2e8f9f7 650 (+) Read from an External PHY register
<> 144:ef7eb2e8f9f7 651 HAL_ETH_ReadPHYRegister();
<> 144:ef7eb2e8f9f7 652 (+) Write to an External PHY register
<> 144:ef7eb2e8f9f7 653 HAL_ETH_WritePHYRegister();
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 @endverbatim
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 * @{
<> 144:ef7eb2e8f9f7 658 */
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /**
<> 144:ef7eb2e8f9f7 661 * @brief Sends an Ethernet frame.
<> 144:ef7eb2e8f9f7 662 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 663 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 664 * @param FrameLength: Amount of data to be sent
<> 144:ef7eb2e8f9f7 665 * @retval HAL status
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 uint32_t bufcount = 0, size = 0, i = 0;
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Process Locked */
<> 144:ef7eb2e8f9f7 672 __HAL_LOCK(heth);
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /* Set the ETH peripheral state to BUSY */
<> 144:ef7eb2e8f9f7 675 heth->State = HAL_ETH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 if (FrameLength == 0)
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 /* Set ETH HAL state to READY */
<> 144:ef7eb2e8f9f7 680 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 683 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
<> 144:ef7eb2e8f9f7 689 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
<> 144:ef7eb2e8f9f7 690 {
<> 144:ef7eb2e8f9f7 691 /* OWN bit set */
<> 144:ef7eb2e8f9f7 692 heth->State = HAL_ETH_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 695 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /* Get the number of needed Tx buffers for the current frame */
<> 144:ef7eb2e8f9f7 701 if (FrameLength > ETH_TX_BUF_SIZE)
<> 144:ef7eb2e8f9f7 702 {
<> 144:ef7eb2e8f9f7 703 bufcount = FrameLength/ETH_TX_BUF_SIZE;
<> 144:ef7eb2e8f9f7 704 if (FrameLength % ETH_TX_BUF_SIZE)
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 bufcount++;
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709 else
<> 144:ef7eb2e8f9f7 710 {
<> 144:ef7eb2e8f9f7 711 bufcount = 1;
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713 if (bufcount == 1)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 /* Set LAST and FIRST segment */
<> 144:ef7eb2e8f9f7 716 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
<> 144:ef7eb2e8f9f7 717 /* Set frame size */
<> 144:ef7eb2e8f9f7 718 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
<> 144:ef7eb2e8f9f7 719 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
<> 144:ef7eb2e8f9f7 720 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
<> 144:ef7eb2e8f9f7 721 /* Point to next descriptor */
<> 144:ef7eb2e8f9f7 722 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
<> 144:ef7eb2e8f9f7 723 }
<> 144:ef7eb2e8f9f7 724 else
<> 144:ef7eb2e8f9f7 725 {
<> 144:ef7eb2e8f9f7 726 for (i=0; i< bufcount; i++)
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 /* Clear FIRST and LAST segment bits */
<> 144:ef7eb2e8f9f7 729 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 if (i == 0)
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 /* Setting the first segment bit */
<> 144:ef7eb2e8f9f7 734 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
<> 144:ef7eb2e8f9f7 735 }
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /* Program size */
<> 144:ef7eb2e8f9f7 738 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 if (i == (bufcount-1))
<> 144:ef7eb2e8f9f7 741 {
<> 144:ef7eb2e8f9f7 742 /* Setting the last segment bit */
<> 144:ef7eb2e8f9f7 743 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
<> 144:ef7eb2e8f9f7 744 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
<> 144:ef7eb2e8f9f7 745 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
<> 144:ef7eb2e8f9f7 746 }
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
<> 144:ef7eb2e8f9f7 749 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
<> 144:ef7eb2e8f9f7 750 /* point to next descriptor */
<> 144:ef7eb2e8f9f7 751 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753 }
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
<> 144:ef7eb2e8f9f7 756 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
<> 144:ef7eb2e8f9f7 757 {
<> 144:ef7eb2e8f9f7 758 /* Clear TBUS ETHERNET DMA flag */
<> 144:ef7eb2e8f9f7 759 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
<> 144:ef7eb2e8f9f7 760 /* Resume DMA transmission*/
<> 144:ef7eb2e8f9f7 761 (heth->Instance)->DMATPDR = 0;
<> 144:ef7eb2e8f9f7 762 }
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* Set ETH HAL State to Ready */
<> 144:ef7eb2e8f9f7 765 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 768 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /* Return function status */
<> 144:ef7eb2e8f9f7 771 return HAL_OK;
<> 144:ef7eb2e8f9f7 772 }
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /**
<> 144:ef7eb2e8f9f7 775 * @brief Checks for received frames.
<> 144:ef7eb2e8f9f7 776 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 777 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 778 * @retval HAL status
<> 144:ef7eb2e8f9f7 779 */
<> 144:ef7eb2e8f9f7 780 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 781 {
<> 144:ef7eb2e8f9f7 782 uint32_t framelength = 0;
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Process Locked */
<> 144:ef7eb2e8f9f7 785 __HAL_LOCK(heth);
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /* Check the ETH state to BUSY */
<> 144:ef7eb2e8f9f7 788 heth->State = HAL_ETH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /* Check if segment is not owned by DMA */
<> 144:ef7eb2e8f9f7 791 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
<> 144:ef7eb2e8f9f7 792 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
<> 144:ef7eb2e8f9f7 793 {
<> 144:ef7eb2e8f9f7 794 /* Check if last segment */
<> 144:ef7eb2e8f9f7 795 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
<> 144:ef7eb2e8f9f7 796 {
<> 144:ef7eb2e8f9f7 797 /* increment segment count */
<> 144:ef7eb2e8f9f7 798 (heth->RxFrameInfos).SegCount++;
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /* Check if last segment is first segment: one segment contains the frame */
<> 144:ef7eb2e8f9f7 801 if ((heth->RxFrameInfos).SegCount == 1)
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
<> 144:ef7eb2e8f9f7 804 }
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
<> 144:ef7eb2e8f9f7 809 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
<> 144:ef7eb2e8f9f7 810 heth->RxFrameInfos.length = framelength;
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* Get the address of the buffer start address */
<> 144:ef7eb2e8f9f7 813 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
<> 144:ef7eb2e8f9f7 814 /* point to next descriptor */
<> 144:ef7eb2e8f9f7 815 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /* Set HAL State to Ready */
<> 144:ef7eb2e8f9f7 818 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 821 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /* Return function status */
<> 144:ef7eb2e8f9f7 824 return HAL_OK;
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826 /* Check if first segment */
<> 144:ef7eb2e8f9f7 827 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
<> 144:ef7eb2e8f9f7 828 {
<> 144:ef7eb2e8f9f7 829 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
<> 144:ef7eb2e8f9f7 830 (heth->RxFrameInfos).LSRxDesc = NULL;
<> 144:ef7eb2e8f9f7 831 (heth->RxFrameInfos).SegCount = 1;
<> 144:ef7eb2e8f9f7 832 /* Point to next descriptor */
<> 144:ef7eb2e8f9f7 833 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835 /* Check if intermediate segment */
<> 144:ef7eb2e8f9f7 836 else
<> 144:ef7eb2e8f9f7 837 {
<> 144:ef7eb2e8f9f7 838 (heth->RxFrameInfos).SegCount++;
<> 144:ef7eb2e8f9f7 839 /* Point to next descriptor */
<> 144:ef7eb2e8f9f7 840 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842 }
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Set ETH HAL State to Ready */
<> 144:ef7eb2e8f9f7 845 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 848 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /* Return function status */
<> 144:ef7eb2e8f9f7 851 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /**
<> 144:ef7eb2e8f9f7 855 * @brief Gets the Received frame in interrupt mode.
<> 144:ef7eb2e8f9f7 856 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 857 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 858 * @retval HAL status
<> 144:ef7eb2e8f9f7 859 */
<> 144:ef7eb2e8f9f7 860 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 861 {
<> 144:ef7eb2e8f9f7 862 uint32_t descriptorscancounter = 0;
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /* Process Locked */
<> 144:ef7eb2e8f9f7 865 __HAL_LOCK(heth);
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /* Set ETH HAL State to BUSY */
<> 144:ef7eb2e8f9f7 868 heth->State = HAL_ETH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 /* Scan descriptors owned by CPU */
<> 144:ef7eb2e8f9f7 871 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
<> 144:ef7eb2e8f9f7 872 {
<> 144:ef7eb2e8f9f7 873 /* Just for security */
<> 144:ef7eb2e8f9f7 874 descriptorscancounter++;
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /* Check if first segment in frame */
<> 144:ef7eb2e8f9f7 877 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
<> 144:ef7eb2e8f9f7 878 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
<> 144:ef7eb2e8f9f7 879 {
<> 144:ef7eb2e8f9f7 880 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
<> 144:ef7eb2e8f9f7 881 heth->RxFrameInfos.SegCount = 1;
<> 144:ef7eb2e8f9f7 882 /* Point to next descriptor */
<> 144:ef7eb2e8f9f7 883 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
<> 144:ef7eb2e8f9f7 884 }
<> 144:ef7eb2e8f9f7 885 /* Check if intermediate segment */
<> 144:ef7eb2e8f9f7 886 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
<> 144:ef7eb2e8f9f7 887 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
<> 144:ef7eb2e8f9f7 888 {
<> 144:ef7eb2e8f9f7 889 /* Increment segment count */
<> 144:ef7eb2e8f9f7 890 (heth->RxFrameInfos.SegCount)++;
<> 144:ef7eb2e8f9f7 891 /* Point to next descriptor */
<> 144:ef7eb2e8f9f7 892 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
<> 144:ef7eb2e8f9f7 893 }
<> 144:ef7eb2e8f9f7 894 /* Should be last segment */
<> 144:ef7eb2e8f9f7 895 else
<> 144:ef7eb2e8f9f7 896 {
<> 144:ef7eb2e8f9f7 897 /* Last segment */
<> 144:ef7eb2e8f9f7 898 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 /* Increment segment count */
<> 144:ef7eb2e8f9f7 901 (heth->RxFrameInfos.SegCount)++;
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 /* Check if last segment is first segment: one segment contains the frame */
<> 144:ef7eb2e8f9f7 904 if ((heth->RxFrameInfos.SegCount) == 1)
<> 144:ef7eb2e8f9f7 905 {
<> 144:ef7eb2e8f9f7 906 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
<> 144:ef7eb2e8f9f7 907 }
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
<> 144:ef7eb2e8f9f7 910 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /* Get the address of the buffer start address */
<> 144:ef7eb2e8f9f7 913 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* Point to next descriptor */
<> 144:ef7eb2e8f9f7 916 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /* Set HAL State to Ready */
<> 144:ef7eb2e8f9f7 919 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 922 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Return function status */
<> 144:ef7eb2e8f9f7 925 return HAL_OK;
<> 144:ef7eb2e8f9f7 926 }
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* Set HAL State to Ready */
<> 144:ef7eb2e8f9f7 930 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 933 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /* Return function status */
<> 144:ef7eb2e8f9f7 936 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /**
<> 144:ef7eb2e8f9f7 940 * @brief This function handles ETH interrupt request.
<> 144:ef7eb2e8f9f7 941 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 942 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 943 * @retval HAL status
<> 144:ef7eb2e8f9f7 944 */
<> 144:ef7eb2e8f9f7 945 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 946 {
<> 144:ef7eb2e8f9f7 947 /* Frame received */
<> 144:ef7eb2e8f9f7 948 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
<> 144:ef7eb2e8f9f7 949 {
<> 144:ef7eb2e8f9f7 950 /* Receive complete callback */
<> 144:ef7eb2e8f9f7 951 HAL_ETH_RxCpltCallback(heth);
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /* Clear the Eth DMA Rx IT pending bits */
<> 144:ef7eb2e8f9f7 954 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 /* Set HAL State to Ready */
<> 144:ef7eb2e8f9f7 957 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 960 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 961
<> 144:ef7eb2e8f9f7 962 }
<> 144:ef7eb2e8f9f7 963 /* Frame transmitted */
<> 144:ef7eb2e8f9f7 964 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
<> 144:ef7eb2e8f9f7 965 {
<> 144:ef7eb2e8f9f7 966 /* Transfer complete callback */
<> 144:ef7eb2e8f9f7 967 HAL_ETH_TxCpltCallback(heth);
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 /* Clear the Eth DMA Tx IT pending bits */
<> 144:ef7eb2e8f9f7 970 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 /* Set HAL State to Ready */
<> 144:ef7eb2e8f9f7 973 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 976 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 977 }
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 /* Clear the interrupt flags */
<> 144:ef7eb2e8f9f7 980 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 /* ETH DMA Error */
<> 144:ef7eb2e8f9f7 983 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
<> 144:ef7eb2e8f9f7 984 {
<> 144:ef7eb2e8f9f7 985 /* Ethernet Error callback */
<> 144:ef7eb2e8f9f7 986 HAL_ETH_ErrorCallback(heth);
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /* Clear the interrupt flags */
<> 144:ef7eb2e8f9f7 989 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /* Set HAL State to Ready */
<> 144:ef7eb2e8f9f7 992 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 995 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997 }
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 /**
<> 144:ef7eb2e8f9f7 1000 * @brief Tx Transfer completed callbacks.
<> 144:ef7eb2e8f9f7 1001 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1002 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1003 * @retval None
<> 144:ef7eb2e8f9f7 1004 */
<> 144:ef7eb2e8f9f7 1005 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 1006 {
<> 144:ef7eb2e8f9f7 1007 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1008 UNUSED(heth);
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1011 the HAL_ETH_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1012 */
<> 144:ef7eb2e8f9f7 1013 }
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 /**
<> 144:ef7eb2e8f9f7 1016 * @brief Rx Transfer completed callbacks.
<> 144:ef7eb2e8f9f7 1017 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1018 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1019 * @retval None
<> 144:ef7eb2e8f9f7 1020 */
<> 144:ef7eb2e8f9f7 1021 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 1022 {
<> 144:ef7eb2e8f9f7 1023 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1024 UNUSED(heth);
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1027 the HAL_ETH_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1028 */
<> 144:ef7eb2e8f9f7 1029 }
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 /**
<> 144:ef7eb2e8f9f7 1032 * @brief Ethernet transfer error callbacks
<> 144:ef7eb2e8f9f7 1033 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1034 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1035 * @retval None
<> 144:ef7eb2e8f9f7 1036 */
<> 144:ef7eb2e8f9f7 1037 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 1038 {
<> 144:ef7eb2e8f9f7 1039 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1040 UNUSED(heth);
<> 144:ef7eb2e8f9f7 1041
<> 144:ef7eb2e8f9f7 1042 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1043 the HAL_ETH_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1044 */
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /**
<> 144:ef7eb2e8f9f7 1048 * @brief Reads a PHY register
<> 144:ef7eb2e8f9f7 1049 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1050 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1051 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
<> 144:ef7eb2e8f9f7 1052 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1053 * PHY_BCR: Transceiver Basic Control Register,
<> 144:ef7eb2e8f9f7 1054 * PHY_BSR: Transceiver Basic Status Register.
<> 144:ef7eb2e8f9f7 1055 * More PHY register could be read depending on the used PHY
<> 144:ef7eb2e8f9f7 1056 * @param RegValue: PHY register value
<> 144:ef7eb2e8f9f7 1057 * @retval HAL status
<> 144:ef7eb2e8f9f7 1058 */
<> 144:ef7eb2e8f9f7 1059 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
<> 144:ef7eb2e8f9f7 1060 {
<> 144:ef7eb2e8f9f7 1061 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 1062 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1063
<> 144:ef7eb2e8f9f7 1064 /* Check parameters */
<> 144:ef7eb2e8f9f7 1065 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /* Check the ETH peripheral state */
<> 144:ef7eb2e8f9f7 1068 if(heth->State == HAL_ETH_STATE_BUSY_RD)
<> 144:ef7eb2e8f9f7 1069 {
<> 144:ef7eb2e8f9f7 1070 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1071 }
<> 144:ef7eb2e8f9f7 1072 /* Set ETH HAL State to BUSY_RD */
<> 144:ef7eb2e8f9f7 1073 heth->State = HAL_ETH_STATE_BUSY_RD;
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* Get the ETHERNET MACMIIAR value */
<> 144:ef7eb2e8f9f7 1076 tmpreg = heth->Instance->MACMIIAR;
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /* Keep only the CSR Clock Range CR[2:0] bits value */
<> 144:ef7eb2e8f9f7 1079 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 /* Prepare the MII address register value */
<> 144:ef7eb2e8f9f7 1082 tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
<> 144:ef7eb2e8f9f7 1083 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
<> 144:ef7eb2e8f9f7 1084 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
<> 144:ef7eb2e8f9f7 1085 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /* Write the result value into the MII Address register */
<> 144:ef7eb2e8f9f7 1088 heth->Instance->MACMIIAR = tmpreg;
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /* Get tick */
<> 144:ef7eb2e8f9f7 1091 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /* Check for the Busy flag */
<> 144:ef7eb2e8f9f7 1094 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
<> 144:ef7eb2e8f9f7 1095 {
<> 144:ef7eb2e8f9f7 1096 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1097 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
<> 144:ef7eb2e8f9f7 1098 {
<> 144:ef7eb2e8f9f7 1099 heth->State= HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 1100
<> 144:ef7eb2e8f9f7 1101 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1102 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 1103
<> 144:ef7eb2e8f9f7 1104 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1105 }
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 tmpreg = heth->Instance->MACMIIAR;
<> 144:ef7eb2e8f9f7 1108 }
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 /* Get MACMIIDR value */
<> 144:ef7eb2e8f9f7 1111 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /* Set ETH HAL State to READY */
<> 144:ef7eb2e8f9f7 1114 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 1115
<> 144:ef7eb2e8f9f7 1116 /* Return function status */
<> 144:ef7eb2e8f9f7 1117 return HAL_OK;
<> 144:ef7eb2e8f9f7 1118 }
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 /**
<> 144:ef7eb2e8f9f7 1121 * @brief Writes to a PHY register.
<> 144:ef7eb2e8f9f7 1122 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1123 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1124 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
<> 144:ef7eb2e8f9f7 1125 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1126 * PHY_BCR: Transceiver Control Register.
<> 144:ef7eb2e8f9f7 1127 * More PHY register could be written depending on the used PHY
<> 144:ef7eb2e8f9f7 1128 * @param RegValue: the value to write
<> 144:ef7eb2e8f9f7 1129 * @retval HAL status
<> 144:ef7eb2e8f9f7 1130 */
<> 144:ef7eb2e8f9f7 1131 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
<> 144:ef7eb2e8f9f7 1132 {
<> 144:ef7eb2e8f9f7 1133 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 1134 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1135
<> 144:ef7eb2e8f9f7 1136 /* Check parameters */
<> 144:ef7eb2e8f9f7 1137 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 /* Check the ETH peripheral state */
<> 144:ef7eb2e8f9f7 1140 if(heth->State == HAL_ETH_STATE_BUSY_WR)
<> 144:ef7eb2e8f9f7 1141 {
<> 144:ef7eb2e8f9f7 1142 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1143 }
<> 144:ef7eb2e8f9f7 1144 /* Set ETH HAL State to BUSY_WR */
<> 144:ef7eb2e8f9f7 1145 heth->State = HAL_ETH_STATE_BUSY_WR;
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 /* Get the ETHERNET MACMIIAR value */
<> 144:ef7eb2e8f9f7 1148 tmpreg = heth->Instance->MACMIIAR;
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 /* Keep only the CSR Clock Range CR[2:0] bits value */
<> 144:ef7eb2e8f9f7 1151 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
<> 144:ef7eb2e8f9f7 1152
<> 144:ef7eb2e8f9f7 1153 /* Prepare the MII register address value */
<> 144:ef7eb2e8f9f7 1154 tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
<> 144:ef7eb2e8f9f7 1155 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
<> 144:ef7eb2e8f9f7 1156 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
<> 144:ef7eb2e8f9f7 1157 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159 /* Give the value to the MII data register */
<> 144:ef7eb2e8f9f7 1160 heth->Instance->MACMIIDR = (uint16_t)RegValue;
<> 144:ef7eb2e8f9f7 1161
<> 144:ef7eb2e8f9f7 1162 /* Write the result value into the MII Address register */
<> 144:ef7eb2e8f9f7 1163 heth->Instance->MACMIIAR = tmpreg;
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 /* Get tick */
<> 144:ef7eb2e8f9f7 1166 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1167
<> 144:ef7eb2e8f9f7 1168 /* Check for the Busy flag */
<> 144:ef7eb2e8f9f7 1169 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
<> 144:ef7eb2e8f9f7 1170 {
<> 144:ef7eb2e8f9f7 1171 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1172 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
<> 144:ef7eb2e8f9f7 1173 {
<> 144:ef7eb2e8f9f7 1174 heth->State= HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1177 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1180 }
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 tmpreg = heth->Instance->MACMIIAR;
<> 144:ef7eb2e8f9f7 1183 }
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 /* Set ETH HAL State to READY */
<> 144:ef7eb2e8f9f7 1186 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 /* Return function status */
<> 144:ef7eb2e8f9f7 1189 return HAL_OK;
<> 144:ef7eb2e8f9f7 1190 }
<> 144:ef7eb2e8f9f7 1191
<> 144:ef7eb2e8f9f7 1192 /**
<> 144:ef7eb2e8f9f7 1193 * @}
<> 144:ef7eb2e8f9f7 1194 */
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1197 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1198 *
<> 144:ef7eb2e8f9f7 1199 @verbatim
<> 144:ef7eb2e8f9f7 1200 ===============================================================================
<> 144:ef7eb2e8f9f7 1201 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1202 ===============================================================================
<> 144:ef7eb2e8f9f7 1203 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1204 (+) Enable MAC and DMA transmission and reception.
<> 144:ef7eb2e8f9f7 1205 HAL_ETH_Start();
<> 144:ef7eb2e8f9f7 1206 (+) Disable MAC and DMA transmission and reception.
<> 144:ef7eb2e8f9f7 1207 HAL_ETH_Stop();
<> 144:ef7eb2e8f9f7 1208 (+) Set the MAC configuration in runtime mode
<> 144:ef7eb2e8f9f7 1209 HAL_ETH_ConfigMAC();
<> 144:ef7eb2e8f9f7 1210 (+) Set the DMA configuration in runtime mode
<> 144:ef7eb2e8f9f7 1211 HAL_ETH_ConfigDMA();
<> 144:ef7eb2e8f9f7 1212
<> 144:ef7eb2e8f9f7 1213 @endverbatim
<> 144:ef7eb2e8f9f7 1214 * @{
<> 144:ef7eb2e8f9f7 1215 */
<> 144:ef7eb2e8f9f7 1216
<> 144:ef7eb2e8f9f7 1217 /**
<> 144:ef7eb2e8f9f7 1218 * @brief Enables Ethernet MAC and DMA reception/transmission
<> 144:ef7eb2e8f9f7 1219 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1220 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1221 * @retval HAL status
<> 144:ef7eb2e8f9f7 1222 */
<> 144:ef7eb2e8f9f7 1223 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 1224 {
<> 144:ef7eb2e8f9f7 1225 /* Process Locked */
<> 144:ef7eb2e8f9f7 1226 __HAL_LOCK(heth);
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 /* Set the ETH peripheral state to BUSY */
<> 144:ef7eb2e8f9f7 1229 heth->State = HAL_ETH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1230
<> 144:ef7eb2e8f9f7 1231 /* Enable transmit state machine of the MAC for transmission on the MII */
<> 144:ef7eb2e8f9f7 1232 ETH_MACTransmissionEnable(heth);
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234 /* Enable receive state machine of the MAC for reception from the MII */
<> 144:ef7eb2e8f9f7 1235 ETH_MACReceptionEnable(heth);
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 /* Flush Transmit FIFO */
<> 144:ef7eb2e8f9f7 1238 ETH_FlushTransmitFIFO(heth);
<> 144:ef7eb2e8f9f7 1239
<> 144:ef7eb2e8f9f7 1240 /* Start DMA transmission */
<> 144:ef7eb2e8f9f7 1241 ETH_DMATransmissionEnable(heth);
<> 144:ef7eb2e8f9f7 1242
<> 144:ef7eb2e8f9f7 1243 /* Start DMA reception */
<> 144:ef7eb2e8f9f7 1244 ETH_DMAReceptionEnable(heth);
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 /* Set the ETH state to READY*/
<> 144:ef7eb2e8f9f7 1247 heth->State= HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1250 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 /* Return function status */
<> 144:ef7eb2e8f9f7 1253 return HAL_OK;
<> 144:ef7eb2e8f9f7 1254 }
<> 144:ef7eb2e8f9f7 1255
<> 144:ef7eb2e8f9f7 1256 /**
<> 144:ef7eb2e8f9f7 1257 * @brief Stop Ethernet MAC and DMA reception/transmission
<> 144:ef7eb2e8f9f7 1258 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1259 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1260 * @retval HAL status
<> 144:ef7eb2e8f9f7 1261 */
<> 144:ef7eb2e8f9f7 1262 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 1263 {
<> 144:ef7eb2e8f9f7 1264 /* Process Locked */
<> 144:ef7eb2e8f9f7 1265 __HAL_LOCK(heth);
<> 144:ef7eb2e8f9f7 1266
<> 144:ef7eb2e8f9f7 1267 /* Set the ETH peripheral state to BUSY */
<> 144:ef7eb2e8f9f7 1268 heth->State = HAL_ETH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 /* Stop DMA transmission */
<> 144:ef7eb2e8f9f7 1271 ETH_DMATransmissionDisable(heth);
<> 144:ef7eb2e8f9f7 1272
<> 144:ef7eb2e8f9f7 1273 /* Stop DMA reception */
<> 144:ef7eb2e8f9f7 1274 ETH_DMAReceptionDisable(heth);
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 /* Disable receive state machine of the MAC for reception from the MII */
<> 144:ef7eb2e8f9f7 1277 ETH_MACReceptionDisable(heth);
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /* Flush Transmit FIFO */
<> 144:ef7eb2e8f9f7 1280 ETH_FlushTransmitFIFO(heth);
<> 144:ef7eb2e8f9f7 1281
<> 144:ef7eb2e8f9f7 1282 /* Disable transmit state machine of the MAC for transmission on the MII */
<> 144:ef7eb2e8f9f7 1283 ETH_MACTransmissionDisable(heth);
<> 144:ef7eb2e8f9f7 1284
<> 144:ef7eb2e8f9f7 1285 /* Set the ETH state*/
<> 144:ef7eb2e8f9f7 1286 heth->State = HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1289 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 /* Return function status */
<> 144:ef7eb2e8f9f7 1292 return HAL_OK;
<> 144:ef7eb2e8f9f7 1293 }
<> 144:ef7eb2e8f9f7 1294
<> 144:ef7eb2e8f9f7 1295 /**
<> 144:ef7eb2e8f9f7 1296 * @brief Set ETH MAC Configuration.
<> 144:ef7eb2e8f9f7 1297 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1298 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1299 * @param macconf: MAC Configuration structure
<> 144:ef7eb2e8f9f7 1300 * @retval HAL status
<> 144:ef7eb2e8f9f7 1301 */
<> 144:ef7eb2e8f9f7 1302 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
<> 144:ef7eb2e8f9f7 1303 {
<> 144:ef7eb2e8f9f7 1304 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 1305
<> 144:ef7eb2e8f9f7 1306 /* Process Locked */
<> 144:ef7eb2e8f9f7 1307 __HAL_LOCK(heth);
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 /* Set the ETH peripheral state to BUSY */
<> 144:ef7eb2e8f9f7 1310 heth->State= HAL_ETH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1311
<> 144:ef7eb2e8f9f7 1312 assert_param(IS_ETH_SPEED(heth->Init.Speed));
<> 144:ef7eb2e8f9f7 1313 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
<> 144:ef7eb2e8f9f7 1314
<> 144:ef7eb2e8f9f7 1315 if (macconf != NULL)
<> 144:ef7eb2e8f9f7 1316 {
<> 144:ef7eb2e8f9f7 1317 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1318 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
<> 144:ef7eb2e8f9f7 1319 assert_param(IS_ETH_JABBER(macconf->Jabber));
<> 144:ef7eb2e8f9f7 1320 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
<> 144:ef7eb2e8f9f7 1321 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
<> 144:ef7eb2e8f9f7 1322 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
<> 144:ef7eb2e8f9f7 1323 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
<> 144:ef7eb2e8f9f7 1324 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
<> 144:ef7eb2e8f9f7 1325 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
<> 144:ef7eb2e8f9f7 1326 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
<> 144:ef7eb2e8f9f7 1327 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
<> 144:ef7eb2e8f9f7 1328 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
<> 144:ef7eb2e8f9f7 1329 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
<> 144:ef7eb2e8f9f7 1330 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
<> 144:ef7eb2e8f9f7 1331 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
<> 144:ef7eb2e8f9f7 1332 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
<> 144:ef7eb2e8f9f7 1333 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
<> 144:ef7eb2e8f9f7 1334 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
<> 144:ef7eb2e8f9f7 1335 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
<> 144:ef7eb2e8f9f7 1336 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
<> 144:ef7eb2e8f9f7 1337 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
<> 144:ef7eb2e8f9f7 1338 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
<> 144:ef7eb2e8f9f7 1339 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
<> 144:ef7eb2e8f9f7 1340 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
<> 144:ef7eb2e8f9f7 1341 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
<> 144:ef7eb2e8f9f7 1342 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
<> 144:ef7eb2e8f9f7 1343 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
<> 144:ef7eb2e8f9f7 1344 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
<> 144:ef7eb2e8f9f7 1345
<> 144:ef7eb2e8f9f7 1346 /*------------------------ ETHERNET MACCR Configuration --------------------*/
<> 144:ef7eb2e8f9f7 1347 /* Get the ETHERNET MACCR value */
<> 144:ef7eb2e8f9f7 1348 tmpreg = (heth->Instance)->MACCR;
<> 144:ef7eb2e8f9f7 1349 /* Clear WD, PCE, PS, TE and RE bits */
<> 144:ef7eb2e8f9f7 1350 tmpreg &= ETH_MACCR_CLEAR_MASK;
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 tmpreg |= (uint32_t)(macconf->Watchdog |
<> 144:ef7eb2e8f9f7 1353 macconf->Jabber |
<> 144:ef7eb2e8f9f7 1354 macconf->InterFrameGap |
<> 144:ef7eb2e8f9f7 1355 macconf->CarrierSense |
<> 144:ef7eb2e8f9f7 1356 (heth->Init).Speed |
<> 144:ef7eb2e8f9f7 1357 macconf->ReceiveOwn |
<> 144:ef7eb2e8f9f7 1358 macconf->LoopbackMode |
<> 144:ef7eb2e8f9f7 1359 (heth->Init).DuplexMode |
<> 144:ef7eb2e8f9f7 1360 macconf->ChecksumOffload |
<> 144:ef7eb2e8f9f7 1361 macconf->RetryTransmission |
<> 144:ef7eb2e8f9f7 1362 macconf->AutomaticPadCRCStrip |
<> 144:ef7eb2e8f9f7 1363 macconf->BackOffLimit |
<> 144:ef7eb2e8f9f7 1364 macconf->DeferralCheck);
<> 144:ef7eb2e8f9f7 1365
<> 144:ef7eb2e8f9f7 1366 /* Write to ETHERNET MACCR */
<> 144:ef7eb2e8f9f7 1367 (heth->Instance)->MACCR = (uint32_t)tmpreg;
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 /* Wait until the write operation will be taken into account :
<> 144:ef7eb2e8f9f7 1370 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1371 tmpreg = (heth->Instance)->MACCR;
<> 144:ef7eb2e8f9f7 1372 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1373 (heth->Instance)->MACCR = tmpreg;
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
<> 144:ef7eb2e8f9f7 1376 /* Write to ETHERNET MACFFR */
<> 144:ef7eb2e8f9f7 1377 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
<> 144:ef7eb2e8f9f7 1378 macconf->SourceAddrFilter |
<> 144:ef7eb2e8f9f7 1379 macconf->PassControlFrames |
<> 144:ef7eb2e8f9f7 1380 macconf->BroadcastFramesReception |
<> 144:ef7eb2e8f9f7 1381 macconf->DestinationAddrFilter |
<> 144:ef7eb2e8f9f7 1382 macconf->PromiscuousMode |
<> 144:ef7eb2e8f9f7 1383 macconf->MulticastFramesFilter |
<> 144:ef7eb2e8f9f7 1384 macconf->UnicastFramesFilter);
<> 144:ef7eb2e8f9f7 1385
<> 144:ef7eb2e8f9f7 1386 /* Wait until the write operation will be taken into account :
<> 144:ef7eb2e8f9f7 1387 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1388 tmpreg = (heth->Instance)->MACFFR;
<> 144:ef7eb2e8f9f7 1389 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1390 (heth->Instance)->MACFFR = tmpreg;
<> 144:ef7eb2e8f9f7 1391
<> 144:ef7eb2e8f9f7 1392 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
<> 144:ef7eb2e8f9f7 1393 /* Write to ETHERNET MACHTHR */
<> 144:ef7eb2e8f9f7 1394 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
<> 144:ef7eb2e8f9f7 1395
<> 144:ef7eb2e8f9f7 1396 /* Write to ETHERNET MACHTLR */
<> 144:ef7eb2e8f9f7 1397 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
<> 144:ef7eb2e8f9f7 1398 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 /* Get the ETHERNET MACFCR value */
<> 144:ef7eb2e8f9f7 1401 tmpreg = (heth->Instance)->MACFCR;
<> 144:ef7eb2e8f9f7 1402 /* Clear xx bits */
<> 144:ef7eb2e8f9f7 1403 tmpreg &= ETH_MACFCR_CLEAR_MASK;
<> 144:ef7eb2e8f9f7 1404
<> 144:ef7eb2e8f9f7 1405 tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
<> 144:ef7eb2e8f9f7 1406 macconf->ZeroQuantaPause |
<> 144:ef7eb2e8f9f7 1407 macconf->PauseLowThreshold |
<> 144:ef7eb2e8f9f7 1408 macconf->UnicastPauseFrameDetect |
<> 144:ef7eb2e8f9f7 1409 macconf->ReceiveFlowControl |
<> 144:ef7eb2e8f9f7 1410 macconf->TransmitFlowControl);
<> 144:ef7eb2e8f9f7 1411
<> 144:ef7eb2e8f9f7 1412 /* Write to ETHERNET MACFCR */
<> 144:ef7eb2e8f9f7 1413 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
<> 144:ef7eb2e8f9f7 1414
<> 144:ef7eb2e8f9f7 1415 /* Wait until the write operation will be taken into account :
<> 144:ef7eb2e8f9f7 1416 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1417 tmpreg = (heth->Instance)->MACFCR;
<> 144:ef7eb2e8f9f7 1418 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1419 (heth->Instance)->MACFCR = tmpreg;
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
<> 144:ef7eb2e8f9f7 1422 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
<> 144:ef7eb2e8f9f7 1423 macconf->VLANTagIdentifier);
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 /* Wait until the write operation will be taken into account :
<> 144:ef7eb2e8f9f7 1426 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1427 tmpreg = (heth->Instance)->MACVLANTR;
<> 144:ef7eb2e8f9f7 1428 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1429 (heth->Instance)->MACVLANTR = tmpreg;
<> 144:ef7eb2e8f9f7 1430 }
<> 144:ef7eb2e8f9f7 1431 else /* macconf == NULL : here we just configure Speed and Duplex mode */
<> 144:ef7eb2e8f9f7 1432 {
<> 144:ef7eb2e8f9f7 1433 /*------------------------ ETHERNET MACCR Configuration --------------------*/
<> 144:ef7eb2e8f9f7 1434 /* Get the ETHERNET MACCR value */
<> 144:ef7eb2e8f9f7 1435 tmpreg = (heth->Instance)->MACCR;
<> 144:ef7eb2e8f9f7 1436
<> 144:ef7eb2e8f9f7 1437 /* Clear FES and DM bits */
<> 144:ef7eb2e8f9f7 1438 tmpreg &= ~((uint32_t)0x00004800);
<> 144:ef7eb2e8f9f7 1439
<> 144:ef7eb2e8f9f7 1440 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
<> 144:ef7eb2e8f9f7 1441
<> 144:ef7eb2e8f9f7 1442 /* Write to ETHERNET MACCR */
<> 144:ef7eb2e8f9f7 1443 (heth->Instance)->MACCR = (uint32_t)tmpreg;
<> 144:ef7eb2e8f9f7 1444
<> 144:ef7eb2e8f9f7 1445 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 1446 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1447 tmpreg = (heth->Instance)->MACCR;
<> 144:ef7eb2e8f9f7 1448 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1449 (heth->Instance)->MACCR = tmpreg;
<> 144:ef7eb2e8f9f7 1450 }
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 /* Set the ETH state to Ready */
<> 144:ef7eb2e8f9f7 1453 heth->State= HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 1454
<> 144:ef7eb2e8f9f7 1455 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1456 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 1457
<> 144:ef7eb2e8f9f7 1458 /* Return function status */
<> 144:ef7eb2e8f9f7 1459 return HAL_OK;
<> 144:ef7eb2e8f9f7 1460 }
<> 144:ef7eb2e8f9f7 1461
<> 144:ef7eb2e8f9f7 1462 /**
<> 144:ef7eb2e8f9f7 1463 * @brief Sets ETH DMA Configuration.
<> 144:ef7eb2e8f9f7 1464 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1465 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1466 * @param dmaconf: DMA Configuration structure
<> 144:ef7eb2e8f9f7 1467 * @retval HAL status
<> 144:ef7eb2e8f9f7 1468 */
<> 144:ef7eb2e8f9f7 1469 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
<> 144:ef7eb2e8f9f7 1470 {
<> 144:ef7eb2e8f9f7 1471 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 1472
<> 144:ef7eb2e8f9f7 1473 /* Process Locked */
<> 144:ef7eb2e8f9f7 1474 __HAL_LOCK(heth);
<> 144:ef7eb2e8f9f7 1475
<> 144:ef7eb2e8f9f7 1476 /* Set the ETH peripheral state to BUSY */
<> 144:ef7eb2e8f9f7 1477 heth->State= HAL_ETH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1478
<> 144:ef7eb2e8f9f7 1479 /* Check parameters */
<> 144:ef7eb2e8f9f7 1480 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
<> 144:ef7eb2e8f9f7 1481 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
<> 144:ef7eb2e8f9f7 1482 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
<> 144:ef7eb2e8f9f7 1483 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
<> 144:ef7eb2e8f9f7 1484 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
<> 144:ef7eb2e8f9f7 1485 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
<> 144:ef7eb2e8f9f7 1486 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
<> 144:ef7eb2e8f9f7 1487 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
<> 144:ef7eb2e8f9f7 1488 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
<> 144:ef7eb2e8f9f7 1489 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
<> 144:ef7eb2e8f9f7 1490 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
<> 144:ef7eb2e8f9f7 1491 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
<> 144:ef7eb2e8f9f7 1492 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
<> 144:ef7eb2e8f9f7 1493 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
<> 144:ef7eb2e8f9f7 1494 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
<> 144:ef7eb2e8f9f7 1495 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
<> 144:ef7eb2e8f9f7 1498 /* Get the ETHERNET DMAOMR value */
<> 144:ef7eb2e8f9f7 1499 tmpreg = (heth->Instance)->DMAOMR;
<> 144:ef7eb2e8f9f7 1500 /* Clear xx bits */
<> 144:ef7eb2e8f9f7 1501 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
<> 144:ef7eb2e8f9f7 1502
<> 144:ef7eb2e8f9f7 1503 tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
<> 144:ef7eb2e8f9f7 1504 dmaconf->ReceiveStoreForward |
<> 144:ef7eb2e8f9f7 1505 dmaconf->FlushReceivedFrame |
<> 144:ef7eb2e8f9f7 1506 dmaconf->TransmitStoreForward |
<> 144:ef7eb2e8f9f7 1507 dmaconf->TransmitThresholdControl |
<> 144:ef7eb2e8f9f7 1508 dmaconf->ForwardErrorFrames |
<> 144:ef7eb2e8f9f7 1509 dmaconf->ForwardUndersizedGoodFrames |
<> 144:ef7eb2e8f9f7 1510 dmaconf->ReceiveThresholdControl |
<> 144:ef7eb2e8f9f7 1511 dmaconf->SecondFrameOperate);
<> 144:ef7eb2e8f9f7 1512
<> 144:ef7eb2e8f9f7 1513 /* Write to ETHERNET DMAOMR */
<> 144:ef7eb2e8f9f7 1514 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
<> 144:ef7eb2e8f9f7 1515
<> 144:ef7eb2e8f9f7 1516 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 1517 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1518 tmpreg = (heth->Instance)->DMAOMR;
<> 144:ef7eb2e8f9f7 1519 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1520 (heth->Instance)->DMAOMR = tmpreg;
<> 144:ef7eb2e8f9f7 1521
<> 144:ef7eb2e8f9f7 1522 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
<> 144:ef7eb2e8f9f7 1523 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
<> 144:ef7eb2e8f9f7 1524 dmaconf->FixedBurst |
<> 144:ef7eb2e8f9f7 1525 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
<> 144:ef7eb2e8f9f7 1526 dmaconf->TxDMABurstLength |
<> 144:ef7eb2e8f9f7 1527 dmaconf->EnhancedDescriptorFormat |
<> 144:ef7eb2e8f9f7 1528 (dmaconf->DescriptorSkipLength << 2) |
<> 144:ef7eb2e8f9f7 1529 dmaconf->DMAArbitration |
<> 144:ef7eb2e8f9f7 1530 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
<> 144:ef7eb2e8f9f7 1531
<> 144:ef7eb2e8f9f7 1532 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 1533 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1534 tmpreg = (heth->Instance)->DMABMR;
<> 144:ef7eb2e8f9f7 1535 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1536 (heth->Instance)->DMABMR = tmpreg;
<> 144:ef7eb2e8f9f7 1537
<> 144:ef7eb2e8f9f7 1538 /* Set the ETH state to Ready */
<> 144:ef7eb2e8f9f7 1539 heth->State= HAL_ETH_STATE_READY;
<> 144:ef7eb2e8f9f7 1540
<> 144:ef7eb2e8f9f7 1541 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1542 __HAL_UNLOCK(heth);
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 /* Return function status */
<> 144:ef7eb2e8f9f7 1545 return HAL_OK;
<> 144:ef7eb2e8f9f7 1546 }
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 /**
<> 144:ef7eb2e8f9f7 1549 * @}
<> 144:ef7eb2e8f9f7 1550 */
<> 144:ef7eb2e8f9f7 1551
<> 144:ef7eb2e8f9f7 1552 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
<> 144:ef7eb2e8f9f7 1553 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1554 *
<> 144:ef7eb2e8f9f7 1555 @verbatim
<> 144:ef7eb2e8f9f7 1556 ===============================================================================
<> 144:ef7eb2e8f9f7 1557 ##### Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1558 ===============================================================================
<> 144:ef7eb2e8f9f7 1559 [..]
<> 144:ef7eb2e8f9f7 1560 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1561 and the data flow.
<> 144:ef7eb2e8f9f7 1562 (+) Get the ETH handle state:
<> 144:ef7eb2e8f9f7 1563 HAL_ETH_GetState();
<> 144:ef7eb2e8f9f7 1564
<> 144:ef7eb2e8f9f7 1565
<> 144:ef7eb2e8f9f7 1566 @endverbatim
<> 144:ef7eb2e8f9f7 1567 * @{
<> 144:ef7eb2e8f9f7 1568 */
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 /**
<> 144:ef7eb2e8f9f7 1571 * @brief Return the ETH HAL state
<> 144:ef7eb2e8f9f7 1572 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1573 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1574 * @retval HAL state
<> 144:ef7eb2e8f9f7 1575 */
<> 144:ef7eb2e8f9f7 1576 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 1577 {
<> 144:ef7eb2e8f9f7 1578 /* Return ETH state */
<> 144:ef7eb2e8f9f7 1579 return heth->State;
<> 144:ef7eb2e8f9f7 1580 }
<> 144:ef7eb2e8f9f7 1581
<> 144:ef7eb2e8f9f7 1582 /**
<> 144:ef7eb2e8f9f7 1583 * @}
<> 144:ef7eb2e8f9f7 1584 */
<> 144:ef7eb2e8f9f7 1585
<> 144:ef7eb2e8f9f7 1586 /**
<> 144:ef7eb2e8f9f7 1587 * @}
<> 144:ef7eb2e8f9f7 1588 */
<> 144:ef7eb2e8f9f7 1589
<> 144:ef7eb2e8f9f7 1590 /** @addtogroup ETH_Private_Functions
<> 144:ef7eb2e8f9f7 1591 * @{
<> 144:ef7eb2e8f9f7 1592 */
<> 144:ef7eb2e8f9f7 1593
<> 144:ef7eb2e8f9f7 1594 /**
<> 144:ef7eb2e8f9f7 1595 * @brief Configures Ethernet MAC and DMA with default parameters.
<> 144:ef7eb2e8f9f7 1596 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1597 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1598 * @param err: Ethernet Init error
<> 144:ef7eb2e8f9f7 1599 * @retval HAL status
<> 144:ef7eb2e8f9f7 1600 */
<> 144:ef7eb2e8f9f7 1601 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
<> 144:ef7eb2e8f9f7 1602 {
<> 144:ef7eb2e8f9f7 1603 ETH_MACInitTypeDef macinit;
<> 144:ef7eb2e8f9f7 1604 ETH_DMAInitTypeDef dmainit;
<> 144:ef7eb2e8f9f7 1605 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
<> 144:ef7eb2e8f9f7 1608 {
<> 144:ef7eb2e8f9f7 1609 /* Set Ethernet duplex mode to Full-duplex */
<> 144:ef7eb2e8f9f7 1610 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 /* Set Ethernet speed to 100M */
<> 144:ef7eb2e8f9f7 1613 (heth->Init).Speed = ETH_SPEED_100M;
<> 144:ef7eb2e8f9f7 1614 }
<> 144:ef7eb2e8f9f7 1615
<> 144:ef7eb2e8f9f7 1616 /* Ethernet MAC default initialization **************************************/
<> 144:ef7eb2e8f9f7 1617 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
<> 144:ef7eb2e8f9f7 1618 macinit.Jabber = ETH_JABBER_ENABLE;
<> 144:ef7eb2e8f9f7 1619 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
<> 144:ef7eb2e8f9f7 1620 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
<> 144:ef7eb2e8f9f7 1621 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
<> 144:ef7eb2e8f9f7 1622 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
<> 144:ef7eb2e8f9f7 1623 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
<> 144:ef7eb2e8f9f7 1624 {
<> 144:ef7eb2e8f9f7 1625 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
<> 144:ef7eb2e8f9f7 1626 }
<> 144:ef7eb2e8f9f7 1627 else
<> 144:ef7eb2e8f9f7 1628 {
<> 144:ef7eb2e8f9f7 1629 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
<> 144:ef7eb2e8f9f7 1630 }
<> 144:ef7eb2e8f9f7 1631 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
<> 144:ef7eb2e8f9f7 1632 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
<> 144:ef7eb2e8f9f7 1633 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
<> 144:ef7eb2e8f9f7 1634 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
<> 144:ef7eb2e8f9f7 1635 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
<> 144:ef7eb2e8f9f7 1636 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
<> 144:ef7eb2e8f9f7 1637 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
<> 144:ef7eb2e8f9f7 1638 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
<> 144:ef7eb2e8f9f7 1639 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
<> 144:ef7eb2e8f9f7 1640 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
<> 144:ef7eb2e8f9f7 1641 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
<> 144:ef7eb2e8f9f7 1642 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
<> 144:ef7eb2e8f9f7 1643 macinit.HashTableHigh = 0x0;
<> 144:ef7eb2e8f9f7 1644 macinit.HashTableLow = 0x0;
<> 144:ef7eb2e8f9f7 1645 macinit.PauseTime = 0x0;
<> 144:ef7eb2e8f9f7 1646 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
<> 144:ef7eb2e8f9f7 1647 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
<> 144:ef7eb2e8f9f7 1648 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
<> 144:ef7eb2e8f9f7 1649 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
<> 144:ef7eb2e8f9f7 1650 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
<> 144:ef7eb2e8f9f7 1651 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
<> 144:ef7eb2e8f9f7 1652 macinit.VLANTagIdentifier = 0x0;
<> 144:ef7eb2e8f9f7 1653
<> 144:ef7eb2e8f9f7 1654 /*------------------------ ETHERNET MACCR Configuration --------------------*/
<> 144:ef7eb2e8f9f7 1655 /* Get the ETHERNET MACCR value */
<> 144:ef7eb2e8f9f7 1656 tmpreg = (heth->Instance)->MACCR;
<> 144:ef7eb2e8f9f7 1657 /* Clear WD, PCE, PS, TE and RE bits */
<> 144:ef7eb2e8f9f7 1658 tmpreg &= ETH_MACCR_CLEAR_MASK;
<> 144:ef7eb2e8f9f7 1659 /* Set the WD bit according to ETH Watchdog value */
<> 144:ef7eb2e8f9f7 1660 /* Set the JD: bit according to ETH Jabber value */
<> 144:ef7eb2e8f9f7 1661 /* Set the IFG bit according to ETH InterFrameGap value */
<> 144:ef7eb2e8f9f7 1662 /* Set the DCRS bit according to ETH CarrierSense value */
<> 144:ef7eb2e8f9f7 1663 /* Set the FES bit according to ETH Speed value */
<> 144:ef7eb2e8f9f7 1664 /* Set the DO bit according to ETH ReceiveOwn value */
<> 144:ef7eb2e8f9f7 1665 /* Set the LM bit according to ETH LoopbackMode value */
<> 144:ef7eb2e8f9f7 1666 /* Set the DM bit according to ETH Mode value */
<> 144:ef7eb2e8f9f7 1667 /* Set the IPCO bit according to ETH ChecksumOffload value */
<> 144:ef7eb2e8f9f7 1668 /* Set the DR bit according to ETH RetryTransmission value */
<> 144:ef7eb2e8f9f7 1669 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
<> 144:ef7eb2e8f9f7 1670 /* Set the BL bit according to ETH BackOffLimit value */
<> 144:ef7eb2e8f9f7 1671 /* Set the DC bit according to ETH DeferralCheck value */
<> 144:ef7eb2e8f9f7 1672 tmpreg |= (uint32_t)(macinit.Watchdog |
<> 144:ef7eb2e8f9f7 1673 macinit.Jabber |
<> 144:ef7eb2e8f9f7 1674 macinit.InterFrameGap |
<> 144:ef7eb2e8f9f7 1675 macinit.CarrierSense |
<> 144:ef7eb2e8f9f7 1676 (heth->Init).Speed |
<> 144:ef7eb2e8f9f7 1677 macinit.ReceiveOwn |
<> 144:ef7eb2e8f9f7 1678 macinit.LoopbackMode |
<> 144:ef7eb2e8f9f7 1679 (heth->Init).DuplexMode |
<> 144:ef7eb2e8f9f7 1680 macinit.ChecksumOffload |
<> 144:ef7eb2e8f9f7 1681 macinit.RetryTransmission |
<> 144:ef7eb2e8f9f7 1682 macinit.AutomaticPadCRCStrip |
<> 144:ef7eb2e8f9f7 1683 macinit.BackOffLimit |
<> 144:ef7eb2e8f9f7 1684 macinit.DeferralCheck);
<> 144:ef7eb2e8f9f7 1685
<> 144:ef7eb2e8f9f7 1686 /* Write to ETHERNET MACCR */
<> 144:ef7eb2e8f9f7 1687 (heth->Instance)->MACCR = (uint32_t)tmpreg;
<> 144:ef7eb2e8f9f7 1688
<> 144:ef7eb2e8f9f7 1689 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 1690 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1691 tmpreg = (heth->Instance)->MACCR;
<> 144:ef7eb2e8f9f7 1692 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1693 (heth->Instance)->MACCR = tmpreg;
<> 144:ef7eb2e8f9f7 1694
<> 144:ef7eb2e8f9f7 1695 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
<> 144:ef7eb2e8f9f7 1696 /* Set the RA bit according to ETH ReceiveAll value */
<> 144:ef7eb2e8f9f7 1697 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
<> 144:ef7eb2e8f9f7 1698 /* Set the PCF bit according to ETH PassControlFrames value */
<> 144:ef7eb2e8f9f7 1699 /* Set the DBF bit according to ETH BroadcastFramesReception value */
<> 144:ef7eb2e8f9f7 1700 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
<> 144:ef7eb2e8f9f7 1701 /* Set the PR bit according to ETH PromiscuousMode value */
<> 144:ef7eb2e8f9f7 1702 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
<> 144:ef7eb2e8f9f7 1703 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
<> 144:ef7eb2e8f9f7 1704 /* Write to ETHERNET MACFFR */
<> 144:ef7eb2e8f9f7 1705 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
<> 144:ef7eb2e8f9f7 1706 macinit.SourceAddrFilter |
<> 144:ef7eb2e8f9f7 1707 macinit.PassControlFrames |
<> 144:ef7eb2e8f9f7 1708 macinit.BroadcastFramesReception |
<> 144:ef7eb2e8f9f7 1709 macinit.DestinationAddrFilter |
<> 144:ef7eb2e8f9f7 1710 macinit.PromiscuousMode |
<> 144:ef7eb2e8f9f7 1711 macinit.MulticastFramesFilter |
<> 144:ef7eb2e8f9f7 1712 macinit.UnicastFramesFilter);
<> 144:ef7eb2e8f9f7 1713
<> 144:ef7eb2e8f9f7 1714 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 1715 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1716 tmpreg = (heth->Instance)->MACFFR;
<> 144:ef7eb2e8f9f7 1717 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1718 (heth->Instance)->MACFFR = tmpreg;
<> 144:ef7eb2e8f9f7 1719
<> 144:ef7eb2e8f9f7 1720 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
<> 144:ef7eb2e8f9f7 1721 /* Write to ETHERNET MACHTHR */
<> 144:ef7eb2e8f9f7 1722 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
<> 144:ef7eb2e8f9f7 1723
<> 144:ef7eb2e8f9f7 1724 /* Write to ETHERNET MACHTLR */
<> 144:ef7eb2e8f9f7 1725 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
<> 144:ef7eb2e8f9f7 1726 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
<> 144:ef7eb2e8f9f7 1727
<> 144:ef7eb2e8f9f7 1728 /* Get the ETHERNET MACFCR value */
<> 144:ef7eb2e8f9f7 1729 tmpreg = (heth->Instance)->MACFCR;
<> 144:ef7eb2e8f9f7 1730 /* Clear xx bits */
<> 144:ef7eb2e8f9f7 1731 tmpreg &= ETH_MACFCR_CLEAR_MASK;
<> 144:ef7eb2e8f9f7 1732
<> 144:ef7eb2e8f9f7 1733 /* Set the PT bit according to ETH PauseTime value */
<> 144:ef7eb2e8f9f7 1734 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
<> 144:ef7eb2e8f9f7 1735 /* Set the PLT bit according to ETH PauseLowThreshold value */
<> 144:ef7eb2e8f9f7 1736 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
<> 144:ef7eb2e8f9f7 1737 /* Set the RFE bit according to ETH ReceiveFlowControl value */
<> 144:ef7eb2e8f9f7 1738 /* Set the TFE bit according to ETH TransmitFlowControl value */
<> 144:ef7eb2e8f9f7 1739 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
<> 144:ef7eb2e8f9f7 1740 macinit.ZeroQuantaPause |
<> 144:ef7eb2e8f9f7 1741 macinit.PauseLowThreshold |
<> 144:ef7eb2e8f9f7 1742 macinit.UnicastPauseFrameDetect |
<> 144:ef7eb2e8f9f7 1743 macinit.ReceiveFlowControl |
<> 144:ef7eb2e8f9f7 1744 macinit.TransmitFlowControl);
<> 144:ef7eb2e8f9f7 1745
<> 144:ef7eb2e8f9f7 1746 /* Write to ETHERNET MACFCR */
<> 144:ef7eb2e8f9f7 1747 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
<> 144:ef7eb2e8f9f7 1748
<> 144:ef7eb2e8f9f7 1749 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 1750 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1751 tmpreg = (heth->Instance)->MACFCR;
<> 144:ef7eb2e8f9f7 1752 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1753 (heth->Instance)->MACFCR = tmpreg;
<> 144:ef7eb2e8f9f7 1754
<> 144:ef7eb2e8f9f7 1755 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
<> 144:ef7eb2e8f9f7 1756 /* Set the ETV bit according to ETH VLANTagComparison value */
<> 144:ef7eb2e8f9f7 1757 /* Set the VL bit according to ETH VLANTagIdentifier value */
<> 144:ef7eb2e8f9f7 1758 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
<> 144:ef7eb2e8f9f7 1759 macinit.VLANTagIdentifier);
<> 144:ef7eb2e8f9f7 1760
<> 144:ef7eb2e8f9f7 1761 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 1762 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1763 tmpreg = (heth->Instance)->MACVLANTR;
<> 144:ef7eb2e8f9f7 1764 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1765 (heth->Instance)->MACVLANTR = tmpreg;
<> 144:ef7eb2e8f9f7 1766
<> 144:ef7eb2e8f9f7 1767 /* Ethernet DMA default initialization ************************************/
<> 144:ef7eb2e8f9f7 1768 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
<> 144:ef7eb2e8f9f7 1769 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
<> 144:ef7eb2e8f9f7 1770 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
<> 144:ef7eb2e8f9f7 1771 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
<> 144:ef7eb2e8f9f7 1772 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
<> 144:ef7eb2e8f9f7 1773 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
<> 144:ef7eb2e8f9f7 1774 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
<> 144:ef7eb2e8f9f7 1775 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
<> 144:ef7eb2e8f9f7 1776 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
<> 144:ef7eb2e8f9f7 1777 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
<> 144:ef7eb2e8f9f7 1778 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
<> 144:ef7eb2e8f9f7 1779 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
<> 144:ef7eb2e8f9f7 1780 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
<> 144:ef7eb2e8f9f7 1781 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
<> 144:ef7eb2e8f9f7 1782 dmainit.DescriptorSkipLength = 0x0;
<> 144:ef7eb2e8f9f7 1783 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
<> 144:ef7eb2e8f9f7 1784
<> 144:ef7eb2e8f9f7 1785 /* Get the ETHERNET DMAOMR value */
<> 144:ef7eb2e8f9f7 1786 tmpreg = (heth->Instance)->DMAOMR;
<> 144:ef7eb2e8f9f7 1787 /* Clear xx bits */
<> 144:ef7eb2e8f9f7 1788 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
<> 144:ef7eb2e8f9f7 1789
<> 144:ef7eb2e8f9f7 1790 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
<> 144:ef7eb2e8f9f7 1791 /* Set the RSF bit according to ETH ReceiveStoreForward value */
<> 144:ef7eb2e8f9f7 1792 /* Set the DFF bit according to ETH FlushReceivedFrame value */
<> 144:ef7eb2e8f9f7 1793 /* Set the TSF bit according to ETH TransmitStoreForward value */
<> 144:ef7eb2e8f9f7 1794 /* Set the TTC bit according to ETH TransmitThresholdControl value */
<> 144:ef7eb2e8f9f7 1795 /* Set the FEF bit according to ETH ForwardErrorFrames value */
<> 144:ef7eb2e8f9f7 1796 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
<> 144:ef7eb2e8f9f7 1797 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
<> 144:ef7eb2e8f9f7 1798 /* Set the OSF bit according to ETH SecondFrameOperate value */
<> 144:ef7eb2e8f9f7 1799 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
<> 144:ef7eb2e8f9f7 1800 dmainit.ReceiveStoreForward |
<> 144:ef7eb2e8f9f7 1801 dmainit.FlushReceivedFrame |
<> 144:ef7eb2e8f9f7 1802 dmainit.TransmitStoreForward |
<> 144:ef7eb2e8f9f7 1803 dmainit.TransmitThresholdControl |
<> 144:ef7eb2e8f9f7 1804 dmainit.ForwardErrorFrames |
<> 144:ef7eb2e8f9f7 1805 dmainit.ForwardUndersizedGoodFrames |
<> 144:ef7eb2e8f9f7 1806 dmainit.ReceiveThresholdControl |
<> 144:ef7eb2e8f9f7 1807 dmainit.SecondFrameOperate);
<> 144:ef7eb2e8f9f7 1808
<> 144:ef7eb2e8f9f7 1809 /* Write to ETHERNET DMAOMR */
<> 144:ef7eb2e8f9f7 1810 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
<> 144:ef7eb2e8f9f7 1811
<> 144:ef7eb2e8f9f7 1812 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 1813 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1814 tmpreg = (heth->Instance)->DMAOMR;
<> 144:ef7eb2e8f9f7 1815 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1816 (heth->Instance)->DMAOMR = tmpreg;
<> 144:ef7eb2e8f9f7 1817
<> 144:ef7eb2e8f9f7 1818 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
<> 144:ef7eb2e8f9f7 1819 /* Set the AAL bit according to ETH AddressAlignedBeats value */
<> 144:ef7eb2e8f9f7 1820 /* Set the FB bit according to ETH FixedBurst value */
<> 144:ef7eb2e8f9f7 1821 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
<> 144:ef7eb2e8f9f7 1822 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
<> 144:ef7eb2e8f9f7 1823 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
<> 144:ef7eb2e8f9f7 1824 /* Set the DSL bit according to ETH DesciptorSkipLength value */
<> 144:ef7eb2e8f9f7 1825 /* Set the PR and DA bits according to ETH DMAArbitration value */
<> 144:ef7eb2e8f9f7 1826 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
<> 144:ef7eb2e8f9f7 1827 dmainit.FixedBurst |
<> 144:ef7eb2e8f9f7 1828 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
<> 144:ef7eb2e8f9f7 1829 dmainit.TxDMABurstLength |
<> 144:ef7eb2e8f9f7 1830 dmainit.EnhancedDescriptorFormat |
<> 144:ef7eb2e8f9f7 1831 (dmainit.DescriptorSkipLength << 2) |
<> 144:ef7eb2e8f9f7 1832 dmainit.DMAArbitration |
<> 144:ef7eb2e8f9f7 1833 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
<> 144:ef7eb2e8f9f7 1834
<> 144:ef7eb2e8f9f7 1835 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 1836 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1837 tmpreg = (heth->Instance)->DMABMR;
<> 144:ef7eb2e8f9f7 1838 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1839 (heth->Instance)->DMABMR = tmpreg;
<> 144:ef7eb2e8f9f7 1840
<> 144:ef7eb2e8f9f7 1841 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
<> 144:ef7eb2e8f9f7 1842 {
<> 144:ef7eb2e8f9f7 1843 /* Enable the Ethernet Rx Interrupt */
<> 144:ef7eb2e8f9f7 1844 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
<> 144:ef7eb2e8f9f7 1845 }
<> 144:ef7eb2e8f9f7 1846
<> 144:ef7eb2e8f9f7 1847 /* Initialize MAC address in ethernet MAC */
<> 144:ef7eb2e8f9f7 1848 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
<> 144:ef7eb2e8f9f7 1849 }
<> 144:ef7eb2e8f9f7 1850
<> 144:ef7eb2e8f9f7 1851 /**
<> 144:ef7eb2e8f9f7 1852 * @brief Configures the selected MAC address.
<> 144:ef7eb2e8f9f7 1853 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1854 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1855 * @param MacAddr: The MAC address to configure
<> 144:ef7eb2e8f9f7 1856 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1857 * @arg ETH_MAC_Address0: MAC Address0
<> 144:ef7eb2e8f9f7 1858 * @arg ETH_MAC_Address1: MAC Address1
<> 144:ef7eb2e8f9f7 1859 * @arg ETH_MAC_Address2: MAC Address2
<> 144:ef7eb2e8f9f7 1860 * @arg ETH_MAC_Address3: MAC Address3
<> 144:ef7eb2e8f9f7 1861 * @param Addr: Pointer to MAC address buffer data (6 bytes)
<> 144:ef7eb2e8f9f7 1862 * @retval HAL status
<> 144:ef7eb2e8f9f7 1863 */
<> 144:ef7eb2e8f9f7 1864 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
<> 144:ef7eb2e8f9f7 1865 {
<> 144:ef7eb2e8f9f7 1866 uint32_t tmpreg;
<> 144:ef7eb2e8f9f7 1867
<> 144:ef7eb2e8f9f7 1868 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1869 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
<> 144:ef7eb2e8f9f7 1870
<> 144:ef7eb2e8f9f7 1871 /* Calculate the selected MAC address high register */
<> 144:ef7eb2e8f9f7 1872 tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
<> 144:ef7eb2e8f9f7 1873 /* Load the selected MAC address high register */
<> 144:ef7eb2e8f9f7 1874 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
<> 144:ef7eb2e8f9f7 1875 /* Calculate the selected MAC address low register */
<> 144:ef7eb2e8f9f7 1876 tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
<> 144:ef7eb2e8f9f7 1877
<> 144:ef7eb2e8f9f7 1878 /* Load the selected MAC address low register */
<> 144:ef7eb2e8f9f7 1879 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
<> 144:ef7eb2e8f9f7 1880 }
<> 144:ef7eb2e8f9f7 1881
<> 144:ef7eb2e8f9f7 1882 /**
<> 144:ef7eb2e8f9f7 1883 * @brief Enables the MAC transmission.
<> 144:ef7eb2e8f9f7 1884 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1885 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1886 * @retval None
<> 144:ef7eb2e8f9f7 1887 */
<> 144:ef7eb2e8f9f7 1888 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 1889 {
<> 144:ef7eb2e8f9f7 1890 __IO uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 1891
<> 144:ef7eb2e8f9f7 1892 /* Enable the MAC transmission */
<> 144:ef7eb2e8f9f7 1893 (heth->Instance)->MACCR |= ETH_MACCR_TE;
<> 144:ef7eb2e8f9f7 1894
<> 144:ef7eb2e8f9f7 1895 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 1896 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1897 tmpreg = (heth->Instance)->MACCR;
<> 144:ef7eb2e8f9f7 1898 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1899 (heth->Instance)->MACCR = tmpreg;
<> 144:ef7eb2e8f9f7 1900 }
<> 144:ef7eb2e8f9f7 1901
<> 144:ef7eb2e8f9f7 1902 /**
<> 144:ef7eb2e8f9f7 1903 * @brief Disables the MAC transmission.
<> 144:ef7eb2e8f9f7 1904 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1905 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1906 * @retval None
<> 144:ef7eb2e8f9f7 1907 */
<> 144:ef7eb2e8f9f7 1908 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 1909 {
<> 144:ef7eb2e8f9f7 1910 __IO uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 1911
<> 144:ef7eb2e8f9f7 1912 /* Disable the MAC transmission */
<> 144:ef7eb2e8f9f7 1913 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
<> 144:ef7eb2e8f9f7 1914
<> 144:ef7eb2e8f9f7 1915 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 1916 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1917 tmpreg = (heth->Instance)->MACCR;
<> 144:ef7eb2e8f9f7 1918 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1919 (heth->Instance)->MACCR = tmpreg;
<> 144:ef7eb2e8f9f7 1920 }
<> 144:ef7eb2e8f9f7 1921
<> 144:ef7eb2e8f9f7 1922 /**
<> 144:ef7eb2e8f9f7 1923 * @brief Enables the MAC reception.
<> 144:ef7eb2e8f9f7 1924 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1925 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1926 * @retval None
<> 144:ef7eb2e8f9f7 1927 */
<> 144:ef7eb2e8f9f7 1928 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 1929 {
<> 144:ef7eb2e8f9f7 1930 __IO uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 1931
<> 144:ef7eb2e8f9f7 1932 /* Enable the MAC reception */
<> 144:ef7eb2e8f9f7 1933 (heth->Instance)->MACCR |= ETH_MACCR_RE;
<> 144:ef7eb2e8f9f7 1934
<> 144:ef7eb2e8f9f7 1935 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 1936 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1937 tmpreg = (heth->Instance)->MACCR;
<> 144:ef7eb2e8f9f7 1938 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1939 (heth->Instance)->MACCR = tmpreg;
<> 144:ef7eb2e8f9f7 1940 }
<> 144:ef7eb2e8f9f7 1941
<> 144:ef7eb2e8f9f7 1942 /**
<> 144:ef7eb2e8f9f7 1943 * @brief Disables the MAC reception.
<> 144:ef7eb2e8f9f7 1944 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1945 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1946 * @retval None
<> 144:ef7eb2e8f9f7 1947 */
<> 144:ef7eb2e8f9f7 1948 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 1949 {
<> 144:ef7eb2e8f9f7 1950 __IO uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 1951
<> 144:ef7eb2e8f9f7 1952 /* Disable the MAC reception */
<> 144:ef7eb2e8f9f7 1953 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
<> 144:ef7eb2e8f9f7 1954
<> 144:ef7eb2e8f9f7 1955 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 1956 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 1957 tmpreg = (heth->Instance)->MACCR;
<> 144:ef7eb2e8f9f7 1958 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 1959 (heth->Instance)->MACCR = tmpreg;
<> 144:ef7eb2e8f9f7 1960 }
<> 144:ef7eb2e8f9f7 1961
<> 144:ef7eb2e8f9f7 1962 /**
<> 144:ef7eb2e8f9f7 1963 * @brief Enables the DMA transmission.
<> 144:ef7eb2e8f9f7 1964 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1965 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1966 * @retval None
<> 144:ef7eb2e8f9f7 1967 */
<> 144:ef7eb2e8f9f7 1968 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 1969 {
<> 144:ef7eb2e8f9f7 1970 /* Enable the DMA transmission */
<> 144:ef7eb2e8f9f7 1971 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
<> 144:ef7eb2e8f9f7 1972 }
<> 144:ef7eb2e8f9f7 1973
<> 144:ef7eb2e8f9f7 1974 /**
<> 144:ef7eb2e8f9f7 1975 * @brief Disables the DMA transmission.
<> 144:ef7eb2e8f9f7 1976 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1977 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1978 * @retval None
<> 144:ef7eb2e8f9f7 1979 */
<> 144:ef7eb2e8f9f7 1980 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 1981 {
<> 144:ef7eb2e8f9f7 1982 /* Disable the DMA transmission */
<> 144:ef7eb2e8f9f7 1983 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
<> 144:ef7eb2e8f9f7 1984 }
<> 144:ef7eb2e8f9f7 1985
<> 144:ef7eb2e8f9f7 1986 /**
<> 144:ef7eb2e8f9f7 1987 * @brief Enables the DMA reception.
<> 144:ef7eb2e8f9f7 1988 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1989 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 1990 * @retval None
<> 144:ef7eb2e8f9f7 1991 */
<> 144:ef7eb2e8f9f7 1992 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 1993 {
<> 144:ef7eb2e8f9f7 1994 /* Enable the DMA reception */
<> 144:ef7eb2e8f9f7 1995 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
<> 144:ef7eb2e8f9f7 1996 }
<> 144:ef7eb2e8f9f7 1997
<> 144:ef7eb2e8f9f7 1998 /**
<> 144:ef7eb2e8f9f7 1999 * @brief Disables the DMA reception.
<> 144:ef7eb2e8f9f7 2000 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2001 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 2002 * @retval None
<> 144:ef7eb2e8f9f7 2003 */
<> 144:ef7eb2e8f9f7 2004 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 2005 {
<> 144:ef7eb2e8f9f7 2006 /* Disable the DMA reception */
<> 144:ef7eb2e8f9f7 2007 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
<> 144:ef7eb2e8f9f7 2008 }
<> 144:ef7eb2e8f9f7 2009
<> 144:ef7eb2e8f9f7 2010 /**
<> 144:ef7eb2e8f9f7 2011 * @brief Clears the ETHERNET transmit FIFO.
<> 144:ef7eb2e8f9f7 2012 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2013 * the configuration information for ETHERNET module
<> 144:ef7eb2e8f9f7 2014 * @retval None
<> 144:ef7eb2e8f9f7 2015 */
<> 144:ef7eb2e8f9f7 2016 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
<> 144:ef7eb2e8f9f7 2017 {
<> 144:ef7eb2e8f9f7 2018 __IO uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 2019
<> 144:ef7eb2e8f9f7 2020 /* Set the Flush Transmit FIFO bit */
<> 144:ef7eb2e8f9f7 2021 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
<> 144:ef7eb2e8f9f7 2022
<> 144:ef7eb2e8f9f7 2023 /* Wait until the write operation will be taken into account:
<> 144:ef7eb2e8f9f7 2024 at least four TX_CLK/RX_CLK clock cycles */
<> 144:ef7eb2e8f9f7 2025 tmpreg = (heth->Instance)->DMAOMR;
<> 144:ef7eb2e8f9f7 2026 HAL_Delay(ETH_REG_WRITE_DELAY);
<> 144:ef7eb2e8f9f7 2027 (heth->Instance)->DMAOMR = tmpreg;
<> 144:ef7eb2e8f9f7 2028 }
<> 144:ef7eb2e8f9f7 2029
<> 144:ef7eb2e8f9f7 2030 /**
<> 144:ef7eb2e8f9f7 2031 * @}
<> 144:ef7eb2e8f9f7 2032 */
<> 144:ef7eb2e8f9f7 2033
<> 144:ef7eb2e8f9f7 2034 #endif /* HAL_ETH_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2035 /**
<> 144:ef7eb2e8f9f7 2036 * @}
<> 144:ef7eb2e8f9f7 2037 */
<> 144:ef7eb2e8f9f7 2038
<> 144:ef7eb2e8f9f7 2039 /**
<> 144:ef7eb2e8f9f7 2040 * @}
<> 144:ef7eb2e8f9f7 2041 */
<> 144:ef7eb2e8f9f7 2042
<> 144:ef7eb2e8f9f7 2043 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/