Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
149:156823d33999 
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_dfsdm.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the Digital Filter for Sigma-Delta Modulators
<> 144:ef7eb2e8f9f7 9 * (DFSDM) peripherals:
<> 144:ef7eb2e8f9f7 10 * + Initialization and configuration of channels and filters
<> 144:ef7eb2e8f9f7 11 * + Regular channels configuration
<> 144:ef7eb2e8f9f7 12 * + Injected channels configuration
<> 144:ef7eb2e8f9f7 13 * + Regular/Injected Channels DMA Configuration
<> 144:ef7eb2e8f9f7 14 * + Interrupts and flags management
<> 144:ef7eb2e8f9f7 15 * + Analog watchdog feature
<> 144:ef7eb2e8f9f7 16 * + Short-circuit detector feature
<> 144:ef7eb2e8f9f7 17 * + Extremes detector feature
<> 144:ef7eb2e8f9f7 18 * + Clock absence detector feature
<> 144:ef7eb2e8f9f7 19 * + Break generation on analog watchdog or short-circuit event
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 @verbatim
<> 144:ef7eb2e8f9f7 22 ==============================================================================
<> 144:ef7eb2e8f9f7 23 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 24 ==============================================================================
<> 144:ef7eb2e8f9f7 25 [..]
<> 144:ef7eb2e8f9f7 26 *** Channel initialization ***
<> 144:ef7eb2e8f9f7 27 ==============================
<> 144:ef7eb2e8f9f7 28 [..]
<> 144:ef7eb2e8f9f7 29 (#) User has first to initialize channels (before filters initialization).
<> 144:ef7eb2e8f9f7 30 (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :
<> 144:ef7eb2e8f9f7 31 (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().
<> 144:ef7eb2e8f9f7 32 (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
<> 144:ef7eb2e8f9f7 33 (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().
<> 144:ef7eb2e8f9f7 34 (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
<> 144:ef7eb2e8f9f7 35 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
<> 144:ef7eb2e8f9f7 36 (#) Configure the output clock, input, serial interface, analog watchdog,
<> 144:ef7eb2e8f9f7 37 offset and data right bit shift parameters for this channel using the
<> 144:ef7eb2e8f9f7 38 HAL_DFSDM_ChannelInit() function.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 *** Channel clock absence detector ***
<> 144:ef7eb2e8f9f7 41 ======================================
<> 144:ef7eb2e8f9f7 42 [..]
<> 144:ef7eb2e8f9f7 43 (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or
<> 144:ef7eb2e8f9f7 44 HAL_DFSDM_ChannelCkabStart_IT().
<> 144:ef7eb2e8f9f7 45 (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock
<> 144:ef7eb2e8f9f7 46 absence.
<> 144:ef7eb2e8f9f7 47 (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if
<> 144:ef7eb2e8f9f7 48 clock absence is detected.
<> 144:ef7eb2e8f9f7 49 (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
<> 144:ef7eb2e8f9f7 50 HAL_DFSDM_ChannelCkabStop_IT().
<> 144:ef7eb2e8f9f7 51 (#) Please note that the same mode (polling or interrupt) has to be used
<> 144:ef7eb2e8f9f7 52 for all channels because the channels are sharing the same interrupt.
<> 144:ef7eb2e8f9f7 53 (#) Please note also that in interrupt mode, if clock absence detector is
<> 144:ef7eb2e8f9f7 54 stopped for one channel, interrupt will be disabled for all channels.
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 *** Channel short circuit detector ***
<> 144:ef7eb2e8f9f7 57 ======================================
<> 144:ef7eb2e8f9f7 58 [..]
<> 144:ef7eb2e8f9f7 59 (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
<> 144:ef7eb2e8f9f7 60 or HAL_DFSDM_ChannelScdStart_IT().
<> 144:ef7eb2e8f9f7 61 (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
<> 144:ef7eb2e8f9f7 62 circuit.
<> 144:ef7eb2e8f9f7 63 (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
<> 144:ef7eb2e8f9f7 64 short circuit is detected.
<> 144:ef7eb2e8f9f7 65 (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
<> 144:ef7eb2e8f9f7 66 or HAL_DFSDM_ChannelScdStop_IT().
<> 144:ef7eb2e8f9f7 67 (#) Please note that the same mode (polling or interrupt) has to be used
<> 144:ef7eb2e8f9f7 68 for all channels because the channels are sharing the same interrupt.
<> 144:ef7eb2e8f9f7 69 (#) Please note also that in interrupt mode, if short circuit detector is
<> 144:ef7eb2e8f9f7 70 stopped for one channel, interrupt will be disabled for all channels.
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 *** Channel analog watchdog value ***
<> 144:ef7eb2e8f9f7 73 =====================================
<> 144:ef7eb2e8f9f7 74 [..]
<> 144:ef7eb2e8f9f7 75 (#) Get analog watchdog filter value of a channel using
<> 144:ef7eb2e8f9f7 76 HAL_DFSDM_ChannelGetAwdValue().
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 *** Channel offset value ***
<> 144:ef7eb2e8f9f7 79 =====================================
<> 144:ef7eb2e8f9f7 80 [..]
<> 144:ef7eb2e8f9f7 81 (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 *** Filter initialization ***
<> 144:ef7eb2e8f9f7 84 =============================
<> 144:ef7eb2e8f9f7 85 [..]
<> 144:ef7eb2e8f9f7 86 (#) After channel initialization, user has to init filters.
<> 144:ef7eb2e8f9f7 87 (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :
<> 144:ef7eb2e8f9f7 88 (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global
<> 144:ef7eb2e8f9f7 89 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
<> 144:ef7eb2e8f9f7 90 Please note that DFSDMz_FLT0 global interrupt could be already
<> 144:ef7eb2e8f9f7 91 enabled if interrupt is used for channel.
<> 144:ef7eb2e8f9f7 92 (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it
<> 144:ef7eb2e8f9f7 93 with DFSDMz filter handle using __HAL_LINKDMA().
<> 144:ef7eb2e8f9f7 94 (#) Configure the regular conversion, injected conversion and filter
<> 144:ef7eb2e8f9f7 95 parameters for this filter using the HAL_DFSDM_FilterInit() function.
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 *** Filter regular channel conversion ***
<> 144:ef7eb2e8f9f7 98 =========================================
<> 144:ef7eb2e8f9f7 99 [..]
<> 144:ef7eb2e8f9f7 100 (#) Select regular channel and enable/disable continuous mode using
<> 144:ef7eb2e8f9f7 101 HAL_DFSDM_FilterConfigRegChannel().
<> 144:ef7eb2e8f9f7 102 (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
<> 144:ef7eb2e8f9f7 103 HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
<> 144:ef7eb2e8f9f7 104 HAL_DFSDM_FilterRegularMsbStart_DMA().
<> 144:ef7eb2e8f9f7 105 (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
<> 144:ef7eb2e8f9f7 106 the end of regular conversion.
<> 144:ef7eb2e8f9f7 107 (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
<> 144:ef7eb2e8f9f7 108 at the end of regular conversion.
<> 144:ef7eb2e8f9f7 109 (#) Get value of regular conversion and corresponding channel using
<> 144:ef7eb2e8f9f7 110 HAL_DFSDM_FilterGetRegularValue().
<> 144:ef7eb2e8f9f7 111 (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
<> 144:ef7eb2e8f9f7 112 HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
<> 144:ef7eb2e8f9f7 113 half transfer and at the transfer complete. Please note that
<> 144:ef7eb2e8f9f7 114 HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
<> 144:ef7eb2e8f9f7 115 circular mode.
<> 144:ef7eb2e8f9f7 116 (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
<> 144:ef7eb2e8f9f7 117 HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 *** Filter injected channels conversion ***
<> 144:ef7eb2e8f9f7 120 ===========================================
<> 144:ef7eb2e8f9f7 121 [..]
<> 144:ef7eb2e8f9f7 122 (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().
<> 144:ef7eb2e8f9f7 123 (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
<> 144:ef7eb2e8f9f7 124 HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
<> 144:ef7eb2e8f9f7 125 HAL_DFSDM_FilterInjectedMsbStart_DMA().
<> 144:ef7eb2e8f9f7 126 (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
<> 144:ef7eb2e8f9f7 127 the end of injected conversion.
<> 144:ef7eb2e8f9f7 128 (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
<> 144:ef7eb2e8f9f7 129 at the end of injected conversion.
<> 144:ef7eb2e8f9f7 130 (#) Get value of injected conversion and corresponding channel using
<> 144:ef7eb2e8f9f7 131 HAL_DFSDM_FilterGetInjectedValue().
<> 144:ef7eb2e8f9f7 132 (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
<> 144:ef7eb2e8f9f7 133 HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
<> 144:ef7eb2e8f9f7 134 half transfer and at the transfer complete. Please note that
<> 144:ef7eb2e8f9f7 135 HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
<> 144:ef7eb2e8f9f7 136 circular mode.
<> 144:ef7eb2e8f9f7 137 (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
<> 144:ef7eb2e8f9f7 138 HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 *** Filter analog watchdog ***
<> 144:ef7eb2e8f9f7 141 ==============================
<> 144:ef7eb2e8f9f7 142 [..]
<> 144:ef7eb2e8f9f7 143 (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().
<> 144:ef7eb2e8f9f7 144 (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.
<> 144:ef7eb2e8f9f7 145 (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 *** Filter extreme detector ***
<> 144:ef7eb2e8f9f7 148 ===============================
<> 144:ef7eb2e8f9f7 149 [..]
<> 144:ef7eb2e8f9f7 150 (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().
<> 144:ef7eb2e8f9f7 151 (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().
<> 144:ef7eb2e8f9f7 152 (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().
<> 144:ef7eb2e8f9f7 153 (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 *** Filter conversion time ***
<> 144:ef7eb2e8f9f7 156 ==============================
<> 144:ef7eb2e8f9f7 157 [..]
<> 144:ef7eb2e8f9f7 158 (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 @endverbatim
<> 144:ef7eb2e8f9f7 161 ******************************************************************************
<> 144:ef7eb2e8f9f7 162 * @attention
<> 144:ef7eb2e8f9f7 163 *
AnnaBridge 167:e84263d55307 164 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 165 *
<> 144:ef7eb2e8f9f7 166 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 167 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 168 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 169 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 170 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 171 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 172 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 173 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 174 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 175 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 176 *
<> 144:ef7eb2e8f9f7 177 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 178 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 179 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 180 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 181 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 182 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 183 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 184 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 185 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 186 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 187 *
<> 144:ef7eb2e8f9f7 188 ******************************************************************************
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 192 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 195 * @{
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197 #ifdef HAL_DFSDM_MODULE_ENABLED
AnnaBridge 167:e84263d55307 198
AnnaBridge 167:e84263d55307 199 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
AnnaBridge 167:e84263d55307 200 defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
AnnaBridge 167:e84263d55307 201 defined(STM32L496xx) || defined(STM32L4A6xx)
<> 144:ef7eb2e8f9f7 202 /** @defgroup DFSDM DFSDM
<> 144:ef7eb2e8f9f7 203 * @brief DFSDM HAL driver module
<> 144:ef7eb2e8f9f7 204 * @{
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 208 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 209 /** @defgroup DFSDM_Private_Define DFSDM Private Define
<> 144:ef7eb2e8f9f7 210 * @{
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212 #define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)
<> 144:ef7eb2e8f9f7 213 #define DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)
<> 144:ef7eb2e8f9f7 214 #define DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)
<> 144:ef7eb2e8f9f7 215 #define DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET)
<> 144:ef7eb2e8f9f7 216 #define DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS)
<> 144:ef7eb2e8f9f7 217 #define DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR)
<> 144:ef7eb2e8f9f7 218 #define DFSDM_FLTCR1_MSB_RCH_OFFSET 8
<> 144:ef7eb2e8f9f7 219 #define DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH)
<> 144:ef7eb2e8f9f7 220 #define DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH)
<> 144:ef7eb2e8f9f7 221 #define DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF)
<> 144:ef7eb2e8f9f7 222 #define DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF)
<> 144:ef7eb2e8f9f7 223 #define DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF)
<> 144:ef7eb2e8f9f7 224 #define DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCSDF)
<> 144:ef7eb2e8f9f7 225 #define DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA)
<> 144:ef7eb2e8f9f7 226 #define DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA)
<> 144:ef7eb2e8f9f7 227 #define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)
<> 144:ef7eb2e8f9f7 228 #define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)
<> 144:ef7eb2e8f9f7 229 #define DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)
<> 144:ef7eb2e8f9f7 230 #define DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)
<> 144:ef7eb2e8f9f7 231 #define DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)
<> 144:ef7eb2e8f9f7 232 #define DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF)
<> 144:ef7eb2e8f9f7 233 #define DFSDM_MSB_MASK 0xFFFF0000U
<> 144:ef7eb2e8f9f7 234 #define DFSDM_LSB_MASK 0x0000FFFFU
<> 144:ef7eb2e8f9f7 235 #define DFSDM_CKAB_TIMEOUT 5000U
AnnaBridge 167:e84263d55307 236 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
AnnaBridge 167:e84263d55307 237 #define DFSDM1_CHANNEL_NUMBER 4U
AnnaBridge 167:e84263d55307 238 #else /* STM32L451xx || STM32L452xx || STM32L462xx */
<> 144:ef7eb2e8f9f7 239 #define DFSDM1_CHANNEL_NUMBER 8U
AnnaBridge 167:e84263d55307 240 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @}
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 246 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 247 /** @defgroup DFSDM_Private_Variables DFSDM Private Variables
<> 144:ef7eb2e8f9f7 248 * @{
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 __IO uint32_t v_dfsdm1ChannelCounter = 0;
<> 144:ef7eb2e8f9f7 251 DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};
<> 144:ef7eb2e8f9f7 252 /**
<> 144:ef7eb2e8f9f7 253 * @}
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 257 /** @defgroup DFSDM_Private_Functions DFSDM Private Functions
<> 144:ef7eb2e8f9f7 258 * @{
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
<> 144:ef7eb2e8f9f7 261 static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance);
<> 144:ef7eb2e8f9f7 262 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 263 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
<> 144:ef7eb2e8f9f7 264 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
<> 144:ef7eb2e8f9f7 265 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
<> 144:ef7eb2e8f9f7 266 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 267 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 268 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 269 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 270 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 271 /**
<> 144:ef7eb2e8f9f7 272 * @}
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 276 /** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions
<> 144:ef7eb2e8f9f7 277 * @{
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 281 * @brief Channel initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 282 *
<> 144:ef7eb2e8f9f7 283 @verbatim
<> 144:ef7eb2e8f9f7 284 ==============================================================================
<> 144:ef7eb2e8f9f7 285 ##### Channel initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 286 ==============================================================================
<> 144:ef7eb2e8f9f7 287 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 288 (+) Initialize the DFSDM channel.
<> 144:ef7eb2e8f9f7 289 (+) De-initialize the DFSDM channel.
<> 144:ef7eb2e8f9f7 290 @endverbatim
<> 144:ef7eb2e8f9f7 291 * @{
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /**
<> 144:ef7eb2e8f9f7 295 * @brief Initialize the DFSDM channel according to the specified parameters
<> 144:ef7eb2e8f9f7 296 * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
<> 144:ef7eb2e8f9f7 297 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 298 * @retval HAL status.
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 301 {
<> 144:ef7eb2e8f9f7 302 /* Check DFSDM Channel handle */
<> 144:ef7eb2e8f9f7 303 if(hdfsdm_channel == NULL)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Check parameters */
<> 144:ef7eb2e8f9f7 309 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 310 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));
<> 144:ef7eb2e8f9f7 311 assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));
<> 144:ef7eb2e8f9f7 312 assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));
<> 144:ef7eb2e8f9f7 313 assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));
<> 144:ef7eb2e8f9f7 314 assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));
<> 144:ef7eb2e8f9f7 315 assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));
<> 144:ef7eb2e8f9f7 316 assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));
<> 144:ef7eb2e8f9f7 317 assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
<> 144:ef7eb2e8f9f7 318 assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
<> 144:ef7eb2e8f9f7 319 assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Check that channel has not been already initialized */
<> 144:ef7eb2e8f9f7 322 if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 325 }
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Call MSP init function */
<> 144:ef7eb2e8f9f7 328 HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* Update the channel counter */
<> 144:ef7eb2e8f9f7 331 v_dfsdm1ChannelCounter++;
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Configure output serial clock and enable global DFSDM interface only for first channel */
<> 144:ef7eb2e8f9f7 334 if(v_dfsdm1ChannelCounter == 1)
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
<> 144:ef7eb2e8f9f7 337 /* Set the output serial clock source */
<> 144:ef7eb2e8f9f7 338 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
<> 144:ef7eb2e8f9f7 339 DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /* Reset clock divider */
<> 144:ef7eb2e8f9f7 342 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
<> 144:ef7eb2e8f9f7 343 if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
<> 144:ef7eb2e8f9f7 346 /* Set the output clock divider */
<> 144:ef7eb2e8f9f7 347 DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) <<
<> 144:ef7eb2e8f9f7 348 DFSDM_CHCFGR1_CLK_DIV_OFFSET);
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* enable the DFSDM global interface */
<> 144:ef7eb2e8f9f7 352 DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
<> 144:ef7eb2e8f9f7 353 }
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Set channel input parameters */
<> 144:ef7eb2e8f9f7 356 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
<> 144:ef7eb2e8f9f7 357 DFSDM_CHCFGR1_CHINSEL);
<> 144:ef7eb2e8f9f7 358 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
<> 144:ef7eb2e8f9f7 359 hdfsdm_channel->Init.Input.DataPacking |
<> 144:ef7eb2e8f9f7 360 hdfsdm_channel->Init.Input.Pins);
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /* Set serial interface parameters */
<> 144:ef7eb2e8f9f7 363 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
<> 144:ef7eb2e8f9f7 364 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
<> 144:ef7eb2e8f9f7 365 hdfsdm_channel->Init.SerialInterface.SpiClock);
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Set analog watchdog parameters */
<> 144:ef7eb2e8f9f7 368 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
<> 144:ef7eb2e8f9f7 369 hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
<> 144:ef7eb2e8f9f7 370 ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_FOSR_OFFSET));
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Set channel offset and right bit shift */
<> 144:ef7eb2e8f9f7 373 hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
<> 144:ef7eb2e8f9f7 374 hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) |
<> 144:ef7eb2e8f9f7 375 (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET));
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Enable DFSDM channel */
<> 144:ef7eb2e8f9f7 378 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Set DFSDM Channel to ready state */
<> 144:ef7eb2e8f9f7 381 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* Store channel handle in DFSDM channel handle table */
<> 144:ef7eb2e8f9f7 384 a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 return HAL_OK;
<> 144:ef7eb2e8f9f7 387 }
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @brief De-initialize the DFSDM channel.
<> 144:ef7eb2e8f9f7 391 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 392 * @retval HAL status.
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 395 {
<> 144:ef7eb2e8f9f7 396 /* Check DFSDM Channel handle */
<> 144:ef7eb2e8f9f7 397 if(hdfsdm_channel == NULL)
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /* Check parameters */
<> 144:ef7eb2e8f9f7 403 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /* Check that channel has not been already deinitialized */
<> 144:ef7eb2e8f9f7 406 if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Disable the DFSDM channel */
<> 144:ef7eb2e8f9f7 412 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /* Update the channel counter */
<> 144:ef7eb2e8f9f7 415 v_dfsdm1ChannelCounter--;
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Disable global DFSDM at deinit of last channel */
<> 144:ef7eb2e8f9f7 418 if(v_dfsdm1ChannelCounter == 0)
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Call MSP deinit function */
<> 144:ef7eb2e8f9f7 424 HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /* Set DFSDM Channel in reset state */
<> 144:ef7eb2e8f9f7 427 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Reset channel handle in DFSDM channel handle table */
<> 144:ef7eb2e8f9f7 430 a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 return HAL_OK;
<> 144:ef7eb2e8f9f7 433 }
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /**
<> 144:ef7eb2e8f9f7 436 * @brief Initialize the DFSDM channel MSP.
<> 144:ef7eb2e8f9f7 437 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 438 * @retval None
<> 144:ef7eb2e8f9f7 439 */
<> 144:ef7eb2e8f9f7 440 __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 441 {
<> 144:ef7eb2e8f9f7 442 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 443 UNUSED(hdfsdm_channel);
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /* NOTE : This function should not be modified, when the function is needed,
<> 144:ef7eb2e8f9f7 446 the HAL_DFSDM_ChannelMspInit could be implemented in the user file.
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 }
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /**
<> 144:ef7eb2e8f9f7 451 * @brief De-initialize the DFSDM channel MSP.
<> 144:ef7eb2e8f9f7 452 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 453 * @retval None
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455 __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 458 UNUSED(hdfsdm_channel);
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* NOTE : This function should not be modified, when the function is needed,
<> 144:ef7eb2e8f9f7 461 the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @}
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
<> 144:ef7eb2e8f9f7 470 * @brief Channel operation functions
<> 144:ef7eb2e8f9f7 471 *
<> 144:ef7eb2e8f9f7 472 @verbatim
<> 144:ef7eb2e8f9f7 473 ==============================================================================
<> 144:ef7eb2e8f9f7 474 ##### Channel operation functions #####
<> 144:ef7eb2e8f9f7 475 ==============================================================================
<> 144:ef7eb2e8f9f7 476 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 477 (+) Manage clock absence detector feature.
<> 144:ef7eb2e8f9f7 478 (+) Manage short circuit detector feature.
<> 144:ef7eb2e8f9f7 479 (+) Get analog watchdog value.
<> 144:ef7eb2e8f9f7 480 (+) Modify offset value.
<> 144:ef7eb2e8f9f7 481 @endverbatim
<> 144:ef7eb2e8f9f7 482 * @{
<> 144:ef7eb2e8f9f7 483 */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /**
<> 144:ef7eb2e8f9f7 486 * @brief This function allows to start clock absence detection in polling mode.
<> 144:ef7eb2e8f9f7 487 * @note Same mode has to be used for all channels.
<> 144:ef7eb2e8f9f7 488 * @note If clock is not available on this channel during 5 seconds,
<> 144:ef7eb2e8f9f7 489 * clock absence detection will not be activated and function
<> 144:ef7eb2e8f9f7 490 * will return HAL_TIMEOUT error.
<> 144:ef7eb2e8f9f7 491 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 492 * @retval HAL status
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 497 uint32_t channel;
<> 144:ef7eb2e8f9f7 498 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /* Check parameters */
<> 144:ef7eb2e8f9f7 501 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 504 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 /* Return error status */
<> 144:ef7eb2e8f9f7 507 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509 else
<> 144:ef7eb2e8f9f7 510 {
<> 144:ef7eb2e8f9f7 511 /* Get channel number from channel instance */
<> 144:ef7eb2e8f9f7 512 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Get timeout */
<> 144:ef7eb2e8f9f7 515 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /* Clear clock absence flag */
<> 144:ef7eb2e8f9f7 518 while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
<> 144:ef7eb2e8f9f7 519 {
<> 144:ef7eb2e8f9f7 520 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /* Check the Timeout */
<> 144:ef7eb2e8f9f7 523 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 /* Set timeout status */
<> 144:ef7eb2e8f9f7 526 status = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 527 break;
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 532 {
<> 144:ef7eb2e8f9f7 533 /* Start clock absence detection */
<> 144:ef7eb2e8f9f7 534 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
<> 144:ef7eb2e8f9f7 535 }
<> 144:ef7eb2e8f9f7 536 }
<> 144:ef7eb2e8f9f7 537 /* Return function status */
<> 144:ef7eb2e8f9f7 538 return status;
<> 144:ef7eb2e8f9f7 539 }
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /**
<> 144:ef7eb2e8f9f7 542 * @brief This function allows to poll for the clock absence detection.
<> 144:ef7eb2e8f9f7 543 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 544 * @param Timeout : Timeout value in milliseconds.
<> 144:ef7eb2e8f9f7 545 * @retval HAL status
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
<> 144:ef7eb2e8f9f7 548 uint32_t Timeout)
<> 144:ef7eb2e8f9f7 549 {
<> 144:ef7eb2e8f9f7 550 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 551 uint32_t channel;
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* Check parameters */
<> 144:ef7eb2e8f9f7 554 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 557 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 /* Return error status */
<> 144:ef7eb2e8f9f7 560 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562 else
<> 144:ef7eb2e8f9f7 563 {
<> 144:ef7eb2e8f9f7 564 /* Get channel number from channel instance */
<> 144:ef7eb2e8f9f7 565 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /* Get timeout */
<> 144:ef7eb2e8f9f7 568 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /* Wait clock absence detection */
<> 144:ef7eb2e8f9f7 571 while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) == 0)
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 /* Check the Timeout */
<> 144:ef7eb2e8f9f7 574 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 575 {
<> 144:ef7eb2e8f9f7 576 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 /* Return timeout status */
<> 144:ef7eb2e8f9f7 579 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 580 }
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /* Clear clock absence detection flag */
<> 144:ef7eb2e8f9f7 585 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /* Return function status */
<> 144:ef7eb2e8f9f7 588 return HAL_OK;
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590 }
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /**
<> 144:ef7eb2e8f9f7 593 * @brief This function allows to stop clock absence detection in polling mode.
<> 144:ef7eb2e8f9f7 594 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 595 * @retval HAL status
<> 144:ef7eb2e8f9f7 596 */
<> 144:ef7eb2e8f9f7 597 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 600 uint32_t channel;
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Check parameters */
<> 144:ef7eb2e8f9f7 603 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 606 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 607 {
<> 144:ef7eb2e8f9f7 608 /* Return error status */
<> 144:ef7eb2e8f9f7 609 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 610 }
<> 144:ef7eb2e8f9f7 611 else
<> 144:ef7eb2e8f9f7 612 {
<> 144:ef7eb2e8f9f7 613 /* Stop clock absence detection */
<> 144:ef7eb2e8f9f7 614 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /* Clear clock absence flag */
<> 144:ef7eb2e8f9f7 617 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 618 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 619 }
<> 144:ef7eb2e8f9f7 620 /* Return function status */
<> 144:ef7eb2e8f9f7 621 return status;
<> 144:ef7eb2e8f9f7 622 }
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /**
<> 144:ef7eb2e8f9f7 625 * @brief This function allows to start clock absence detection in interrupt mode.
<> 144:ef7eb2e8f9f7 626 * @note Same mode has to be used for all channels.
<> 144:ef7eb2e8f9f7 627 * @note If clock is not available on this channel during 5 seconds,
<> 144:ef7eb2e8f9f7 628 * clock absence detection will not be activated and function
<> 144:ef7eb2e8f9f7 629 * will return HAL_TIMEOUT error.
<> 144:ef7eb2e8f9f7 630 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 631 * @retval HAL status
<> 144:ef7eb2e8f9f7 632 */
<> 144:ef7eb2e8f9f7 633 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 634 {
<> 144:ef7eb2e8f9f7 635 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 636 uint32_t channel;
<> 144:ef7eb2e8f9f7 637 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /* Check parameters */
<> 144:ef7eb2e8f9f7 640 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 643 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 644 {
<> 144:ef7eb2e8f9f7 645 /* Return error status */
<> 144:ef7eb2e8f9f7 646 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648 else
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 /* Get channel number from channel instance */
<> 144:ef7eb2e8f9f7 651 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* Get timeout */
<> 144:ef7eb2e8f9f7 654 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /* Clear clock absence flag */
<> 144:ef7eb2e8f9f7 657 while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* Check the Timeout */
<> 144:ef7eb2e8f9f7 662 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
<> 144:ef7eb2e8f9f7 663 {
<> 144:ef7eb2e8f9f7 664 /* Set timeout status */
<> 144:ef7eb2e8f9f7 665 status = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 666 break;
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668 }
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 /* Activate clock absence detection interrupt */
<> 144:ef7eb2e8f9f7 673 DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* Start clock absence detection */
<> 144:ef7eb2e8f9f7 676 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
<> 144:ef7eb2e8f9f7 677 }
<> 144:ef7eb2e8f9f7 678 }
<> 144:ef7eb2e8f9f7 679 /* Return function status */
<> 144:ef7eb2e8f9f7 680 return status;
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /**
<> 144:ef7eb2e8f9f7 684 * @brief Clock absence detection callback.
<> 144:ef7eb2e8f9f7 685 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 686 * @retval None
<> 144:ef7eb2e8f9f7 687 */
<> 144:ef7eb2e8f9f7 688 __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 691 UNUSED(hdfsdm_channel);
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 694 the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 695 */
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /**
<> 144:ef7eb2e8f9f7 699 * @brief This function allows to stop clock absence detection in interrupt mode.
<> 144:ef7eb2e8f9f7 700 * @note Interrupt will be disabled for all channels
<> 144:ef7eb2e8f9f7 701 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 702 * @retval HAL status
<> 144:ef7eb2e8f9f7 703 */
<> 144:ef7eb2e8f9f7 704 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 707 uint32_t channel;
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /* Check parameters */
<> 144:ef7eb2e8f9f7 710 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 713 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 /* Return error status */
<> 144:ef7eb2e8f9f7 716 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 717 }
<> 144:ef7eb2e8f9f7 718 else
<> 144:ef7eb2e8f9f7 719 {
<> 144:ef7eb2e8f9f7 720 /* Stop clock absence detection */
<> 144:ef7eb2e8f9f7 721 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /* Clear clock absence flag */
<> 144:ef7eb2e8f9f7 724 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 725 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /* Disable clock absence detection interrupt */
<> 144:ef7eb2e8f9f7 728 DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730 /* Return function status */
<> 144:ef7eb2e8f9f7 731 return status;
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /**
<> 144:ef7eb2e8f9f7 735 * @brief This function allows to start short circuit detection in polling mode.
<> 144:ef7eb2e8f9f7 736 * @note Same mode has to be used for all channels
<> 144:ef7eb2e8f9f7 737 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 738 * @param Threshold : Short circuit detector threshold.
<> 144:ef7eb2e8f9f7 739 * This parameter must be a number between Min_Data = 0 and Max_Data = 255.
<> 144:ef7eb2e8f9f7 740 * @param BreakSignal : Break signals assigned to short circuit event.
<> 144:ef7eb2e8f9f7 741 * This parameter can be a values combination of @ref DFSDM_BreakSignals.
<> 144:ef7eb2e8f9f7 742 * @retval HAL status
<> 144:ef7eb2e8f9f7 743 */
<> 144:ef7eb2e8f9f7 744 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
<> 144:ef7eb2e8f9f7 745 uint32_t Threshold,
<> 144:ef7eb2e8f9f7 746 uint32_t BreakSignal)
<> 144:ef7eb2e8f9f7 747 {
<> 144:ef7eb2e8f9f7 748 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* Check parameters */
<> 144:ef7eb2e8f9f7 751 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 752 assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
<> 144:ef7eb2e8f9f7 753 assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 756 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 757 {
<> 144:ef7eb2e8f9f7 758 /* Return error status */
<> 144:ef7eb2e8f9f7 759 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761 else
<> 144:ef7eb2e8f9f7 762 {
<> 144:ef7eb2e8f9f7 763 /* Configure threshold and break signals */
<> 144:ef7eb2e8f9f7 764 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
<> 144:ef7eb2e8f9f7 765 hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
<> 144:ef7eb2e8f9f7 766 Threshold);
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /* Start short circuit detection */
<> 144:ef7eb2e8f9f7 769 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
<> 144:ef7eb2e8f9f7 770 }
<> 144:ef7eb2e8f9f7 771 /* Return function status */
<> 144:ef7eb2e8f9f7 772 return status;
<> 144:ef7eb2e8f9f7 773 }
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /**
<> 144:ef7eb2e8f9f7 776 * @brief This function allows to poll for the short circuit detection.
<> 144:ef7eb2e8f9f7 777 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 778 * @param Timeout : Timeout value in milliseconds.
<> 144:ef7eb2e8f9f7 779 * @retval HAL status
<> 144:ef7eb2e8f9f7 780 */
<> 144:ef7eb2e8f9f7 781 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
<> 144:ef7eb2e8f9f7 782 uint32_t Timeout)
<> 144:ef7eb2e8f9f7 783 {
<> 144:ef7eb2e8f9f7 784 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 785 uint32_t channel;
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /* Check parameters */
<> 144:ef7eb2e8f9f7 788 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 791 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 792 {
<> 144:ef7eb2e8f9f7 793 /* Return error status */
<> 144:ef7eb2e8f9f7 794 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 795 }
<> 144:ef7eb2e8f9f7 796 else
<> 144:ef7eb2e8f9f7 797 {
<> 144:ef7eb2e8f9f7 798 /* Get channel number from channel instance */
<> 144:ef7eb2e8f9f7 799 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /* Get timeout */
<> 144:ef7eb2e8f9f7 802 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Wait short circuit detection */
<> 144:ef7eb2e8f9f7 805 while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0)
<> 144:ef7eb2e8f9f7 806 {
<> 144:ef7eb2e8f9f7 807 /* Check the Timeout */
<> 144:ef7eb2e8f9f7 808 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 809 {
<> 144:ef7eb2e8f9f7 810 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 811 {
<> 144:ef7eb2e8f9f7 812 /* Return timeout status */
<> 144:ef7eb2e8f9f7 813 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815 }
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /* Clear short circuit detection flag */
<> 144:ef7eb2e8f9f7 819 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /* Return function status */
<> 144:ef7eb2e8f9f7 822 return HAL_OK;
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824 }
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 /**
<> 144:ef7eb2e8f9f7 827 * @brief This function allows to stop short circuit detection in polling mode.
<> 144:ef7eb2e8f9f7 828 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 829 * @retval HAL status
<> 144:ef7eb2e8f9f7 830 */
<> 144:ef7eb2e8f9f7 831 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 832 {
<> 144:ef7eb2e8f9f7 833 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 834 uint32_t channel;
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Check parameters */
<> 144:ef7eb2e8f9f7 837 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 840 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 841 {
<> 144:ef7eb2e8f9f7 842 /* Return error status */
<> 144:ef7eb2e8f9f7 843 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 844 }
<> 144:ef7eb2e8f9f7 845 else
<> 144:ef7eb2e8f9f7 846 {
<> 144:ef7eb2e8f9f7 847 /* Stop short circuit detection */
<> 144:ef7eb2e8f9f7 848 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /* Clear short circuit detection flag */
<> 144:ef7eb2e8f9f7 851 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 852 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 853 }
<> 144:ef7eb2e8f9f7 854 /* Return function status */
<> 144:ef7eb2e8f9f7 855 return status;
<> 144:ef7eb2e8f9f7 856 }
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /**
<> 144:ef7eb2e8f9f7 859 * @brief This function allows to start short circuit detection in interrupt mode.
<> 144:ef7eb2e8f9f7 860 * @note Same mode has to be used for all channels
<> 144:ef7eb2e8f9f7 861 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 862 * @param Threshold : Short circuit detector threshold.
<> 144:ef7eb2e8f9f7 863 * This parameter must be a number between Min_Data = 0 and Max_Data = 255.
<> 144:ef7eb2e8f9f7 864 * @param BreakSignal : Break signals assigned to short circuit event.
<> 144:ef7eb2e8f9f7 865 * This parameter can be a values combination of @ref DFSDM_BreakSignals.
<> 144:ef7eb2e8f9f7 866 * @retval HAL status
<> 144:ef7eb2e8f9f7 867 */
<> 144:ef7eb2e8f9f7 868 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
<> 144:ef7eb2e8f9f7 869 uint32_t Threshold,
<> 144:ef7eb2e8f9f7 870 uint32_t BreakSignal)
<> 144:ef7eb2e8f9f7 871 {
<> 144:ef7eb2e8f9f7 872 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /* Check parameters */
<> 144:ef7eb2e8f9f7 875 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 876 assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
<> 144:ef7eb2e8f9f7 877 assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 880 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 881 {
<> 144:ef7eb2e8f9f7 882 /* Return error status */
<> 144:ef7eb2e8f9f7 883 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 884 }
<> 144:ef7eb2e8f9f7 885 else
<> 144:ef7eb2e8f9f7 886 {
<> 144:ef7eb2e8f9f7 887 /* Activate short circuit detection interrupt */
<> 144:ef7eb2e8f9f7 888 DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /* Configure threshold and break signals */
<> 144:ef7eb2e8f9f7 891 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
<> 144:ef7eb2e8f9f7 892 hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
<> 144:ef7eb2e8f9f7 893 Threshold);
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /* Start short circuit detection */
<> 144:ef7eb2e8f9f7 896 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
<> 144:ef7eb2e8f9f7 897 }
<> 144:ef7eb2e8f9f7 898 /* Return function status */
<> 144:ef7eb2e8f9f7 899 return status;
<> 144:ef7eb2e8f9f7 900 }
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 /**
<> 144:ef7eb2e8f9f7 903 * @brief Short circuit detection callback.
<> 144:ef7eb2e8f9f7 904 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 905 * @retval None
<> 144:ef7eb2e8f9f7 906 */
<> 144:ef7eb2e8f9f7 907 __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 908 {
<> 144:ef7eb2e8f9f7 909 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 910 UNUSED(hdfsdm_channel);
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 913 the HAL_DFSDM_ChannelScdCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 914 */
<> 144:ef7eb2e8f9f7 915 }
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /**
<> 144:ef7eb2e8f9f7 918 * @brief This function allows to stop short circuit detection in interrupt mode.
<> 144:ef7eb2e8f9f7 919 * @note Interrupt will be disabled for all channels
<> 144:ef7eb2e8f9f7 920 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 921 * @retval HAL status
<> 144:ef7eb2e8f9f7 922 */
<> 144:ef7eb2e8f9f7 923 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 924 {
<> 144:ef7eb2e8f9f7 925 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 926 uint32_t channel;
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 /* Check parameters */
<> 144:ef7eb2e8f9f7 929 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 932 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 933 {
<> 144:ef7eb2e8f9f7 934 /* Return error status */
<> 144:ef7eb2e8f9f7 935 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 936 }
<> 144:ef7eb2e8f9f7 937 else
<> 144:ef7eb2e8f9f7 938 {
<> 144:ef7eb2e8f9f7 939 /* Stop short circuit detection */
<> 144:ef7eb2e8f9f7 940 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 /* Clear short circuit detection flag */
<> 144:ef7eb2e8f9f7 943 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 944 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 /* Disable short circuit detection interrupt */
<> 144:ef7eb2e8f9f7 947 DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
<> 144:ef7eb2e8f9f7 948 }
<> 144:ef7eb2e8f9f7 949 /* Return function status */
<> 144:ef7eb2e8f9f7 950 return status;
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /**
<> 144:ef7eb2e8f9f7 954 * @brief This function allows to get channel analog watchdog value.
<> 144:ef7eb2e8f9f7 955 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 956 * @retval Channel analog watchdog value.
<> 144:ef7eb2e8f9f7 957 */
<> 144:ef7eb2e8f9f7 958 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 959 {
<> 144:ef7eb2e8f9f7 960 return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
<> 144:ef7eb2e8f9f7 961 }
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 /**
<> 144:ef7eb2e8f9f7 964 * @brief This function allows to modify channel offset value.
<> 144:ef7eb2e8f9f7 965 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 966 * @param Offset : DFSDM channel offset.
<> 144:ef7eb2e8f9f7 967 * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
<> 144:ef7eb2e8f9f7 968 * @retval HAL status.
<> 144:ef7eb2e8f9f7 969 */
<> 144:ef7eb2e8f9f7 970 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
<> 144:ef7eb2e8f9f7 971 int32_t Offset)
<> 144:ef7eb2e8f9f7 972 {
<> 144:ef7eb2e8f9f7 973 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 /* Check parameters */
<> 144:ef7eb2e8f9f7 976 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 977 assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 980 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 981 {
<> 144:ef7eb2e8f9f7 982 /* Return error status */
<> 144:ef7eb2e8f9f7 983 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 984 }
<> 144:ef7eb2e8f9f7 985 else
<> 144:ef7eb2e8f9f7 986 {
<> 144:ef7eb2e8f9f7 987 /* Modify channel offset */
<> 144:ef7eb2e8f9f7 988 hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
<> 144:ef7eb2e8f9f7 989 hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET);
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991 /* Return function status */
<> 144:ef7eb2e8f9f7 992 return status;
<> 144:ef7eb2e8f9f7 993 }
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 /**
<> 144:ef7eb2e8f9f7 996 * @}
<> 144:ef7eb2e8f9f7 997 */
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
<> 144:ef7eb2e8f9f7 1000 * @brief Channel state function
<> 144:ef7eb2e8f9f7 1001 *
<> 144:ef7eb2e8f9f7 1002 @verbatim
<> 144:ef7eb2e8f9f7 1003 ==============================================================================
<> 144:ef7eb2e8f9f7 1004 ##### Channel state function #####
<> 144:ef7eb2e8f9f7 1005 ==============================================================================
<> 144:ef7eb2e8f9f7 1006 [..] This section provides function allowing to:
<> 144:ef7eb2e8f9f7 1007 (+) Get channel handle state.
<> 144:ef7eb2e8f9f7 1008 @endverbatim
<> 144:ef7eb2e8f9f7 1009 * @{
<> 144:ef7eb2e8f9f7 1010 */
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /**
<> 144:ef7eb2e8f9f7 1013 * @brief This function allows to get the current DFSDM channel handle state.
<> 144:ef7eb2e8f9f7 1014 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 1015 * @retval DFSDM channel state.
<> 144:ef7eb2e8f9f7 1016 */
<> 144:ef7eb2e8f9f7 1017 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 1018 {
<> 144:ef7eb2e8f9f7 1019 /* Return DFSDM channel handle state */
<> 144:ef7eb2e8f9f7 1020 return hdfsdm_channel->State;
<> 144:ef7eb2e8f9f7 1021 }
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /**
<> 144:ef7eb2e8f9f7 1024 * @}
<> 144:ef7eb2e8f9f7 1025 */
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 1028 * @brief Filter initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 1029 *
<> 144:ef7eb2e8f9f7 1030 @verbatim
<> 144:ef7eb2e8f9f7 1031 ==============================================================================
<> 144:ef7eb2e8f9f7 1032 ##### Filter initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 1033 ==============================================================================
<> 144:ef7eb2e8f9f7 1034 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1035 (+) Initialize the DFSDM filter.
<> 144:ef7eb2e8f9f7 1036 (+) De-initialize the DFSDM filter.
<> 144:ef7eb2e8f9f7 1037 @endverbatim
<> 144:ef7eb2e8f9f7 1038 * @{
<> 144:ef7eb2e8f9f7 1039 */
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 /**
<> 144:ef7eb2e8f9f7 1042 * @brief Initialize the DFSDM filter according to the specified parameters
<> 144:ef7eb2e8f9f7 1043 * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
<> 144:ef7eb2e8f9f7 1044 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1045 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1046 */
<> 144:ef7eb2e8f9f7 1047 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1048 {
<> 144:ef7eb2e8f9f7 1049 /* Check DFSDM Channel handle */
<> 144:ef7eb2e8f9f7 1050 if(hdfsdm_filter == NULL)
<> 144:ef7eb2e8f9f7 1051 {
<> 144:ef7eb2e8f9f7 1052 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1053 }
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 /* Check parameters */
<> 144:ef7eb2e8f9f7 1056 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1057 assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));
<> 144:ef7eb2e8f9f7 1058 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));
<> 144:ef7eb2e8f9f7 1059 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));
<> 144:ef7eb2e8f9f7 1060 assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));
<> 144:ef7eb2e8f9f7 1061 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));
<> 144:ef7eb2e8f9f7 1062 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));
<> 144:ef7eb2e8f9f7 1063 assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));
<> 144:ef7eb2e8f9f7 1064 assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));
<> 144:ef7eb2e8f9f7 1065 assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /* Check parameters compatibility */
<> 144:ef7eb2e8f9f7 1068 if((hdfsdm_filter->Instance == DFSDM1_Filter0) &&
<> 144:ef7eb2e8f9f7 1069 ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
<> 144:ef7eb2e8f9f7 1070 (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
<> 144:ef7eb2e8f9f7 1071 {
<> 144:ef7eb2e8f9f7 1072 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* Initialize DFSDM filter variables with default values */
<> 144:ef7eb2e8f9f7 1076 hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF;
<> 144:ef7eb2e8f9f7 1077 hdfsdm_filter->InjectedChannelsNbr = 1;
<> 144:ef7eb2e8f9f7 1078 hdfsdm_filter->InjConvRemaining = 1;
<> 144:ef7eb2e8f9f7 1079 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 /* Call MSP init function */
<> 144:ef7eb2e8f9f7 1082 HAL_DFSDM_FilterMspInit(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1083
<> 144:ef7eb2e8f9f7 1084 /* Set regular parameters */
<> 144:ef7eb2e8f9f7 1085 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
<> 144:ef7eb2e8f9f7 1086 if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)
<> 144:ef7eb2e8f9f7 1087 {
<> 144:ef7eb2e8f9f7 1088 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;
<> 144:ef7eb2e8f9f7 1089 }
<> 144:ef7eb2e8f9f7 1090 else
<> 144:ef7eb2e8f9f7 1091 {
<> 144:ef7eb2e8f9f7 1092 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
<> 144:ef7eb2e8f9f7 1093 }
<> 144:ef7eb2e8f9f7 1094
<> 144:ef7eb2e8f9f7 1095 if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)
<> 144:ef7eb2e8f9f7 1096 {
<> 144:ef7eb2e8f9f7 1097 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;
<> 144:ef7eb2e8f9f7 1098 }
<> 144:ef7eb2e8f9f7 1099 else
<> 144:ef7eb2e8f9f7 1100 {
<> 144:ef7eb2e8f9f7 1101 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);
<> 144:ef7eb2e8f9f7 1102 }
<> 144:ef7eb2e8f9f7 1103
<> 144:ef7eb2e8f9f7 1104 /* Set injected parameters */
<> 144:ef7eb2e8f9f7 1105 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);
<> 144:ef7eb2e8f9f7 1106 if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)
<> 144:ef7eb2e8f9f7 1107 {
<> 144:ef7eb2e8f9f7 1108 assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));
<> 144:ef7eb2e8f9f7 1109 assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));
<> 144:ef7eb2e8f9f7 1110 hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);
<> 144:ef7eb2e8f9f7 1111 }
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)
<> 144:ef7eb2e8f9f7 1114 {
<> 144:ef7eb2e8f9f7 1115 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;
<> 144:ef7eb2e8f9f7 1116 }
<> 144:ef7eb2e8f9f7 1117 else
<> 144:ef7eb2e8f9f7 1118 {
<> 144:ef7eb2e8f9f7 1119 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122 if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)
<> 144:ef7eb2e8f9f7 1123 {
<> 144:ef7eb2e8f9f7 1124 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;
<> 144:ef7eb2e8f9f7 1125 }
<> 144:ef7eb2e8f9f7 1126 else
<> 144:ef7eb2e8f9f7 1127 {
<> 144:ef7eb2e8f9f7 1128 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
<> 144:ef7eb2e8f9f7 1129 }
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /* Set filter parameters */
<> 144:ef7eb2e8f9f7 1132 hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
<> 144:ef7eb2e8f9f7 1133 hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
<> 144:ef7eb2e8f9f7 1134 ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_OFFSET) |
<> 144:ef7eb2e8f9f7 1135 (hdfsdm_filter->Init.FilterParam.IntOversampling - 1));
<> 144:ef7eb2e8f9f7 1136
<> 144:ef7eb2e8f9f7 1137 /* Store regular and injected triggers and injected scan mode*/
<> 144:ef7eb2e8f9f7 1138 hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger;
<> 144:ef7eb2e8f9f7 1139 hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger;
<> 144:ef7eb2e8f9f7 1140 hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
<> 144:ef7eb2e8f9f7 1141 hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
<> 144:ef7eb2e8f9f7 1142
<> 144:ef7eb2e8f9f7 1143 /* Enable DFSDM filter */
<> 144:ef7eb2e8f9f7 1144 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 /* Set DFSDM filter to ready state */
<> 144:ef7eb2e8f9f7 1147 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 return HAL_OK;
<> 144:ef7eb2e8f9f7 1150 }
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 /**
<> 144:ef7eb2e8f9f7 1153 * @brief De-initializes the DFSDM filter.
<> 144:ef7eb2e8f9f7 1154 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1155 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1156 */
<> 144:ef7eb2e8f9f7 1157 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1158 {
<> 144:ef7eb2e8f9f7 1159 /* Check DFSDM filter handle */
<> 144:ef7eb2e8f9f7 1160 if(hdfsdm_filter == NULL)
<> 144:ef7eb2e8f9f7 1161 {
<> 144:ef7eb2e8f9f7 1162 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1163 }
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 /* Check parameters */
<> 144:ef7eb2e8f9f7 1166 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1167
<> 144:ef7eb2e8f9f7 1168 /* Disable the DFSDM filter */
<> 144:ef7eb2e8f9f7 1169 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /* Call MSP deinit function */
<> 144:ef7eb2e8f9f7 1172 HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /* Set DFSDM filter in reset state */
<> 144:ef7eb2e8f9f7 1175 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 return HAL_OK;
<> 144:ef7eb2e8f9f7 1178 }
<> 144:ef7eb2e8f9f7 1179
<> 144:ef7eb2e8f9f7 1180 /**
<> 144:ef7eb2e8f9f7 1181 * @brief Initializes the DFSDM filter MSP.
<> 144:ef7eb2e8f9f7 1182 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1183 * @retval None
<> 144:ef7eb2e8f9f7 1184 */
<> 144:ef7eb2e8f9f7 1185 __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1186 {
<> 144:ef7eb2e8f9f7 1187 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1188 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 /* NOTE : This function should not be modified, when the function is needed,
<> 144:ef7eb2e8f9f7 1191 the HAL_DFSDM_FilterMspInit could be implemented in the user file.
<> 144:ef7eb2e8f9f7 1192 */
<> 144:ef7eb2e8f9f7 1193 }
<> 144:ef7eb2e8f9f7 1194
<> 144:ef7eb2e8f9f7 1195 /**
<> 144:ef7eb2e8f9f7 1196 * @brief De-initializes the DFSDM filter MSP.
<> 144:ef7eb2e8f9f7 1197 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1198 * @retval None
<> 144:ef7eb2e8f9f7 1199 */
<> 144:ef7eb2e8f9f7 1200 __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1201 {
<> 144:ef7eb2e8f9f7 1202 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1203 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 /* NOTE : This function should not be modified, when the function is needed,
<> 144:ef7eb2e8f9f7 1206 the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.
<> 144:ef7eb2e8f9f7 1207 */
<> 144:ef7eb2e8f9f7 1208 }
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210 /**
<> 144:ef7eb2e8f9f7 1211 * @}
<> 144:ef7eb2e8f9f7 1212 */
<> 144:ef7eb2e8f9f7 1213
<> 144:ef7eb2e8f9f7 1214 /** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
<> 144:ef7eb2e8f9f7 1215 * @brief Filter control functions
<> 144:ef7eb2e8f9f7 1216 *
<> 144:ef7eb2e8f9f7 1217 @verbatim
<> 144:ef7eb2e8f9f7 1218 ==============================================================================
<> 144:ef7eb2e8f9f7 1219 ##### Filter control functions #####
<> 144:ef7eb2e8f9f7 1220 ==============================================================================
<> 144:ef7eb2e8f9f7 1221 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1222 (+) Select channel and enable/disable continuous mode for regular conversion.
<> 144:ef7eb2e8f9f7 1223 (+) Select channels for injected conversion.
<> 144:ef7eb2e8f9f7 1224 @endverbatim
<> 144:ef7eb2e8f9f7 1225 * @{
<> 144:ef7eb2e8f9f7 1226 */
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 /**
<> 144:ef7eb2e8f9f7 1229 * @brief This function allows to select channel and to enable/disable
<> 144:ef7eb2e8f9f7 1230 * continuous mode for regular conversion.
<> 144:ef7eb2e8f9f7 1231 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1232 * @param Channel : Channel for regular conversion.
<> 144:ef7eb2e8f9f7 1233 * This parameter can be a value of @ref DFSDM_Channel_Selection.
<> 144:ef7eb2e8f9f7 1234 * @param ContinuousMode : Enable/disable continuous mode for regular conversion.
<> 144:ef7eb2e8f9f7 1235 * This parameter can be a value of @ref DFSDM_ContinuousMode.
<> 144:ef7eb2e8f9f7 1236 * @retval HAL status
<> 144:ef7eb2e8f9f7 1237 */
<> 144:ef7eb2e8f9f7 1238 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1239 uint32_t Channel,
<> 144:ef7eb2e8f9f7 1240 uint32_t ContinuousMode)
<> 144:ef7eb2e8f9f7 1241 {
<> 144:ef7eb2e8f9f7 1242 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1243
<> 144:ef7eb2e8f9f7 1244 /* Check parameters */
<> 144:ef7eb2e8f9f7 1245 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1246 assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 1247 assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1250 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
<> 144:ef7eb2e8f9f7 1251 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
<> 144:ef7eb2e8f9f7 1252 {
<> 144:ef7eb2e8f9f7 1253 /* Configure channel and continuous mode for regular conversion */
<> 144:ef7eb2e8f9f7 1254 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
<> 144:ef7eb2e8f9f7 1255 if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
<> 144:ef7eb2e8f9f7 1256 {
<> 144:ef7eb2e8f9f7 1257 hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
<> 144:ef7eb2e8f9f7 1258 DFSDM_FLTCR1_RCONT);
<> 144:ef7eb2e8f9f7 1259 }
<> 144:ef7eb2e8f9f7 1260 else
<> 144:ef7eb2e8f9f7 1261 {
<> 144:ef7eb2e8f9f7 1262 hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);
<> 144:ef7eb2e8f9f7 1263 }
<> 144:ef7eb2e8f9f7 1264 /* Store continuous mode information */
<> 144:ef7eb2e8f9f7 1265 hdfsdm_filter->RegularContMode = ContinuousMode;
<> 144:ef7eb2e8f9f7 1266 }
<> 144:ef7eb2e8f9f7 1267 else
<> 144:ef7eb2e8f9f7 1268 {
<> 144:ef7eb2e8f9f7 1269 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1270 }
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Return function status */
<> 144:ef7eb2e8f9f7 1273 return status;
<> 144:ef7eb2e8f9f7 1274 }
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 /**
<> 144:ef7eb2e8f9f7 1277 * @brief This function allows to select channels for injected conversion.
<> 144:ef7eb2e8f9f7 1278 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1279 * @param Channel : Channels for injected conversion.
<> 144:ef7eb2e8f9f7 1280 * This parameter can be a values combination of @ref DFSDM_Channel_Selection.
<> 144:ef7eb2e8f9f7 1281 * @retval HAL status
<> 144:ef7eb2e8f9f7 1282 */
<> 144:ef7eb2e8f9f7 1283 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1284 uint32_t Channel)
<> 144:ef7eb2e8f9f7 1285 {
<> 144:ef7eb2e8f9f7 1286 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 /* Check parameters */
<> 144:ef7eb2e8f9f7 1289 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1290 assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 1291
<> 144:ef7eb2e8f9f7 1292 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1293 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
<> 144:ef7eb2e8f9f7 1294 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
<> 144:ef7eb2e8f9f7 1295 {
<> 144:ef7eb2e8f9f7 1296 /* Configure channel for injected conversion */
<> 144:ef7eb2e8f9f7 1297 hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
<> 144:ef7eb2e8f9f7 1298 /* Store number of injected channels */
<> 144:ef7eb2e8f9f7 1299 hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
<> 144:ef7eb2e8f9f7 1300 /* Update number of injected channels remaining */
<> 144:ef7eb2e8f9f7 1301 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
<> 144:ef7eb2e8f9f7 1302 hdfsdm_filter->InjectedChannelsNbr : 1;
<> 144:ef7eb2e8f9f7 1303 }
<> 144:ef7eb2e8f9f7 1304 else
<> 144:ef7eb2e8f9f7 1305 {
<> 144:ef7eb2e8f9f7 1306 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1307 }
<> 144:ef7eb2e8f9f7 1308 /* Return function status */
<> 144:ef7eb2e8f9f7 1309 return status;
<> 144:ef7eb2e8f9f7 1310 }
<> 144:ef7eb2e8f9f7 1311
<> 144:ef7eb2e8f9f7 1312 /**
<> 144:ef7eb2e8f9f7 1313 * @}
<> 144:ef7eb2e8f9f7 1314 */
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
<> 144:ef7eb2e8f9f7 1317 * @brief Filter operation functions
<> 144:ef7eb2e8f9f7 1318 *
<> 144:ef7eb2e8f9f7 1319 @verbatim
<> 144:ef7eb2e8f9f7 1320 ==============================================================================
<> 144:ef7eb2e8f9f7 1321 ##### Filter operation functions #####
<> 144:ef7eb2e8f9f7 1322 ==============================================================================
<> 144:ef7eb2e8f9f7 1323 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1324 (+) Start conversion of regular/injected channel.
<> 144:ef7eb2e8f9f7 1325 (+) Poll for the end of regular/injected conversion.
<> 144:ef7eb2e8f9f7 1326 (+) Stop conversion of regular/injected channel.
<> 144:ef7eb2e8f9f7 1327 (+) Start conversion of regular/injected channel and enable interrupt.
<> 144:ef7eb2e8f9f7 1328 (+) Call the callback functions at the end of regular/injected conversions.
<> 144:ef7eb2e8f9f7 1329 (+) Stop conversion of regular/injected channel and disable interrupt.
<> 144:ef7eb2e8f9f7 1330 (+) Start conversion of regular/injected channel and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1331 (+) Stop conversion of regular/injected channel and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1332 (+) Start analog watchdog and enable interrupt.
<> 144:ef7eb2e8f9f7 1333 (+) Call the callback function when analog watchdog occurs.
<> 144:ef7eb2e8f9f7 1334 (+) Stop analog watchdog and disable interrupt.
<> 144:ef7eb2e8f9f7 1335 (+) Start extreme detector.
<> 144:ef7eb2e8f9f7 1336 (+) Stop extreme detector.
<> 144:ef7eb2e8f9f7 1337 (+) Get result of regular channel conversion.
<> 144:ef7eb2e8f9f7 1338 (+) Get result of injected channel conversion.
<> 144:ef7eb2e8f9f7 1339 (+) Get extreme detector maximum and minimum values.
<> 144:ef7eb2e8f9f7 1340 (+) Get conversion time.
<> 144:ef7eb2e8f9f7 1341 (+) Handle DFSDM interrupt request.
<> 144:ef7eb2e8f9f7 1342 @endverbatim
<> 144:ef7eb2e8f9f7 1343 * @{
<> 144:ef7eb2e8f9f7 1344 */
<> 144:ef7eb2e8f9f7 1345
<> 144:ef7eb2e8f9f7 1346 /**
<> 144:ef7eb2e8f9f7 1347 * @brief This function allows to start regular conversion in polling mode.
<> 144:ef7eb2e8f9f7 1348 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1349 * in idle state or if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1350 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1351 * @retval HAL status
<> 144:ef7eb2e8f9f7 1352 */
<> 144:ef7eb2e8f9f7 1353 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1354 {
<> 144:ef7eb2e8f9f7 1355 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1356
<> 144:ef7eb2e8f9f7 1357 /* Check parameters */
<> 144:ef7eb2e8f9f7 1358 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1359
<> 144:ef7eb2e8f9f7 1360 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1361 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1362 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
<> 144:ef7eb2e8f9f7 1363 {
<> 144:ef7eb2e8f9f7 1364 /* Start regular conversion */
<> 144:ef7eb2e8f9f7 1365 DFSDM_RegConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1366 }
<> 144:ef7eb2e8f9f7 1367 else
<> 144:ef7eb2e8f9f7 1368 {
<> 144:ef7eb2e8f9f7 1369 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1370 }
<> 144:ef7eb2e8f9f7 1371 /* Return function status */
<> 144:ef7eb2e8f9f7 1372 return status;
<> 144:ef7eb2e8f9f7 1373 }
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 /**
<> 144:ef7eb2e8f9f7 1376 * @brief This function allows to poll for the end of regular conversion.
<> 144:ef7eb2e8f9f7 1377 * @note This function should be called only if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1378 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1379 * @param Timeout : Timeout value in milliseconds.
<> 144:ef7eb2e8f9f7 1380 * @retval HAL status
<> 144:ef7eb2e8f9f7 1381 */
<> 144:ef7eb2e8f9f7 1382 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1383 uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1384 {
<> 144:ef7eb2e8f9f7 1385 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /* Check parameters */
<> 144:ef7eb2e8f9f7 1388 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1391 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
<> 144:ef7eb2e8f9f7 1392 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1393 {
<> 144:ef7eb2e8f9f7 1394 /* Return error status */
<> 144:ef7eb2e8f9f7 1395 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1396 }
<> 144:ef7eb2e8f9f7 1397 else
<> 144:ef7eb2e8f9f7 1398 {
<> 144:ef7eb2e8f9f7 1399 /* Get timeout */
<> 144:ef7eb2e8f9f7 1400 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 /* Wait end of regular conversion */
<> 144:ef7eb2e8f9f7 1403 while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
<> 144:ef7eb2e8f9f7 1404 {
<> 144:ef7eb2e8f9f7 1405 /* Check the Timeout */
<> 144:ef7eb2e8f9f7 1406 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1407 {
<> 144:ef7eb2e8f9f7 1408 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1409 {
<> 144:ef7eb2e8f9f7 1410 /* Return timeout status */
<> 144:ef7eb2e8f9f7 1411 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1412 }
<> 144:ef7eb2e8f9f7 1413 }
<> 144:ef7eb2e8f9f7 1414 }
<> 144:ef7eb2e8f9f7 1415 /* Check if overrun occurs */
<> 144:ef7eb2e8f9f7 1416 if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)
<> 144:ef7eb2e8f9f7 1417 {
<> 144:ef7eb2e8f9f7 1418 /* Update error code and call error callback */
<> 144:ef7eb2e8f9f7 1419 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
<> 144:ef7eb2e8f9f7 1420 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1421
<> 144:ef7eb2e8f9f7 1422 /* Clear regular overrun flag */
<> 144:ef7eb2e8f9f7 1423 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
<> 144:ef7eb2e8f9f7 1424 }
<> 144:ef7eb2e8f9f7 1425 /* Update DFSDM filter state only if not continuous conversion and SW trigger */
<> 144:ef7eb2e8f9f7 1426 if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
<> 144:ef7eb2e8f9f7 1427 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
<> 144:ef7eb2e8f9f7 1428 {
<> 144:ef7eb2e8f9f7 1429 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
<> 144:ef7eb2e8f9f7 1430 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
<> 144:ef7eb2e8f9f7 1431 }
<> 144:ef7eb2e8f9f7 1432 /* Return function status */
<> 144:ef7eb2e8f9f7 1433 return HAL_OK;
<> 144:ef7eb2e8f9f7 1434 }
<> 144:ef7eb2e8f9f7 1435 }
<> 144:ef7eb2e8f9f7 1436
<> 144:ef7eb2e8f9f7 1437 /**
<> 144:ef7eb2e8f9f7 1438 * @brief This function allows to stop regular conversion in polling mode.
<> 144:ef7eb2e8f9f7 1439 * @note This function should be called only if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1440 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1441 * @retval HAL status
<> 144:ef7eb2e8f9f7 1442 */
<> 144:ef7eb2e8f9f7 1443 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1444 {
<> 144:ef7eb2e8f9f7 1445 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1446
<> 144:ef7eb2e8f9f7 1447 /* Check parameters */
<> 144:ef7eb2e8f9f7 1448 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1449
<> 144:ef7eb2e8f9f7 1450 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1451 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
<> 144:ef7eb2e8f9f7 1452 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1453 {
<> 144:ef7eb2e8f9f7 1454 /* Return error status */
<> 144:ef7eb2e8f9f7 1455 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1456 }
<> 144:ef7eb2e8f9f7 1457 else
<> 144:ef7eb2e8f9f7 1458 {
<> 144:ef7eb2e8f9f7 1459 /* Stop regular conversion */
<> 144:ef7eb2e8f9f7 1460 DFSDM_RegConvStop(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1461 }
<> 144:ef7eb2e8f9f7 1462 /* Return function status */
<> 144:ef7eb2e8f9f7 1463 return status;
<> 144:ef7eb2e8f9f7 1464 }
<> 144:ef7eb2e8f9f7 1465
<> 144:ef7eb2e8f9f7 1466 /**
<> 144:ef7eb2e8f9f7 1467 * @brief This function allows to start regular conversion in interrupt mode.
<> 144:ef7eb2e8f9f7 1468 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1469 * in idle state or if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1470 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1471 * @retval HAL status
<> 144:ef7eb2e8f9f7 1472 */
<> 144:ef7eb2e8f9f7 1473 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1474 {
<> 144:ef7eb2e8f9f7 1475 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1476
<> 144:ef7eb2e8f9f7 1477 /* Check parameters */
<> 144:ef7eb2e8f9f7 1478 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1481 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1482 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
<> 144:ef7eb2e8f9f7 1483 {
<> 144:ef7eb2e8f9f7 1484 /* Enable interrupts for regular conversions */
<> 144:ef7eb2e8f9f7 1485 hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 /* Start regular conversion */
<> 144:ef7eb2e8f9f7 1488 DFSDM_RegConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1489 }
<> 144:ef7eb2e8f9f7 1490 else
<> 144:ef7eb2e8f9f7 1491 {
<> 144:ef7eb2e8f9f7 1492 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1493 }
<> 144:ef7eb2e8f9f7 1494 /* Return function status */
<> 144:ef7eb2e8f9f7 1495 return status;
<> 144:ef7eb2e8f9f7 1496 }
<> 144:ef7eb2e8f9f7 1497
<> 144:ef7eb2e8f9f7 1498 /**
<> 144:ef7eb2e8f9f7 1499 * @brief This function allows to stop regular conversion in interrupt mode.
<> 144:ef7eb2e8f9f7 1500 * @note This function should be called only if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1501 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1502 * @retval HAL status
<> 144:ef7eb2e8f9f7 1503 */
<> 144:ef7eb2e8f9f7 1504 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1505 {
<> 144:ef7eb2e8f9f7 1506 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1507
<> 144:ef7eb2e8f9f7 1508 /* Check parameters */
<> 144:ef7eb2e8f9f7 1509 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1510
<> 144:ef7eb2e8f9f7 1511 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1512 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
<> 144:ef7eb2e8f9f7 1513 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1514 {
<> 144:ef7eb2e8f9f7 1515 /* Return error status */
<> 144:ef7eb2e8f9f7 1516 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1517 }
<> 144:ef7eb2e8f9f7 1518 else
<> 144:ef7eb2e8f9f7 1519 {
<> 144:ef7eb2e8f9f7 1520 /* Disable interrupts for regular conversions */
<> 144:ef7eb2e8f9f7 1521 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
<> 144:ef7eb2e8f9f7 1522
<> 144:ef7eb2e8f9f7 1523 /* Stop regular conversion */
<> 144:ef7eb2e8f9f7 1524 DFSDM_RegConvStop(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1525 }
<> 144:ef7eb2e8f9f7 1526 /* Return function status */
<> 144:ef7eb2e8f9f7 1527 return status;
<> 144:ef7eb2e8f9f7 1528 }
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 /**
<> 144:ef7eb2e8f9f7 1531 * @brief This function allows to start regular conversion in DMA mode.
<> 144:ef7eb2e8f9f7 1532 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1533 * in idle state or if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1534 * Please note that data on buffer will contain signed regular conversion
<> 144:ef7eb2e8f9f7 1535 * value on 24 most significant bits and corresponding channel on 3 least
<> 144:ef7eb2e8f9f7 1536 * significant bits.
<> 144:ef7eb2e8f9f7 1537 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1538 * @param pData : The destination buffer address.
<> 144:ef7eb2e8f9f7 1539 * @param Length : The length of data to be transferred from DFSDM filter to memory.
<> 144:ef7eb2e8f9f7 1540 * @retval HAL status
<> 144:ef7eb2e8f9f7 1541 */
<> 144:ef7eb2e8f9f7 1542 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1543 int32_t *pData,
<> 144:ef7eb2e8f9f7 1544 uint32_t Length)
<> 144:ef7eb2e8f9f7 1545 {
<> 144:ef7eb2e8f9f7 1546 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 /* Check parameters */
<> 144:ef7eb2e8f9f7 1549 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1550
<> 144:ef7eb2e8f9f7 1551 /* Check destination address and length */
<> 144:ef7eb2e8f9f7 1552 if((pData == NULL) || (Length == 0))
<> 144:ef7eb2e8f9f7 1553 {
<> 144:ef7eb2e8f9f7 1554 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1555 }
<> 144:ef7eb2e8f9f7 1556 /* Check that DMA is enabled for regular conversion */
<> 144:ef7eb2e8f9f7 1557 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
<> 144:ef7eb2e8f9f7 1558 {
<> 144:ef7eb2e8f9f7 1559 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1560 }
<> 144:ef7eb2e8f9f7 1561 /* Check parameters compatibility */
<> 144:ef7eb2e8f9f7 1562 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 1563 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
<> 144:ef7eb2e8f9f7 1564 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
<> 144:ef7eb2e8f9f7 1565 (Length != 1))
<> 144:ef7eb2e8f9f7 1566 {
<> 144:ef7eb2e8f9f7 1567 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1568 }
<> 144:ef7eb2e8f9f7 1569 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 1570 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
<> 144:ef7eb2e8f9f7 1571 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
<> 144:ef7eb2e8f9f7 1572 {
<> 144:ef7eb2e8f9f7 1573 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1574 }
<> 144:ef7eb2e8f9f7 1575 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1576 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1577 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
<> 144:ef7eb2e8f9f7 1578 {
<> 144:ef7eb2e8f9f7 1579 /* Set callbacks on DMA handler */
<> 144:ef7eb2e8f9f7 1580 hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
<> 144:ef7eb2e8f9f7 1581 hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
<> 144:ef7eb2e8f9f7 1582 hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
<> 144:ef7eb2e8f9f7 1583 DFSDM_DMARegularHalfConvCplt : NULL;
<> 144:ef7eb2e8f9f7 1584
<> 144:ef7eb2e8f9f7 1585 /* Start DMA in interrupt mode */
<> 144:ef7eb2e8f9f7 1586 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
<> 144:ef7eb2e8f9f7 1587 (uint32_t) pData, Length) != HAL_OK)
<> 144:ef7eb2e8f9f7 1588 {
<> 144:ef7eb2e8f9f7 1589 /* Set DFSDM filter in error state */
<> 144:ef7eb2e8f9f7 1590 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1591 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1592 }
<> 144:ef7eb2e8f9f7 1593 else
<> 144:ef7eb2e8f9f7 1594 {
<> 144:ef7eb2e8f9f7 1595 /* Start regular conversion */
<> 144:ef7eb2e8f9f7 1596 DFSDM_RegConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1597 }
<> 144:ef7eb2e8f9f7 1598 }
<> 144:ef7eb2e8f9f7 1599 else
<> 144:ef7eb2e8f9f7 1600 {
<> 144:ef7eb2e8f9f7 1601 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1602 }
<> 144:ef7eb2e8f9f7 1603 /* Return function status */
<> 144:ef7eb2e8f9f7 1604 return status;
<> 144:ef7eb2e8f9f7 1605 }
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 /**
<> 144:ef7eb2e8f9f7 1608 * @brief This function allows to start regular conversion in DMA mode and to get
<> 144:ef7eb2e8f9f7 1609 * only the 16 most significant bits of conversion.
<> 144:ef7eb2e8f9f7 1610 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1611 * in idle state or if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1612 * Please note that data on buffer will contain signed 16 most significant
<> 144:ef7eb2e8f9f7 1613 * bits of regular conversion.
<> 144:ef7eb2e8f9f7 1614 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1615 * @param pData : The destination buffer address.
<> 144:ef7eb2e8f9f7 1616 * @param Length : The length of data to be transferred from DFSDM filter to memory.
<> 144:ef7eb2e8f9f7 1617 * @retval HAL status
<> 144:ef7eb2e8f9f7 1618 */
<> 144:ef7eb2e8f9f7 1619 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1620 int16_t *pData,
<> 144:ef7eb2e8f9f7 1621 uint32_t Length)
<> 144:ef7eb2e8f9f7 1622 {
<> 144:ef7eb2e8f9f7 1623 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1624
<> 144:ef7eb2e8f9f7 1625 /* Check parameters */
<> 144:ef7eb2e8f9f7 1626 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1627
<> 144:ef7eb2e8f9f7 1628 /* Check destination address and length */
<> 144:ef7eb2e8f9f7 1629 if((pData == NULL) || (Length == 0))
<> 144:ef7eb2e8f9f7 1630 {
<> 144:ef7eb2e8f9f7 1631 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1632 }
<> 144:ef7eb2e8f9f7 1633 /* Check that DMA is enabled for regular conversion */
<> 144:ef7eb2e8f9f7 1634 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
<> 144:ef7eb2e8f9f7 1635 {
<> 144:ef7eb2e8f9f7 1636 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1637 }
<> 144:ef7eb2e8f9f7 1638 /* Check parameters compatibility */
<> 144:ef7eb2e8f9f7 1639 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 1640 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
<> 144:ef7eb2e8f9f7 1641 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
<> 144:ef7eb2e8f9f7 1642 (Length != 1))
<> 144:ef7eb2e8f9f7 1643 {
<> 144:ef7eb2e8f9f7 1644 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1645 }
<> 144:ef7eb2e8f9f7 1646 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 1647 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
<> 144:ef7eb2e8f9f7 1648 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
<> 144:ef7eb2e8f9f7 1649 {
<> 144:ef7eb2e8f9f7 1650 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1651 }
<> 144:ef7eb2e8f9f7 1652 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1653 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1654 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
<> 144:ef7eb2e8f9f7 1655 {
<> 144:ef7eb2e8f9f7 1656 /* Set callbacks on DMA handler */
<> 144:ef7eb2e8f9f7 1657 hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
<> 144:ef7eb2e8f9f7 1658 hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
<> 144:ef7eb2e8f9f7 1659 hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
<> 144:ef7eb2e8f9f7 1660 DFSDM_DMARegularHalfConvCplt : NULL;
<> 144:ef7eb2e8f9f7 1661
<> 144:ef7eb2e8f9f7 1662 /* Start DMA in interrupt mode */
<> 144:ef7eb2e8f9f7 1663 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2, \
<> 144:ef7eb2e8f9f7 1664 (uint32_t) pData, Length) != HAL_OK)
<> 144:ef7eb2e8f9f7 1665 {
<> 144:ef7eb2e8f9f7 1666 /* Set DFSDM filter in error state */
<> 144:ef7eb2e8f9f7 1667 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1668 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1669 }
<> 144:ef7eb2e8f9f7 1670 else
<> 144:ef7eb2e8f9f7 1671 {
<> 144:ef7eb2e8f9f7 1672 /* Start regular conversion */
<> 144:ef7eb2e8f9f7 1673 DFSDM_RegConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1674 }
<> 144:ef7eb2e8f9f7 1675 }
<> 144:ef7eb2e8f9f7 1676 else
<> 144:ef7eb2e8f9f7 1677 {
<> 144:ef7eb2e8f9f7 1678 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1679 }
<> 144:ef7eb2e8f9f7 1680 /* Return function status */
<> 144:ef7eb2e8f9f7 1681 return status;
<> 144:ef7eb2e8f9f7 1682 }
<> 144:ef7eb2e8f9f7 1683
<> 144:ef7eb2e8f9f7 1684 /**
<> 144:ef7eb2e8f9f7 1685 * @brief This function allows to stop regular conversion in DMA mode.
<> 144:ef7eb2e8f9f7 1686 * @note This function should be called only if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1687 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1688 * @retval HAL status
<> 144:ef7eb2e8f9f7 1689 */
<> 144:ef7eb2e8f9f7 1690 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1691 {
<> 144:ef7eb2e8f9f7 1692 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1693
<> 144:ef7eb2e8f9f7 1694 /* Check parameters */
<> 144:ef7eb2e8f9f7 1695 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1696
<> 144:ef7eb2e8f9f7 1697 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1698 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
<> 144:ef7eb2e8f9f7 1699 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1700 {
<> 144:ef7eb2e8f9f7 1701 /* Return error status */
<> 144:ef7eb2e8f9f7 1702 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1703 }
<> 144:ef7eb2e8f9f7 1704 else
<> 144:ef7eb2e8f9f7 1705 {
<> 144:ef7eb2e8f9f7 1706 /* Stop current DMA transfer */
<> 144:ef7eb2e8f9f7 1707 if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)
<> 144:ef7eb2e8f9f7 1708 {
<> 144:ef7eb2e8f9f7 1709 /* Set DFSDM filter in error state */
<> 144:ef7eb2e8f9f7 1710 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1711 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1712 }
<> 144:ef7eb2e8f9f7 1713 else
<> 144:ef7eb2e8f9f7 1714 {
<> 144:ef7eb2e8f9f7 1715 /* Stop regular conversion */
<> 144:ef7eb2e8f9f7 1716 DFSDM_RegConvStop(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1717 }
<> 144:ef7eb2e8f9f7 1718 }
<> 144:ef7eb2e8f9f7 1719 /* Return function status */
<> 144:ef7eb2e8f9f7 1720 return status;
<> 144:ef7eb2e8f9f7 1721 }
<> 144:ef7eb2e8f9f7 1722
<> 144:ef7eb2e8f9f7 1723 /**
<> 144:ef7eb2e8f9f7 1724 * @brief This function allows to get regular conversion value.
<> 144:ef7eb2e8f9f7 1725 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1726 * @param Channel : Corresponding channel of regular conversion.
<> 144:ef7eb2e8f9f7 1727 * @retval Regular conversion value
<> 144:ef7eb2e8f9f7 1728 */
<> 144:ef7eb2e8f9f7 1729 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1730 uint32_t *Channel)
<> 144:ef7eb2e8f9f7 1731 {
<> 144:ef7eb2e8f9f7 1732 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 1733 int32_t value = 0;
<> 144:ef7eb2e8f9f7 1734
<> 144:ef7eb2e8f9f7 1735 /* Check parameters */
<> 144:ef7eb2e8f9f7 1736 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1737 assert_param(Channel != NULL);
<> 144:ef7eb2e8f9f7 1738
<> 144:ef7eb2e8f9f7 1739 /* Get value of data register for regular channel */
<> 144:ef7eb2e8f9f7 1740 reg = hdfsdm_filter->Instance->FLTRDATAR;
<> 144:ef7eb2e8f9f7 1741
<> 144:ef7eb2e8f9f7 1742 /* Extract channel and regular conversion value */
<> 144:ef7eb2e8f9f7 1743 *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
AnnaBridge 167:e84263d55307 1744 value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET);
<> 144:ef7eb2e8f9f7 1745
<> 144:ef7eb2e8f9f7 1746 /* return regular conversion value */
<> 144:ef7eb2e8f9f7 1747 return value;
<> 144:ef7eb2e8f9f7 1748 }
<> 144:ef7eb2e8f9f7 1749
<> 144:ef7eb2e8f9f7 1750 /**
<> 144:ef7eb2e8f9f7 1751 * @brief This function allows to start injected conversion in polling mode.
<> 144:ef7eb2e8f9f7 1752 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1753 * in idle state or if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1754 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1755 * @retval HAL status
<> 144:ef7eb2e8f9f7 1756 */
<> 144:ef7eb2e8f9f7 1757 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1758 {
<> 144:ef7eb2e8f9f7 1759 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1760
<> 144:ef7eb2e8f9f7 1761 /* Check parameters */
<> 144:ef7eb2e8f9f7 1762 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1763
<> 144:ef7eb2e8f9f7 1764 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1765 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1766 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
<> 144:ef7eb2e8f9f7 1767 {
<> 144:ef7eb2e8f9f7 1768 /* Start injected conversion */
<> 144:ef7eb2e8f9f7 1769 DFSDM_InjConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1770 }
<> 144:ef7eb2e8f9f7 1771 else
<> 144:ef7eb2e8f9f7 1772 {
<> 144:ef7eb2e8f9f7 1773 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1774 }
<> 144:ef7eb2e8f9f7 1775 /* Return function status */
<> 144:ef7eb2e8f9f7 1776 return status;
<> 144:ef7eb2e8f9f7 1777 }
<> 144:ef7eb2e8f9f7 1778
<> 144:ef7eb2e8f9f7 1779 /**
<> 144:ef7eb2e8f9f7 1780 * @brief This function allows to poll for the end of injected conversion.
<> 144:ef7eb2e8f9f7 1781 * @note This function should be called only if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1782 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1783 * @param Timeout : Timeout value in milliseconds.
<> 144:ef7eb2e8f9f7 1784 * @retval HAL status
<> 144:ef7eb2e8f9f7 1785 */
<> 144:ef7eb2e8f9f7 1786 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1787 uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1788 {
<> 144:ef7eb2e8f9f7 1789 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 1790
<> 144:ef7eb2e8f9f7 1791 /* Check parameters */
<> 144:ef7eb2e8f9f7 1792 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1793
<> 144:ef7eb2e8f9f7 1794 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1795 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
<> 144:ef7eb2e8f9f7 1796 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1797 {
<> 144:ef7eb2e8f9f7 1798 /* Return error status */
<> 144:ef7eb2e8f9f7 1799 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1800 }
<> 144:ef7eb2e8f9f7 1801 else
<> 144:ef7eb2e8f9f7 1802 {
<> 144:ef7eb2e8f9f7 1803 /* Get timeout */
<> 144:ef7eb2e8f9f7 1804 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1805
<> 144:ef7eb2e8f9f7 1806 /* Wait end of injected conversions */
<> 144:ef7eb2e8f9f7 1807 while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
<> 144:ef7eb2e8f9f7 1808 {
<> 144:ef7eb2e8f9f7 1809 /* Check the Timeout */
<> 144:ef7eb2e8f9f7 1810 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1811 {
<> 144:ef7eb2e8f9f7 1812 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1813 {
<> 144:ef7eb2e8f9f7 1814 /* Return timeout status */
<> 144:ef7eb2e8f9f7 1815 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1816 }
<> 144:ef7eb2e8f9f7 1817 }
<> 144:ef7eb2e8f9f7 1818 }
<> 144:ef7eb2e8f9f7 1819 /* Check if overrun occurs */
<> 144:ef7eb2e8f9f7 1820 if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)
<> 144:ef7eb2e8f9f7 1821 {
<> 144:ef7eb2e8f9f7 1822 /* Update error code and call error callback */
<> 144:ef7eb2e8f9f7 1823 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
<> 144:ef7eb2e8f9f7 1824 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1825
<> 144:ef7eb2e8f9f7 1826 /* Clear injected overrun flag */
<> 144:ef7eb2e8f9f7 1827 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
<> 144:ef7eb2e8f9f7 1828 }
<> 144:ef7eb2e8f9f7 1829
<> 144:ef7eb2e8f9f7 1830 /* Update remaining injected conversions */
<> 144:ef7eb2e8f9f7 1831 hdfsdm_filter->InjConvRemaining--;
<> 144:ef7eb2e8f9f7 1832 if(hdfsdm_filter->InjConvRemaining == 0)
<> 144:ef7eb2e8f9f7 1833 {
<> 144:ef7eb2e8f9f7 1834 /* Update DFSDM filter state only if trigger is software */
<> 144:ef7eb2e8f9f7 1835 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
<> 144:ef7eb2e8f9f7 1836 {
<> 144:ef7eb2e8f9f7 1837 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
<> 144:ef7eb2e8f9f7 1838 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
<> 144:ef7eb2e8f9f7 1839 }
<> 144:ef7eb2e8f9f7 1840
<> 144:ef7eb2e8f9f7 1841 /* end of injected sequence, reset the value */
<> 144:ef7eb2e8f9f7 1842 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
<> 144:ef7eb2e8f9f7 1843 hdfsdm_filter->InjectedChannelsNbr : 1;
<> 144:ef7eb2e8f9f7 1844 }
<> 144:ef7eb2e8f9f7 1845
<> 144:ef7eb2e8f9f7 1846 /* Return function status */
<> 144:ef7eb2e8f9f7 1847 return HAL_OK;
<> 144:ef7eb2e8f9f7 1848 }
<> 144:ef7eb2e8f9f7 1849 }
<> 144:ef7eb2e8f9f7 1850
<> 144:ef7eb2e8f9f7 1851 /**
<> 144:ef7eb2e8f9f7 1852 * @brief This function allows to stop injected conversion in polling mode.
<> 144:ef7eb2e8f9f7 1853 * @note This function should be called only if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1854 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1855 * @retval HAL status
<> 144:ef7eb2e8f9f7 1856 */
<> 144:ef7eb2e8f9f7 1857 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1858 {
<> 144:ef7eb2e8f9f7 1859 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 /* Check parameters */
<> 144:ef7eb2e8f9f7 1862 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1863
<> 144:ef7eb2e8f9f7 1864 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1865 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
<> 144:ef7eb2e8f9f7 1866 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1867 {
<> 144:ef7eb2e8f9f7 1868 /* Return error status */
<> 144:ef7eb2e8f9f7 1869 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1870 }
<> 144:ef7eb2e8f9f7 1871 else
<> 144:ef7eb2e8f9f7 1872 {
<> 144:ef7eb2e8f9f7 1873 /* Stop injected conversion */
<> 144:ef7eb2e8f9f7 1874 DFSDM_InjConvStop(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1875 }
<> 144:ef7eb2e8f9f7 1876 /* Return function status */
<> 144:ef7eb2e8f9f7 1877 return status;
<> 144:ef7eb2e8f9f7 1878 }
<> 144:ef7eb2e8f9f7 1879
<> 144:ef7eb2e8f9f7 1880 /**
<> 144:ef7eb2e8f9f7 1881 * @brief This function allows to start injected conversion in interrupt mode.
<> 144:ef7eb2e8f9f7 1882 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1883 * in idle state or if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1884 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1885 * @retval HAL status
<> 144:ef7eb2e8f9f7 1886 */
<> 144:ef7eb2e8f9f7 1887 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1888 {
<> 144:ef7eb2e8f9f7 1889 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1890
<> 144:ef7eb2e8f9f7 1891 /* Check parameters */
<> 144:ef7eb2e8f9f7 1892 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1893
<> 144:ef7eb2e8f9f7 1894 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1895 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1896 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
<> 144:ef7eb2e8f9f7 1897 {
<> 144:ef7eb2e8f9f7 1898 /* Enable interrupts for injected conversions */
<> 144:ef7eb2e8f9f7 1899 hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
<> 144:ef7eb2e8f9f7 1900
<> 144:ef7eb2e8f9f7 1901 /* Start injected conversion */
<> 144:ef7eb2e8f9f7 1902 DFSDM_InjConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1903 }
<> 144:ef7eb2e8f9f7 1904 else
<> 144:ef7eb2e8f9f7 1905 {
<> 144:ef7eb2e8f9f7 1906 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1907 }
<> 144:ef7eb2e8f9f7 1908 /* Return function status */
<> 144:ef7eb2e8f9f7 1909 return status;
<> 144:ef7eb2e8f9f7 1910 }
<> 144:ef7eb2e8f9f7 1911
<> 144:ef7eb2e8f9f7 1912 /**
<> 144:ef7eb2e8f9f7 1913 * @brief This function allows to stop injected conversion in interrupt mode.
<> 144:ef7eb2e8f9f7 1914 * @note This function should be called only if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1915 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1916 * @retval HAL status
<> 144:ef7eb2e8f9f7 1917 */
<> 144:ef7eb2e8f9f7 1918 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1919 {
<> 144:ef7eb2e8f9f7 1920 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1921
<> 144:ef7eb2e8f9f7 1922 /* Check parameters */
<> 144:ef7eb2e8f9f7 1923 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1924
<> 144:ef7eb2e8f9f7 1925 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1926 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
<> 144:ef7eb2e8f9f7 1927 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1928 {
<> 144:ef7eb2e8f9f7 1929 /* Return error status */
<> 144:ef7eb2e8f9f7 1930 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1931 }
<> 144:ef7eb2e8f9f7 1932 else
<> 144:ef7eb2e8f9f7 1933 {
<> 144:ef7eb2e8f9f7 1934 /* Disable interrupts for injected conversions */
<> 144:ef7eb2e8f9f7 1935 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
<> 144:ef7eb2e8f9f7 1936
<> 144:ef7eb2e8f9f7 1937 /* Stop injected conversion */
<> 144:ef7eb2e8f9f7 1938 DFSDM_InjConvStop(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1939 }
<> 144:ef7eb2e8f9f7 1940 /* Return function status */
<> 144:ef7eb2e8f9f7 1941 return status;
<> 144:ef7eb2e8f9f7 1942 }
<> 144:ef7eb2e8f9f7 1943
<> 144:ef7eb2e8f9f7 1944 /**
<> 144:ef7eb2e8f9f7 1945 * @brief This function allows to start injected conversion in DMA mode.
<> 144:ef7eb2e8f9f7 1946 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1947 * in idle state or if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1948 * Please note that data on buffer will contain signed injected conversion
<> 144:ef7eb2e8f9f7 1949 * value on 24 most significant bits and corresponding channel on 3 least
<> 144:ef7eb2e8f9f7 1950 * significant bits.
<> 144:ef7eb2e8f9f7 1951 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1952 * @param pData : The destination buffer address.
<> 144:ef7eb2e8f9f7 1953 * @param Length : The length of data to be transferred from DFSDM filter to memory.
<> 144:ef7eb2e8f9f7 1954 * @retval HAL status
<> 144:ef7eb2e8f9f7 1955 */
<> 144:ef7eb2e8f9f7 1956 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1957 int32_t *pData,
<> 144:ef7eb2e8f9f7 1958 uint32_t Length)
<> 144:ef7eb2e8f9f7 1959 {
<> 144:ef7eb2e8f9f7 1960 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1961
<> 144:ef7eb2e8f9f7 1962 /* Check parameters */
<> 144:ef7eb2e8f9f7 1963 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1964
<> 144:ef7eb2e8f9f7 1965 /* Check destination address and length */
<> 144:ef7eb2e8f9f7 1966 if((pData == NULL) || (Length == 0))
<> 144:ef7eb2e8f9f7 1967 {
<> 144:ef7eb2e8f9f7 1968 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1969 }
<> 144:ef7eb2e8f9f7 1970 /* Check that DMA is enabled for injected conversion */
<> 144:ef7eb2e8f9f7 1971 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
<> 144:ef7eb2e8f9f7 1972 {
<> 144:ef7eb2e8f9f7 1973 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1974 }
<> 144:ef7eb2e8f9f7 1975 /* Check parameters compatibility */
<> 144:ef7eb2e8f9f7 1976 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 1977 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
<> 144:ef7eb2e8f9f7 1978 (Length > hdfsdm_filter->InjConvRemaining))
<> 144:ef7eb2e8f9f7 1979 {
<> 144:ef7eb2e8f9f7 1980 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1981 }
<> 144:ef7eb2e8f9f7 1982 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 1983 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
<> 144:ef7eb2e8f9f7 1984 {
<> 144:ef7eb2e8f9f7 1985 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1986 }
<> 144:ef7eb2e8f9f7 1987 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1988 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1989 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
<> 144:ef7eb2e8f9f7 1990 {
<> 144:ef7eb2e8f9f7 1991 /* Set callbacks on DMA handler */
<> 144:ef7eb2e8f9f7 1992 hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
<> 144:ef7eb2e8f9f7 1993 hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
<> 144:ef7eb2e8f9f7 1994 hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
<> 144:ef7eb2e8f9f7 1995 DFSDM_DMAInjectedHalfConvCplt : NULL;
<> 144:ef7eb2e8f9f7 1996
<> 144:ef7eb2e8f9f7 1997 /* Start DMA in interrupt mode */
<> 144:ef7eb2e8f9f7 1998 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
<> 144:ef7eb2e8f9f7 1999 (uint32_t) pData, Length) != HAL_OK)
<> 144:ef7eb2e8f9f7 2000 {
<> 144:ef7eb2e8f9f7 2001 /* Set DFSDM filter in error state */
<> 144:ef7eb2e8f9f7 2002 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
<> 144:ef7eb2e8f9f7 2003 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2004 }
<> 144:ef7eb2e8f9f7 2005 else
<> 144:ef7eb2e8f9f7 2006 {
<> 144:ef7eb2e8f9f7 2007 /* Start injected conversion */
<> 144:ef7eb2e8f9f7 2008 DFSDM_InjConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2009 }
<> 144:ef7eb2e8f9f7 2010 }
<> 144:ef7eb2e8f9f7 2011 else
<> 144:ef7eb2e8f9f7 2012 {
<> 144:ef7eb2e8f9f7 2013 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2014 }
<> 144:ef7eb2e8f9f7 2015 /* Return function status */
<> 144:ef7eb2e8f9f7 2016 return status;
<> 144:ef7eb2e8f9f7 2017 }
<> 144:ef7eb2e8f9f7 2018
<> 144:ef7eb2e8f9f7 2019 /**
<> 144:ef7eb2e8f9f7 2020 * @brief This function allows to start injected conversion in DMA mode and to get
<> 144:ef7eb2e8f9f7 2021 * only the 16 most significant bits of conversion.
<> 144:ef7eb2e8f9f7 2022 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 2023 * in idle state or if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 2024 * Please note that data on buffer will contain signed 16 most significant
<> 144:ef7eb2e8f9f7 2025 * bits of injected conversion.
<> 144:ef7eb2e8f9f7 2026 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2027 * @param pData : The destination buffer address.
<> 144:ef7eb2e8f9f7 2028 * @param Length : The length of data to be transferred from DFSDM filter to memory.
<> 144:ef7eb2e8f9f7 2029 * @retval HAL status
<> 144:ef7eb2e8f9f7 2030 */
<> 144:ef7eb2e8f9f7 2031 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2032 int16_t *pData,
<> 144:ef7eb2e8f9f7 2033 uint32_t Length)
<> 144:ef7eb2e8f9f7 2034 {
<> 144:ef7eb2e8f9f7 2035 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 2036
<> 144:ef7eb2e8f9f7 2037 /* Check parameters */
<> 144:ef7eb2e8f9f7 2038 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2039
<> 144:ef7eb2e8f9f7 2040 /* Check destination address and length */
<> 144:ef7eb2e8f9f7 2041 if((pData == NULL) || (Length == 0))
<> 144:ef7eb2e8f9f7 2042 {
<> 144:ef7eb2e8f9f7 2043 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2044 }
<> 144:ef7eb2e8f9f7 2045 /* Check that DMA is enabled for injected conversion */
<> 144:ef7eb2e8f9f7 2046 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
<> 144:ef7eb2e8f9f7 2047 {
<> 144:ef7eb2e8f9f7 2048 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2049 }
<> 144:ef7eb2e8f9f7 2050 /* Check parameters compatibility */
<> 144:ef7eb2e8f9f7 2051 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 2052 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
<> 144:ef7eb2e8f9f7 2053 (Length > hdfsdm_filter->InjConvRemaining))
<> 144:ef7eb2e8f9f7 2054 {
<> 144:ef7eb2e8f9f7 2055 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2056 }
<> 144:ef7eb2e8f9f7 2057 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 2058 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
<> 144:ef7eb2e8f9f7 2059 {
<> 144:ef7eb2e8f9f7 2060 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2061 }
<> 144:ef7eb2e8f9f7 2062 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 2063 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 2064 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
<> 144:ef7eb2e8f9f7 2065 {
<> 144:ef7eb2e8f9f7 2066 /* Set callbacks on DMA handler */
<> 144:ef7eb2e8f9f7 2067 hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
<> 144:ef7eb2e8f9f7 2068 hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
<> 144:ef7eb2e8f9f7 2069 hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
<> 144:ef7eb2e8f9f7 2070 DFSDM_DMAInjectedHalfConvCplt : NULL;
<> 144:ef7eb2e8f9f7 2071
<> 144:ef7eb2e8f9f7 2072 /* Start DMA in interrupt mode */
<> 144:ef7eb2e8f9f7 2073 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2, \
<> 144:ef7eb2e8f9f7 2074 (uint32_t) pData, Length) != HAL_OK)
<> 144:ef7eb2e8f9f7 2075 {
<> 144:ef7eb2e8f9f7 2076 /* Set DFSDM filter in error state */
<> 144:ef7eb2e8f9f7 2077 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
<> 144:ef7eb2e8f9f7 2078 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2079 }
<> 144:ef7eb2e8f9f7 2080 else
<> 144:ef7eb2e8f9f7 2081 {
<> 144:ef7eb2e8f9f7 2082 /* Start injected conversion */
<> 144:ef7eb2e8f9f7 2083 DFSDM_InjConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2084 }
<> 144:ef7eb2e8f9f7 2085 }
<> 144:ef7eb2e8f9f7 2086 else
<> 144:ef7eb2e8f9f7 2087 {
<> 144:ef7eb2e8f9f7 2088 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2089 }
<> 144:ef7eb2e8f9f7 2090 /* Return function status */
<> 144:ef7eb2e8f9f7 2091 return status;
<> 144:ef7eb2e8f9f7 2092 }
<> 144:ef7eb2e8f9f7 2093
<> 144:ef7eb2e8f9f7 2094 /**
<> 144:ef7eb2e8f9f7 2095 * @brief This function allows to stop injected conversion in DMA mode.
<> 144:ef7eb2e8f9f7 2096 * @note This function should be called only if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 2097 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2098 * @retval HAL status
<> 144:ef7eb2e8f9f7 2099 */
<> 144:ef7eb2e8f9f7 2100 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2101 {
<> 144:ef7eb2e8f9f7 2102 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 2103
<> 144:ef7eb2e8f9f7 2104 /* Check parameters */
<> 144:ef7eb2e8f9f7 2105 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2106
<> 144:ef7eb2e8f9f7 2107 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 2108 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
<> 144:ef7eb2e8f9f7 2109 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 2110 {
<> 144:ef7eb2e8f9f7 2111 /* Return error status */
<> 144:ef7eb2e8f9f7 2112 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2113 }
<> 144:ef7eb2e8f9f7 2114 else
<> 144:ef7eb2e8f9f7 2115 {
<> 144:ef7eb2e8f9f7 2116 /* Stop current DMA transfer */
<> 144:ef7eb2e8f9f7 2117 if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)
<> 144:ef7eb2e8f9f7 2118 {
<> 144:ef7eb2e8f9f7 2119 /* Set DFSDM filter in error state */
<> 144:ef7eb2e8f9f7 2120 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
<> 144:ef7eb2e8f9f7 2121 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2122 }
<> 144:ef7eb2e8f9f7 2123 else
<> 144:ef7eb2e8f9f7 2124 {
<> 144:ef7eb2e8f9f7 2125 /* Stop regular conversion */
<> 144:ef7eb2e8f9f7 2126 DFSDM_InjConvStop(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2127 }
<> 144:ef7eb2e8f9f7 2128 }
<> 144:ef7eb2e8f9f7 2129 /* Return function status */
<> 144:ef7eb2e8f9f7 2130 return status;
<> 144:ef7eb2e8f9f7 2131 }
<> 144:ef7eb2e8f9f7 2132
<> 144:ef7eb2e8f9f7 2133 /**
<> 144:ef7eb2e8f9f7 2134 * @brief This function allows to get injected conversion value.
<> 144:ef7eb2e8f9f7 2135 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2136 * @param Channel : Corresponding channel of injected conversion.
<> 144:ef7eb2e8f9f7 2137 * @retval Injected conversion value
<> 144:ef7eb2e8f9f7 2138 */
<> 144:ef7eb2e8f9f7 2139 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2140 uint32_t *Channel)
<> 144:ef7eb2e8f9f7 2141 {
<> 144:ef7eb2e8f9f7 2142 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2143 int32_t value = 0;
<> 144:ef7eb2e8f9f7 2144
<> 144:ef7eb2e8f9f7 2145 /* Check parameters */
<> 144:ef7eb2e8f9f7 2146 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2147 assert_param(Channel != NULL);
<> 144:ef7eb2e8f9f7 2148
<> 144:ef7eb2e8f9f7 2149 /* Get value of data register for injected channel */
<> 144:ef7eb2e8f9f7 2150 reg = hdfsdm_filter->Instance->FLTJDATAR;
<> 144:ef7eb2e8f9f7 2151
<> 144:ef7eb2e8f9f7 2152 /* Extract channel and injected conversion value */
<> 144:ef7eb2e8f9f7 2153 *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
AnnaBridge 167:e84263d55307 2154 value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET);
<> 144:ef7eb2e8f9f7 2155
<> 144:ef7eb2e8f9f7 2156 /* return regular conversion value */
<> 144:ef7eb2e8f9f7 2157 return value;
<> 144:ef7eb2e8f9f7 2158 }
<> 144:ef7eb2e8f9f7 2159
<> 144:ef7eb2e8f9f7 2160 /**
<> 144:ef7eb2e8f9f7 2161 * @brief This function allows to start filter analog watchdog in interrupt mode.
<> 144:ef7eb2e8f9f7 2162 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2163 * @param awdParam : DFSDM filter analog watchdog parameters.
<> 144:ef7eb2e8f9f7 2164 * @retval HAL status
<> 144:ef7eb2e8f9f7 2165 */
<> 144:ef7eb2e8f9f7 2166 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2167 DFSDM_Filter_AwdParamTypeDef *awdParam)
<> 144:ef7eb2e8f9f7 2168 {
<> 144:ef7eb2e8f9f7 2169 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 2170
<> 144:ef7eb2e8f9f7 2171 /* Check parameters */
<> 144:ef7eb2e8f9f7 2172 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2173 assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));
<> 144:ef7eb2e8f9f7 2174 assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));
<> 144:ef7eb2e8f9f7 2175 assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));
<> 144:ef7eb2e8f9f7 2176 assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
<> 144:ef7eb2e8f9f7 2177 assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
<> 144:ef7eb2e8f9f7 2178 assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
<> 144:ef7eb2e8f9f7 2179
<> 144:ef7eb2e8f9f7 2180 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 2181 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
<> 144:ef7eb2e8f9f7 2182 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
<> 144:ef7eb2e8f9f7 2183 {
<> 144:ef7eb2e8f9f7 2184 /* Return error status */
<> 144:ef7eb2e8f9f7 2185 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2186 }
<> 144:ef7eb2e8f9f7 2187 else
<> 144:ef7eb2e8f9f7 2188 {
<> 144:ef7eb2e8f9f7 2189 /* Set analog watchdog data source */
<> 144:ef7eb2e8f9f7 2190 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
<> 144:ef7eb2e8f9f7 2191 hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;
<> 144:ef7eb2e8f9f7 2192
<> 144:ef7eb2e8f9f7 2193 /* Set thresholds and break signals */
<> 144:ef7eb2e8f9f7 2194 hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
<> 144:ef7eb2e8f9f7 2195 hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \
<> 144:ef7eb2e8f9f7 2196 awdParam->HighBreakSignal);
<> 144:ef7eb2e8f9f7 2197 hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
<> 144:ef7eb2e8f9f7 2198 hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \
<> 144:ef7eb2e8f9f7 2199 awdParam->LowBreakSignal);
<> 144:ef7eb2e8f9f7 2200
<> 144:ef7eb2e8f9f7 2201 /* Set channels and interrupt for analog watchdog */
<> 144:ef7eb2e8f9f7 2202 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
<> 144:ef7eb2e8f9f7 2203 hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \
<> 144:ef7eb2e8f9f7 2204 DFSDM_FLTCR2_AWDIE);
<> 144:ef7eb2e8f9f7 2205 }
<> 144:ef7eb2e8f9f7 2206 /* Return function status */
<> 144:ef7eb2e8f9f7 2207 return status;
<> 144:ef7eb2e8f9f7 2208 }
<> 144:ef7eb2e8f9f7 2209
<> 144:ef7eb2e8f9f7 2210 /**
<> 144:ef7eb2e8f9f7 2211 * @brief This function allows to stop filter analog watchdog in interrupt mode.
<> 144:ef7eb2e8f9f7 2212 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2213 * @retval HAL status
<> 144:ef7eb2e8f9f7 2214 */
<> 144:ef7eb2e8f9f7 2215 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2216 {
<> 144:ef7eb2e8f9f7 2217 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 2218
<> 144:ef7eb2e8f9f7 2219 /* Check parameters */
<> 144:ef7eb2e8f9f7 2220 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2221
<> 144:ef7eb2e8f9f7 2222 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 2223 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
<> 144:ef7eb2e8f9f7 2224 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
<> 144:ef7eb2e8f9f7 2225 {
<> 144:ef7eb2e8f9f7 2226 /* Return error status */
<> 144:ef7eb2e8f9f7 2227 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2228 }
<> 144:ef7eb2e8f9f7 2229 else
<> 144:ef7eb2e8f9f7 2230 {
<> 144:ef7eb2e8f9f7 2231 /* Reset channels for analog watchdog and deactivate interrupt */
<> 144:ef7eb2e8f9f7 2232 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);
<> 144:ef7eb2e8f9f7 2233
<> 144:ef7eb2e8f9f7 2234 /* Clear all analog watchdog flags */
<> 144:ef7eb2e8f9f7 2235 hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
<> 144:ef7eb2e8f9f7 2236
<> 144:ef7eb2e8f9f7 2237 /* Reset thresholds and break signals */
<> 144:ef7eb2e8f9f7 2238 hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
<> 144:ef7eb2e8f9f7 2239 hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
<> 144:ef7eb2e8f9f7 2240
<> 144:ef7eb2e8f9f7 2241 /* Reset analog watchdog data source */
<> 144:ef7eb2e8f9f7 2242 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
<> 144:ef7eb2e8f9f7 2243 }
<> 144:ef7eb2e8f9f7 2244 /* Return function status */
<> 144:ef7eb2e8f9f7 2245 return status;
<> 144:ef7eb2e8f9f7 2246 }
<> 144:ef7eb2e8f9f7 2247
<> 144:ef7eb2e8f9f7 2248 /**
<> 144:ef7eb2e8f9f7 2249 * @brief This function allows to start extreme detector feature.
<> 144:ef7eb2e8f9f7 2250 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2251 * @param Channel : Channels where extreme detector is enabled.
<> 144:ef7eb2e8f9f7 2252 * This parameter can be a values combination of @ref DFSDM_Channel_Selection.
<> 144:ef7eb2e8f9f7 2253 * @retval HAL status
<> 144:ef7eb2e8f9f7 2254 */
<> 144:ef7eb2e8f9f7 2255 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2256 uint32_t Channel)
<> 144:ef7eb2e8f9f7 2257 {
<> 144:ef7eb2e8f9f7 2258 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 2259
<> 144:ef7eb2e8f9f7 2260 /* Check parameters */
<> 144:ef7eb2e8f9f7 2261 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2262 assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 2263
<> 144:ef7eb2e8f9f7 2264 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 2265 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
<> 144:ef7eb2e8f9f7 2266 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
<> 144:ef7eb2e8f9f7 2267 {
<> 144:ef7eb2e8f9f7 2268 /* Return error status */
<> 144:ef7eb2e8f9f7 2269 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2270 }
<> 144:ef7eb2e8f9f7 2271 else
<> 144:ef7eb2e8f9f7 2272 {
<> 144:ef7eb2e8f9f7 2273 /* Set channels for extreme detector */
<> 144:ef7eb2e8f9f7 2274 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
<> 144:ef7eb2e8f9f7 2275 hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET);
<> 144:ef7eb2e8f9f7 2276 }
<> 144:ef7eb2e8f9f7 2277 /* Return function status */
<> 144:ef7eb2e8f9f7 2278 return status;
<> 144:ef7eb2e8f9f7 2279 }
<> 144:ef7eb2e8f9f7 2280
<> 144:ef7eb2e8f9f7 2281 /**
<> 144:ef7eb2e8f9f7 2282 * @brief This function allows to stop extreme detector feature.
<> 144:ef7eb2e8f9f7 2283 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2284 * @retval HAL status
<> 144:ef7eb2e8f9f7 2285 */
<> 144:ef7eb2e8f9f7 2286 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2287 {
<> 144:ef7eb2e8f9f7 2288 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 2289 __IO uint32_t reg1;
<> 144:ef7eb2e8f9f7 2290 __IO uint32_t reg2;
<> 144:ef7eb2e8f9f7 2291
<> 144:ef7eb2e8f9f7 2292 /* Check parameters */
<> 144:ef7eb2e8f9f7 2293 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2294
<> 144:ef7eb2e8f9f7 2295 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 2296 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
<> 144:ef7eb2e8f9f7 2297 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
<> 144:ef7eb2e8f9f7 2298 {
<> 144:ef7eb2e8f9f7 2299 /* Return error status */
<> 144:ef7eb2e8f9f7 2300 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2301 }
<> 144:ef7eb2e8f9f7 2302 else
<> 144:ef7eb2e8f9f7 2303 {
<> 144:ef7eb2e8f9f7 2304 /* Reset channels for extreme detector */
<> 144:ef7eb2e8f9f7 2305 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
<> 144:ef7eb2e8f9f7 2306
<> 144:ef7eb2e8f9f7 2307 /* Clear extreme detector values */
<> 144:ef7eb2e8f9f7 2308 reg1 = hdfsdm_filter->Instance->FLTEXMAX;
<> 144:ef7eb2e8f9f7 2309 reg2 = hdfsdm_filter->Instance->FLTEXMIN;
<> 144:ef7eb2e8f9f7 2310 UNUSED(reg1); /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2311 UNUSED(reg2); /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2312 }
<> 144:ef7eb2e8f9f7 2313 /* Return function status */
<> 144:ef7eb2e8f9f7 2314 return status;
<> 144:ef7eb2e8f9f7 2315 }
<> 144:ef7eb2e8f9f7 2316
<> 144:ef7eb2e8f9f7 2317 /**
<> 144:ef7eb2e8f9f7 2318 * @brief This function allows to get extreme detector maximum value.
<> 144:ef7eb2e8f9f7 2319 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2320 * @param Channel : Corresponding channel.
<> 144:ef7eb2e8f9f7 2321 * @retval Extreme detector maximum value
<> 144:ef7eb2e8f9f7 2322 * This value is between Min_Data = -8388608 and Max_Data = 8388607.
<> 144:ef7eb2e8f9f7 2323 */
<> 144:ef7eb2e8f9f7 2324 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2325 uint32_t *Channel)
<> 144:ef7eb2e8f9f7 2326 {
<> 144:ef7eb2e8f9f7 2327 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2328 int32_t value = 0;
<> 144:ef7eb2e8f9f7 2329
<> 144:ef7eb2e8f9f7 2330 /* Check parameters */
<> 144:ef7eb2e8f9f7 2331 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2332 assert_param(Channel != NULL);
<> 144:ef7eb2e8f9f7 2333
<> 144:ef7eb2e8f9f7 2334 /* Get value of extreme detector maximum register */
<> 144:ef7eb2e8f9f7 2335 reg = hdfsdm_filter->Instance->FLTEXMAX;
<> 144:ef7eb2e8f9f7 2336
<> 144:ef7eb2e8f9f7 2337 /* Extract channel and extreme detector maximum value */
<> 144:ef7eb2e8f9f7 2338 *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
AnnaBridge 167:e84263d55307 2339 value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET);
<> 144:ef7eb2e8f9f7 2340
<> 144:ef7eb2e8f9f7 2341 /* return extreme detector maximum value */
<> 144:ef7eb2e8f9f7 2342 return value;
<> 144:ef7eb2e8f9f7 2343 }
<> 144:ef7eb2e8f9f7 2344
<> 144:ef7eb2e8f9f7 2345 /**
<> 144:ef7eb2e8f9f7 2346 * @brief This function allows to get extreme detector minimum value.
<> 144:ef7eb2e8f9f7 2347 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2348 * @param Channel : Corresponding channel.
<> 144:ef7eb2e8f9f7 2349 * @retval Extreme detector minimum value
<> 144:ef7eb2e8f9f7 2350 * This value is between Min_Data = -8388608 and Max_Data = 8388607.
<> 144:ef7eb2e8f9f7 2351 */
<> 144:ef7eb2e8f9f7 2352 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2353 uint32_t *Channel)
<> 144:ef7eb2e8f9f7 2354 {
<> 144:ef7eb2e8f9f7 2355 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2356 int32_t value = 0;
<> 144:ef7eb2e8f9f7 2357
<> 144:ef7eb2e8f9f7 2358 /* Check parameters */
<> 144:ef7eb2e8f9f7 2359 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2360 assert_param(Channel != NULL);
<> 144:ef7eb2e8f9f7 2361
<> 144:ef7eb2e8f9f7 2362 /* Get value of extreme detector minimum register */
<> 144:ef7eb2e8f9f7 2363 reg = hdfsdm_filter->Instance->FLTEXMIN;
<> 144:ef7eb2e8f9f7 2364
<> 144:ef7eb2e8f9f7 2365 /* Extract channel and extreme detector minimum value */
<> 144:ef7eb2e8f9f7 2366 *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
AnnaBridge 167:e84263d55307 2367 value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET);
<> 144:ef7eb2e8f9f7 2368
<> 144:ef7eb2e8f9f7 2369 /* return extreme detector minimum value */
<> 144:ef7eb2e8f9f7 2370 return value;
<> 144:ef7eb2e8f9f7 2371 }
<> 144:ef7eb2e8f9f7 2372
<> 144:ef7eb2e8f9f7 2373 /**
<> 144:ef7eb2e8f9f7 2374 * @brief This function allows to get conversion time value.
<> 144:ef7eb2e8f9f7 2375 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2376 * @retval Conversion time value
<> 144:ef7eb2e8f9f7 2377 * @note To get time in second, this value has to be divided by DFSDM clock frequency.
<> 144:ef7eb2e8f9f7 2378 */
<> 144:ef7eb2e8f9f7 2379 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2380 {
<> 144:ef7eb2e8f9f7 2381 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2382 uint32_t value = 0;
<> 144:ef7eb2e8f9f7 2383
<> 144:ef7eb2e8f9f7 2384 /* Check parameters */
<> 144:ef7eb2e8f9f7 2385 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2386
<> 144:ef7eb2e8f9f7 2387 /* Get value of conversion timer register */
<> 144:ef7eb2e8f9f7 2388 reg = hdfsdm_filter->Instance->FLTCNVTIMR;
<> 144:ef7eb2e8f9f7 2389
<> 144:ef7eb2e8f9f7 2390 /* Extract conversion time value */
<> 144:ef7eb2e8f9f7 2391 value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET);
<> 144:ef7eb2e8f9f7 2392
<> 144:ef7eb2e8f9f7 2393 /* return extreme detector minimum value */
<> 144:ef7eb2e8f9f7 2394 return value;
<> 144:ef7eb2e8f9f7 2395 }
<> 144:ef7eb2e8f9f7 2396
<> 144:ef7eb2e8f9f7 2397 /**
<> 144:ef7eb2e8f9f7 2398 * @brief This function handles the DFSDM interrupts.
<> 144:ef7eb2e8f9f7 2399 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2400 * @retval None
<> 144:ef7eb2e8f9f7 2401 */
<> 144:ef7eb2e8f9f7 2402 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2403 {
<> 144:ef7eb2e8f9f7 2404 /* Check if overrun occurs during regular conversion */
<> 144:ef7eb2e8f9f7 2405 if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0) && \
<> 144:ef7eb2e8f9f7 2406 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0))
<> 144:ef7eb2e8f9f7 2407 {
<> 144:ef7eb2e8f9f7 2408 /* Clear regular overrun flag */
<> 144:ef7eb2e8f9f7 2409 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
<> 144:ef7eb2e8f9f7 2410
<> 144:ef7eb2e8f9f7 2411 /* Update error code */
<> 144:ef7eb2e8f9f7 2412 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
<> 144:ef7eb2e8f9f7 2413
<> 144:ef7eb2e8f9f7 2414 /* Call error callback */
<> 144:ef7eb2e8f9f7 2415 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2416 }
<> 144:ef7eb2e8f9f7 2417 /* Check if overrun occurs during injected conversion */
<> 144:ef7eb2e8f9f7 2418 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \
<> 144:ef7eb2e8f9f7 2419 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0))
<> 144:ef7eb2e8f9f7 2420 {
<> 144:ef7eb2e8f9f7 2421 /* Clear injected overrun flag */
<> 144:ef7eb2e8f9f7 2422 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
<> 144:ef7eb2e8f9f7 2423
<> 144:ef7eb2e8f9f7 2424 /* Update error code */
<> 144:ef7eb2e8f9f7 2425 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
<> 144:ef7eb2e8f9f7 2426
<> 144:ef7eb2e8f9f7 2427 /* Call error callback */
<> 144:ef7eb2e8f9f7 2428 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2429 }
<> 144:ef7eb2e8f9f7 2430 /* Check if end of regular conversion */
<> 144:ef7eb2e8f9f7 2431 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \
<> 144:ef7eb2e8f9f7 2432 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0))
<> 144:ef7eb2e8f9f7 2433 {
<> 144:ef7eb2e8f9f7 2434 /* Call regular conversion complete callback */
<> 144:ef7eb2e8f9f7 2435 HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2436
<> 144:ef7eb2e8f9f7 2437 /* End of conversion if mode is not continuous and software trigger */
<> 144:ef7eb2e8f9f7 2438 if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
<> 144:ef7eb2e8f9f7 2439 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
<> 144:ef7eb2e8f9f7 2440 {
<> 144:ef7eb2e8f9f7 2441 /* Disable interrupts for regular conversions */
<> 144:ef7eb2e8f9f7 2442 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
<> 144:ef7eb2e8f9f7 2443
<> 144:ef7eb2e8f9f7 2444 /* Update DFSDM filter state */
<> 144:ef7eb2e8f9f7 2445 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
<> 144:ef7eb2e8f9f7 2446 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
<> 144:ef7eb2e8f9f7 2447 }
<> 144:ef7eb2e8f9f7 2448 }
<> 144:ef7eb2e8f9f7 2449 /* Check if end of injected conversion */
<> 144:ef7eb2e8f9f7 2450 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0) && \
<> 144:ef7eb2e8f9f7 2451 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0))
<> 144:ef7eb2e8f9f7 2452 {
<> 144:ef7eb2e8f9f7 2453 /* Call injected conversion complete callback */
<> 144:ef7eb2e8f9f7 2454 HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2455
<> 144:ef7eb2e8f9f7 2456 /* Update remaining injected conversions */
<> 144:ef7eb2e8f9f7 2457 hdfsdm_filter->InjConvRemaining--;
<> 144:ef7eb2e8f9f7 2458 if(hdfsdm_filter->InjConvRemaining == 0)
<> 144:ef7eb2e8f9f7 2459 {
<> 144:ef7eb2e8f9f7 2460 /* End of conversion if trigger is software */
<> 144:ef7eb2e8f9f7 2461 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
<> 144:ef7eb2e8f9f7 2462 {
<> 144:ef7eb2e8f9f7 2463 /* Disable interrupts for injected conversions */
<> 144:ef7eb2e8f9f7 2464 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);
<> 144:ef7eb2e8f9f7 2465
<> 144:ef7eb2e8f9f7 2466 /* Update DFSDM filter state */
<> 144:ef7eb2e8f9f7 2467 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
<> 144:ef7eb2e8f9f7 2468 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
<> 144:ef7eb2e8f9f7 2469 }
<> 144:ef7eb2e8f9f7 2470 /* end of injected sequence, reset the value */
<> 144:ef7eb2e8f9f7 2471 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
<> 144:ef7eb2e8f9f7 2472 hdfsdm_filter->InjectedChannelsNbr : 1;
<> 144:ef7eb2e8f9f7 2473 }
<> 144:ef7eb2e8f9f7 2474 }
<> 144:ef7eb2e8f9f7 2475 /* Check if analog watchdog occurs */
<> 144:ef7eb2e8f9f7 2476 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0) && \
<> 144:ef7eb2e8f9f7 2477 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0))
<> 144:ef7eb2e8f9f7 2478 {
<> 144:ef7eb2e8f9f7 2479 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2480 uint32_t threshold = 0;
<> 144:ef7eb2e8f9f7 2481 uint32_t channel = 0;
<> 144:ef7eb2e8f9f7 2482
<> 144:ef7eb2e8f9f7 2483 /* Get channel and threshold */
<> 144:ef7eb2e8f9f7 2484 reg = hdfsdm_filter->Instance->FLTAWSR;
<> 144:ef7eb2e8f9f7 2485 threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
<> 144:ef7eb2e8f9f7 2486 if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
<> 144:ef7eb2e8f9f7 2487 {
<> 144:ef7eb2e8f9f7 2488 reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET;
<> 144:ef7eb2e8f9f7 2489 }
<> 144:ef7eb2e8f9f7 2490 while((reg & 1) == 0)
<> 144:ef7eb2e8f9f7 2491 {
<> 144:ef7eb2e8f9f7 2492 channel++;
<> 144:ef7eb2e8f9f7 2493 reg = reg >> 1;
<> 144:ef7eb2e8f9f7 2494 }
<> 144:ef7eb2e8f9f7 2495 /* Clear analog watchdog flag */
<> 144:ef7eb2e8f9f7 2496 hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
<> 144:ef7eb2e8f9f7 2497 (1 << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \
<> 144:ef7eb2e8f9f7 2498 (1 << channel);
<> 144:ef7eb2e8f9f7 2499
<> 144:ef7eb2e8f9f7 2500 /* Call analog watchdog callback */
<> 144:ef7eb2e8f9f7 2501 HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
<> 144:ef7eb2e8f9f7 2502 }
<> 144:ef7eb2e8f9f7 2503 /* Check if clock absence occurs */
<> 144:ef7eb2e8f9f7 2504 else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
<> 144:ef7eb2e8f9f7 2505 ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0) && \
<> 144:ef7eb2e8f9f7 2506 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0))
<> 144:ef7eb2e8f9f7 2507 {
<> 144:ef7eb2e8f9f7 2508 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2509 uint32_t channel = 0;
<> 144:ef7eb2e8f9f7 2510
<> 144:ef7eb2e8f9f7 2511 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET);
<> 144:ef7eb2e8f9f7 2512
<> 144:ef7eb2e8f9f7 2513 while(channel < DFSDM1_CHANNEL_NUMBER)
<> 144:ef7eb2e8f9f7 2514 {
<> 144:ef7eb2e8f9f7 2515 /* Check if flag is set and corresponding channel is enabled */
<> 144:ef7eb2e8f9f7 2516 if(((reg & 1) != 0) && (a_dfsdm1ChannelHandle[channel] != NULL))
<> 144:ef7eb2e8f9f7 2517 {
<> 144:ef7eb2e8f9f7 2518 /* Check clock absence has been enabled for this channel */
<> 144:ef7eb2e8f9f7 2519 if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0)
<> 144:ef7eb2e8f9f7 2520 {
<> 144:ef7eb2e8f9f7 2521 /* Clear clock absence flag */
<> 144:ef7eb2e8f9f7 2522 hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 2523
<> 144:ef7eb2e8f9f7 2524 /* Call clock absence callback */
<> 144:ef7eb2e8f9f7 2525 HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
<> 144:ef7eb2e8f9f7 2526 }
<> 144:ef7eb2e8f9f7 2527 }
<> 144:ef7eb2e8f9f7 2528 channel++;
<> 144:ef7eb2e8f9f7 2529 reg = reg >> 1;
<> 144:ef7eb2e8f9f7 2530 }
<> 144:ef7eb2e8f9f7 2531 }
<> 144:ef7eb2e8f9f7 2532 /* Check if short circuit detection occurs */
<> 144:ef7eb2e8f9f7 2533 else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
<> 144:ef7eb2e8f9f7 2534 ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0) && \
<> 144:ef7eb2e8f9f7 2535 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0))
<> 144:ef7eb2e8f9f7 2536 {
<> 144:ef7eb2e8f9f7 2537 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2538 uint32_t channel = 0;
<> 144:ef7eb2e8f9f7 2539
<> 144:ef7eb2e8f9f7 2540 /* Get channel */
<> 144:ef7eb2e8f9f7 2541 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET);
<> 144:ef7eb2e8f9f7 2542 while((reg & 1) == 0)
<> 144:ef7eb2e8f9f7 2543 {
<> 144:ef7eb2e8f9f7 2544 channel++;
<> 144:ef7eb2e8f9f7 2545 reg = reg >> 1;
<> 144:ef7eb2e8f9f7 2546 }
<> 144:ef7eb2e8f9f7 2547
<> 144:ef7eb2e8f9f7 2548 /* Clear short circuit detection flag */
<> 144:ef7eb2e8f9f7 2549 hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 2550
<> 144:ef7eb2e8f9f7 2551 /* Call short circuit detection callback */
<> 144:ef7eb2e8f9f7 2552 HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
<> 144:ef7eb2e8f9f7 2553 }
<> 144:ef7eb2e8f9f7 2554 }
<> 144:ef7eb2e8f9f7 2555
<> 144:ef7eb2e8f9f7 2556 /**
<> 144:ef7eb2e8f9f7 2557 * @brief Regular conversion complete callback.
<> 144:ef7eb2e8f9f7 2558 * @note In interrupt mode, user has to read conversion value in this function
<> 144:ef7eb2e8f9f7 2559 * using HAL_DFSDM_FilterGetRegularValue.
<> 144:ef7eb2e8f9f7 2560 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2561 * @retval None
<> 144:ef7eb2e8f9f7 2562 */
<> 144:ef7eb2e8f9f7 2563 __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2564 {
<> 144:ef7eb2e8f9f7 2565 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2566 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2567
<> 144:ef7eb2e8f9f7 2568 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2569 the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.
<> 144:ef7eb2e8f9f7 2570 */
<> 144:ef7eb2e8f9f7 2571 }
<> 144:ef7eb2e8f9f7 2572
<> 144:ef7eb2e8f9f7 2573 /**
<> 144:ef7eb2e8f9f7 2574 * @brief Half regular conversion complete callback.
<> 144:ef7eb2e8f9f7 2575 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2576 * @retval None
<> 144:ef7eb2e8f9f7 2577 */
<> 144:ef7eb2e8f9f7 2578 __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2579 {
<> 144:ef7eb2e8f9f7 2580 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2581 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2582
<> 144:ef7eb2e8f9f7 2583 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2584 the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.
<> 144:ef7eb2e8f9f7 2585 */
<> 144:ef7eb2e8f9f7 2586 }
<> 144:ef7eb2e8f9f7 2587
<> 144:ef7eb2e8f9f7 2588 /**
<> 144:ef7eb2e8f9f7 2589 * @brief Injected conversion complete callback.
<> 144:ef7eb2e8f9f7 2590 * @note In interrupt mode, user has to read conversion value in this function
<> 144:ef7eb2e8f9f7 2591 * using HAL_DFSDM_FilterGetInjectedValue.
<> 144:ef7eb2e8f9f7 2592 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2593 * @retval None
<> 144:ef7eb2e8f9f7 2594 */
<> 144:ef7eb2e8f9f7 2595 __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2596 {
<> 144:ef7eb2e8f9f7 2597 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2598 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2599
<> 144:ef7eb2e8f9f7 2600 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2601 the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.
<> 144:ef7eb2e8f9f7 2602 */
<> 144:ef7eb2e8f9f7 2603 }
<> 144:ef7eb2e8f9f7 2604
<> 144:ef7eb2e8f9f7 2605 /**
<> 144:ef7eb2e8f9f7 2606 * @brief Half injected conversion complete callback.
<> 144:ef7eb2e8f9f7 2607 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2608 * @retval None
<> 144:ef7eb2e8f9f7 2609 */
<> 144:ef7eb2e8f9f7 2610 __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2611 {
<> 144:ef7eb2e8f9f7 2612 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2613 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2614
<> 144:ef7eb2e8f9f7 2615 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2616 the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.
<> 144:ef7eb2e8f9f7 2617 */
<> 144:ef7eb2e8f9f7 2618 }
<> 144:ef7eb2e8f9f7 2619
<> 144:ef7eb2e8f9f7 2620 /**
<> 144:ef7eb2e8f9f7 2621 * @brief Filter analog watchdog callback.
<> 144:ef7eb2e8f9f7 2622 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2623 * @param Channel : Corresponding channel.
<> 144:ef7eb2e8f9f7 2624 * @param Threshold : Low or high threshold has been reached.
<> 144:ef7eb2e8f9f7 2625 * @retval None
<> 144:ef7eb2e8f9f7 2626 */
<> 144:ef7eb2e8f9f7 2627 __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2628 uint32_t Channel, uint32_t Threshold)
<> 144:ef7eb2e8f9f7 2629 {
<> 144:ef7eb2e8f9f7 2630 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2631 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2632 UNUSED(Channel);
<> 144:ef7eb2e8f9f7 2633 UNUSED(Threshold);
<> 144:ef7eb2e8f9f7 2634
<> 144:ef7eb2e8f9f7 2635 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2636 the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.
<> 144:ef7eb2e8f9f7 2637 */
<> 144:ef7eb2e8f9f7 2638 }
<> 144:ef7eb2e8f9f7 2639
<> 144:ef7eb2e8f9f7 2640 /**
<> 144:ef7eb2e8f9f7 2641 * @brief Error callback.
<> 144:ef7eb2e8f9f7 2642 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2643 * @retval None
<> 144:ef7eb2e8f9f7 2644 */
<> 144:ef7eb2e8f9f7 2645 __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2646 {
<> 144:ef7eb2e8f9f7 2647 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2648 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2649
<> 144:ef7eb2e8f9f7 2650 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2651 the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.
<> 144:ef7eb2e8f9f7 2652 */
<> 144:ef7eb2e8f9f7 2653 }
<> 144:ef7eb2e8f9f7 2654
<> 144:ef7eb2e8f9f7 2655 /**
<> 144:ef7eb2e8f9f7 2656 * @}
<> 144:ef7eb2e8f9f7 2657 */
<> 144:ef7eb2e8f9f7 2658
<> 144:ef7eb2e8f9f7 2659 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
<> 144:ef7eb2e8f9f7 2660 * @brief Filter state functions
<> 144:ef7eb2e8f9f7 2661 *
<> 144:ef7eb2e8f9f7 2662 @verbatim
<> 144:ef7eb2e8f9f7 2663 ==============================================================================
<> 144:ef7eb2e8f9f7 2664 ##### Filter state functions #####
<> 144:ef7eb2e8f9f7 2665 ==============================================================================
<> 144:ef7eb2e8f9f7 2666 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2667 (+) Get the DFSDM filter state.
<> 144:ef7eb2e8f9f7 2668 (+) Get the DFSDM filter error.
<> 144:ef7eb2e8f9f7 2669 @endverbatim
<> 144:ef7eb2e8f9f7 2670 * @{
<> 144:ef7eb2e8f9f7 2671 */
<> 144:ef7eb2e8f9f7 2672
<> 144:ef7eb2e8f9f7 2673 /**
<> 144:ef7eb2e8f9f7 2674 * @brief This function allows to get the current DFSDM filter handle state.
<> 144:ef7eb2e8f9f7 2675 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2676 * @retval DFSDM filter state.
<> 144:ef7eb2e8f9f7 2677 */
<> 144:ef7eb2e8f9f7 2678 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2679 {
<> 144:ef7eb2e8f9f7 2680 /* Return DFSDM filter handle state */
<> 144:ef7eb2e8f9f7 2681 return hdfsdm_filter->State;
<> 144:ef7eb2e8f9f7 2682 }
<> 144:ef7eb2e8f9f7 2683
<> 144:ef7eb2e8f9f7 2684 /**
<> 144:ef7eb2e8f9f7 2685 * @brief This function allows to get the current DFSDM filter error.
<> 144:ef7eb2e8f9f7 2686 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2687 * @retval DFSDM filter error code.
<> 144:ef7eb2e8f9f7 2688 */
<> 144:ef7eb2e8f9f7 2689 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2690 {
<> 144:ef7eb2e8f9f7 2691 return hdfsdm_filter->ErrorCode;
<> 144:ef7eb2e8f9f7 2692 }
<> 144:ef7eb2e8f9f7 2693
<> 144:ef7eb2e8f9f7 2694 /**
<> 144:ef7eb2e8f9f7 2695 * @}
<> 144:ef7eb2e8f9f7 2696 */
<> 144:ef7eb2e8f9f7 2697
<> 144:ef7eb2e8f9f7 2698 /**
<> 144:ef7eb2e8f9f7 2699 * @}
<> 144:ef7eb2e8f9f7 2700 */
<> 144:ef7eb2e8f9f7 2701 /* End of exported functions -------------------------------------------------*/
<> 144:ef7eb2e8f9f7 2702
<> 144:ef7eb2e8f9f7 2703 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 2704 /** @addtogroup DFSDM_Private_Functions DFSDM Private Functions
<> 144:ef7eb2e8f9f7 2705 * @{
<> 144:ef7eb2e8f9f7 2706 */
<> 144:ef7eb2e8f9f7 2707
<> 144:ef7eb2e8f9f7 2708 /**
<> 144:ef7eb2e8f9f7 2709 * @brief DMA half transfer complete callback for regular conversion.
<> 144:ef7eb2e8f9f7 2710 * @param hdma : DMA handle.
<> 144:ef7eb2e8f9f7 2711 * @retval None
<> 144:ef7eb2e8f9f7 2712 */
<> 144:ef7eb2e8f9f7 2713 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2714 {
<> 144:ef7eb2e8f9f7 2715 /* Get DFSDM filter handle */
<> 144:ef7eb2e8f9f7 2716 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2717
<> 144:ef7eb2e8f9f7 2718 /* Call regular half conversion complete callback */
<> 144:ef7eb2e8f9f7 2719 HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2720 }
<> 144:ef7eb2e8f9f7 2721
<> 144:ef7eb2e8f9f7 2722 /**
<> 144:ef7eb2e8f9f7 2723 * @brief DMA transfer complete callback for regular conversion.
<> 144:ef7eb2e8f9f7 2724 * @param hdma : DMA handle.
<> 144:ef7eb2e8f9f7 2725 * @retval None
<> 144:ef7eb2e8f9f7 2726 */
<> 144:ef7eb2e8f9f7 2727 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2728 {
<> 144:ef7eb2e8f9f7 2729 /* Get DFSDM filter handle */
<> 144:ef7eb2e8f9f7 2730 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2731
<> 144:ef7eb2e8f9f7 2732 /* Call regular conversion complete callback */
<> 144:ef7eb2e8f9f7 2733 HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2734 }
<> 144:ef7eb2e8f9f7 2735
<> 144:ef7eb2e8f9f7 2736 /**
<> 144:ef7eb2e8f9f7 2737 * @brief DMA half transfer complete callback for injected conversion.
<> 144:ef7eb2e8f9f7 2738 * @param hdma : DMA handle.
<> 144:ef7eb2e8f9f7 2739 * @retval None
<> 144:ef7eb2e8f9f7 2740 */
<> 144:ef7eb2e8f9f7 2741 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2742 {
<> 144:ef7eb2e8f9f7 2743 /* Get DFSDM filter handle */
<> 144:ef7eb2e8f9f7 2744 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2745
<> 144:ef7eb2e8f9f7 2746 /* Call injected half conversion complete callback */
<> 144:ef7eb2e8f9f7 2747 HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2748 }
<> 144:ef7eb2e8f9f7 2749
<> 144:ef7eb2e8f9f7 2750 /**
<> 144:ef7eb2e8f9f7 2751 * @brief DMA transfer complete callback for injected conversion.
<> 144:ef7eb2e8f9f7 2752 * @param hdma : DMA handle.
<> 144:ef7eb2e8f9f7 2753 * @retval None
<> 144:ef7eb2e8f9f7 2754 */
<> 144:ef7eb2e8f9f7 2755 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2756 {
<> 144:ef7eb2e8f9f7 2757 /* Get DFSDM filter handle */
<> 144:ef7eb2e8f9f7 2758 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2759
<> 144:ef7eb2e8f9f7 2760 /* Call injected conversion complete callback */
<> 144:ef7eb2e8f9f7 2761 HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2762 }
<> 144:ef7eb2e8f9f7 2763
<> 144:ef7eb2e8f9f7 2764 /**
<> 144:ef7eb2e8f9f7 2765 * @brief DMA error callback.
<> 144:ef7eb2e8f9f7 2766 * @param hdma : DMA handle.
<> 144:ef7eb2e8f9f7 2767 * @retval None
<> 144:ef7eb2e8f9f7 2768 */
<> 144:ef7eb2e8f9f7 2769 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2770 {
<> 144:ef7eb2e8f9f7 2771 /* Get DFSDM filter handle */
<> 144:ef7eb2e8f9f7 2772 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2773
<> 144:ef7eb2e8f9f7 2774 /* Update error code */
<> 144:ef7eb2e8f9f7 2775 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
<> 144:ef7eb2e8f9f7 2776
<> 144:ef7eb2e8f9f7 2777 /* Call error callback */
<> 144:ef7eb2e8f9f7 2778 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2779 }
<> 144:ef7eb2e8f9f7 2780
<> 144:ef7eb2e8f9f7 2781 /**
<> 144:ef7eb2e8f9f7 2782 * @brief This function allows to get the number of injected channels.
<> 144:ef7eb2e8f9f7 2783 * @param Channels : bitfield of injected channels.
<> 144:ef7eb2e8f9f7 2784 * @retval Number of injected channels.
<> 144:ef7eb2e8f9f7 2785 */
<> 144:ef7eb2e8f9f7 2786 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
<> 144:ef7eb2e8f9f7 2787 {
<> 144:ef7eb2e8f9f7 2788 uint32_t nbChannels = 0;
<> 144:ef7eb2e8f9f7 2789 uint32_t tmp;
<> 144:ef7eb2e8f9f7 2790
<> 144:ef7eb2e8f9f7 2791 /* Get the number of channels from bitfield */
<> 144:ef7eb2e8f9f7 2792 tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);
<> 144:ef7eb2e8f9f7 2793 while(tmp != 0)
<> 144:ef7eb2e8f9f7 2794 {
<> 144:ef7eb2e8f9f7 2795 if((tmp & 1) != 0)
<> 144:ef7eb2e8f9f7 2796 {
<> 144:ef7eb2e8f9f7 2797 nbChannels++;
<> 144:ef7eb2e8f9f7 2798 }
<> 144:ef7eb2e8f9f7 2799 tmp = (uint32_t) (tmp >> 1);
<> 144:ef7eb2e8f9f7 2800 }
<> 144:ef7eb2e8f9f7 2801 return nbChannels;
<> 144:ef7eb2e8f9f7 2802 }
<> 144:ef7eb2e8f9f7 2803
<> 144:ef7eb2e8f9f7 2804 /**
<> 144:ef7eb2e8f9f7 2805 * @brief This function allows to get the channel number from channel instance.
<> 144:ef7eb2e8f9f7 2806 * @param Instance : DFSDM channel instance.
<> 144:ef7eb2e8f9f7 2807 * @retval Channel number.
<> 144:ef7eb2e8f9f7 2808 */
<> 144:ef7eb2e8f9f7 2809 static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
<> 144:ef7eb2e8f9f7 2810 {
<> 144:ef7eb2e8f9f7 2811 uint32_t channel = 0xFF;
<> 144:ef7eb2e8f9f7 2812
<> 144:ef7eb2e8f9f7 2813 /* Get channel from instance */
<> 144:ef7eb2e8f9f7 2814 if(Instance == DFSDM1_Channel0)
<> 144:ef7eb2e8f9f7 2815 {
<> 144:ef7eb2e8f9f7 2816 channel = 0;
<> 144:ef7eb2e8f9f7 2817 }
<> 144:ef7eb2e8f9f7 2818 else if(Instance == DFSDM1_Channel1)
<> 144:ef7eb2e8f9f7 2819 {
<> 144:ef7eb2e8f9f7 2820 channel = 1;
<> 144:ef7eb2e8f9f7 2821 }
<> 144:ef7eb2e8f9f7 2822 else if(Instance == DFSDM1_Channel2)
<> 144:ef7eb2e8f9f7 2823 {
<> 144:ef7eb2e8f9f7 2824 channel = 2;
<> 144:ef7eb2e8f9f7 2825 }
<> 144:ef7eb2e8f9f7 2826 else if(Instance == DFSDM1_Channel3)
<> 144:ef7eb2e8f9f7 2827 {
<> 144:ef7eb2e8f9f7 2828 channel = 3;
<> 144:ef7eb2e8f9f7 2829 }
AnnaBridge 167:e84263d55307 2830 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
AnnaBridge 167:e84263d55307 2831 defined(STM32L496xx) || defined(STM32L4A6xx)
<> 144:ef7eb2e8f9f7 2832 else if(Instance == DFSDM1_Channel4)
<> 144:ef7eb2e8f9f7 2833 {
<> 144:ef7eb2e8f9f7 2834 channel = 4;
<> 144:ef7eb2e8f9f7 2835 }
<> 144:ef7eb2e8f9f7 2836 else if(Instance == DFSDM1_Channel5)
<> 144:ef7eb2e8f9f7 2837 {
<> 144:ef7eb2e8f9f7 2838 channel = 5;
<> 144:ef7eb2e8f9f7 2839 }
<> 144:ef7eb2e8f9f7 2840 else if(Instance == DFSDM1_Channel6)
<> 144:ef7eb2e8f9f7 2841 {
<> 144:ef7eb2e8f9f7 2842 channel = 6;
<> 144:ef7eb2e8f9f7 2843 }
<> 144:ef7eb2e8f9f7 2844 else if(Instance == DFSDM1_Channel7)
<> 144:ef7eb2e8f9f7 2845 {
<> 144:ef7eb2e8f9f7 2846 channel = 7;
<> 144:ef7eb2e8f9f7 2847 }
AnnaBridge 167:e84263d55307 2848 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
<> 144:ef7eb2e8f9f7 2849
<> 144:ef7eb2e8f9f7 2850 return channel;
<> 144:ef7eb2e8f9f7 2851 }
<> 144:ef7eb2e8f9f7 2852
<> 144:ef7eb2e8f9f7 2853 /**
<> 144:ef7eb2e8f9f7 2854 * @brief This function allows to really start regular conversion.
<> 144:ef7eb2e8f9f7 2855 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2856 * @retval None
<> 144:ef7eb2e8f9f7 2857 */
<> 144:ef7eb2e8f9f7 2858 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2859 {
<> 144:ef7eb2e8f9f7 2860 /* Check regular trigger */
<> 144:ef7eb2e8f9f7 2861 if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)
<> 144:ef7eb2e8f9f7 2862 {
<> 144:ef7eb2e8f9f7 2863 /* Software start of regular conversion */
<> 144:ef7eb2e8f9f7 2864 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
<> 144:ef7eb2e8f9f7 2865 }
<> 144:ef7eb2e8f9f7 2866 else /* synchronous trigger */
<> 144:ef7eb2e8f9f7 2867 {
<> 144:ef7eb2e8f9f7 2868 /* Disable DFSDM filter */
<> 144:ef7eb2e8f9f7 2869 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
<> 144:ef7eb2e8f9f7 2870
<> 144:ef7eb2e8f9f7 2871 /* Set RSYNC bit in DFSDM_FLTCR1 register */
<> 144:ef7eb2e8f9f7 2872 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
<> 144:ef7eb2e8f9f7 2873
<> 144:ef7eb2e8f9f7 2874 /* Enable DFSDM filter */
<> 144:ef7eb2e8f9f7 2875 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
<> 144:ef7eb2e8f9f7 2876
<> 144:ef7eb2e8f9f7 2877 /* If injected conversion was in progress, restart it */
<> 144:ef7eb2e8f9f7 2878 if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
<> 144:ef7eb2e8f9f7 2879 {
<> 144:ef7eb2e8f9f7 2880 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
<> 144:ef7eb2e8f9f7 2881 {
<> 144:ef7eb2e8f9f7 2882 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
<> 144:ef7eb2e8f9f7 2883 }
<> 144:ef7eb2e8f9f7 2884 /* Update remaining injected conversions */
<> 144:ef7eb2e8f9f7 2885 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
<> 144:ef7eb2e8f9f7 2886 hdfsdm_filter->InjectedChannelsNbr : 1;
<> 144:ef7eb2e8f9f7 2887 }
<> 144:ef7eb2e8f9f7 2888 }
<> 144:ef7eb2e8f9f7 2889 /* Update DFSDM filter state */
<> 144:ef7eb2e8f9f7 2890 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
<> 144:ef7eb2e8f9f7 2891 HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
<> 144:ef7eb2e8f9f7 2892 }
<> 144:ef7eb2e8f9f7 2893
<> 144:ef7eb2e8f9f7 2894 /**
<> 144:ef7eb2e8f9f7 2895 * @brief This function allows to really stop regular conversion.
<> 144:ef7eb2e8f9f7 2896 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2897 * @retval None
<> 144:ef7eb2e8f9f7 2898 */
<> 144:ef7eb2e8f9f7 2899 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2900 {
<> 144:ef7eb2e8f9f7 2901 /* Disable DFSDM filter */
<> 144:ef7eb2e8f9f7 2902 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
<> 144:ef7eb2e8f9f7 2903
<> 144:ef7eb2e8f9f7 2904 /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */
<> 144:ef7eb2e8f9f7 2905 if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)
<> 144:ef7eb2e8f9f7 2906 {
<> 144:ef7eb2e8f9f7 2907 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
<> 144:ef7eb2e8f9f7 2908 }
<> 144:ef7eb2e8f9f7 2909
<> 144:ef7eb2e8f9f7 2910 /* Enable DFSDM filter */
<> 144:ef7eb2e8f9f7 2911 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
<> 144:ef7eb2e8f9f7 2912
<> 144:ef7eb2e8f9f7 2913 /* If injected conversion was in progress, restart it */
<> 144:ef7eb2e8f9f7 2914 if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
<> 144:ef7eb2e8f9f7 2915 {
<> 144:ef7eb2e8f9f7 2916 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
<> 144:ef7eb2e8f9f7 2917 {
<> 144:ef7eb2e8f9f7 2918 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
<> 144:ef7eb2e8f9f7 2919 }
<> 144:ef7eb2e8f9f7 2920 /* Update remaining injected conversions */
<> 144:ef7eb2e8f9f7 2921 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
<> 144:ef7eb2e8f9f7 2922 hdfsdm_filter->InjectedChannelsNbr : 1;
<> 144:ef7eb2e8f9f7 2923 }
<> 144:ef7eb2e8f9f7 2924
<> 144:ef7eb2e8f9f7 2925 /* Update DFSDM filter state */
<> 144:ef7eb2e8f9f7 2926 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
<> 144:ef7eb2e8f9f7 2927 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
<> 144:ef7eb2e8f9f7 2928 }
<> 144:ef7eb2e8f9f7 2929
<> 144:ef7eb2e8f9f7 2930 /**
<> 144:ef7eb2e8f9f7 2931 * @brief This function allows to really start injected conversion.
<> 144:ef7eb2e8f9f7 2932 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2933 * @retval None
<> 144:ef7eb2e8f9f7 2934 */
<> 144:ef7eb2e8f9f7 2935 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2936 {
<> 144:ef7eb2e8f9f7 2937 /* Check injected trigger */
<> 144:ef7eb2e8f9f7 2938 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
<> 144:ef7eb2e8f9f7 2939 {
<> 144:ef7eb2e8f9f7 2940 /* Software start of injected conversion */
<> 144:ef7eb2e8f9f7 2941 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
<> 144:ef7eb2e8f9f7 2942 }
<> 144:ef7eb2e8f9f7 2943 else /* external or synchronous trigger */
<> 144:ef7eb2e8f9f7 2944 {
<> 144:ef7eb2e8f9f7 2945 /* Disable DFSDM filter */
<> 144:ef7eb2e8f9f7 2946 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
<> 144:ef7eb2e8f9f7 2947
<> 144:ef7eb2e8f9f7 2948 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
<> 144:ef7eb2e8f9f7 2949 {
<> 144:ef7eb2e8f9f7 2950 /* Set JSYNC bit in DFSDM_FLTCR1 register */
<> 144:ef7eb2e8f9f7 2951 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;
<> 144:ef7eb2e8f9f7 2952 }
<> 144:ef7eb2e8f9f7 2953 else /* external trigger */
<> 144:ef7eb2e8f9f7 2954 {
<> 144:ef7eb2e8f9f7 2955 /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
<> 144:ef7eb2e8f9f7 2956 hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
<> 144:ef7eb2e8f9f7 2957 }
<> 144:ef7eb2e8f9f7 2958
<> 144:ef7eb2e8f9f7 2959 /* Enable DFSDM filter */
<> 144:ef7eb2e8f9f7 2960 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
<> 144:ef7eb2e8f9f7 2961
<> 144:ef7eb2e8f9f7 2962 /* If regular conversion was in progress, restart it */
<> 144:ef7eb2e8f9f7 2963 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
<> 144:ef7eb2e8f9f7 2964 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
<> 144:ef7eb2e8f9f7 2965 {
<> 144:ef7eb2e8f9f7 2966 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
<> 144:ef7eb2e8f9f7 2967 }
<> 144:ef7eb2e8f9f7 2968 }
<> 144:ef7eb2e8f9f7 2969 /* Update DFSDM filter state */
<> 144:ef7eb2e8f9f7 2970 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
<> 144:ef7eb2e8f9f7 2971 HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;
<> 144:ef7eb2e8f9f7 2972 }
<> 144:ef7eb2e8f9f7 2973
<> 144:ef7eb2e8f9f7 2974 /**
<> 144:ef7eb2e8f9f7 2975 * @brief This function allows to really stop injected conversion.
<> 144:ef7eb2e8f9f7 2976 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2977 * @retval None
<> 144:ef7eb2e8f9f7 2978 */
<> 144:ef7eb2e8f9f7 2979 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2980 {
<> 144:ef7eb2e8f9f7 2981 /* Disable DFSDM filter */
<> 144:ef7eb2e8f9f7 2982 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
<> 144:ef7eb2e8f9f7 2983
<> 144:ef7eb2e8f9f7 2984 /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */
<> 144:ef7eb2e8f9f7 2985 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
<> 144:ef7eb2e8f9f7 2986 {
<> 144:ef7eb2e8f9f7 2987 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);
<> 144:ef7eb2e8f9f7 2988 }
<> 144:ef7eb2e8f9f7 2989 else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)
<> 144:ef7eb2e8f9f7 2990 {
<> 144:ef7eb2e8f9f7 2991 /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
<> 144:ef7eb2e8f9f7 2992 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
<> 144:ef7eb2e8f9f7 2993 }
<> 144:ef7eb2e8f9f7 2994
<> 144:ef7eb2e8f9f7 2995 /* Enable DFSDM filter */
<> 144:ef7eb2e8f9f7 2996 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
<> 144:ef7eb2e8f9f7 2997
<> 144:ef7eb2e8f9f7 2998 /* If regular conversion was in progress, restart it */
<> 144:ef7eb2e8f9f7 2999 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
<> 144:ef7eb2e8f9f7 3000 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
<> 144:ef7eb2e8f9f7 3001 {
<> 144:ef7eb2e8f9f7 3002 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
<> 144:ef7eb2e8f9f7 3003 }
<> 144:ef7eb2e8f9f7 3004
<> 144:ef7eb2e8f9f7 3005 /* Update remaining injected conversions */
<> 144:ef7eb2e8f9f7 3006 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
<> 144:ef7eb2e8f9f7 3007 hdfsdm_filter->InjectedChannelsNbr : 1;
<> 144:ef7eb2e8f9f7 3008
<> 144:ef7eb2e8f9f7 3009 /* Update DFSDM filter state */
<> 144:ef7eb2e8f9f7 3010 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
<> 144:ef7eb2e8f9f7 3011 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
<> 144:ef7eb2e8f9f7 3012 }
<> 144:ef7eb2e8f9f7 3013
<> 144:ef7eb2e8f9f7 3014 /**
<> 144:ef7eb2e8f9f7 3015 * @}
<> 144:ef7eb2e8f9f7 3016 */
<> 144:ef7eb2e8f9f7 3017 /* End of private functions --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 3018
<> 144:ef7eb2e8f9f7 3019 /**
<> 144:ef7eb2e8f9f7 3020 * @}
<> 144:ef7eb2e8f9f7 3021 */
AnnaBridge 167:e84263d55307 3022 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
<> 144:ef7eb2e8f9f7 3023 #endif /* HAL_DFSDM_MODULE_ENABLED */
AnnaBridge 167:e84263d55307 3024
<> 144:ef7eb2e8f9f7 3025 /**
<> 144:ef7eb2e8f9f7 3026 * @}
<> 144:ef7eb2e8f9f7 3027 */
<> 144:ef7eb2e8f9f7 3028
<> 144:ef7eb2e8f9f7 3029 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/