Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c@181:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
181:96ed750bd169
Parent:
167:e84263d55307 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_usart.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief USART LL module driver.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 40 #include "stm32l4xx_ll_usart.h"
<> 144:ef7eb2e8f9f7 41 #include "stm32l4xx_ll_rcc.h"
<> 144:ef7eb2e8f9f7 42 #include "stm32l4xx_ll_bus.h"
<> 144:ef7eb2e8f9f7 43 #ifdef USE_FULL_ASSERT
<> 144:ef7eb2e8f9f7 44 #include "stm32_assert.h"
<> 144:ef7eb2e8f9f7 45 #else
<> 144:ef7eb2e8f9f7 46 #define assert_param(expr) ((void)0U)
<> 144:ef7eb2e8f9f7 47 #endif
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup USART_LL
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 62 /** @addtogroup USART_LL_Private_Constants
<> 144:ef7eb2e8f9f7 63 * @{
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /**
<> 144:ef7eb2e8f9f7 67 * @}
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 72 /** @addtogroup USART_LL_Private_Macros
<> 144:ef7eb2e8f9f7 73 * @{
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
<> 144:ef7eb2e8f9f7 77 * divided by the smallest oversampling used on the USART (i.e. 8) */
<> 144:ef7eb2e8f9f7 78 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
<> 144:ef7eb2e8f9f7 79
AnnaBridge 167:e84263d55307 80 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
AnnaBridge 167:e84263d55307 81 #define IS_LL_USART_BRR(__VALUE__) (((__VALUE__) >= 16U) \
AnnaBridge 167:e84263d55307 82 && ((__VALUE__) <= 0x0000FFFFU))
AnnaBridge 167:e84263d55307 83
<> 144:ef7eb2e8f9f7 84 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
<> 144:ef7eb2e8f9f7 85 || ((__VALUE__) == LL_USART_DIRECTION_RX) \
<> 144:ef7eb2e8f9f7 86 || ((__VALUE__) == LL_USART_DIRECTION_TX) \
<> 144:ef7eb2e8f9f7 87 || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 90 || ((__VALUE__) == LL_USART_PARITY_EVEN) \
<> 144:ef7eb2e8f9f7 91 || ((__VALUE__) == LL_USART_PARITY_ODD))
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
<> 144:ef7eb2e8f9f7 94 || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
<> 144:ef7eb2e8f9f7 95 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
<> 144:ef7eb2e8f9f7 98 || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
<> 144:ef7eb2e8f9f7 101 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
<> 144:ef7eb2e8f9f7 104 || ((__VALUE__) == LL_USART_PHASE_2EDGE))
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
<> 144:ef7eb2e8f9f7 107 || ((__VALUE__) == LL_USART_POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
<> 144:ef7eb2e8f9f7 110 || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
<> 144:ef7eb2e8f9f7 113 || ((__VALUE__) == LL_USART_STOPBITS_1) \
<> 144:ef7eb2e8f9f7 114 || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
<> 144:ef7eb2e8f9f7 115 || ((__VALUE__) == LL_USART_STOPBITS_2))
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
<> 144:ef7eb2e8f9f7 118 || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
<> 144:ef7eb2e8f9f7 119 || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
<> 144:ef7eb2e8f9f7 120 || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @}
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 /** @addtogroup USART_LL_Exported_Functions
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @addtogroup USART_LL_EF_Init
<> 144:ef7eb2e8f9f7 134 * @{
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /**
<> 144:ef7eb2e8f9f7 138 * @brief De-initialize USART registers (Registers restored to their default values).
<> 144:ef7eb2e8f9f7 139 * @param USARTx USART Instance
<> 144:ef7eb2e8f9f7 140 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 141 * - SUCCESS: USART registers are de-initialized
<> 144:ef7eb2e8f9f7 142 * - ERROR: USART registers are not de-initialized
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 ErrorStatus status = SUCCESS;
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Check the parameters */
<> 144:ef7eb2e8f9f7 149 assert_param(IS_UART_INSTANCE(USARTx));
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 if (USARTx == USART1)
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 /* Force reset of USART clock */
<> 144:ef7eb2e8f9f7 154 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /* Release reset of USART clock */
<> 144:ef7eb2e8f9f7 157 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159 else if (USARTx == USART2)
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 /* Force reset of USART clock */
<> 144:ef7eb2e8f9f7 162 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Release reset of USART clock */
<> 144:ef7eb2e8f9f7 165 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
<> 144:ef7eb2e8f9f7 166 }
<> 144:ef7eb2e8f9f7 167 #if defined(USART3)
<> 144:ef7eb2e8f9f7 168 else if (USARTx == USART3)
<> 144:ef7eb2e8f9f7 169 {
<> 144:ef7eb2e8f9f7 170 /* Force reset of USART clock */
<> 144:ef7eb2e8f9f7 171 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /* Release reset of USART clock */
<> 144:ef7eb2e8f9f7 174 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176 #endif /* USART3 */
<> 144:ef7eb2e8f9f7 177 #if defined(UART4)
<> 144:ef7eb2e8f9f7 178 else if (USARTx == UART4)
<> 144:ef7eb2e8f9f7 179 {
<> 144:ef7eb2e8f9f7 180 /* Force reset of UART clock */
<> 144:ef7eb2e8f9f7 181 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Release reset of UART clock */
<> 144:ef7eb2e8f9f7 184 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186 #endif /* UART4 */
<> 144:ef7eb2e8f9f7 187 #if defined(UART5)
<> 144:ef7eb2e8f9f7 188 else if (USARTx == UART5)
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190 /* Force reset of UART clock */
<> 144:ef7eb2e8f9f7 191 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Release reset of UART clock */
<> 144:ef7eb2e8f9f7 194 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
<> 144:ef7eb2e8f9f7 195 }
<> 144:ef7eb2e8f9f7 196 #endif /* UART5 */
<> 144:ef7eb2e8f9f7 197 else
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 status = ERROR;
<> 144:ef7eb2e8f9f7 200 }
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 return (status);
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /**
<> 144:ef7eb2e8f9f7 206 * @brief Initialize USART registers according to the specified
<> 144:ef7eb2e8f9f7 207 * parameters in USART_InitStruct.
<> 144:ef7eb2e8f9f7 208 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
<> 144:ef7eb2e8f9f7 209 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 144:ef7eb2e8f9f7 210 * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
<> 144:ef7eb2e8f9f7 211 * @param USARTx USART Instance
<> 144:ef7eb2e8f9f7 212 * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
<> 144:ef7eb2e8f9f7 213 * that contains the configuration information for the specified USART peripheral.
<> 144:ef7eb2e8f9f7 214 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 215 * - SUCCESS: USART registers are initialized according to USART_InitStruct content
<> 144:ef7eb2e8f9f7 216 * - ERROR: Problem occurred during USART Registers initialization
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 ErrorStatus status = ERROR;
<> 144:ef7eb2e8f9f7 221 uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Check the parameters */
<> 144:ef7eb2e8f9f7 224 assert_param(IS_UART_INSTANCE(USARTx));
<> 144:ef7eb2e8f9f7 225 assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
<> 144:ef7eb2e8f9f7 226 assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
<> 144:ef7eb2e8f9f7 227 assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
<> 144:ef7eb2e8f9f7 228 assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
<> 144:ef7eb2e8f9f7 229 assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
<> 144:ef7eb2e8f9f7 230 assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
<> 144:ef7eb2e8f9f7 231 assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /* USART needs to be in disabled state, in order to be able to configure some bits in
<> 144:ef7eb2e8f9f7 234 CRx registers */
<> 144:ef7eb2e8f9f7 235 if (LL_USART_IsEnabled(USARTx) == 0U)
<> 144:ef7eb2e8f9f7 236 {
AnnaBridge 167:e84263d55307 237 /*---------------------------- USART CR1 Configuration ---------------------
<> 144:ef7eb2e8f9f7 238 * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
<> 144:ef7eb2e8f9f7 239 * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
<> 144:ef7eb2e8f9f7 240 * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
<> 144:ef7eb2e8f9f7 241 * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
<> 144:ef7eb2e8f9f7 242 * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244 MODIFY_REG(USARTx->CR1,
<> 144:ef7eb2e8f9f7 245 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
<> 144:ef7eb2e8f9f7 246 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
<> 144:ef7eb2e8f9f7 247 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
<> 144:ef7eb2e8f9f7 248 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
<> 144:ef7eb2e8f9f7 249
AnnaBridge 167:e84263d55307 250 /*---------------------------- USART CR2 Configuration ---------------------
<> 144:ef7eb2e8f9f7 251 * Configure USARTx CR2 (Stop bits) with parameters:
<> 144:ef7eb2e8f9f7 252 * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
<> 144:ef7eb2e8f9f7 253 * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255 LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
<> 144:ef7eb2e8f9f7 256
AnnaBridge 167:e84263d55307 257 /*---------------------------- USART CR3 Configuration ---------------------
<> 144:ef7eb2e8f9f7 258 * Configure USARTx CR3 (Hardware Flow Control) with parameters:
<> 144:ef7eb2e8f9f7 259 * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261 LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
<> 144:ef7eb2e8f9f7 262
AnnaBridge 167:e84263d55307 263 /*---------------------------- USART BRR Configuration ---------------------
<> 144:ef7eb2e8f9f7 264 * Retrieve Clock frequency used for USART Peripheral
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 if (USARTx == USART1)
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270 else if (USARTx == USART2)
<> 144:ef7eb2e8f9f7 271 {
<> 144:ef7eb2e8f9f7 272 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274 #if defined(USART3)
<> 144:ef7eb2e8f9f7 275 else if (USARTx == USART3)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279 #endif /* USART3 */
<> 144:ef7eb2e8f9f7 280 #if defined(UART4)
<> 144:ef7eb2e8f9f7 281 else if (USARTx == UART4)
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285 #endif /* UART4 */
<> 144:ef7eb2e8f9f7 286 #if defined(UART5)
<> 144:ef7eb2e8f9f7 287 else if (USARTx == UART5)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291 #endif /* UART5 */
<> 144:ef7eb2e8f9f7 292 else
<> 144:ef7eb2e8f9f7 293 {
<> 144:ef7eb2e8f9f7 294 /* Nothing to do, as error code is already assigned to ERROR value */
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* Configure the USART Baud Rate :
<> 144:ef7eb2e8f9f7 298 - valid baud rate value (different from 0) is required
<> 144:ef7eb2e8f9f7 299 - Peripheral clock as returned by RCC service, should be valid (different from 0).
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
<> 144:ef7eb2e8f9f7 302 && (USART_InitStruct->BaudRate != 0U))
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 status = SUCCESS;
<> 144:ef7eb2e8f9f7 305 LL_USART_SetBaudRate(USARTx,
<> 144:ef7eb2e8f9f7 306 periphclk,
<> 144:ef7eb2e8f9f7 307 USART_InitStruct->OverSampling,
<> 144:ef7eb2e8f9f7 308 USART_InitStruct->BaudRate);
AnnaBridge 167:e84263d55307 309
AnnaBridge 167:e84263d55307 310 /* Check BRR is greater than or equal to 16d */
AnnaBridge 167:e84263d55307 311 assert_param(IS_LL_USART_BRR(USARTx->BRR));
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314 /* Endif (=> USART not in Disabled state => return ERROR) */
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 return (status);
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /**
<> 144:ef7eb2e8f9f7 320 * @brief Set each @ref LL_USART_InitTypeDef field to default value.
<> 144:ef7eb2e8f9f7 321 * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
<> 144:ef7eb2e8f9f7 322 * whose fields will be set to default values.
<> 144:ef7eb2e8f9f7 323 * @retval None
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 /* Set USART_InitStruct fields to default values */
<> 144:ef7eb2e8f9f7 329 USART_InitStruct->BaudRate = 9600U;
<> 144:ef7eb2e8f9f7 330 USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
<> 144:ef7eb2e8f9f7 331 USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
<> 144:ef7eb2e8f9f7 332 USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
<> 144:ef7eb2e8f9f7 333 USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
<> 144:ef7eb2e8f9f7 334 USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
<> 144:ef7eb2e8f9f7 335 USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @brief Initialize USART Clock related settings according to the
<> 144:ef7eb2e8f9f7 340 * specified parameters in the USART_ClockInitStruct.
<> 144:ef7eb2e8f9f7 341 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
<> 144:ef7eb2e8f9f7 342 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 144:ef7eb2e8f9f7 343 * @param USARTx USART Instance
<> 144:ef7eb2e8f9f7 344 * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
<> 144:ef7eb2e8f9f7 345 * that contains the Clock configuration information for the specified USART peripheral.
<> 144:ef7eb2e8f9f7 346 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 347 * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
<> 144:ef7eb2e8f9f7 348 * - ERROR: Problem occurred during USART Registers initialization
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
<> 144:ef7eb2e8f9f7 351 {
<> 144:ef7eb2e8f9f7 352 ErrorStatus status = SUCCESS;
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* Check USART Instance and Clock signal output parameters */
<> 144:ef7eb2e8f9f7 355 assert_param(IS_UART_INSTANCE(USARTx));
<> 144:ef7eb2e8f9f7 356 assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* USART needs to be in disabled state, in order to be able to configure some bits in
<> 144:ef7eb2e8f9f7 359 CRx registers */
<> 144:ef7eb2e8f9f7 360 if (LL_USART_IsEnabled(USARTx) == 0U)
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 /*---------------------------- USART CR2 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 363 /* If Clock signal has to be output */
<> 144:ef7eb2e8f9f7 364 if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
<> 144:ef7eb2e8f9f7 365 {
<> 144:ef7eb2e8f9f7 366 /* Deactivate Clock signal delivery :
<> 144:ef7eb2e8f9f7 367 * - Disable Clock Output: USART_CR2_CLKEN cleared
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369 LL_USART_DisableSCLKOutput(USARTx);
<> 144:ef7eb2e8f9f7 370 }
<> 144:ef7eb2e8f9f7 371 else
<> 144:ef7eb2e8f9f7 372 {
<> 144:ef7eb2e8f9f7 373 /* Ensure USART instance is USART capable */
<> 144:ef7eb2e8f9f7 374 assert_param(IS_USART_INSTANCE(USARTx));
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Check clock related parameters */
<> 144:ef7eb2e8f9f7 377 assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
<> 144:ef7eb2e8f9f7 378 assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
<> 144:ef7eb2e8f9f7 379 assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /*---------------------------- USART CR2 Configuration -----------------------
<> 144:ef7eb2e8f9f7 382 * Configure USARTx CR2 (Clock signal related bits) with parameters:
<> 144:ef7eb2e8f9f7 383 * - Enable Clock Output: USART_CR2_CLKEN set
<> 144:ef7eb2e8f9f7 384 * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
<> 144:ef7eb2e8f9f7 385 * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
<> 144:ef7eb2e8f9f7 386 * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 MODIFY_REG(USARTx->CR2,
<> 144:ef7eb2e8f9f7 389 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
<> 144:ef7eb2e8f9f7 390 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
<> 144:ef7eb2e8f9f7 391 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
<> 144:ef7eb2e8f9f7 392 }
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394 /* Else (USART not in Disabled state => return ERROR */
<> 144:ef7eb2e8f9f7 395 else
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 status = ERROR;
<> 144:ef7eb2e8f9f7 398 }
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 return (status);
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /**
<> 144:ef7eb2e8f9f7 404 * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
<> 144:ef7eb2e8f9f7 405 * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
<> 144:ef7eb2e8f9f7 406 * whose fields will be set to default values.
<> 144:ef7eb2e8f9f7 407 * @retval None
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 /* Set LL_USART_ClockInitStruct fields with default values */
<> 144:ef7eb2e8f9f7 412 USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
<> 144:ef7eb2e8f9f7 413 USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 144:ef7eb2e8f9f7 414 USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 144:ef7eb2e8f9f7 415 USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 144:ef7eb2e8f9f7 416 }
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /**
<> 144:ef7eb2e8f9f7 419 * @}
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /**
<> 144:ef7eb2e8f9f7 423 * @}
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /**
<> 144:ef7eb2e8f9f7 427 * @}
<> 144:ef7eb2e8f9f7 428 */
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 #endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /**
<> 144:ef7eb2e8f9f7 433 * @}
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 #endif /* USE_FULL_LL_DRIVER */
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 439