Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h@181:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
181:96ed750bd169
Parent:
167:e84263d55307 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_rng.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of RNG LL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L4xx_LL_RNG_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L4xx_LL_RNG_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l4xx.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 #if defined(RNG)
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @defgroup RNG_LL RNG
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 62 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 65 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 66 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
<> 144:ef7eb2e8f9f7 67 * @{
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
<> 144:ef7eb2e8f9f7 71 * @brief Flags defines which can be used with LL_RNG_ReadReg function
<> 144:ef7eb2e8f9f7 72 * @{
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74 #define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
<> 144:ef7eb2e8f9f7 75 #define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
<> 144:ef7eb2e8f9f7 76 #define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
<> 144:ef7eb2e8f9f7 77 #define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
<> 144:ef7eb2e8f9f7 78 #define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
<> 144:ef7eb2e8f9f7 79 /**
<> 144:ef7eb2e8f9f7 80 * @}
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /** @defgroup RNG_LL_EC_IT IT Defines
<> 144:ef7eb2e8f9f7 84 * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
<> 144:ef7eb2e8f9f7 85 * @{
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87 #define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
<> 144:ef7eb2e8f9f7 88 /**
<> 144:ef7eb2e8f9f7 89 * @}
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /**
<> 144:ef7eb2e8f9f7 93 * @}
<> 144:ef7eb2e8f9f7 94 */
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 97 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
<> 144:ef7eb2e8f9f7 98 * @{
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /**
<> 144:ef7eb2e8f9f7 106 * @brief Write a value in RNG register
<> 144:ef7eb2e8f9f7 107 * @param __INSTANCE__ RNG Instance
<> 144:ef7eb2e8f9f7 108 * @param __REG__ Register to be written
<> 144:ef7eb2e8f9f7 109 * @param __VALUE__ Value to be written in the register
<> 144:ef7eb2e8f9f7 110 * @retval None
<> 144:ef7eb2e8f9f7 111 */
<> 144:ef7eb2e8f9f7 112 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /**
<> 144:ef7eb2e8f9f7 115 * @brief Read a value in RNG register
<> 144:ef7eb2e8f9f7 116 * @param __INSTANCE__ RNG Instance
<> 144:ef7eb2e8f9f7 117 * @param __REG__ Register to be read
<> 144:ef7eb2e8f9f7 118 * @retval Register value
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 144:ef7eb2e8f9f7 121 /**
<> 144:ef7eb2e8f9f7 122 * @}
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @}
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 131 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /**
<> 144:ef7eb2e8f9f7 139 * @brief Enable Random Number Generation
<> 144:ef7eb2e8f9f7 140 * @rmtoll CR RNGEN LL_RNG_Enable
<> 144:ef7eb2e8f9f7 141 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 142 * @retval None
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 SET_BIT(RNGx->CR, RNG_CR_RNGEN);
<> 144:ef7eb2e8f9f7 147 }
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /**
<> 144:ef7eb2e8f9f7 150 * @brief Disable Random Number Generation
<> 144:ef7eb2e8f9f7 151 * @rmtoll CR RNGEN LL_RNG_Disable
<> 144:ef7eb2e8f9f7 152 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 153 * @retval None
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 156 {
<> 144:ef7eb2e8f9f7 157 CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /**
<> 144:ef7eb2e8f9f7 161 * @brief Check if Random Number Generator is enabled
<> 144:ef7eb2e8f9f7 162 * @rmtoll CR RNGEN LL_RNG_IsEnabled
<> 144:ef7eb2e8f9f7 163 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 164 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 return (READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN));
<> 144:ef7eb2e8f9f7 169 }
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /**
<> 144:ef7eb2e8f9f7 172 * @}
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
<> 144:ef7eb2e8f9f7 176 * @{
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @brief Indicate if the RNG Data ready Flag is set or not
<> 144:ef7eb2e8f9f7 181 * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
<> 144:ef7eb2e8f9f7 182 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 183 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 186 {
<> 144:ef7eb2e8f9f7 187 return (READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY));
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @brief Indicate if the Clock Error Current Status Flag is set or not
<> 144:ef7eb2e8f9f7 192 * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
<> 144:ef7eb2e8f9f7 193 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 194 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 197 {
<> 144:ef7eb2e8f9f7 198 return (READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS));
<> 144:ef7eb2e8f9f7 199 }
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /**
<> 144:ef7eb2e8f9f7 202 * @brief Indicate if the Seed Error Current Status Flag is set or not
<> 144:ef7eb2e8f9f7 203 * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
<> 144:ef7eb2e8f9f7 204 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 205 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 208 {
<> 144:ef7eb2e8f9f7 209 return (READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS));
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @brief Indicate if the Clock Error Interrupt Status Flag is set or not
<> 144:ef7eb2e8f9f7 214 * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
<> 144:ef7eb2e8f9f7 215 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 216 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 return (READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS));
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @brief Indicate if the Seed Error Interrupt Status Flag is set or not
<> 144:ef7eb2e8f9f7 225 * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
<> 144:ef7eb2e8f9f7 226 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 227 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 230 {
<> 144:ef7eb2e8f9f7 231 return (READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS));
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @brief Clear Clock Error interrupt Status (CEIS) Flag
<> 144:ef7eb2e8f9f7 236 * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
<> 144:ef7eb2e8f9f7 237 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 238 * @retval None
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @brief Clear Seed Error interrupt Status (SEIS) Flag
<> 144:ef7eb2e8f9f7 247 * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
<> 144:ef7eb2e8f9f7 248 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 249 * @retval None
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 252 {
<> 144:ef7eb2e8f9f7 253 WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
<> 144:ef7eb2e8f9f7 254 }
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @}
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /** @defgroup RNG_LL_EF_IT_Management IT Management
<> 144:ef7eb2e8f9f7 261 * @{
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @brief Enable Random Number Generator Interrupt
<> 144:ef7eb2e8f9f7 266 * (applies for either Seed error, Clock Error or Data ready interrupts)
<> 144:ef7eb2e8f9f7 267 * @rmtoll CR IE LL_RNG_EnableIT
<> 144:ef7eb2e8f9f7 268 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 269 * @retval None
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 SET_BIT(RNGx->CR, RNG_CR_IE);
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @brief Disable Random Number Generator Interrupt
<> 144:ef7eb2e8f9f7 278 * (applies for either Seed error, Clock Error or Data ready interrupts)
<> 144:ef7eb2e8f9f7 279 * @rmtoll CR IE LL_RNG_DisableIT
<> 144:ef7eb2e8f9f7 280 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 281 * @retval None
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 284 {
<> 144:ef7eb2e8f9f7 285 CLEAR_BIT(RNGx->CR, RNG_CR_IE);
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /**
<> 144:ef7eb2e8f9f7 289 * @brief Check if Random Number Generator Interrupt is enabled
<> 144:ef7eb2e8f9f7 290 * (applies for either Seed error, Clock Error or Data ready interrupts)
<> 144:ef7eb2e8f9f7 291 * @rmtoll CR IE LL_RNG_IsEnabledIT
<> 144:ef7eb2e8f9f7 292 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 293 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 return (READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE));
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @}
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /** @defgroup RNG_LL_EF_Data_Management Data Management
<> 144:ef7eb2e8f9f7 305 * @{
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /**
<> 144:ef7eb2e8f9f7 309 * @brief Return32-bit Random Number value
<> 144:ef7eb2e8f9f7 310 * @rmtoll DR RNDATA LL_RNG_ReadRandData32
<> 144:ef7eb2e8f9f7 311 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 312 * @retval Generated 32-bit random value
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 return (uint32_t)(READ_REG(RNGx->DR));
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /**
<> 144:ef7eb2e8f9f7 320 * @}
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 324 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 325 * @{
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /**
<> 144:ef7eb2e8f9f7 331 * @}
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 #endif /* USE_FULL_LL_DRIVER */
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /**
<> 144:ef7eb2e8f9f7 336 * @}
<> 144:ef7eb2e8f9f7 337 */
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /**
<> 144:ef7eb2e8f9f7 340 * @}
<> 144:ef7eb2e8f9f7 341 */
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 #endif /* defined(RNG) */
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @}
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 350 }
<> 144:ef7eb2e8f9f7 351 #endif
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 #endif /* __STM32L4xx_LL_RNG_H */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/