Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c@181:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
181:96ed750bd169
Parent:
167:e84263d55307 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_i2c.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief I2C LL module driver.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 40 #include "stm32l4xx_ll_i2c.h"
<> 144:ef7eb2e8f9f7 41 #include "stm32l4xx_ll_bus.h"
<> 144:ef7eb2e8f9f7 42 #ifdef USE_FULL_ASSERT
<> 144:ef7eb2e8f9f7 43 #include "stm32_assert.h"
<> 144:ef7eb2e8f9f7 44 #else
<> 144:ef7eb2e8f9f7 45 #define assert_param(expr) ((void)0U)
<> 144:ef7eb2e8f9f7 46 #endif
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
AnnaBridge 167:e84263d55307 52 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @defgroup I2C_LL I2C
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 62 /** @addtogroup I2C_LL_Private_Macros
<> 144:ef7eb2e8f9f7 63 * @{
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 #define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
<> 144:ef7eb2e8f9f7 67 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
<> 144:ef7eb2e8f9f7 68 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
<> 144:ef7eb2e8f9f7 69 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 #define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
<> 144:ef7eb2e8f9f7 72 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 #define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
<> 144:ef7eb2e8f9f7 75
AnnaBridge 167:e84263d55307 76 #define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
<> 144:ef7eb2e8f9f7 79 ((__VALUE__) == LL_I2C_NACK))
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
<> 144:ef7eb2e8f9f7 82 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
<> 144:ef7eb2e8f9f7 83 /**
<> 144:ef7eb2e8f9f7 84 * @}
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 90 /** @addtogroup I2C_LL_Exported_Functions
<> 144:ef7eb2e8f9f7 91 * @{
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /** @addtogroup I2C_LL_EF_Init
<> 144:ef7eb2e8f9f7 95 * @{
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /**
<> 144:ef7eb2e8f9f7 99 * @brief De-initialize the I2C registers to their default reset values.
<> 144:ef7eb2e8f9f7 100 * @param I2Cx I2C Instance.
<> 144:ef7eb2e8f9f7 101 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 102 * - SUCCESS: I2C registers are de-initialized
<> 144:ef7eb2e8f9f7 103 * - ERROR: I2C registers are not de-initialized
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
<> 144:ef7eb2e8f9f7 106 {
<> 144:ef7eb2e8f9f7 107 ErrorStatus status = SUCCESS;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /* Check the I2C Instance I2Cx */
<> 144:ef7eb2e8f9f7 110 assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 if (I2Cx == I2C1)
<> 144:ef7eb2e8f9f7 113 {
<> 144:ef7eb2e8f9f7 114 /* Force reset of I2C clock */
<> 144:ef7eb2e8f9f7 115 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /* Release reset of I2C clock */
<> 144:ef7eb2e8f9f7 118 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
<> 144:ef7eb2e8f9f7 119 }
<> 144:ef7eb2e8f9f7 120 #if defined(I2C2)
<> 144:ef7eb2e8f9f7 121 else if (I2Cx == I2C2)
<> 144:ef7eb2e8f9f7 122 {
<> 144:ef7eb2e8f9f7 123 /* Force reset of I2C clock */
<> 144:ef7eb2e8f9f7 124 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* Release reset of I2C clock */
<> 144:ef7eb2e8f9f7 127 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 }
<> 144:ef7eb2e8f9f7 130 #endif
<> 144:ef7eb2e8f9f7 131 else if (I2Cx == I2C3)
<> 144:ef7eb2e8f9f7 132 {
<> 144:ef7eb2e8f9f7 133 /* Force reset of I2C clock */
<> 144:ef7eb2e8f9f7 134 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* Release reset of I2C clock */
<> 144:ef7eb2e8f9f7 137 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
<> 144:ef7eb2e8f9f7 138 }
AnnaBridge 167:e84263d55307 139 #if defined(I2C4)
AnnaBridge 167:e84263d55307 140 else if (I2Cx == I2C4)
AnnaBridge 167:e84263d55307 141 {
AnnaBridge 167:e84263d55307 142 /* Force reset of I2C clock */
AnnaBridge 167:e84263d55307 143 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_I2C4);
AnnaBridge 167:e84263d55307 144
AnnaBridge 167:e84263d55307 145 /* Release reset of I2C clock */
AnnaBridge 167:e84263d55307 146 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_I2C4);
AnnaBridge 167:e84263d55307 147 }
AnnaBridge 167:e84263d55307 148 #endif
<> 144:ef7eb2e8f9f7 149 else
<> 144:ef7eb2e8f9f7 150 {
<> 144:ef7eb2e8f9f7 151 status = ERROR;
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 return status;
<> 144:ef7eb2e8f9f7 155 }
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /**
<> 144:ef7eb2e8f9f7 158 * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
<> 144:ef7eb2e8f9f7 159 * @param I2Cx I2C Instance.
<> 144:ef7eb2e8f9f7 160 * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 161 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 162 * - SUCCESS: I2C registers are initialized
<> 144:ef7eb2e8f9f7 163 * - ERROR: Not applicable
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
<> 144:ef7eb2e8f9f7 166 {
<> 144:ef7eb2e8f9f7 167 /* Check the I2C Instance I2Cx */
<> 144:ef7eb2e8f9f7 168 assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /* Check the I2C parameters from I2C_InitStruct */
<> 144:ef7eb2e8f9f7 171 assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
<> 144:ef7eb2e8f9f7 172 assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
<> 144:ef7eb2e8f9f7 173 assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
<> 144:ef7eb2e8f9f7 174 assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
<> 144:ef7eb2e8f9f7 175 assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
<> 144:ef7eb2e8f9f7 176 assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /* Disable the selected I2Cx Peripheral */
<> 144:ef7eb2e8f9f7 179 LL_I2C_Disable(I2Cx);
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /*---------------------------- I2Cx CR1 Configuration ------------------------
<> 144:ef7eb2e8f9f7 182 * Configure the analog and digital noise filters with parameters :
<> 144:ef7eb2e8f9f7 183 * - AnalogFilter: I2C_CR1_ANFOFF bit
<> 144:ef7eb2e8f9f7 184 * - DigitalFilter: I2C_CR1_DNF[3:0] bits
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186 LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /*---------------------------- I2Cx TIMINGR Configuration --------------------
<> 144:ef7eb2e8f9f7 189 * Configure the SDA setup, hold time and the SCL high, low period with parameter :
<> 144:ef7eb2e8f9f7 190 * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
<> 144:ef7eb2e8f9f7 191 * I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193 LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /* Enable the selected I2Cx Peripheral */
<> 144:ef7eb2e8f9f7 196 LL_I2C_Enable(I2Cx);
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /*---------------------------- I2Cx OAR1 Configuration -----------------------
<> 144:ef7eb2e8f9f7 199 * Disable, Configure and Enable I2Cx device own address 1 with parameters :
<> 144:ef7eb2e8f9f7 200 * - OwnAddress1: I2C_OAR1_OA1[9:0] bits
<> 144:ef7eb2e8f9f7 201 * - OwnAddrSize: I2C_OAR1_OA1MODE bit
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 LL_I2C_DisableOwnAddress1(I2Cx);
<> 144:ef7eb2e8f9f7 204 LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
AnnaBridge 167:e84263d55307 205
AnnaBridge 167:e84263d55307 206 /* OwnAdress1 == 0 is reserved for General Call address */
AnnaBridge 167:e84263d55307 207 if (I2C_InitStruct->OwnAddress1 != 0U)
AnnaBridge 167:e84263d55307 208 {
AnnaBridge 167:e84263d55307 209 LL_I2C_EnableOwnAddress1(I2Cx);
AnnaBridge 167:e84263d55307 210 }
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /*---------------------------- I2Cx MODE Configuration -----------------------
<> 144:ef7eb2e8f9f7 213 * Configure I2Cx peripheral mode with parameter :
<> 144:ef7eb2e8f9f7 214 * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /*---------------------------- I2Cx CR2 Configuration ------------------------
<> 144:ef7eb2e8f9f7 219 * Configure the ACKnowledge or Non ACKnowledge condition
<> 144:ef7eb2e8f9f7 220 * after the address receive match code or next received byte with parameter :
<> 144:ef7eb2e8f9f7 221 * - TypeAcknowledge: I2C_CR2_NACK bit
<> 144:ef7eb2e8f9f7 222 */
<> 144:ef7eb2e8f9f7 223 LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 return SUCCESS;
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /**
<> 144:ef7eb2e8f9f7 229 * @brief Set each @ref LL_I2C_InitTypeDef field to default value.
<> 144:ef7eb2e8f9f7 230 * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 231 * @retval None
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 /* Set I2C_InitStruct fields to default values */
<> 144:ef7eb2e8f9f7 236 I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
<> 144:ef7eb2e8f9f7 237 I2C_InitStruct->Timing = 0U;
<> 144:ef7eb2e8f9f7 238 I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
<> 144:ef7eb2e8f9f7 239 I2C_InitStruct->DigitalFilter = 0U;
<> 144:ef7eb2e8f9f7 240 I2C_InitStruct->OwnAddress1 = 0U;
<> 144:ef7eb2e8f9f7 241 I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
<> 144:ef7eb2e8f9f7 242 I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @}
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @}
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @}
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
AnnaBridge 167:e84263d55307 257 #endif /* I2C1 || I2C2 || I2C3 || I2C4 */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @}
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 #endif /* USE_FULL_LL_DRIVER */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/