Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c@181:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
181:96ed750bd169
Parent:
167:e84263d55307 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_dma.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief DMA LL module driver.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 40 #include "stm32l4xx_ll_dma.h"
<> 144:ef7eb2e8f9f7 41 #include "stm32l4xx_ll_bus.h"
<> 144:ef7eb2e8f9f7 42 #ifdef USE_FULL_ASSERT
<> 144:ef7eb2e8f9f7 43 #include "stm32_assert.h"
<> 144:ef7eb2e8f9f7 44 #else
<> 144:ef7eb2e8f9f7 45 #define assert_param(expr) ((void)0U)
<> 144:ef7eb2e8f9f7 46 #endif
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 #if defined (DMA1) || defined (DMA2)
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @defgroup DMA_LL DMA
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 62 /** @addtogroup DMA_LL_Private_Macros
<> 144:ef7eb2e8f9f7 63 * @{
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
<> 144:ef7eb2e8f9f7 66 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
<> 144:ef7eb2e8f9f7 67 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
<> 144:ef7eb2e8f9f7 70 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
<> 144:ef7eb2e8f9f7 73 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
<> 144:ef7eb2e8f9f7 76 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 79 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 80 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 83 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 84 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU)
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \
<> 144:ef7eb2e8f9f7 89 ((__VALUE__) == LL_DMA_REQUEST_1) || \
<> 144:ef7eb2e8f9f7 90 ((__VALUE__) == LL_DMA_REQUEST_2) || \
<> 144:ef7eb2e8f9f7 91 ((__VALUE__) == LL_DMA_REQUEST_3) || \
<> 144:ef7eb2e8f9f7 92 ((__VALUE__) == LL_DMA_REQUEST_4) || \
<> 144:ef7eb2e8f9f7 93 ((__VALUE__) == LL_DMA_REQUEST_5) || \
<> 144:ef7eb2e8f9f7 94 ((__VALUE__) == LL_DMA_REQUEST_6) || \
<> 144:ef7eb2e8f9f7 95 ((__VALUE__) == LL_DMA_REQUEST_7))
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
<> 144:ef7eb2e8f9f7 98 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
<> 144:ef7eb2e8f9f7 99 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
<> 144:ef7eb2e8f9f7 100 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 #if defined (DMA2)
<> 144:ef7eb2e8f9f7 103 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<> 144:ef7eb2e8f9f7 104 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
<> 144:ef7eb2e8f9f7 105 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 106 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 107 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 108 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 109 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 110 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 111 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
<> 144:ef7eb2e8f9f7 112 (((INSTANCE) == DMA2) && \
<> 144:ef7eb2e8f9f7 113 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 114 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 115 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 116 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 117 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 118 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 119 ((CHANNEL) == LL_DMA_CHANNEL_7))))
<> 144:ef7eb2e8f9f7 120 #else
<> 144:ef7eb2e8f9f7 121 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
<> 144:ef7eb2e8f9f7 122 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 123 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 124 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 125 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 126 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 127 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 128 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
<> 144:ef7eb2e8f9f7 129 (((INSTANCE) == DMA2) && \
<> 144:ef7eb2e8f9f7 130 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 131 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 132 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 133 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 134 ((CHANNEL) == LL_DMA_CHANNEL_5))))
<> 144:ef7eb2e8f9f7 135 #endif
<> 144:ef7eb2e8f9f7 136 #else
<> 144:ef7eb2e8f9f7 137 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
<> 144:ef7eb2e8f9f7 138 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
<> 144:ef7eb2e8f9f7 139 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 140 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 141 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 142 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 143 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 144 ((CHANNEL) == LL_DMA_CHANNEL_7))))
<> 144:ef7eb2e8f9f7 145 #endif
<> 144:ef7eb2e8f9f7 146 /**
<> 144:ef7eb2e8f9f7 147 * @}
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 153 /** @addtogroup DMA_LL_Exported_Functions
<> 144:ef7eb2e8f9f7 154 * @{
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /** @addtogroup DMA_LL_EF_Init
<> 144:ef7eb2e8f9f7 158 * @{
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @brief De-initialize the DMA registers to their default reset values.
<> 144:ef7eb2e8f9f7 163 * @param DMAx DMAx Instance
<> 144:ef7eb2e8f9f7 164 * @param Channel This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 165 * @arg @ref LL_DMA_CHANNEL_1
<> 144:ef7eb2e8f9f7 166 * @arg @ref LL_DMA_CHANNEL_2
<> 144:ef7eb2e8f9f7 167 * @arg @ref LL_DMA_CHANNEL_3
<> 144:ef7eb2e8f9f7 168 * @arg @ref LL_DMA_CHANNEL_4
<> 144:ef7eb2e8f9f7 169 * @arg @ref LL_DMA_CHANNEL_5
<> 144:ef7eb2e8f9f7 170 * @arg @ref LL_DMA_CHANNEL_6
<> 144:ef7eb2e8f9f7 171 * @arg @ref LL_DMA_CHANNEL_7
<> 144:ef7eb2e8f9f7 172 * @arg @ref LL_DMA_CHANNEL_ALL
<> 144:ef7eb2e8f9f7 173 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 174 * - SUCCESS: DMA registers are de-initialized
<> 144:ef7eb2e8f9f7 175 * - ERROR: DMA registers are not de-initialized
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
<> 144:ef7eb2e8f9f7 178 {
<> 144:ef7eb2e8f9f7 179 DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
<> 144:ef7eb2e8f9f7 180 ErrorStatus status = SUCCESS;
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Check the DMA Instance DMAx and Channel parameters*/
<> 144:ef7eb2e8f9f7 183 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 if (Channel == LL_DMA_CHANNEL_ALL)
<> 144:ef7eb2e8f9f7 186 {
<> 144:ef7eb2e8f9f7 187 if (DMAx == DMA1)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 /* Force reset of DMA clock */
<> 144:ef7eb2e8f9f7 190 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Release reset of DMA clock */
<> 144:ef7eb2e8f9f7 193 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
<> 144:ef7eb2e8f9f7 194 }
<> 144:ef7eb2e8f9f7 195 #if defined(DMA2)
<> 144:ef7eb2e8f9f7 196 else if (DMAx == DMA2)
<> 144:ef7eb2e8f9f7 197 {
<> 144:ef7eb2e8f9f7 198 /* Force reset of DMA clock */
<> 144:ef7eb2e8f9f7 199 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Release reset of DMA clock */
<> 144:ef7eb2e8f9f7 202 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204 #endif
<> 144:ef7eb2e8f9f7 205 else
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 status = ERROR;
<> 144:ef7eb2e8f9f7 208 }
<> 144:ef7eb2e8f9f7 209 }
<> 144:ef7eb2e8f9f7 210 else
<> 144:ef7eb2e8f9f7 211 {
<> 144:ef7eb2e8f9f7 212 tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Disable the selected DMAx_Channely */
<> 144:ef7eb2e8f9f7 215 CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Reset DMAx_Channely control register */
<> 144:ef7eb2e8f9f7 218 LL_DMA_WriteReg(tmp, CCR, 0U);
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* Reset DMAx_Channely remaining bytes register */
<> 144:ef7eb2e8f9f7 221 LL_DMA_WriteReg(tmp, CNDTR, 0U);
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Reset DMAx_Channely peripheral address register */
<> 144:ef7eb2e8f9f7 224 LL_DMA_WriteReg(tmp, CPAR, 0U);
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Reset DMAx_Channely memory address register */
<> 144:ef7eb2e8f9f7 227 LL_DMA_WriteReg(tmp, CMAR, 0U);
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Reset Request register field for DMAx Channel */
<> 144:ef7eb2e8f9f7 230 LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 if (Channel == LL_DMA_CHANNEL_1)
<> 144:ef7eb2e8f9f7 233 {
<> 144:ef7eb2e8f9f7 234 /* Reset interrupt pending bits for DMAx Channel1 */
<> 144:ef7eb2e8f9f7 235 LL_DMA_ClearFlag_GI1(DMAx);
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237 else if (Channel == LL_DMA_CHANNEL_2)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 /* Reset interrupt pending bits for DMAx Channel2 */
<> 144:ef7eb2e8f9f7 240 LL_DMA_ClearFlag_GI2(DMAx);
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242 else if (Channel == LL_DMA_CHANNEL_3)
<> 144:ef7eb2e8f9f7 243 {
<> 144:ef7eb2e8f9f7 244 /* Reset interrupt pending bits for DMAx Channel3 */
<> 144:ef7eb2e8f9f7 245 LL_DMA_ClearFlag_GI3(DMAx);
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247 else if (Channel == LL_DMA_CHANNEL_4)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 /* Reset interrupt pending bits for DMAx Channel4 */
<> 144:ef7eb2e8f9f7 250 LL_DMA_ClearFlag_GI4(DMAx);
<> 144:ef7eb2e8f9f7 251 }
<> 144:ef7eb2e8f9f7 252 else if (Channel == LL_DMA_CHANNEL_5)
<> 144:ef7eb2e8f9f7 253 {
<> 144:ef7eb2e8f9f7 254 /* Reset interrupt pending bits for DMAx Channel5 */
<> 144:ef7eb2e8f9f7 255 LL_DMA_ClearFlag_GI5(DMAx);
<> 144:ef7eb2e8f9f7 256 }
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 else if (Channel == LL_DMA_CHANNEL_6)
<> 144:ef7eb2e8f9f7 259 {
<> 144:ef7eb2e8f9f7 260 /* Reset interrupt pending bits for DMAx Channel6 */
<> 144:ef7eb2e8f9f7 261 LL_DMA_ClearFlag_GI6(DMAx);
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263 else if (Channel == LL_DMA_CHANNEL_7)
<> 144:ef7eb2e8f9f7 264 {
<> 144:ef7eb2e8f9f7 265 /* Reset interrupt pending bits for DMAx Channel7 */
<> 144:ef7eb2e8f9f7 266 LL_DMA_ClearFlag_GI7(DMAx);
<> 144:ef7eb2e8f9f7 267 }
<> 144:ef7eb2e8f9f7 268 else
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 status = ERROR;
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 return status;
<> 144:ef7eb2e8f9f7 275 }
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /**
<> 144:ef7eb2e8f9f7 278 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
<> 144:ef7eb2e8f9f7 279 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
<> 144:ef7eb2e8f9f7 280 * @arg @ref __LL_DMA_GET_INSTANCE
<> 144:ef7eb2e8f9f7 281 * @arg @ref __LL_DMA_GET_CHANNEL
<> 144:ef7eb2e8f9f7 282 * @param DMAx DMAx Instance
<> 144:ef7eb2e8f9f7 283 * @param Channel This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 284 * @arg @ref LL_DMA_CHANNEL_1
<> 144:ef7eb2e8f9f7 285 * @arg @ref LL_DMA_CHANNEL_2
<> 144:ef7eb2e8f9f7 286 * @arg @ref LL_DMA_CHANNEL_3
<> 144:ef7eb2e8f9f7 287 * @arg @ref LL_DMA_CHANNEL_4
<> 144:ef7eb2e8f9f7 288 * @arg @ref LL_DMA_CHANNEL_5
<> 144:ef7eb2e8f9f7 289 * @arg @ref LL_DMA_CHANNEL_6
<> 144:ef7eb2e8f9f7 290 * @arg @ref LL_DMA_CHANNEL_7
<> 144:ef7eb2e8f9f7 291 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 292 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 293 * - SUCCESS: DMA registers are initialized
<> 144:ef7eb2e8f9f7 294 * - ERROR: Not applicable
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 /* Check the DMA Instance DMAx and Channel parameters*/
<> 144:ef7eb2e8f9f7 299 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Check the DMA parameters from DMA_InitStruct */
<> 144:ef7eb2e8f9f7 302 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
<> 144:ef7eb2e8f9f7 303 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
<> 144:ef7eb2e8f9f7 304 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
<> 144:ef7eb2e8f9f7 305 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
<> 144:ef7eb2e8f9f7 306 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
<> 144:ef7eb2e8f9f7 307 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
<> 144:ef7eb2e8f9f7 308 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
<> 144:ef7eb2e8f9f7 309 assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
<> 144:ef7eb2e8f9f7 310 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /*---------------------------- DMAx CCR Configuration ------------------------
<> 144:ef7eb2e8f9f7 313 * Configure DMAx_Channely: data transfer direction, data transfer mode,
<> 144:ef7eb2e8f9f7 314 * peripheral and memory increment mode,
<> 144:ef7eb2e8f9f7 315 * data size alignment and priority level with parameters :
<> 144:ef7eb2e8f9f7 316 * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
<> 144:ef7eb2e8f9f7 317 * - Mode: DMA_CCR_CIRC bit
<> 144:ef7eb2e8f9f7 318 * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
<> 144:ef7eb2e8f9f7 319 * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
<> 144:ef7eb2e8f9f7 320 * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
<> 144:ef7eb2e8f9f7 321 * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
<> 144:ef7eb2e8f9f7 322 * - Priority: DMA_CCR_PL[1:0] bits
<> 144:ef7eb2e8f9f7 323 */
<> 144:ef7eb2e8f9f7 324 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
<> 144:ef7eb2e8f9f7 325 DMA_InitStruct->Mode | \
<> 144:ef7eb2e8f9f7 326 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
<> 144:ef7eb2e8f9f7 327 DMA_InitStruct->MemoryOrM2MDstIncMode | \
<> 144:ef7eb2e8f9f7 328 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
<> 144:ef7eb2e8f9f7 329 DMA_InitStruct->MemoryOrM2MDstDataSize | \
<> 144:ef7eb2e8f9f7 330 DMA_InitStruct->Priority);
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /*-------------------------- DMAx CMAR Configuration -------------------------
<> 144:ef7eb2e8f9f7 333 * Configure the memory or destination base address with parameter :
<> 144:ef7eb2e8f9f7 334 * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /*-------------------------- DMAx CPAR Configuration -------------------------
<> 144:ef7eb2e8f9f7 339 * Configure the peripheral or source base address with parameter :
<> 144:ef7eb2e8f9f7 340 * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
<> 144:ef7eb2e8f9f7 341 */
<> 144:ef7eb2e8f9f7 342 LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /*--------------------------- DMAx CNDTR Configuration -----------------------
<> 144:ef7eb2e8f9f7 345 * Configure the peripheral base address with parameter :
<> 144:ef7eb2e8f9f7 346 * - NbData: DMA_CNDTR_NDT[15:0] bits
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348 LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /*--------------------------- DMAx CSELR Configuration -----------------------
<> 144:ef7eb2e8f9f7 351 * Configure the peripheral base address with parameter :
<> 144:ef7eb2e8f9f7 352 * - PeriphRequest: DMA_CSELR[31:0] bits
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 return SUCCESS;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
<> 144:ef7eb2e8f9f7 361 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 362 * @retval None
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
<> 144:ef7eb2e8f9f7 365 {
<> 144:ef7eb2e8f9f7 366 /* Set DMA_InitStruct fields to default values */
<> 144:ef7eb2e8f9f7 367 DMA_InitStruct->PeriphOrM2MSrcAddress = (uint32_t)0x00000000U;
<> 144:ef7eb2e8f9f7 368 DMA_InitStruct->MemoryOrM2MDstAddress = (uint32_t)0x00000000U;
<> 144:ef7eb2e8f9f7 369 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
<> 144:ef7eb2e8f9f7 370 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
<> 144:ef7eb2e8f9f7 371 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
<> 144:ef7eb2e8f9f7 372 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
<> 144:ef7eb2e8f9f7 373 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
<> 144:ef7eb2e8f9f7 374 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
<> 144:ef7eb2e8f9f7 375 DMA_InitStruct->NbData = (uint32_t)0x00000000U;
<> 144:ef7eb2e8f9f7 376 DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0;
<> 144:ef7eb2e8f9f7 377 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /**
<> 144:ef7eb2e8f9f7 381 * @}
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /**
<> 144:ef7eb2e8f9f7 385 * @}
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @}
<> 144:ef7eb2e8f9f7 390 */
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 #endif /* DMA1 || DMA2 */
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /**
<> 144:ef7eb2e8f9f7 395 * @}
<> 144:ef7eb2e8f9f7 396 */
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 #endif /* USE_FULL_LL_DRIVER */
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/