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mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h@181:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
181:96ed750bd169
Parent:
167:e84263d55307 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_pwr_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of PWR HAL Extended module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L4xx_HAL_PWR_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L4xx_HAL_PWR_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l4xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup PWREx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /**
<> 144:ef7eb2e8f9f7 66 * @brief PWR PVM configuration structure definition
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68 typedef struct
<> 144:ef7eb2e8f9f7 69 {
<> 144:ef7eb2e8f9f7 70 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold.
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref PWREx_PVM_Type.
<> 144:ef7eb2e8f9f7 72 @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
<> 144:ef7eb2e8f9f7 73 @if STM32L486xx
<> 144:ef7eb2e8f9f7 74 @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device).
<> 144:ef7eb2e8f9f7 75 @endif
<> 144:ef7eb2e8f9f7 76 @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
<> 144:ef7eb2e8f9f7 77 @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref PWREx_PVM_Mode. */
<> 144:ef7eb2e8f9f7 81 }PWR_PVMTypeDef;
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /**
<> 144:ef7eb2e8f9f7 84 * @}
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
<> 144:ef7eb2e8f9f7 90 * @{
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
<> 144:ef7eb2e8f9f7 94 * @{
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96 #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */
<> 144:ef7eb2e8f9f7 97 /**
<> 144:ef7eb2e8f9f7 98 * @}
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
<> 144:ef7eb2e8f9f7 106 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
<> 144:ef7eb2e8f9f7 107 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
<> 144:ef7eb2e8f9f7 108 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
<> 144:ef7eb2e8f9f7 109 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
<> 144:ef7eb2e8f9f7 110 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
<> 144:ef7eb2e8f9f7 111 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
<> 144:ef7eb2e8f9f7 112 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
<> 144:ef7eb2e8f9f7 113 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
<> 144:ef7eb2e8f9f7 114 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
<> 144:ef7eb2e8f9f7 115 #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
<> 144:ef7eb2e8f9f7 116 #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
<> 144:ef7eb2e8f9f7 117 #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
<> 144:ef7eb2e8f9f7 118 #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
<> 144:ef7eb2e8f9f7 119 #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
<> 144:ef7eb2e8f9f7 120 /**
<> 144:ef7eb2e8f9f7 121 * @}
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
<> 144:ef7eb2e8f9f7 125 * @{
<> 144:ef7eb2e8f9f7 126 */
AnnaBridge 167:e84263d55307 127 #if defined(PWR_CR2_PVME1)
<> 144:ef7eb2e8f9f7 128 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
AnnaBridge 167:e84263d55307 129 #endif /* PWR_CR2_PVME1 */
AnnaBridge 167:e84263d55307 130 #if defined(PWR_CR2_PVME2)
<> 144:ef7eb2e8f9f7 131 #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
AnnaBridge 167:e84263d55307 132 #endif /* PWR_CR2_PVME2 */
<> 144:ef7eb2e8f9f7 133 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
<> 144:ef7eb2e8f9f7 134 #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */
<> 144:ef7eb2e8f9f7 135 /**
<> 144:ef7eb2e8f9f7 136 * @}
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142 #define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
<> 144:ef7eb2e8f9f7 143 #define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
<> 144:ef7eb2e8f9f7 144 #define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 145 #define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 146 #define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
<> 144:ef7eb2e8f9f7 147 #define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 148 #define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 149 /**
<> 144:ef7eb2e8f9f7 150 * @}
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
<> 144:ef7eb2e8f9f7 156 * @{
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 */
<> 144:ef7eb2e8f9f7 159 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */
<> 144:ef7eb2e8f9f7 160 /**
<> 144:ef7eb2e8f9f7 161 * @}
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
<> 144:ef7eb2e8f9f7 166 * @{
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168 #define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */
<> 144:ef7eb2e8f9f7 169 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @}
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
<> 144:ef7eb2e8f9f7 175 * @{
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177 #define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 178 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @}
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
<> 144:ef7eb2e8f9f7 184 * @{
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186 #define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */
<> 144:ef7eb2e8f9f7 187 #define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */
<> 144:ef7eb2e8f9f7 188 #define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */
<> 144:ef7eb2e8f9f7 189 #define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */
<> 144:ef7eb2e8f9f7 190 #define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */
<> 144:ef7eb2e8f9f7 191 #define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */
<> 144:ef7eb2e8f9f7 192 #define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */
<> 144:ef7eb2e8f9f7 193 #define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */
<> 144:ef7eb2e8f9f7 194 #define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */
<> 144:ef7eb2e8f9f7 195 #define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */
<> 144:ef7eb2e8f9f7 196 #define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */
<> 144:ef7eb2e8f9f7 197 #define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */
<> 144:ef7eb2e8f9f7 198 #define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */
<> 144:ef7eb2e8f9f7 199 #define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */
<> 144:ef7eb2e8f9f7 200 #define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */
<> 144:ef7eb2e8f9f7 201 #define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */
<> 144:ef7eb2e8f9f7 202 /**
<> 144:ef7eb2e8f9f7 203 * @}
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /** @defgroup PWREx_GPIO GPIO port
<> 144:ef7eb2e8f9f7 207 * @{
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209 #define PWR_GPIO_A 0x00000000 /*!< GPIO port A */
<> 144:ef7eb2e8f9f7 210 #define PWR_GPIO_B 0x00000001 /*!< GPIO port B */
<> 144:ef7eb2e8f9f7 211 #define PWR_GPIO_C 0x00000002 /*!< GPIO port C */
AnnaBridge 167:e84263d55307 212 #if defined(GPIOD_BASE)
<> 144:ef7eb2e8f9f7 213 #define PWR_GPIO_D 0x00000003 /*!< GPIO port D */
AnnaBridge 167:e84263d55307 214 #endif
AnnaBridge 167:e84263d55307 215 #if defined(GPIOE_BASE)
<> 144:ef7eb2e8f9f7 216 #define PWR_GPIO_E 0x00000004 /*!< GPIO port E */
<> 144:ef7eb2e8f9f7 217 #endif
AnnaBridge 167:e84263d55307 218 #if defined(GPIOF_BASE)
<> 144:ef7eb2e8f9f7 219 #define PWR_GPIO_F 0x00000005 /*!< GPIO port F */
AnnaBridge 167:e84263d55307 220 #endif
AnnaBridge 167:e84263d55307 221 #if defined(GPIOG_BASE)
<> 144:ef7eb2e8f9f7 222 #define PWR_GPIO_G 0x00000006 /*!< GPIO port G */
<> 144:ef7eb2e8f9f7 223 #endif
<> 144:ef7eb2e8f9f7 224 #define PWR_GPIO_H 0x00000007 /*!< GPIO port H */
AnnaBridge 167:e84263d55307 225 #if defined(GPIOI_BASE)
AnnaBridge 167:e84263d55307 226 #define PWR_GPIO_I 0x00000008 /*!< GPIO port I */
AnnaBridge 167:e84263d55307 227 #endif
<> 144:ef7eb2e8f9f7 228 /**
<> 144:ef7eb2e8f9f7 229 * @}
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
<> 144:ef7eb2e8f9f7 233 * @{
<> 144:ef7eb2e8f9f7 234 */
AnnaBridge 167:e84263d55307 235 #if defined(PWR_CR2_PVME1)
<> 144:ef7eb2e8f9f7 236 #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */
AnnaBridge 167:e84263d55307 237 #endif /* PWR_CR2_PVME1 */
AnnaBridge 167:e84263d55307 238 #if defined(PWR_CR2_PVME2)
<> 144:ef7eb2e8f9f7 239 #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */
AnnaBridge 167:e84263d55307 240 #endif /* PWR_CR2_PVME2 */
<> 144:ef7eb2e8f9f7 241 #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */
<> 144:ef7eb2e8f9f7 242 #define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @}
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
<> 144:ef7eb2e8f9f7 248 * @{
<> 144:ef7eb2e8f9f7 249 */
AnnaBridge 167:e84263d55307 250 #if defined(PWR_CR2_PVME1)
<> 144:ef7eb2e8f9f7 251 #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */
AnnaBridge 167:e84263d55307 252 #endif /* PWR_CR2_PVME1 */
AnnaBridge 167:e84263d55307 253 #if defined(PWR_CR2_PVME2)
<> 144:ef7eb2e8f9f7 254 #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */
AnnaBridge 167:e84263d55307 255 #endif /* PWR_CR2_PVME2 */
<> 144:ef7eb2e8f9f7 256 #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */
<> 144:ef7eb2e8f9f7 257 #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */
<> 144:ef7eb2e8f9f7 258 /**
<> 144:ef7eb2e8f9f7 259 * @}
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /** @defgroup PWREx_Flag PWR Status Flags
<> 144:ef7eb2e8f9f7 263 * Elements values convention: 0000 0000 0XXY YYYYb
<> 144:ef7eb2e8f9f7 264 * - Y YYYY : Flag position in the XX register (5 bits)
<> 144:ef7eb2e8f9f7 265 * - XX : Status register (2 bits)
<> 144:ef7eb2e8f9f7 266 * - 01: SR1 register
<> 144:ef7eb2e8f9f7 267 * - 10: SR2 register
<> 144:ef7eb2e8f9f7 268 * The only exception is PWR_FLAG_WU, encompassing all
<> 144:ef7eb2e8f9f7 269 * wake-up flags and set to PWR_SR1_WUF.
<> 144:ef7eb2e8f9f7 270 * @{
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272 #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */
<> 144:ef7eb2e8f9f7 273 #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */
<> 144:ef7eb2e8f9f7 274 #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */
<> 144:ef7eb2e8f9f7 275 #define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */
<> 144:ef7eb2e8f9f7 276 #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */
<> 144:ef7eb2e8f9f7 277 #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */
<> 144:ef7eb2e8f9f7 278 #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */
<> 144:ef7eb2e8f9f7 279 #define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */
<> 144:ef7eb2e8f9f7 282 #define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */
<> 144:ef7eb2e8f9f7 283 #define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */
<> 144:ef7eb2e8f9f7 284 #define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */
AnnaBridge 167:e84263d55307 285 #if defined(PWR_CR2_PVME1)
<> 144:ef7eb2e8f9f7 286 #define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */
AnnaBridge 167:e84263d55307 287 #endif /* PWR_CR2_PVME1 */
AnnaBridge 167:e84263d55307 288 #if defined(PWR_CR2_PVME2)
<> 144:ef7eb2e8f9f7 289 #define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */
AnnaBridge 167:e84263d55307 290 #endif /* PWR_CR2_PVME2 */
<> 144:ef7eb2e8f9f7 291 #define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */
<> 144:ef7eb2e8f9f7 292 #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @}
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /**
<> 144:ef7eb2e8f9f7 298 * @}
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 302 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
<> 144:ef7eb2e8f9f7 303 * @{
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305
AnnaBridge 167:e84263d55307 306 #if defined(PWR_CR2_PVME1)
<> 144:ef7eb2e8f9f7 307 /**
<> 144:ef7eb2e8f9f7 308 * @brief Enable the PVM1 Extended Interrupt Line.
<> 144:ef7eb2e8f9f7 309 * @retval None
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @brief Disable the PVM1 Extended Interrupt Line.
<> 144:ef7eb2e8f9f7 315 * @retval None
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /**
<> 144:ef7eb2e8f9f7 320 * @brief Enable the PVM1 Event Line.
<> 144:ef7eb2e8f9f7 321 * @retval None
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @brief Disable the PVM1 Event Line.
<> 144:ef7eb2e8f9f7 327 * @retval None
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /**
<> 144:ef7eb2e8f9f7 332 * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 333 * @retval None
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 339 * @retval None
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /**
<> 144:ef7eb2e8f9f7 344 * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 345 * @retval None
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 352 * @retval None
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /**
<> 144:ef7eb2e8f9f7 358 * @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
<> 144:ef7eb2e8f9f7 359 * @retval None
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 362 do { \
<> 144:ef7eb2e8f9f7 363 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
<> 144:ef7eb2e8f9f7 364 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
<> 144:ef7eb2e8f9f7 365 } while(0)
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /**
<> 144:ef7eb2e8f9f7 368 * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 369 * @retval None
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 372 do { \
<> 144:ef7eb2e8f9f7 373 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
<> 144:ef7eb2e8f9f7 374 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
<> 144:ef7eb2e8f9f7 375 } while(0)
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /**
<> 144:ef7eb2e8f9f7 378 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 379 * @retval None
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /**
<> 144:ef7eb2e8f9f7 384 * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
<> 144:ef7eb2e8f9f7 385 * @retval EXTI PVM1 Line Status.
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 #define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @brief Clear the PVM1 EXTI flag.
<> 144:ef7eb2e8f9f7 391 * @retval None
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
<> 144:ef7eb2e8f9f7 394
AnnaBridge 167:e84263d55307 395 #endif /* PWR_CR2_PVME1 */
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397
AnnaBridge 167:e84263d55307 398 #if defined(PWR_CR2_PVME2)
<> 144:ef7eb2e8f9f7 399 /**
<> 144:ef7eb2e8f9f7 400 * @brief Enable the PVM2 Extended Interrupt Line.
<> 144:ef7eb2e8f9f7 401 * @retval None
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /**
<> 144:ef7eb2e8f9f7 406 * @brief Disable the PVM2 Extended Interrupt Line.
<> 144:ef7eb2e8f9f7 407 * @retval None
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /**
<> 144:ef7eb2e8f9f7 412 * @brief Enable the PVM2 Event Line.
<> 144:ef7eb2e8f9f7 413 * @retval None
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /**
<> 144:ef7eb2e8f9f7 418 * @brief Disable the PVM2 Event Line.
<> 144:ef7eb2e8f9f7 419 * @retval None
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /**
<> 144:ef7eb2e8f9f7 424 * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 425 * @retval None
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 431 * @retval None
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /**
<> 144:ef7eb2e8f9f7 436 * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 437 * @retval None
<> 144:ef7eb2e8f9f7 438 */
<> 144:ef7eb2e8f9f7 439 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /**
<> 144:ef7eb2e8f9f7 443 * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 444 * @retval None
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /**
<> 144:ef7eb2e8f9f7 450 * @brief PVM2 EXTI line configuration: set rising & falling edge trigger.
<> 144:ef7eb2e8f9f7 451 * @retval None
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 454 do { \
<> 144:ef7eb2e8f9f7 455 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \
<> 144:ef7eb2e8f9f7 456 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \
<> 144:ef7eb2e8f9f7 457 } while(0)
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /**
<> 144:ef7eb2e8f9f7 460 * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 461 * @retval None
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 464 do { \
<> 144:ef7eb2e8f9f7 465 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \
<> 144:ef7eb2e8f9f7 466 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \
<> 144:ef7eb2e8f9f7 467 } while(0)
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /**
<> 144:ef7eb2e8f9f7 470 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 471 * @retval None
<> 144:ef7eb2e8f9f7 472 */
<> 144:ef7eb2e8f9f7 473 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /**
<> 144:ef7eb2e8f9f7 476 * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
<> 144:ef7eb2e8f9f7 477 * @retval EXTI PVM2 Line Status.
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479 #define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /**
<> 144:ef7eb2e8f9f7 482 * @brief Clear the PVM2 EXTI flag.
<> 144:ef7eb2e8f9f7 483 * @retval None
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
<> 144:ef7eb2e8f9f7 486
AnnaBridge 167:e84263d55307 487 #endif /* PWR_CR2_PVME2 */
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /**
<> 144:ef7eb2e8f9f7 491 * @brief Enable the PVM3 Extended Interrupt Line.
<> 144:ef7eb2e8f9f7 492 * @retval None
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /**
<> 144:ef7eb2e8f9f7 497 * @brief Disable the PVM3 Extended Interrupt Line.
<> 144:ef7eb2e8f9f7 498 * @retval None
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /**
<> 144:ef7eb2e8f9f7 503 * @brief Enable the PVM3 Event Line.
<> 144:ef7eb2e8f9f7 504 * @retval None
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @brief Disable the PVM3 Event Line.
<> 144:ef7eb2e8f9f7 510 * @retval None
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /**
<> 144:ef7eb2e8f9f7 515 * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 516 * @retval None
<> 144:ef7eb2e8f9f7 517 */
<> 144:ef7eb2e8f9f7 518 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /**
<> 144:ef7eb2e8f9f7 521 * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 522 * @retval None
<> 144:ef7eb2e8f9f7 523 */
<> 144:ef7eb2e8f9f7 524 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /**
<> 144:ef7eb2e8f9f7 527 * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 528 * @retval None
<> 144:ef7eb2e8f9f7 529 */
<> 144:ef7eb2e8f9f7 530 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /**
<> 144:ef7eb2e8f9f7 534 * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 535 * @retval None
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /**
<> 144:ef7eb2e8f9f7 541 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
<> 144:ef7eb2e8f9f7 542 * @retval None
<> 144:ef7eb2e8f9f7 543 */
<> 144:ef7eb2e8f9f7 544 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 545 do { \
<> 144:ef7eb2e8f9f7 546 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
<> 144:ef7eb2e8f9f7 547 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
<> 144:ef7eb2e8f9f7 548 } while(0)
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /**
<> 144:ef7eb2e8f9f7 551 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 552 * @retval None
<> 144:ef7eb2e8f9f7 553 */
<> 144:ef7eb2e8f9f7 554 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 555 do { \
<> 144:ef7eb2e8f9f7 556 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
<> 144:ef7eb2e8f9f7 557 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
<> 144:ef7eb2e8f9f7 558 } while(0)
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /**
<> 144:ef7eb2e8f9f7 561 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 562 * @retval None
<> 144:ef7eb2e8f9f7 563 */
<> 144:ef7eb2e8f9f7 564 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /**
<> 144:ef7eb2e8f9f7 567 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
<> 144:ef7eb2e8f9f7 568 * @retval EXTI PVM3 Line Status.
<> 144:ef7eb2e8f9f7 569 */
<> 144:ef7eb2e8f9f7 570 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /**
<> 144:ef7eb2e8f9f7 573 * @brief Clear the PVM3 EXTI flag.
<> 144:ef7eb2e8f9f7 574 * @retval None
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /**
<> 144:ef7eb2e8f9f7 582 * @brief Enable the PVM4 Extended Interrupt Line.
<> 144:ef7eb2e8f9f7 583 * @retval None
<> 144:ef7eb2e8f9f7 584 */
<> 144:ef7eb2e8f9f7 585 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /**
<> 144:ef7eb2e8f9f7 588 * @brief Disable the PVM4 Extended Interrupt Line.
<> 144:ef7eb2e8f9f7 589 * @retval None
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /**
<> 144:ef7eb2e8f9f7 594 * @brief Enable the PVM4 Event Line.
<> 144:ef7eb2e8f9f7 595 * @retval None
<> 144:ef7eb2e8f9f7 596 */
<> 144:ef7eb2e8f9f7 597 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /**
<> 144:ef7eb2e8f9f7 600 * @brief Disable the PVM4 Event Line.
<> 144:ef7eb2e8f9f7 601 * @retval None
<> 144:ef7eb2e8f9f7 602 */
<> 144:ef7eb2e8f9f7 603 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /**
<> 144:ef7eb2e8f9f7 606 * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 607 * @retval None
<> 144:ef7eb2e8f9f7 608 */
<> 144:ef7eb2e8f9f7 609 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /**
<> 144:ef7eb2e8f9f7 612 * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 613 * @retval None
<> 144:ef7eb2e8f9f7 614 */
<> 144:ef7eb2e8f9f7 615 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /**
<> 144:ef7eb2e8f9f7 618 * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 619 * @retval None
<> 144:ef7eb2e8f9f7 620 */
<> 144:ef7eb2e8f9f7 621 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /**
<> 144:ef7eb2e8f9f7 625 * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 626 * @retval None
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /**
<> 144:ef7eb2e8f9f7 632 * @brief PVM4 EXTI line configuration: set rising & falling edge trigger.
<> 144:ef7eb2e8f9f7 633 * @retval None
<> 144:ef7eb2e8f9f7 634 */
<> 144:ef7eb2e8f9f7 635 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 636 do { \
<> 144:ef7eb2e8f9f7 637 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \
<> 144:ef7eb2e8f9f7 638 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \
<> 144:ef7eb2e8f9f7 639 } while(0)
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /**
<> 144:ef7eb2e8f9f7 642 * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 643 * @retval None
<> 144:ef7eb2e8f9f7 644 */
<> 144:ef7eb2e8f9f7 645 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 646 do { \
<> 144:ef7eb2e8f9f7 647 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \
<> 144:ef7eb2e8f9f7 648 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \
<> 144:ef7eb2e8f9f7 649 } while(0)
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /**
<> 144:ef7eb2e8f9f7 652 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 653 * @retval None
<> 144:ef7eb2e8f9f7 654 */
<> 144:ef7eb2e8f9f7 655 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /**
<> 144:ef7eb2e8f9f7 658 * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
<> 144:ef7eb2e8f9f7 659 * @retval EXTI PVM4 Line Status.
<> 144:ef7eb2e8f9f7 660 */
<> 144:ef7eb2e8f9f7 661 #define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /**
<> 144:ef7eb2e8f9f7 664 * @brief Clear the PVM4 EXTI flag.
<> 144:ef7eb2e8f9f7 665 * @retval None
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /**
<> 144:ef7eb2e8f9f7 671 * @brief Configure the main internal regulator output voltage.
<> 144:ef7eb2e8f9f7 672 * @param __REGULATOR__: specifies the regulator output voltage to achieve
<> 144:ef7eb2e8f9f7 673 * a tradeoff between performance and power consumption.
<> 144:ef7eb2e8f9f7 674 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 675 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
<> 144:ef7eb2e8f9f7 676 * typical output voltage at 1.2 V,
<> 144:ef7eb2e8f9f7 677 * system frequency up to 80 MHz.
<> 144:ef7eb2e8f9f7 678 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
<> 144:ef7eb2e8f9f7 679 * typical output voltage at 1.0 V,
<> 144:ef7eb2e8f9f7 680 * system frequency up to 26 MHz.
<> 144:ef7eb2e8f9f7 681 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
<> 144:ef7eb2e8f9f7 682 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User
<> 144:ef7eb2e8f9f7 683 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
<> 144:ef7eb2e8f9f7 684 * @retval None
<> 144:ef7eb2e8f9f7 685 */
<> 144:ef7eb2e8f9f7 686 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
<> 144:ef7eb2e8f9f7 687 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 688 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
<> 144:ef7eb2e8f9f7 689 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 690 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
<> 144:ef7eb2e8f9f7 691 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 692 } while(0)
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /**
<> 144:ef7eb2e8f9f7 695 * @}
<> 144:ef7eb2e8f9f7 696 */
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* Private macros --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 699 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
<> 144:ef7eb2e8f9f7 700 * @{
<> 144:ef7eb2e8f9f7 701 */
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
<> 144:ef7eb2e8f9f7 704 ((PIN) == PWR_WAKEUP_PIN2) || \
<> 144:ef7eb2e8f9f7 705 ((PIN) == PWR_WAKEUP_PIN3) || \
<> 144:ef7eb2e8f9f7 706 ((PIN) == PWR_WAKEUP_PIN4) || \
<> 144:ef7eb2e8f9f7 707 ((PIN) == PWR_WAKEUP_PIN5) || \
<> 144:ef7eb2e8f9f7 708 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
<> 144:ef7eb2e8f9f7 709 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
<> 144:ef7eb2e8f9f7 710 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
<> 144:ef7eb2e8f9f7 711 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
<> 144:ef7eb2e8f9f7 712 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
<> 144:ef7eb2e8f9f7 713 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
<> 144:ef7eb2e8f9f7 714 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
<> 144:ef7eb2e8f9f7 715 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
<> 144:ef7eb2e8f9f7 716 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
<> 144:ef7eb2e8f9f7 717 ((PIN) == PWR_WAKEUP_PIN5_LOW))
<> 144:ef7eb2e8f9f7 718
AnnaBridge 167:e84263d55307 719 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
AnnaBridge 167:e84263d55307 720 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 721 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
<> 144:ef7eb2e8f9f7 722 ((TYPE) == PWR_PVM_2) ||\
<> 144:ef7eb2e8f9f7 723 ((TYPE) == PWR_PVM_3) ||\
<> 144:ef7eb2e8f9f7 724 ((TYPE) == PWR_PVM_4))
<> 144:ef7eb2e8f9f7 725 #elif defined (STM32L471xx)
<> 144:ef7eb2e8f9f7 726 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\
<> 144:ef7eb2e8f9f7 727 ((TYPE) == PWR_PVM_3) ||\
<> 144:ef7eb2e8f9f7 728 ((TYPE) == PWR_PVM_4))
<> 144:ef7eb2e8f9f7 729 #endif
<> 144:ef7eb2e8f9f7 730
AnnaBridge 167:e84263d55307 731 #if defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 732 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
<> 144:ef7eb2e8f9f7 733 ((TYPE) == PWR_PVM_3) ||\
<> 144:ef7eb2e8f9f7 734 ((TYPE) == PWR_PVM_4))
AnnaBridge 167:e84263d55307 735 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx)
<> 144:ef7eb2e8f9f7 736 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\
<> 144:ef7eb2e8f9f7 737 ((TYPE) == PWR_PVM_4))
<> 144:ef7eb2e8f9f7 738 #endif
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\
<> 144:ef7eb2e8f9f7 741 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\
<> 144:ef7eb2e8f9f7 742 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\
<> 144:ef7eb2e8f9f7 743 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\
<> 144:ef7eb2e8f9f7 744 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\
<> 144:ef7eb2e8f9f7 745 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\
<> 144:ef7eb2e8f9f7 746 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
<> 144:ef7eb2e8f9f7 749 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
<> 144:ef7eb2e8f9f7 752 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
<> 144:ef7eb2e8f9f7 755 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759
AnnaBridge 167:e84263d55307 760 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \
AnnaBridge 167:e84263d55307 761 defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 762 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
<> 144:ef7eb2e8f9f7 763 ((GPIO) == PWR_GPIO_B) ||\
<> 144:ef7eb2e8f9f7 764 ((GPIO) == PWR_GPIO_C) ||\
<> 144:ef7eb2e8f9f7 765 ((GPIO) == PWR_GPIO_D) ||\
<> 144:ef7eb2e8f9f7 766 ((GPIO) == PWR_GPIO_E) ||\
<> 144:ef7eb2e8f9f7 767 ((GPIO) == PWR_GPIO_H))
<> 144:ef7eb2e8f9f7 768 #elif defined (STM32L432xx) || defined (STM32L442xx)
<> 144:ef7eb2e8f9f7 769 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
<> 144:ef7eb2e8f9f7 770 ((GPIO) == PWR_GPIO_B) ||\
<> 144:ef7eb2e8f9f7 771 ((GPIO) == PWR_GPIO_C) ||\
<> 144:ef7eb2e8f9f7 772 ((GPIO) == PWR_GPIO_H))
AnnaBridge 167:e84263d55307 773 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
AnnaBridge 167:e84263d55307 774 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
AnnaBridge 167:e84263d55307 775 ((GPIO) == PWR_GPIO_B) ||\
AnnaBridge 167:e84263d55307 776 ((GPIO) == PWR_GPIO_C) ||\
AnnaBridge 167:e84263d55307 777 ((GPIO) == PWR_GPIO_D) ||\
AnnaBridge 167:e84263d55307 778 ((GPIO) == PWR_GPIO_E) ||\
AnnaBridge 167:e84263d55307 779 ((GPIO) == PWR_GPIO_F) ||\
AnnaBridge 167:e84263d55307 780 ((GPIO) == PWR_GPIO_G) ||\
AnnaBridge 167:e84263d55307 781 ((GPIO) == PWR_GPIO_H))
AnnaBridge 167:e84263d55307 782 #elif defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 783 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
AnnaBridge 167:e84263d55307 784 ((GPIO) == PWR_GPIO_B) ||\
AnnaBridge 167:e84263d55307 785 ((GPIO) == PWR_GPIO_C) ||\
AnnaBridge 167:e84263d55307 786 ((GPIO) == PWR_GPIO_D) ||\
AnnaBridge 167:e84263d55307 787 ((GPIO) == PWR_GPIO_E) ||\
AnnaBridge 167:e84263d55307 788 ((GPIO) == PWR_GPIO_F) ||\
AnnaBridge 167:e84263d55307 789 ((GPIO) == PWR_GPIO_G) ||\
AnnaBridge 167:e84263d55307 790 ((GPIO) == PWR_GPIO_H) ||\
AnnaBridge 167:e84263d55307 791 ((GPIO) == PWR_GPIO_I))
<> 144:ef7eb2e8f9f7 792 #endif
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /**
<> 144:ef7eb2e8f9f7 796 * @}
<> 144:ef7eb2e8f9f7 797 */
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
<> 144:ef7eb2e8f9f7 801 * @{
<> 144:ef7eb2e8f9f7 802 */
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 805 * @{
<> 144:ef7eb2e8f9f7 806 */
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /* Peripheral Control functions **********************************************/
<> 144:ef7eb2e8f9f7 810 uint32_t HAL_PWREx_GetVoltageRange(void);
<> 144:ef7eb2e8f9f7 811 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
<> 144:ef7eb2e8f9f7 812 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
AnnaBridge 167:e84263d55307 813 void HAL_PWREx_DisableBatteryCharging(void);
AnnaBridge 167:e84263d55307 814 #if defined(PWR_CR2_USV)
<> 144:ef7eb2e8f9f7 815 void HAL_PWREx_EnableVddUSB(void);
<> 144:ef7eb2e8f9f7 816 void HAL_PWREx_DisableVddUSB(void);
AnnaBridge 167:e84263d55307 817 #endif /* PWR_CR2_USV */
AnnaBridge 167:e84263d55307 818 #if defined(PWR_CR2_IOSV)
<> 144:ef7eb2e8f9f7 819 void HAL_PWREx_EnableVddIO2(void);
<> 144:ef7eb2e8f9f7 820 void HAL_PWREx_DisableVddIO2(void);
AnnaBridge 167:e84263d55307 821 #endif /* PWR_CR2_IOSV */
<> 144:ef7eb2e8f9f7 822 void HAL_PWREx_EnableInternalWakeUpLine(void);
<> 144:ef7eb2e8f9f7 823 void HAL_PWREx_DisableInternalWakeUpLine(void);
<> 144:ef7eb2e8f9f7 824 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
<> 144:ef7eb2e8f9f7 825 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
<> 144:ef7eb2e8f9f7 826 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
<> 144:ef7eb2e8f9f7 827 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
<> 144:ef7eb2e8f9f7 828 void HAL_PWREx_EnablePullUpPullDownConfig(void);
<> 144:ef7eb2e8f9f7 829 void HAL_PWREx_DisablePullUpPullDownConfig(void);
<> 144:ef7eb2e8f9f7 830 void HAL_PWREx_EnableSRAM2ContentRetention(void);
<> 144:ef7eb2e8f9f7 831 void HAL_PWREx_DisableSRAM2ContentRetention(void);
AnnaBridge 167:e84263d55307 832 #if defined(PWR_CR2_PVME1)
<> 144:ef7eb2e8f9f7 833 void HAL_PWREx_EnablePVM1(void);
<> 144:ef7eb2e8f9f7 834 void HAL_PWREx_DisablePVM1(void);
AnnaBridge 167:e84263d55307 835 #endif /* PWR_CR2_PVME1 */
AnnaBridge 167:e84263d55307 836 #if defined(PWR_CR2_PVME2)
<> 144:ef7eb2e8f9f7 837 void HAL_PWREx_EnablePVM2(void);
<> 144:ef7eb2e8f9f7 838 void HAL_PWREx_DisablePVM2(void);
AnnaBridge 167:e84263d55307 839 #endif /* PWR_CR2_PVME2 */
<> 144:ef7eb2e8f9f7 840 void HAL_PWREx_EnablePVM3(void);
<> 144:ef7eb2e8f9f7 841 void HAL_PWREx_DisablePVM3(void);
<> 144:ef7eb2e8f9f7 842 void HAL_PWREx_EnablePVM4(void);
<> 144:ef7eb2e8f9f7 843 void HAL_PWREx_DisablePVM4(void);
<> 144:ef7eb2e8f9f7 844 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* Low Power modes configuration functions ************************************/
<> 144:ef7eb2e8f9f7 848 void HAL_PWREx_EnableLowPowerRunMode(void);
<> 144:ef7eb2e8f9f7 849 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
<> 144:ef7eb2e8f9f7 850 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
<> 144:ef7eb2e8f9f7 851 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
<> 144:ef7eb2e8f9f7 852 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
<> 144:ef7eb2e8f9f7 853 void HAL_PWREx_EnterSHUTDOWNMode(void);
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 void HAL_PWREx_PVD_PVM_IRQHandler(void);
AnnaBridge 167:e84263d55307 856 #if defined(PWR_CR2_PVME1)
<> 144:ef7eb2e8f9f7 857 void HAL_PWREx_PVM1Callback(void);
AnnaBridge 167:e84263d55307 858 #endif /* PWR_CR2_PVME1 */
AnnaBridge 167:e84263d55307 859 #if defined(PWR_CR2_PVME2)
<> 144:ef7eb2e8f9f7 860 void HAL_PWREx_PVM2Callback(void);
AnnaBridge 167:e84263d55307 861 #endif /* PWR_CR2_PVME2 */
<> 144:ef7eb2e8f9f7 862 void HAL_PWREx_PVM3Callback(void);
<> 144:ef7eb2e8f9f7 863 void HAL_PWREx_PVM4Callback(void);
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /**
<> 144:ef7eb2e8f9f7 866 * @}
<> 144:ef7eb2e8f9f7 867 */
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /**
<> 144:ef7eb2e8f9f7 870 * @}
<> 144:ef7eb2e8f9f7 871 */
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /**
<> 144:ef7eb2e8f9f7 874 * @}
<> 144:ef7eb2e8f9f7 875 */
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /**
<> 144:ef7eb2e8f9f7 878 * @}
<> 144:ef7eb2e8f9f7 879 */
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883 #endif
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 #endif /* __STM32L4xx_HAL_PWR_EX_H */
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/