Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c@181:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
181:96ed750bd169
Parent:
167:e84263d55307 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_pwr_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Extended PWR HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Power Controller (PWR) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Extended Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 ******************************************************************************
<> 144:ef7eb2e8f9f7 14 * @attention
<> 144:ef7eb2e8f9f7 15 *
AnnaBridge 167:e84263d55307 16 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 17 *
<> 144:ef7eb2e8f9f7 18 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 19 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 20 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 21 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 23 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 24 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 26 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 27 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 39 *
<> 144:ef7eb2e8f9f7 40 ******************************************************************************
<> 144:ef7eb2e8f9f7 41 */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 44 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @defgroup PWREx PWREx
<> 144:ef7eb2e8f9f7 51 * @brief PWR Extended HAL module driver
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 #ifdef HAL_PWR_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59
AnnaBridge 167:e84263d55307 60 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
AnnaBridge 167:e84263d55307 61 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
AnnaBridge 167:e84263d55307 62 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
AnnaBridge 167:e84263d55307 63 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
AnnaBridge 167:e84263d55307 64 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
AnnaBridge 167:e84263d55307 65 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x00000003) /* PH0/PH1 */
AnnaBridge 167:e84263d55307 66 #elif defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 67 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000FFFF) /* PH0..PH15 */
AnnaBridge 167:e84263d55307 68 #endif
AnnaBridge 167:e84263d55307 69
AnnaBridge 167:e84263d55307 70 #if defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 71 #define PWR_PORTI_AVAILABLE_PINS ((uint32_t)0x00000FFF) /* PI0..PI11 */
AnnaBridge 167:e84263d55307 72 #endif
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
<> 144:ef7eb2e8f9f7 75 * @{
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
<> 144:ef7eb2e8f9f7 79 * @{
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81 #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */
<> 144:ef7eb2e8f9f7 82 #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */
<> 144:ef7eb2e8f9f7 83 #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */
<> 144:ef7eb2e8f9f7 84 #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */
<> 144:ef7eb2e8f9f7 85 /**
<> 144:ef7eb2e8f9f7 86 * @}
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
<> 144:ef7eb2e8f9f7 90 * @{
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92 #define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @}
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /**
<> 144:ef7eb2e8f9f7 100 * @}
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 106 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 107 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 108 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 115 * @brief Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 116 *
<> 144:ef7eb2e8f9f7 117 @verbatim
<> 144:ef7eb2e8f9f7 118 ===============================================================================
<> 144:ef7eb2e8f9f7 119 ##### Extended Peripheral Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 120 ===============================================================================
<> 144:ef7eb2e8f9f7 121 [..]
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 @endverbatim
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /**
<> 144:ef7eb2e8f9f7 129 * @brief Return Voltage Scaling Range.
<> 144:ef7eb2e8f9f7 130 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 uint32_t HAL_PWREx_GetVoltageRange(void)
<> 144:ef7eb2e8f9f7 133 {
<> 144:ef7eb2e8f9f7 134 return (PWR->CR1 & PWR_CR1_VOS);
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /**
<> 144:ef7eb2e8f9f7 140 * @brief Configure the main internal regulator output voltage.
<> 144:ef7eb2e8f9f7 141 * @param VoltageScaling: specifies the regulator output voltage to achieve
<> 144:ef7eb2e8f9f7 142 * a tradeoff between performance and power consumption.
<> 144:ef7eb2e8f9f7 143 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 144 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
<> 144:ef7eb2e8f9f7 145 * typical output voltage at 1.2 V,
<> 144:ef7eb2e8f9f7 146 * system frequency up to 80 MHz.
<> 144:ef7eb2e8f9f7 147 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
<> 144:ef7eb2e8f9f7 148 * typical output voltage at 1.0 V,
<> 144:ef7eb2e8f9f7 149 * system frequency up to 26 MHz.
<> 144:ef7eb2e8f9f7 150 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
<> 144:ef7eb2e8f9f7 151 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
<> 144:ef7eb2e8f9f7 152 * When moving from Range 2 to Range 1, the system frequency can be increased to
<> 144:ef7eb2e8f9f7 153 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
<> 144:ef7eb2e8f9f7 154 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
<> 144:ef7eb2e8f9f7 155 * cleared before returning the status. If the flag is not cleared within
<> 144:ef7eb2e8f9f7 156 * 50 microseconds, HAL_TIMEOUT status is reported.
<> 144:ef7eb2e8f9f7 157 * @retval HAL Status
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* If Set Range 1 */
<> 144:ef7eb2e8f9f7 166 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
<> 144:ef7eb2e8f9f7 169 {
<> 144:ef7eb2e8f9f7 170 /* Set Range 1 */
<> 144:ef7eb2e8f9f7 171 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /* Wait until VOSF is cleared */
<> 144:ef7eb2e8f9f7 174 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 175 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)))
<> 144:ef7eb2e8f9f7 176 {
<> 144:ef7eb2e8f9f7 177 wait_loop_index--;
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
<> 144:ef7eb2e8f9f7 180 {
<> 144:ef7eb2e8f9f7 181 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 182 }
<> 144:ef7eb2e8f9f7 183 }
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185 else
<> 144:ef7eb2e8f9f7 186 {
<> 144:ef7eb2e8f9f7 187 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 /* Set Range 2 */
<> 144:ef7eb2e8f9f7 190 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
<> 144:ef7eb2e8f9f7 191 /* No need to wait for VOSF to be cleared for this transition */
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 return HAL_OK;
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /**
<> 144:ef7eb2e8f9f7 200 * @brief Enable battery charging.
<> 144:ef7eb2e8f9f7 201 * When VDD is present, charge the external battery on VBAT thru an internal resistor.
<> 144:ef7eb2e8f9f7 202 * @param ResistorSelection: specifies the resistor impedance.
<> 144:ef7eb2e8f9f7 203 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 204 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
<> 144:ef7eb2e8f9f7 205 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
<> 144:ef7eb2e8f9f7 206 * @retval None
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* Specify resistor selection */
<> 144:ef7eb2e8f9f7 213 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /* Enable battery charging */
<> 144:ef7eb2e8f9f7 216 SET_BIT(PWR->CR4, PWR_CR4_VBE);
<> 144:ef7eb2e8f9f7 217 }
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /**
<> 144:ef7eb2e8f9f7 221 * @brief Disable battery charging.
<> 144:ef7eb2e8f9f7 222 * @retval None
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 void HAL_PWREx_DisableBatteryCharging(void)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
<> 144:ef7eb2e8f9f7 227 }
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229
AnnaBridge 167:e84263d55307 230 #if defined(PWR_CR2_USV)
<> 144:ef7eb2e8f9f7 231 /**
<> 144:ef7eb2e8f9f7 232 * @brief Enable VDDUSB supply.
<> 144:ef7eb2e8f9f7 233 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
<> 144:ef7eb2e8f9f7 234 * @retval None
<> 144:ef7eb2e8f9f7 235 */
<> 144:ef7eb2e8f9f7 236 void HAL_PWREx_EnableVddUSB(void)
<> 144:ef7eb2e8f9f7 237 {
<> 144:ef7eb2e8f9f7 238 SET_BIT(PWR->CR2, PWR_CR2_USV);
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /**
<> 144:ef7eb2e8f9f7 243 * @brief Disable VDDUSB supply.
<> 144:ef7eb2e8f9f7 244 * @retval None
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246 void HAL_PWREx_DisableVddUSB(void)
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
<> 144:ef7eb2e8f9f7 249 }
AnnaBridge 167:e84263d55307 250 #endif /* PWR_CR2_USV */
<> 144:ef7eb2e8f9f7 251
AnnaBridge 167:e84263d55307 252 #if defined(PWR_CR2_IOSV)
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @brief Enable VDDIO2 supply.
<> 144:ef7eb2e8f9f7 255 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
<> 144:ef7eb2e8f9f7 256 * @retval None
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258 void HAL_PWREx_EnableVddIO2(void)
<> 144:ef7eb2e8f9f7 259 {
<> 144:ef7eb2e8f9f7 260 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @brief Disable VDDIO2 supply.
<> 144:ef7eb2e8f9f7 266 * @retval None
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 void HAL_PWREx_DisableVddIO2(void)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
<> 144:ef7eb2e8f9f7 271 }
AnnaBridge 167:e84263d55307 272 #endif /* PWR_CR2_IOSV */
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /**
<> 144:ef7eb2e8f9f7 276 * @brief Enable Internal Wake-up Line.
<> 144:ef7eb2e8f9f7 277 * @retval None
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 void HAL_PWREx_EnableInternalWakeUpLine(void)
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @brief Disable Internal Wake-up Line.
<> 144:ef7eb2e8f9f7 287 * @retval None
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289 void HAL_PWREx_DisableInternalWakeUpLine(void)
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 298 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
<> 144:ef7eb2e8f9f7 299 * pull-up state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 300 * @note This state is effective in Standby and Shutdown modes only if APC bit
<> 144:ef7eb2e8f9f7 301 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
<> 144:ef7eb2e8f9f7 302 * @note The configuration is lost when exiting the Shutdown mode due to the
<> 144:ef7eb2e8f9f7 303 * power-on reset, maintained when exiting the Standby mode.
<> 144:ef7eb2e8f9f7 304 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
<> 144:ef7eb2e8f9f7 305 * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
<> 144:ef7eb2e8f9f7 306 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
<> 144:ef7eb2e8f9f7 307 * parameter at the same time are set.
<> 144:ef7eb2e8f9f7 308 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
AnnaBridge 167:e84263d55307 309 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
<> 144:ef7eb2e8f9f7 310 * @param GPIONumber: Specify the I/O pins numbers.
<> 144:ef7eb2e8f9f7 311 * This parameter can be one of the following values:
AnnaBridge 167:e84263d55307 312 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
<> 144:ef7eb2e8f9f7 313 * I/O pins are available) or the logical OR of several of them to set
<> 144:ef7eb2e8f9f7 314 * several bits for a given port in a single API call.
<> 144:ef7eb2e8f9f7 315 * @retval HAL Status
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 assert_param(IS_PWR_GPIO(GPIO));
<> 144:ef7eb2e8f9f7 320 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 switch (GPIO)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 case PWR_GPIO_A:
<> 144:ef7eb2e8f9f7 325 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
AnnaBridge 167:e84263d55307 326 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
<> 144:ef7eb2e8f9f7 327 break;
<> 144:ef7eb2e8f9f7 328 case PWR_GPIO_B:
<> 144:ef7eb2e8f9f7 329 SET_BIT(PWR->PUCRB, GPIONumber);
AnnaBridge 167:e84263d55307 330 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
AnnaBridge 167:e84263d55307 331 break;
<> 144:ef7eb2e8f9f7 332 case PWR_GPIO_C:
<> 144:ef7eb2e8f9f7 333 SET_BIT(PWR->PUCRC, GPIONumber);
AnnaBridge 167:e84263d55307 334 CLEAR_BIT(PWR->PDCRC, GPIONumber);
AnnaBridge 167:e84263d55307 335 break;
AnnaBridge 167:e84263d55307 336 #if defined(GPIOD)
<> 144:ef7eb2e8f9f7 337 case PWR_GPIO_D:
<> 144:ef7eb2e8f9f7 338 SET_BIT(PWR->PUCRD, GPIONumber);
AnnaBridge 167:e84263d55307 339 CLEAR_BIT(PWR->PDCRD, GPIONumber);
<> 144:ef7eb2e8f9f7 340 break;
AnnaBridge 167:e84263d55307 341 #endif
AnnaBridge 167:e84263d55307 342 #if defined(GPIOE)
<> 144:ef7eb2e8f9f7 343 case PWR_GPIO_E:
<> 144:ef7eb2e8f9f7 344 SET_BIT(PWR->PUCRE, GPIONumber);
AnnaBridge 167:e84263d55307 345 CLEAR_BIT(PWR->PDCRE, GPIONumber);
AnnaBridge 167:e84263d55307 346 break;
AnnaBridge 167:e84263d55307 347 #endif
AnnaBridge 167:e84263d55307 348 #if defined(GPIOF)
AnnaBridge 167:e84263d55307 349 case PWR_GPIO_F:
AnnaBridge 167:e84263d55307 350 SET_BIT(PWR->PUCRF, GPIONumber);
AnnaBridge 167:e84263d55307 351 CLEAR_BIT(PWR->PDCRF, GPIONumber);
<> 144:ef7eb2e8f9f7 352 break;
<> 144:ef7eb2e8f9f7 353 #endif
AnnaBridge 167:e84263d55307 354 #if defined(GPIOG)
<> 144:ef7eb2e8f9f7 355 case PWR_GPIO_G:
<> 144:ef7eb2e8f9f7 356 SET_BIT(PWR->PUCRG, GPIONumber);
AnnaBridge 167:e84263d55307 357 CLEAR_BIT(PWR->PDCRG, GPIONumber);
<> 144:ef7eb2e8f9f7 358 break;
AnnaBridge 167:e84263d55307 359 #endif
<> 144:ef7eb2e8f9f7 360 case PWR_GPIO_H:
<> 144:ef7eb2e8f9f7 361 SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
AnnaBridge 167:e84263d55307 362 #if defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 363 CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
AnnaBridge 167:e84263d55307 364 #else
AnnaBridge 167:e84263d55307 365 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
AnnaBridge 167:e84263d55307 366 #endif
AnnaBridge 167:e84263d55307 367 break;
AnnaBridge 167:e84263d55307 368 #if defined(GPIOI)
AnnaBridge 167:e84263d55307 369 case PWR_GPIO_I:
AnnaBridge 167:e84263d55307 370 SET_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
AnnaBridge 167:e84263d55307 371 CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
AnnaBridge 167:e84263d55307 372 break;
AnnaBridge 167:e84263d55307 373 #endif
<> 144:ef7eb2e8f9f7 374 default:
AnnaBridge 167:e84263d55307 375 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 376 }
AnnaBridge 167:e84263d55307 377
<> 144:ef7eb2e8f9f7 378 return HAL_OK;
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /**
<> 144:ef7eb2e8f9f7 383 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
<> 144:ef7eb2e8f9f7 384 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
<> 144:ef7eb2e8f9f7 385 * in pull-up state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 386 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
<> 144:ef7eb2e8f9f7 387 * parameter at the same time are reset.
<> 144:ef7eb2e8f9f7 388 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
AnnaBridge 167:e84263d55307 389 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
<> 144:ef7eb2e8f9f7 390 * @param GPIONumber: Specify the I/O pins numbers.
<> 144:ef7eb2e8f9f7 391 * This parameter can be one of the following values:
AnnaBridge 167:e84263d55307 392 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
<> 144:ef7eb2e8f9f7 393 * I/O pins are available) or the logical OR of several of them to reset
<> 144:ef7eb2e8f9f7 394 * several bits for a given port in a single API call.
<> 144:ef7eb2e8f9f7 395 * @retval HAL Status
<> 144:ef7eb2e8f9f7 396 */
<> 144:ef7eb2e8f9f7 397 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 assert_param(IS_PWR_GPIO(GPIO));
<> 144:ef7eb2e8f9f7 400 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 switch (GPIO)
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 case PWR_GPIO_A:
AnnaBridge 167:e84263d55307 405 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
<> 144:ef7eb2e8f9f7 406 break;
<> 144:ef7eb2e8f9f7 407 case PWR_GPIO_B:
<> 144:ef7eb2e8f9f7 408 CLEAR_BIT(PWR->PUCRB, GPIONumber);
AnnaBridge 167:e84263d55307 409 break;
<> 144:ef7eb2e8f9f7 410 case PWR_GPIO_C:
<> 144:ef7eb2e8f9f7 411 CLEAR_BIT(PWR->PUCRC, GPIONumber);
AnnaBridge 167:e84263d55307 412 break;
AnnaBridge 167:e84263d55307 413 #if defined(GPIOD)
<> 144:ef7eb2e8f9f7 414 case PWR_GPIO_D:
<> 144:ef7eb2e8f9f7 415 CLEAR_BIT(PWR->PUCRD, GPIONumber);
<> 144:ef7eb2e8f9f7 416 break;
AnnaBridge 167:e84263d55307 417 #endif
AnnaBridge 167:e84263d55307 418 #if defined(GPIOE)
<> 144:ef7eb2e8f9f7 419 case PWR_GPIO_E:
<> 144:ef7eb2e8f9f7 420 CLEAR_BIT(PWR->PUCRE, GPIONumber);
<> 144:ef7eb2e8f9f7 421 break;
<> 144:ef7eb2e8f9f7 422 #endif
AnnaBridge 167:e84263d55307 423 #if defined(GPIOF)
<> 144:ef7eb2e8f9f7 424 case PWR_GPIO_F:
<> 144:ef7eb2e8f9f7 425 CLEAR_BIT(PWR->PUCRF, GPIONumber);
<> 144:ef7eb2e8f9f7 426 break;
AnnaBridge 167:e84263d55307 427 #endif
AnnaBridge 167:e84263d55307 428 #if defined(GPIOG)
<> 144:ef7eb2e8f9f7 429 case PWR_GPIO_G:
<> 144:ef7eb2e8f9f7 430 CLEAR_BIT(PWR->PUCRG, GPIONumber);
<> 144:ef7eb2e8f9f7 431 break;
AnnaBridge 167:e84263d55307 432 #endif
AnnaBridge 167:e84263d55307 433 case PWR_GPIO_H:
<> 144:ef7eb2e8f9f7 434 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
AnnaBridge 167:e84263d55307 435 break;
AnnaBridge 167:e84263d55307 436 #if defined(GPIOI)
AnnaBridge 167:e84263d55307 437 case PWR_GPIO_I:
AnnaBridge 167:e84263d55307 438 CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
AnnaBridge 167:e84263d55307 439 break;
AnnaBridge 167:e84263d55307 440 #endif
<> 144:ef7eb2e8f9f7 441 default:
AnnaBridge 167:e84263d55307 442 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 443 }
AnnaBridge 167:e84263d55307 444
<> 144:ef7eb2e8f9f7 445 return HAL_OK;
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /**
<> 144:ef7eb2e8f9f7 451 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 452 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
<> 144:ef7eb2e8f9f7 453 * pull-down state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 454 * @note This state is effective in Standby and Shutdown modes only if APC bit
<> 144:ef7eb2e8f9f7 455 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
<> 144:ef7eb2e8f9f7 456 * @note The configuration is lost when exiting the Shutdown mode due to the
<> 144:ef7eb2e8f9f7 457 * power-on reset, maintained when exiting the Standby mode.
<> 144:ef7eb2e8f9f7 458 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
<> 144:ef7eb2e8f9f7 459 * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
<> 144:ef7eb2e8f9f7 460 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
<> 144:ef7eb2e8f9f7 461 * parameter at the same time are set.
<> 144:ef7eb2e8f9f7 462 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
AnnaBridge 167:e84263d55307 463 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
<> 144:ef7eb2e8f9f7 464 * @param GPIONumber: Specify the I/O pins numbers.
<> 144:ef7eb2e8f9f7 465 * This parameter can be one of the following values:
AnnaBridge 167:e84263d55307 466 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
<> 144:ef7eb2e8f9f7 467 * I/O pins are available) or the logical OR of several of them to set
<> 144:ef7eb2e8f9f7 468 * several bits for a given port in a single API call.
<> 144:ef7eb2e8f9f7 469 * @retval HAL Status
<> 144:ef7eb2e8f9f7 470 */
<> 144:ef7eb2e8f9f7 471 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 assert_param(IS_PWR_GPIO(GPIO));
<> 144:ef7eb2e8f9f7 474 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 switch (GPIO)
AnnaBridge 167:e84263d55307 477 {
<> 144:ef7eb2e8f9f7 478 case PWR_GPIO_A:
AnnaBridge 167:e84263d55307 479 SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
AnnaBridge 167:e84263d55307 480 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
<> 144:ef7eb2e8f9f7 481 break;
<> 144:ef7eb2e8f9f7 482 case PWR_GPIO_B:
<> 144:ef7eb2e8f9f7 483 SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
AnnaBridge 167:e84263d55307 484 CLEAR_BIT(PWR->PUCRB, GPIONumber);
AnnaBridge 167:e84263d55307 485 break;
<> 144:ef7eb2e8f9f7 486 case PWR_GPIO_C:
<> 144:ef7eb2e8f9f7 487 SET_BIT(PWR->PDCRC, GPIONumber);
AnnaBridge 167:e84263d55307 488 CLEAR_BIT(PWR->PUCRC, GPIONumber);
AnnaBridge 167:e84263d55307 489 break;
AnnaBridge 167:e84263d55307 490 #if defined(GPIOD)
<> 144:ef7eb2e8f9f7 491 case PWR_GPIO_D:
<> 144:ef7eb2e8f9f7 492 SET_BIT(PWR->PDCRD, GPIONumber);
AnnaBridge 167:e84263d55307 493 CLEAR_BIT(PWR->PUCRD, GPIONumber);
<> 144:ef7eb2e8f9f7 494 break;
AnnaBridge 167:e84263d55307 495 #endif
AnnaBridge 167:e84263d55307 496 #if defined(GPIOE)
<> 144:ef7eb2e8f9f7 497 case PWR_GPIO_E:
<> 144:ef7eb2e8f9f7 498 SET_BIT(PWR->PDCRE, GPIONumber);
AnnaBridge 167:e84263d55307 499 CLEAR_BIT(PWR->PUCRE, GPIONumber);
AnnaBridge 167:e84263d55307 500 break;
AnnaBridge 167:e84263d55307 501 #endif
AnnaBridge 167:e84263d55307 502 #if defined(GPIOF)
AnnaBridge 167:e84263d55307 503 case PWR_GPIO_F:
AnnaBridge 167:e84263d55307 504 SET_BIT(PWR->PDCRF, GPIONumber);
AnnaBridge 167:e84263d55307 505 CLEAR_BIT(PWR->PUCRF, GPIONumber);
<> 144:ef7eb2e8f9f7 506 break;
<> 144:ef7eb2e8f9f7 507 #endif
AnnaBridge 167:e84263d55307 508 #if defined(GPIOG)
<> 144:ef7eb2e8f9f7 509 case PWR_GPIO_G:
<> 144:ef7eb2e8f9f7 510 SET_BIT(PWR->PDCRG, GPIONumber);
AnnaBridge 167:e84263d55307 511 CLEAR_BIT(PWR->PUCRG, GPIONumber);
<> 144:ef7eb2e8f9f7 512 break;
AnnaBridge 167:e84263d55307 513 #endif
<> 144:ef7eb2e8f9f7 514 case PWR_GPIO_H:
AnnaBridge 167:e84263d55307 515 #if defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 516 SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
AnnaBridge 167:e84263d55307 517 #else
<> 144:ef7eb2e8f9f7 518 SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
AnnaBridge 167:e84263d55307 519 #endif
AnnaBridge 167:e84263d55307 520 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
AnnaBridge 167:e84263d55307 521 break;
AnnaBridge 167:e84263d55307 522 #if defined(GPIOI)
AnnaBridge 167:e84263d55307 523 case PWR_GPIO_I:
AnnaBridge 167:e84263d55307 524 SET_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
AnnaBridge 167:e84263d55307 525 CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
AnnaBridge 167:e84263d55307 526 break;
AnnaBridge 167:e84263d55307 527 #endif
<> 144:ef7eb2e8f9f7 528 default:
AnnaBridge 167:e84263d55307 529 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 530 }
AnnaBridge 167:e84263d55307 531
<> 144:ef7eb2e8f9f7 532 return HAL_OK;
<> 144:ef7eb2e8f9f7 533 }
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /**
<> 144:ef7eb2e8f9f7 537 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 538 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
<> 144:ef7eb2e8f9f7 539 * in pull-down state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 540 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
<> 144:ef7eb2e8f9f7 541 * parameter at the same time are reset.
<> 144:ef7eb2e8f9f7 542 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
AnnaBridge 167:e84263d55307 543 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
<> 144:ef7eb2e8f9f7 544 * @param GPIONumber: Specify the I/O pins numbers.
<> 144:ef7eb2e8f9f7 545 * This parameter can be one of the following values:
AnnaBridge 167:e84263d55307 546 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
<> 144:ef7eb2e8f9f7 547 * I/O pins are available) or the logical OR of several of them to reset
<> 144:ef7eb2e8f9f7 548 * several bits for a given port in a single API call.
<> 144:ef7eb2e8f9f7 549 * @retval HAL Status
<> 144:ef7eb2e8f9f7 550 */
<> 144:ef7eb2e8f9f7 551 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
<> 144:ef7eb2e8f9f7 552 {
<> 144:ef7eb2e8f9f7 553 assert_param(IS_PWR_GPIO(GPIO));
<> 144:ef7eb2e8f9f7 554 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 switch (GPIO)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 case PWR_GPIO_A:
AnnaBridge 167:e84263d55307 559 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
<> 144:ef7eb2e8f9f7 560 break;
<> 144:ef7eb2e8f9f7 561 case PWR_GPIO_B:
AnnaBridge 167:e84263d55307 562 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
<> 144:ef7eb2e8f9f7 563 break;
<> 144:ef7eb2e8f9f7 564 case PWR_GPIO_C:
<> 144:ef7eb2e8f9f7 565 CLEAR_BIT(PWR->PDCRC, GPIONumber);
AnnaBridge 167:e84263d55307 566 break;
AnnaBridge 167:e84263d55307 567 #if defined(GPIOD)
<> 144:ef7eb2e8f9f7 568 case PWR_GPIO_D:
<> 144:ef7eb2e8f9f7 569 CLEAR_BIT(PWR->PDCRD, GPIONumber);
<> 144:ef7eb2e8f9f7 570 break;
AnnaBridge 167:e84263d55307 571 #endif
AnnaBridge 167:e84263d55307 572 #if defined(GPIOE)
<> 144:ef7eb2e8f9f7 573 case PWR_GPIO_E:
<> 144:ef7eb2e8f9f7 574 CLEAR_BIT(PWR->PDCRE, GPIONumber);
<> 144:ef7eb2e8f9f7 575 break;
<> 144:ef7eb2e8f9f7 576 #endif
AnnaBridge 167:e84263d55307 577 #if defined(GPIOF)
<> 144:ef7eb2e8f9f7 578 case PWR_GPIO_F:
<> 144:ef7eb2e8f9f7 579 CLEAR_BIT(PWR->PDCRF, GPIONumber);
<> 144:ef7eb2e8f9f7 580 break;
AnnaBridge 167:e84263d55307 581 #endif
AnnaBridge 167:e84263d55307 582 #if defined(GPIOG)
<> 144:ef7eb2e8f9f7 583 case PWR_GPIO_G:
<> 144:ef7eb2e8f9f7 584 CLEAR_BIT(PWR->PDCRG, GPIONumber);
<> 144:ef7eb2e8f9f7 585 break;
AnnaBridge 167:e84263d55307 586 #endif
<> 144:ef7eb2e8f9f7 587 case PWR_GPIO_H:
AnnaBridge 167:e84263d55307 588 #if defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 589 CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
AnnaBridge 167:e84263d55307 590 #else
AnnaBridge 167:e84263d55307 591 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
AnnaBridge 167:e84263d55307 592 #endif
AnnaBridge 167:e84263d55307 593 break;
AnnaBridge 167:e84263d55307 594 #if defined(GPIOI)
AnnaBridge 167:e84263d55307 595 case PWR_GPIO_I:
AnnaBridge 167:e84263d55307 596 CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
AnnaBridge 167:e84263d55307 597 break;
AnnaBridge 167:e84263d55307 598 #endif
<> 144:ef7eb2e8f9f7 599 default:
AnnaBridge 167:e84263d55307 600 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 601 }
AnnaBridge 167:e84263d55307 602
<> 144:ef7eb2e8f9f7 603 return HAL_OK;
<> 144:ef7eb2e8f9f7 604 }
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /**
<> 144:ef7eb2e8f9f7 609 * @brief Enable pull-up and pull-down configuration.
<> 144:ef7eb2e8f9f7 610 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
<> 144:ef7eb2e8f9f7 611 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 612 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
<> 144:ef7eb2e8f9f7 613 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
<> 144:ef7eb2e8f9f7 614 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
<> 144:ef7eb2e8f9f7 615 * is no conflict when setting PUy or PDy bit.
<> 144:ef7eb2e8f9f7 616 * @retval None
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618 void HAL_PWREx_EnablePullUpPullDownConfig(void)
<> 144:ef7eb2e8f9f7 619 {
<> 144:ef7eb2e8f9f7 620 SET_BIT(PWR->CR3, PWR_CR3_APC);
<> 144:ef7eb2e8f9f7 621 }
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /**
<> 144:ef7eb2e8f9f7 625 * @brief Disable pull-up and pull-down configuration.
<> 144:ef7eb2e8f9f7 626 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
<> 144:ef7eb2e8f9f7 627 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 628 * @retval None
<> 144:ef7eb2e8f9f7 629 */
<> 144:ef7eb2e8f9f7 630 void HAL_PWREx_DisablePullUpPullDownConfig(void)
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
<> 144:ef7eb2e8f9f7 633 }
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /**
<> 144:ef7eb2e8f9f7 638 * @brief Enable SRAM2 content retention in Standby mode.
<> 144:ef7eb2e8f9f7 639 * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in
<> 144:ef7eb2e8f9f7 640 * Standby mode and its content is kept.
<> 144:ef7eb2e8f9f7 641 * @retval None
<> 144:ef7eb2e8f9f7 642 */
<> 144:ef7eb2e8f9f7 643 void HAL_PWREx_EnableSRAM2ContentRetention(void)
<> 144:ef7eb2e8f9f7 644 {
<> 144:ef7eb2e8f9f7 645 SET_BIT(PWR->CR3, PWR_CR3_RRS);
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /**
<> 144:ef7eb2e8f9f7 650 * @brief Disable SRAM2 content retention in Standby mode.
<> 144:ef7eb2e8f9f7 651 * @note When RRS bit is reset, SRAM2 is powered off in Standby mode
<> 144:ef7eb2e8f9f7 652 * and its content is lost.
<> 144:ef7eb2e8f9f7 653 * @retval None
<> 144:ef7eb2e8f9f7 654 */
<> 144:ef7eb2e8f9f7 655 void HAL_PWREx_DisableSRAM2ContentRetention(void)
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
<> 144:ef7eb2e8f9f7 658 }
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662
AnnaBridge 167:e84263d55307 663 #if defined(PWR_CR2_PVME1)
<> 144:ef7eb2e8f9f7 664 /**
<> 144:ef7eb2e8f9f7 665 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
<> 144:ef7eb2e8f9f7 666 * @retval None
<> 144:ef7eb2e8f9f7 667 */
<> 144:ef7eb2e8f9f7 668 void HAL_PWREx_EnablePVM1(void)
<> 144:ef7eb2e8f9f7 669 {
<> 144:ef7eb2e8f9f7 670 SET_BIT(PWR->CR2, PWR_PVM_1);
<> 144:ef7eb2e8f9f7 671 }
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /**
<> 144:ef7eb2e8f9f7 674 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
<> 144:ef7eb2e8f9f7 675 * @retval None
<> 144:ef7eb2e8f9f7 676 */
<> 144:ef7eb2e8f9f7 677 void HAL_PWREx_DisablePVM1(void)
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 CLEAR_BIT(PWR->CR2, PWR_PVM_1);
<> 144:ef7eb2e8f9f7 680 }
AnnaBridge 167:e84263d55307 681 #endif /* PWR_CR2_PVME1 */
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683
AnnaBridge 167:e84263d55307 684 #if defined(PWR_CR2_PVME2)
<> 144:ef7eb2e8f9f7 685 /**
<> 144:ef7eb2e8f9f7 686 * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
<> 144:ef7eb2e8f9f7 687 * @retval None
<> 144:ef7eb2e8f9f7 688 */
<> 144:ef7eb2e8f9f7 689 void HAL_PWREx_EnablePVM2(void)
<> 144:ef7eb2e8f9f7 690 {
<> 144:ef7eb2e8f9f7 691 SET_BIT(PWR->CR2, PWR_PVM_2);
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /**
<> 144:ef7eb2e8f9f7 695 * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
<> 144:ef7eb2e8f9f7 696 * @retval None
<> 144:ef7eb2e8f9f7 697 */
<> 144:ef7eb2e8f9f7 698 void HAL_PWREx_DisablePVM2(void)
<> 144:ef7eb2e8f9f7 699 {
<> 144:ef7eb2e8f9f7 700 CLEAR_BIT(PWR->CR2, PWR_PVM_2);
<> 144:ef7eb2e8f9f7 701 }
AnnaBridge 167:e84263d55307 702 #endif /* PWR_CR2_PVME2 */
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /**
<> 144:ef7eb2e8f9f7 706 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
<> 144:ef7eb2e8f9f7 707 * @retval None
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709 void HAL_PWREx_EnablePVM3(void)
<> 144:ef7eb2e8f9f7 710 {
<> 144:ef7eb2e8f9f7 711 SET_BIT(PWR->CR2, PWR_PVM_3);
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /**
<> 144:ef7eb2e8f9f7 715 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
<> 144:ef7eb2e8f9f7 716 * @retval None
<> 144:ef7eb2e8f9f7 717 */
<> 144:ef7eb2e8f9f7 718 void HAL_PWREx_DisablePVM3(void)
<> 144:ef7eb2e8f9f7 719 {
<> 144:ef7eb2e8f9f7 720 CLEAR_BIT(PWR->CR2, PWR_PVM_3);
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /**
<> 144:ef7eb2e8f9f7 725 * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.
<> 144:ef7eb2e8f9f7 726 * @retval None
<> 144:ef7eb2e8f9f7 727 */
<> 144:ef7eb2e8f9f7 728 void HAL_PWREx_EnablePVM4(void)
<> 144:ef7eb2e8f9f7 729 {
<> 144:ef7eb2e8f9f7 730 SET_BIT(PWR->CR2, PWR_PVM_4);
<> 144:ef7eb2e8f9f7 731 }
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 /**
<> 144:ef7eb2e8f9f7 734 * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.
<> 144:ef7eb2e8f9f7 735 * @retval None
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737 void HAL_PWREx_DisablePVM4(void)
<> 144:ef7eb2e8f9f7 738 {
<> 144:ef7eb2e8f9f7 739 CLEAR_BIT(PWR->CR2, PWR_PVM_4);
<> 144:ef7eb2e8f9f7 740 }
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /**
<> 144:ef7eb2e8f9f7 746 * @brief Configure the Peripheral Voltage Monitoring (PVM).
<> 144:ef7eb2e8f9f7 747 * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
<> 144:ef7eb2e8f9f7 748 * PVM configuration information.
<> 144:ef7eb2e8f9f7 749 * @note The API configures a single PVM according to the information contained
<> 144:ef7eb2e8f9f7 750 * in the input structure. To configure several PVMs, the API must be singly
<> 144:ef7eb2e8f9f7 751 * called for each PVM used.
<> 144:ef7eb2e8f9f7 752 * @note Refer to the electrical characteristics of your device datasheet for
<> 144:ef7eb2e8f9f7 753 * more details about the voltage thresholds corresponding to each
<> 144:ef7eb2e8f9f7 754 * detection level and to each monitored supply.
<> 144:ef7eb2e8f9f7 755 * @retval HAL status
<> 144:ef7eb2e8f9f7 756 */
<> 144:ef7eb2e8f9f7 757 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
<> 144:ef7eb2e8f9f7 758 {
<> 144:ef7eb2e8f9f7 759 /* Check the parameters */
<> 144:ef7eb2e8f9f7 760 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
<> 144:ef7eb2e8f9f7 761 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* Configure EXTI 35 to 38 interrupts if so required:
<> 144:ef7eb2e8f9f7 765 scan thru PVMType to detect which PVMx is set and
<> 144:ef7eb2e8f9f7 766 configure the corresponding EXTI line accordingly. */
<> 144:ef7eb2e8f9f7 767 switch (sConfigPVM->PVMType)
<> 144:ef7eb2e8f9f7 768 {
AnnaBridge 167:e84263d55307 769 #if defined(PWR_CR2_PVME1)
<> 144:ef7eb2e8f9f7 770 case PWR_PVM_1:
<> 144:ef7eb2e8f9f7 771 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
<> 144:ef7eb2e8f9f7 772 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
<> 144:ef7eb2e8f9f7 773 __HAL_PWR_PVM1_EXTI_DISABLE_IT();
<> 144:ef7eb2e8f9f7 774 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 775 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 /* Configure interrupt mode */
<> 144:ef7eb2e8f9f7 778 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
<> 144:ef7eb2e8f9f7 779 {
<> 144:ef7eb2e8f9f7 780 __HAL_PWR_PVM1_EXTI_ENABLE_IT();
<> 144:ef7eb2e8f9f7 781 }
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /* Configure event mode */
<> 144:ef7eb2e8f9f7 784 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
<> 144:ef7eb2e8f9f7 787 }
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /* Configure the edge */
<> 144:ef7eb2e8f9f7 790 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
<> 144:ef7eb2e8f9f7 791 {
<> 144:ef7eb2e8f9f7 792 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 793 }
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
<> 144:ef7eb2e8f9f7 796 {
<> 144:ef7eb2e8f9f7 797 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 798 }
<> 144:ef7eb2e8f9f7 799 break;
AnnaBridge 167:e84263d55307 800 #endif /* PWR_CR2_PVME1 */
<> 144:ef7eb2e8f9f7 801
AnnaBridge 167:e84263d55307 802 #if defined(PWR_CR2_PVME2)
<> 144:ef7eb2e8f9f7 803 case PWR_PVM_2:
<> 144:ef7eb2e8f9f7 804 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
<> 144:ef7eb2e8f9f7 805 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
<> 144:ef7eb2e8f9f7 806 __HAL_PWR_PVM2_EXTI_DISABLE_IT();
<> 144:ef7eb2e8f9f7 807 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 808 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 /* Configure interrupt mode */
<> 144:ef7eb2e8f9f7 811 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 __HAL_PWR_PVM2_EXTI_ENABLE_IT();
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /* Configure event mode */
<> 144:ef7eb2e8f9f7 817 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
<> 144:ef7eb2e8f9f7 820 }
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /* Configure the edge */
<> 144:ef7eb2e8f9f7 823 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
<> 144:ef7eb2e8f9f7 824 {
<> 144:ef7eb2e8f9f7 825 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 826 }
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
<> 144:ef7eb2e8f9f7 829 {
<> 144:ef7eb2e8f9f7 830 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832 break;
AnnaBridge 167:e84263d55307 833 #endif /* PWR_CR2_PVME2 */
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 case PWR_PVM_3:
<> 144:ef7eb2e8f9f7 836 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
<> 144:ef7eb2e8f9f7 837 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
<> 144:ef7eb2e8f9f7 838 __HAL_PWR_PVM3_EXTI_DISABLE_IT();
<> 144:ef7eb2e8f9f7 839 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 840 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /* Configure interrupt mode */
<> 144:ef7eb2e8f9f7 843 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 __HAL_PWR_PVM3_EXTI_ENABLE_IT();
<> 144:ef7eb2e8f9f7 846 }
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /* Configure event mode */
<> 144:ef7eb2e8f9f7 849 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /* Configure the edge */
<> 144:ef7eb2e8f9f7 855 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
<> 144:ef7eb2e8f9f7 856 {
<> 144:ef7eb2e8f9f7 857 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 858 }
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
<> 144:ef7eb2e8f9f7 861 {
<> 144:ef7eb2e8f9f7 862 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864 break;
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 case PWR_PVM_4:
<> 144:ef7eb2e8f9f7 867 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
<> 144:ef7eb2e8f9f7 868 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
<> 144:ef7eb2e8f9f7 869 __HAL_PWR_PVM4_EXTI_DISABLE_IT();
<> 144:ef7eb2e8f9f7 870 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 871 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* Configure interrupt mode */
<> 144:ef7eb2e8f9f7 874 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
<> 144:ef7eb2e8f9f7 875 {
<> 144:ef7eb2e8f9f7 876 __HAL_PWR_PVM4_EXTI_ENABLE_IT();
<> 144:ef7eb2e8f9f7 877 }
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /* Configure event mode */
<> 144:ef7eb2e8f9f7 880 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
<> 144:ef7eb2e8f9f7 881 {
<> 144:ef7eb2e8f9f7 882 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
<> 144:ef7eb2e8f9f7 883 }
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /* Configure the edge */
<> 144:ef7eb2e8f9f7 886 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
<> 144:ef7eb2e8f9f7 887 {
<> 144:ef7eb2e8f9f7 888 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 889 }
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
<> 144:ef7eb2e8f9f7 892 {
<> 144:ef7eb2e8f9f7 893 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 894 }
<> 144:ef7eb2e8f9f7 895 break;
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 default:
<> 144:ef7eb2e8f9f7 898 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 }
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 return HAL_OK;
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 /**
<> 144:ef7eb2e8f9f7 909 * @brief Enter Low-power Run mode
<> 144:ef7eb2e8f9f7 910 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 911 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
<> 144:ef7eb2e8f9f7 912 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
<> 144:ef7eb2e8f9f7 913 * Additionally, the clock frequency must be reduced below 2 MHz.
<> 144:ef7eb2e8f9f7 914 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
<> 144:ef7eb2e8f9f7 915 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
<> 144:ef7eb2e8f9f7 916 * @retval None
<> 144:ef7eb2e8f9f7 917 */
<> 144:ef7eb2e8f9f7 918 void HAL_PWREx_EnableLowPowerRunMode(void)
<> 144:ef7eb2e8f9f7 919 {
<> 144:ef7eb2e8f9f7 920 /* Set Regulator parameter */
<> 144:ef7eb2e8f9f7 921 SET_BIT(PWR->CR1, PWR_CR1_LPR);
<> 144:ef7eb2e8f9f7 922 }
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /**
<> 144:ef7eb2e8f9f7 926 * @brief Exit Low-power Run mode.
<> 144:ef7eb2e8f9f7 927 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
<> 144:ef7eb2e8f9f7 928 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
<> 144:ef7eb2e8f9f7 929 * returns HAL_TIMEOUT status). The system clock frequency can then be
<> 144:ef7eb2e8f9f7 930 * increased above 2 MHz.
<> 144:ef7eb2e8f9f7 931 * @retval HAL Status
<> 144:ef7eb2e8f9f7 932 */
<> 144:ef7eb2e8f9f7 933 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
<> 144:ef7eb2e8f9f7 934 {
<> 144:ef7eb2e8f9f7 935 uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /* Clear LPR bit */
<> 144:ef7eb2e8f9f7 938 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940 /* Wait until REGLPF is reset */
<> 144:ef7eb2e8f9f7 941 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 942 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)))
<> 144:ef7eb2e8f9f7 943 {
<> 144:ef7eb2e8f9f7 944 wait_loop_index--;
<> 144:ef7eb2e8f9f7 945 }
<> 144:ef7eb2e8f9f7 946 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
<> 144:ef7eb2e8f9f7 947 {
<> 144:ef7eb2e8f9f7 948 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 949 }
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 return HAL_OK;
<> 144:ef7eb2e8f9f7 952 }
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954
<> 144:ef7eb2e8f9f7 955 /**
<> 144:ef7eb2e8f9f7 956 * @brief Enter Stop 0 mode.
<> 144:ef7eb2e8f9f7 957 * @note In Stop 0 mode, main and low voltage regulators are ON.
<> 144:ef7eb2e8f9f7 958 * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 959 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
<> 144:ef7eb2e8f9f7 960 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
<> 144:ef7eb2e8f9f7 961 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
<> 144:ef7eb2e8f9f7 962 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
<> 144:ef7eb2e8f9f7 963 * only to the peripheral requesting it.
<> 144:ef7eb2e8f9f7 964 * SRAM1, SRAM2 and register contents are preserved.
<> 144:ef7eb2e8f9f7 965 * The BOR is available.
<> 144:ef7eb2e8f9f7 966 * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
<> 144:ef7eb2e8f9f7 967 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
<> 144:ef7eb2e8f9f7 968 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
<> 144:ef7eb2e8f9f7 969 * @note By keeping the internal regulator ON during Stop 0 mode, the consumption
<> 144:ef7eb2e8f9f7 970 * is higher although the startup time is reduced.
<> 144:ef7eb2e8f9f7 971 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 972 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 973 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
<> 144:ef7eb2e8f9f7 974 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
<> 144:ef7eb2e8f9f7 975 * @retval None
<> 144:ef7eb2e8f9f7 976 */
<> 144:ef7eb2e8f9f7 977 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
<> 144:ef7eb2e8f9f7 978 {
<> 144:ef7eb2e8f9f7 979 /* Check the parameters */
<> 144:ef7eb2e8f9f7 980 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 /* Stop 0 mode with Main Regulator */
<> 144:ef7eb2e8f9f7 983 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 986 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /* Select Stop mode entry --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 989 if(STOPEntry == PWR_STOPENTRY_WFI)
<> 144:ef7eb2e8f9f7 990 {
<> 144:ef7eb2e8f9f7 991 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 992 __WFI();
<> 144:ef7eb2e8f9f7 993 }
<> 144:ef7eb2e8f9f7 994 else
<> 144:ef7eb2e8f9f7 995 {
<> 144:ef7eb2e8f9f7 996 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 997 __SEV();
<> 144:ef7eb2e8f9f7 998 __WFE();
<> 144:ef7eb2e8f9f7 999 __WFE();
<> 144:ef7eb2e8f9f7 1000 }
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 /* Reset SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 1003 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 1004 }
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /**
<> 144:ef7eb2e8f9f7 1008 * @brief Enter Stop 1 mode.
<> 144:ef7eb2e8f9f7 1009 * @note In Stop 1 mode, only low power voltage regulator is ON.
<> 144:ef7eb2e8f9f7 1010 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 1011 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
<> 144:ef7eb2e8f9f7 1012 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
<> 144:ef7eb2e8f9f7 1013 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
<> 144:ef7eb2e8f9f7 1014 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
<> 144:ef7eb2e8f9f7 1015 * only to the peripheral requesting it.
<> 144:ef7eb2e8f9f7 1016 * SRAM1, SRAM2 and register contents are preserved.
<> 144:ef7eb2e8f9f7 1017 * The BOR is available.
<> 144:ef7eb2e8f9f7 1018 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
<> 144:ef7eb2e8f9f7 1019 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
<> 144:ef7eb2e8f9f7 1020 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
<> 144:ef7eb2e8f9f7 1021 * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
<> 144:ef7eb2e8f9f7 1022 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 1023 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1024 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
<> 144:ef7eb2e8f9f7 1025 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
<> 144:ef7eb2e8f9f7 1026 * @retval None
<> 144:ef7eb2e8f9f7 1027 */
<> 144:ef7eb2e8f9f7 1028 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
<> 144:ef7eb2e8f9f7 1029 {
<> 144:ef7eb2e8f9f7 1030 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1031 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
<> 144:ef7eb2e8f9f7 1032
<> 144:ef7eb2e8f9f7 1033 /* Stop 1 mode with Low-Power Regulator */
<> 144:ef7eb2e8f9f7 1034 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
<> 144:ef7eb2e8f9f7 1035
<> 144:ef7eb2e8f9f7 1036 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 1037 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 /* Select Stop mode entry --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1040 if(STOPEntry == PWR_STOPENTRY_WFI)
<> 144:ef7eb2e8f9f7 1041 {
<> 144:ef7eb2e8f9f7 1042 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 1043 __WFI();
<> 144:ef7eb2e8f9f7 1044 }
<> 144:ef7eb2e8f9f7 1045 else
<> 144:ef7eb2e8f9f7 1046 {
<> 144:ef7eb2e8f9f7 1047 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 1048 __SEV();
<> 144:ef7eb2e8f9f7 1049 __WFE();
<> 144:ef7eb2e8f9f7 1050 __WFE();
<> 144:ef7eb2e8f9f7 1051 }
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 /* Reset SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 1054 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 1055 }
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 /**
<> 144:ef7eb2e8f9f7 1059 * @brief Enter Stop 2 mode.
<> 144:ef7eb2e8f9f7 1060 * @note In Stop 2 mode, only low power voltage regulator is ON.
<> 144:ef7eb2e8f9f7 1061 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 1062 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,
<> 144:ef7eb2e8f9f7 1063 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
<> 144:ef7eb2e8f9f7 1064 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
<> 144:ef7eb2e8f9f7 1065 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
<> 144:ef7eb2e8f9f7 1066 * to the peripheral requesting it.
<> 144:ef7eb2e8f9f7 1067 * SRAM1, SRAM2 and register contents are preserved.
<> 144:ef7eb2e8f9f7 1068 * The BOR is available.
<> 144:ef7eb2e8f9f7 1069 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
<> 144:ef7eb2e8f9f7 1070 * Otherwise, Stop 1 mode is entered.
<> 144:ef7eb2e8f9f7 1071 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
<> 144:ef7eb2e8f9f7 1072 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
<> 144:ef7eb2e8f9f7 1073 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
<> 144:ef7eb2e8f9f7 1074 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 1075 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1076 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
<> 144:ef7eb2e8f9f7 1077 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
<> 144:ef7eb2e8f9f7 1078 * @retval None
<> 144:ef7eb2e8f9f7 1079 */
<> 144:ef7eb2e8f9f7 1080 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
<> 144:ef7eb2e8f9f7 1081 {
<> 144:ef7eb2e8f9f7 1082 /* Check the parameter */
<> 144:ef7eb2e8f9f7 1083 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
<> 144:ef7eb2e8f9f7 1084
<> 144:ef7eb2e8f9f7 1085 /* Set Stop mode 2 */
<> 144:ef7eb2e8f9f7 1086 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 1089 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 /* Select Stop mode entry --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1092 if(STOPEntry == PWR_STOPENTRY_WFI)
<> 144:ef7eb2e8f9f7 1093 {
<> 144:ef7eb2e8f9f7 1094 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 1095 __WFI();
<> 144:ef7eb2e8f9f7 1096 }
<> 144:ef7eb2e8f9f7 1097 else
<> 144:ef7eb2e8f9f7 1098 {
<> 144:ef7eb2e8f9f7 1099 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 1100 __SEV();
<> 144:ef7eb2e8f9f7 1101 __WFE();
<> 144:ef7eb2e8f9f7 1102 __WFE();
<> 144:ef7eb2e8f9f7 1103 }
<> 144:ef7eb2e8f9f7 1104
<> 144:ef7eb2e8f9f7 1105 /* Reset SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 1106 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 1107 }
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /**
<> 144:ef7eb2e8f9f7 1114 * @brief Enter Shutdown mode.
<> 144:ef7eb2e8f9f7 1115 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
<> 144:ef7eb2e8f9f7 1116 * off. The voltage regulator is disabled and Vcore domain is powered off.
<> 144:ef7eb2e8f9f7 1117 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
<> 144:ef7eb2e8f9f7 1118 * The BOR is not available.
<> 144:ef7eb2e8f9f7 1119 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
<> 144:ef7eb2e8f9f7 1120 * @retval None
<> 144:ef7eb2e8f9f7 1121 */
<> 144:ef7eb2e8f9f7 1122 void HAL_PWREx_EnterSHUTDOWNMode(void)
<> 144:ef7eb2e8f9f7 1123 {
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 /* Set Shutdown mode */
<> 144:ef7eb2e8f9f7 1126 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 1129 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /* This option is used to ensure that store operations are completed */
<> 144:ef7eb2e8f9f7 1132 #if defined ( __CC_ARM)
<> 144:ef7eb2e8f9f7 1133 __force_stores();
<> 144:ef7eb2e8f9f7 1134 #endif
<> 144:ef7eb2e8f9f7 1135 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 1136 __WFI();
<> 144:ef7eb2e8f9f7 1137 }
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 /**
<> 144:ef7eb2e8f9f7 1143 * @brief This function handles the PWR PVD/PVMx interrupt request.
<> 144:ef7eb2e8f9f7 1144 * @note This API should be called under the PVD_PVM_IRQHandler().
<> 144:ef7eb2e8f9f7 1145 * @retval None
<> 144:ef7eb2e8f9f7 1146 */
<> 144:ef7eb2e8f9f7 1147 void HAL_PWREx_PVD_PVM_IRQHandler(void)
<> 144:ef7eb2e8f9f7 1148 {
<> 144:ef7eb2e8f9f7 1149 /* Check PWR exti flag */
<> 144:ef7eb2e8f9f7 1150 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
<> 144:ef7eb2e8f9f7 1151 {
<> 144:ef7eb2e8f9f7 1152 /* PWR PVD interrupt user callback */
<> 144:ef7eb2e8f9f7 1153 HAL_PWR_PVDCallback();
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /* Clear PVD exti pending bit */
<> 144:ef7eb2e8f9f7 1156 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
<> 144:ef7eb2e8f9f7 1157 }
<> 144:ef7eb2e8f9f7 1158 /* Next, successively check PVMx exti flags */
AnnaBridge 167:e84263d55307 1159 #if defined(PWR_CR2_PVME1)
<> 144:ef7eb2e8f9f7 1160 if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET)
<> 144:ef7eb2e8f9f7 1161 {
<> 144:ef7eb2e8f9f7 1162 /* PWR PVM1 interrupt user callback */
<> 144:ef7eb2e8f9f7 1163 HAL_PWREx_PVM1Callback();
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 /* Clear PVM1 exti pending bit */
<> 144:ef7eb2e8f9f7 1166 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
<> 144:ef7eb2e8f9f7 1167 }
AnnaBridge 167:e84263d55307 1168 #endif /* PWR_CR2_PVME1 */
AnnaBridge 167:e84263d55307 1169 #if defined(PWR_CR2_PVME2)
<> 144:ef7eb2e8f9f7 1170 if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET)
<> 144:ef7eb2e8f9f7 1171 {
<> 144:ef7eb2e8f9f7 1172 /* PWR PVM2 interrupt user callback */
<> 144:ef7eb2e8f9f7 1173 HAL_PWREx_PVM2Callback();
<> 144:ef7eb2e8f9f7 1174
<> 144:ef7eb2e8f9f7 1175 /* Clear PVM2 exti pending bit */
<> 144:ef7eb2e8f9f7 1176 __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
<> 144:ef7eb2e8f9f7 1177 }
AnnaBridge 167:e84263d55307 1178 #endif /* PWR_CR2_PVME2 */
<> 144:ef7eb2e8f9f7 1179 if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET)
<> 144:ef7eb2e8f9f7 1180 {
<> 144:ef7eb2e8f9f7 1181 /* PWR PVM3 interrupt user callback */
<> 144:ef7eb2e8f9f7 1182 HAL_PWREx_PVM3Callback();
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 /* Clear PVM3 exti pending bit */
<> 144:ef7eb2e8f9f7 1185 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
<> 144:ef7eb2e8f9f7 1186 }
<> 144:ef7eb2e8f9f7 1187 if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET)
<> 144:ef7eb2e8f9f7 1188 {
<> 144:ef7eb2e8f9f7 1189 /* PWR PVM4 interrupt user callback */
<> 144:ef7eb2e8f9f7 1190 HAL_PWREx_PVM4Callback();
<> 144:ef7eb2e8f9f7 1191
<> 144:ef7eb2e8f9f7 1192 /* Clear PVM4 exti pending bit */
<> 144:ef7eb2e8f9f7 1193 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
<> 144:ef7eb2e8f9f7 1194 }
<> 144:ef7eb2e8f9f7 1195 }
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197
AnnaBridge 167:e84263d55307 1198 #if defined(PWR_CR2_PVME1)
<> 144:ef7eb2e8f9f7 1199 /**
<> 144:ef7eb2e8f9f7 1200 * @brief PWR PVM1 interrupt callback
<> 144:ef7eb2e8f9f7 1201 * @retval None
<> 144:ef7eb2e8f9f7 1202 */
<> 144:ef7eb2e8f9f7 1203 __weak void HAL_PWREx_PVM1Callback(void)
<> 144:ef7eb2e8f9f7 1204 {
<> 144:ef7eb2e8f9f7 1205 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1206 HAL_PWREx_PVM1Callback() API can be implemented in the user file
<> 144:ef7eb2e8f9f7 1207 */
<> 144:ef7eb2e8f9f7 1208 }
AnnaBridge 167:e84263d55307 1209 #endif /* PWR_CR2_PVME1 */
<> 144:ef7eb2e8f9f7 1210
AnnaBridge 167:e84263d55307 1211 #if defined(PWR_CR2_PVME2)
<> 144:ef7eb2e8f9f7 1212 /**
<> 144:ef7eb2e8f9f7 1213 * @brief PWR PVM2 interrupt callback
<> 144:ef7eb2e8f9f7 1214 * @retval None
<> 144:ef7eb2e8f9f7 1215 */
<> 144:ef7eb2e8f9f7 1216 __weak void HAL_PWREx_PVM2Callback(void)
<> 144:ef7eb2e8f9f7 1217 {
<> 144:ef7eb2e8f9f7 1218 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1219 HAL_PWREx_PVM2Callback() API can be implemented in the user file
<> 144:ef7eb2e8f9f7 1220 */
<> 144:ef7eb2e8f9f7 1221 }
AnnaBridge 167:e84263d55307 1222 #endif /* PWR_CR2_PVME2 */
<> 144:ef7eb2e8f9f7 1223
<> 144:ef7eb2e8f9f7 1224 /**
<> 144:ef7eb2e8f9f7 1225 * @brief PWR PVM3 interrupt callback
<> 144:ef7eb2e8f9f7 1226 * @retval None
<> 144:ef7eb2e8f9f7 1227 */
<> 144:ef7eb2e8f9f7 1228 __weak void HAL_PWREx_PVM3Callback(void)
<> 144:ef7eb2e8f9f7 1229 {
<> 144:ef7eb2e8f9f7 1230 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1231 HAL_PWREx_PVM3Callback() API can be implemented in the user file
<> 144:ef7eb2e8f9f7 1232 */
<> 144:ef7eb2e8f9f7 1233 }
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 /**
<> 144:ef7eb2e8f9f7 1236 * @brief PWR PVM4 interrupt callback
<> 144:ef7eb2e8f9f7 1237 * @retval None
<> 144:ef7eb2e8f9f7 1238 */
<> 144:ef7eb2e8f9f7 1239 __weak void HAL_PWREx_PVM4Callback(void)
<> 144:ef7eb2e8f9f7 1240 {
<> 144:ef7eb2e8f9f7 1241 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1242 HAL_PWREx_PVM4Callback() API can be implemented in the user file
<> 144:ef7eb2e8f9f7 1243 */
<> 144:ef7eb2e8f9f7 1244 }
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246
<> 144:ef7eb2e8f9f7 1247 /**
<> 144:ef7eb2e8f9f7 1248 * @}
<> 144:ef7eb2e8f9f7 1249 */
<> 144:ef7eb2e8f9f7 1250
<> 144:ef7eb2e8f9f7 1251 /**
<> 144:ef7eb2e8f9f7 1252 * @}
<> 144:ef7eb2e8f9f7 1253 */
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 #endif /* HAL_PWR_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1256 /**
<> 144:ef7eb2e8f9f7 1257 * @}
<> 144:ef7eb2e8f9f7 1258 */
<> 144:ef7eb2e8f9f7 1259
<> 144:ef7eb2e8f9f7 1260 /**
<> 144:ef7eb2e8f9f7 1261 * @}
<> 144:ef7eb2e8f9f7 1262 */
<> 144:ef7eb2e8f9f7 1263
<> 144:ef7eb2e8f9f7 1264 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/