mbed library sources. Supersedes mbed-src.
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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c@181:96ed750bd169, 2018-01-17 (annotated)
- Committer:
- Anna Bridge
- Date:
- Wed Jan 17 15:23:54 2018 +0000
- Revision:
- 181:96ed750bd169
- Parent:
- 167:e84263d55307
mbed-dev libray. Release version 158
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32l4xx_hal_iwdg.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
AnnaBridge | 167:e84263d55307 | 5 | * @version V1.7.1 |
AnnaBridge | 167:e84263d55307 | 6 | * @date 21-April-2017 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief IWDG HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 8 | * This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 9 | * functionalities of the Independent Watchdog (IWDG) peripheral: |
<> | 144:ef7eb2e8f9f7 | 10 | * + Initialization and Start functions |
<> | 144:ef7eb2e8f9f7 | 11 | * + IO operation functions |
<> | 144:ef7eb2e8f9f7 | 12 | * |
<> | 144:ef7eb2e8f9f7 | 13 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 14 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 15 | ##### IWDG Generic features ##### |
<> | 144:ef7eb2e8f9f7 | 16 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 17 | [..] |
<> | 144:ef7eb2e8f9f7 | 18 | (+) The IWDG can be started by either software or hardware (configurable |
<> | 144:ef7eb2e8f9f7 | 19 | through option byte). |
<> | 144:ef7eb2e8f9f7 | 20 | |
<> | 144:ef7eb2e8f9f7 | 21 | (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even |
<> | 144:ef7eb2e8f9f7 | 22 | if the main clock fails. |
<> | 144:ef7eb2e8f9f7 | 23 | |
<> | 144:ef7eb2e8f9f7 | 24 | (+) Once the IWDG is started, the LSI is forced ON and both can not be |
<> | 144:ef7eb2e8f9f7 | 25 | disabled. The counter starts counting down from the reset value (0xFFF). |
<> | 144:ef7eb2e8f9f7 | 26 | When it reaches the end of count value (0x000) a reset signal is |
<> | 144:ef7eb2e8f9f7 | 27 | generated (IWDG reset). |
<> | 144:ef7eb2e8f9f7 | 28 | |
<> | 144:ef7eb2e8f9f7 | 29 | (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, |
<> | 144:ef7eb2e8f9f7 | 30 | the IWDG_RLR value is reloaded in the counter and the watchdog reset is |
<> | 144:ef7eb2e8f9f7 | 31 | prevented. |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | (+) The IWDG is implemented in the VDD voltage domain that is still functional |
<> | 144:ef7eb2e8f9f7 | 34 | in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). |
<> | 144:ef7eb2e8f9f7 | 35 | IWDGRST flag in RCC_CSR register can be used to inform when an IWDG |
<> | 144:ef7eb2e8f9f7 | 36 | reset occurs. |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | (+) Debug mode : When the microcontroller enters debug mode (core halted), |
<> | 144:ef7eb2e8f9f7 | 39 | the IWDG counter either continues to work normally or stops, depending |
<> | 144:ef7eb2e8f9f7 | 40 | on DBG_IWDG_STOP configuration bit in DBG module, accessible through |
<> | 144:ef7eb2e8f9f7 | 41 | __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s |
<> | 144:ef7eb2e8f9f7 | 44 | The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx |
<> | 144:ef7eb2e8f9f7 | 45 | devices provide the capability to measure the LSI frequency (LSI clock |
<> | 144:ef7eb2e8f9f7 | 46 | connected internally to TIM16 CH1 input capture). The measured value |
<> | 144:ef7eb2e8f9f7 | 47 | can be used to have an IWDG timeout with an acceptable accuracy. |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 50 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 51 | [..] |
<> | 144:ef7eb2e8f9f7 | 52 | (#) Use IWDG using HAL_IWDG_Init() function to : |
AnnaBridge | 167:e84263d55307 | 53 | (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI |
<> | 144:ef7eb2e8f9f7 | 54 | clock is forced ON and IWDG counter starts downcounting. |
AnnaBridge | 167:e84263d55307 | 55 | (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR & |
<> | 144:ef7eb2e8f9f7 | 56 | IWDG_WINR. |
AnnaBridge | 167:e84263d55307 | 57 | (++) Configure the IWDG prescaler and counter reload value. This reload |
<> | 144:ef7eb2e8f9f7 | 58 | value will be loaded in the IWDG counter each time the watchdog is |
<> | 144:ef7eb2e8f9f7 | 59 | reloaded, then the IWDG will start counting down from this value. |
AnnaBridge | 167:e84263d55307 | 60 | (++) Wait for status flags to be reset |
AnnaBridge | 167:e84263d55307 | 61 | (++) Depending on window parameter: |
AnnaBridge | 167:e84263d55307 | 62 | (+++) If Window Init parameter is same as Window register value, |
<> | 144:ef7eb2e8f9f7 | 63 | nothing more is done but reload counter value in order to exit |
<> | 144:ef7eb2e8f9f7 | 64 | function withy exact time base. |
AnnaBridge | 167:e84263d55307 | 65 | (+++) Else modify Window register. This will automatically reload |
<> | 144:ef7eb2e8f9f7 | 66 | watchdog counter. |
<> | 144:ef7eb2e8f9f7 | 67 | |
<> | 144:ef7eb2e8f9f7 | 68 | (#) Then the application program must refresh the IWDG counter at regular |
<> | 144:ef7eb2e8f9f7 | 69 | intervals during normal operation to prevent an MCU reset, using |
<> | 144:ef7eb2e8f9f7 | 70 | HAL_IWDG_Refresh() function. |
<> | 144:ef7eb2e8f9f7 | 71 | |
<> | 144:ef7eb2e8f9f7 | 72 | *** IWDG HAL driver macros list *** |
<> | 144:ef7eb2e8f9f7 | 73 | ==================================== |
<> | 144:ef7eb2e8f9f7 | 74 | [..] |
<> | 144:ef7eb2e8f9f7 | 75 | Below the list of most used macros in IWDG HAL driver: |
<> | 144:ef7eb2e8f9f7 | 76 | (+) __HAL_IWDG_START: Enable the IWDG peripheral |
<> | 144:ef7eb2e8f9f7 | 77 | (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in |
<> | 144:ef7eb2e8f9f7 | 78 | the reload register |
<> | 144:ef7eb2e8f9f7 | 79 | |
<> | 144:ef7eb2e8f9f7 | 80 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 81 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 82 | * @attention |
<> | 144:ef7eb2e8f9f7 | 83 | * |
AnnaBridge | 167:e84263d55307 | 84 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 85 | * |
<> | 144:ef7eb2e8f9f7 | 86 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 87 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 88 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 89 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 90 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 91 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 92 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 93 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 94 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 95 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 96 | * |
<> | 144:ef7eb2e8f9f7 | 97 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 98 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 99 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 100 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 101 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 102 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 103 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 104 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 105 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 106 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 107 | * |
<> | 144:ef7eb2e8f9f7 | 108 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 109 | */ |
<> | 144:ef7eb2e8f9f7 | 110 | |
<> | 144:ef7eb2e8f9f7 | 111 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 112 | #include "stm32l4xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 113 | |
<> | 144:ef7eb2e8f9f7 | 114 | /** @addtogroup STM32L4xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 115 | * @{ |
<> | 144:ef7eb2e8f9f7 | 116 | */ |
<> | 144:ef7eb2e8f9f7 | 117 | |
<> | 144:ef7eb2e8f9f7 | 118 | #ifdef HAL_IWDG_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 119 | /** @addtogroup IWDG |
<> | 144:ef7eb2e8f9f7 | 120 | * @brief IWDG HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 121 | * @{ |
<> | 144:ef7eb2e8f9f7 | 122 | */ |
<> | 144:ef7eb2e8f9f7 | 123 | |
<> | 144:ef7eb2e8f9f7 | 124 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 125 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 126 | /** @defgroup IWDG_Private_Defines IWDG Private Defines |
<> | 144:ef7eb2e8f9f7 | 127 | * @{ |
<> | 144:ef7eb2e8f9f7 | 128 | */ |
<> | 144:ef7eb2e8f9f7 | 129 | /* Status register need 5 RC LSI divided by prescaler clock to be updated. With |
<> | 144:ef7eb2e8f9f7 | 130 | higher prescaler (256), and according to HSI variation, we need to wait at |
<> | 144:ef7eb2e8f9f7 | 131 | least 6 cycles so 48 ms. */ |
<> | 144:ef7eb2e8f9f7 | 132 | #define HAL_IWDG_DEFAULT_TIMEOUT 48u |
<> | 144:ef7eb2e8f9f7 | 133 | /** |
<> | 144:ef7eb2e8f9f7 | 134 | * @} |
<> | 144:ef7eb2e8f9f7 | 135 | */ |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 138 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 139 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 140 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 141 | |
<> | 144:ef7eb2e8f9f7 | 142 | /** @addtogroup IWDG_Exported_Functions |
<> | 144:ef7eb2e8f9f7 | 143 | * @{ |
<> | 144:ef7eb2e8f9f7 | 144 | */ |
<> | 144:ef7eb2e8f9f7 | 145 | |
<> | 144:ef7eb2e8f9f7 | 146 | /** @addtogroup IWDG_Exported_Functions_Group1 |
<> | 144:ef7eb2e8f9f7 | 147 | * @brief Initialization and Start functions. |
<> | 144:ef7eb2e8f9f7 | 148 | * |
<> | 144:ef7eb2e8f9f7 | 149 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 150 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 151 | ##### Initialization and Start functions ##### |
<> | 144:ef7eb2e8f9f7 | 152 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 153 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 154 | (+) Initialize the IWDG according to the specified parameters in the |
<> | 144:ef7eb2e8f9f7 | 155 | IWDG_InitTypeDef of associated handle. |
<> | 144:ef7eb2e8f9f7 | 156 | (+) Manage Window option. |
<> | 144:ef7eb2e8f9f7 | 157 | (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog |
<> | 144:ef7eb2e8f9f7 | 158 | is reloaded in order to exit function with correct time base. |
<> | 144:ef7eb2e8f9f7 | 159 | |
<> | 144:ef7eb2e8f9f7 | 160 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 161 | * @{ |
<> | 144:ef7eb2e8f9f7 | 162 | */ |
<> | 144:ef7eb2e8f9f7 | 163 | |
<> | 144:ef7eb2e8f9f7 | 164 | /** |
<> | 144:ef7eb2e8f9f7 | 165 | * @brief Initialize the IWDG according to the specified parameters in the |
<> | 144:ef7eb2e8f9f7 | 166 | * IWDG_InitTypeDef and start watchdog. Before exiting function, |
<> | 144:ef7eb2e8f9f7 | 167 | * watchdog is refreshed in order to have correct time base. |
<> | 144:ef7eb2e8f9f7 | 168 | * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 169 | * the configuration information for the specified IWDG module. |
<> | 144:ef7eb2e8f9f7 | 170 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 171 | */ |
<> | 144:ef7eb2e8f9f7 | 172 | HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) |
<> | 144:ef7eb2e8f9f7 | 173 | { |
<> | 144:ef7eb2e8f9f7 | 174 | uint32_t tickstart; |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | /* Check the IWDG handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 177 | if(hiwdg == NULL) |
<> | 144:ef7eb2e8f9f7 | 178 | { |
<> | 144:ef7eb2e8f9f7 | 179 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 180 | } |
<> | 144:ef7eb2e8f9f7 | 181 | |
<> | 144:ef7eb2e8f9f7 | 182 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 183 | assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); |
<> | 144:ef7eb2e8f9f7 | 184 | assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); |
<> | 144:ef7eb2e8f9f7 | 185 | assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); |
<> | 144:ef7eb2e8f9f7 | 186 | assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); |
<> | 144:ef7eb2e8f9f7 | 187 | |
<> | 144:ef7eb2e8f9f7 | 188 | /* Enable IWDG. LSI is turned on automaticaly */ |
<> | 144:ef7eb2e8f9f7 | 189 | __HAL_IWDG_START(hiwdg); |
<> | 144:ef7eb2e8f9f7 | 190 | |
<> | 144:ef7eb2e8f9f7 | 191 | /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing |
<> | 144:ef7eb2e8f9f7 | 192 | 0x5555 in KR */ |
<> | 144:ef7eb2e8f9f7 | 193 | IWDG_ENABLE_WRITE_ACCESS(hiwdg); |
<> | 144:ef7eb2e8f9f7 | 194 | |
<> | 144:ef7eb2e8f9f7 | 195 | /* Write to IWDG registers the Prescaler & Reload values to work with */ |
<> | 144:ef7eb2e8f9f7 | 196 | hiwdg->Instance->PR = hiwdg->Init.Prescaler; |
<> | 144:ef7eb2e8f9f7 | 197 | hiwdg->Instance->RLR = hiwdg->Init.Reload; |
<> | 144:ef7eb2e8f9f7 | 198 | |
<> | 144:ef7eb2e8f9f7 | 199 | /* Check pending flag, if previous update not done, return timeout */ |
<> | 144:ef7eb2e8f9f7 | 200 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 201 | |
<> | 144:ef7eb2e8f9f7 | 202 | /* Wait for register to be updated */ |
<> | 144:ef7eb2e8f9f7 | 203 | while(hiwdg->Instance->SR != RESET) |
<> | 144:ef7eb2e8f9f7 | 204 | { |
<> | 144:ef7eb2e8f9f7 | 205 | if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) |
<> | 144:ef7eb2e8f9f7 | 206 | { |
<> | 144:ef7eb2e8f9f7 | 207 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 208 | } |
<> | 144:ef7eb2e8f9f7 | 209 | } |
<> | 144:ef7eb2e8f9f7 | 210 | |
<> | 144:ef7eb2e8f9f7 | 211 | /* If window parameter is different than current value, modify window |
<> | 144:ef7eb2e8f9f7 | 212 | register */ |
<> | 144:ef7eb2e8f9f7 | 213 | if(hiwdg->Instance->WINR != hiwdg->Init.Window) |
<> | 144:ef7eb2e8f9f7 | 214 | { |
<> | 144:ef7eb2e8f9f7 | 215 | /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, |
<> | 144:ef7eb2e8f9f7 | 216 | even if window feature is disabled, Watchdog will be reloaded by writing |
<> | 144:ef7eb2e8f9f7 | 217 | windows register */ |
<> | 144:ef7eb2e8f9f7 | 218 | hiwdg->Instance->WINR = hiwdg->Init.Window; |
<> | 144:ef7eb2e8f9f7 | 219 | } |
<> | 144:ef7eb2e8f9f7 | 220 | else |
<> | 144:ef7eb2e8f9f7 | 221 | { |
<> | 144:ef7eb2e8f9f7 | 222 | /* Reload IWDG counter with value defined in the reload register */ |
<> | 144:ef7eb2e8f9f7 | 223 | __HAL_IWDG_RELOAD_COUNTER(hiwdg); |
<> | 144:ef7eb2e8f9f7 | 224 | } |
<> | 144:ef7eb2e8f9f7 | 225 | |
<> | 144:ef7eb2e8f9f7 | 226 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 227 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 228 | } |
<> | 144:ef7eb2e8f9f7 | 229 | |
<> | 144:ef7eb2e8f9f7 | 230 | /** |
<> | 144:ef7eb2e8f9f7 | 231 | * @} |
<> | 144:ef7eb2e8f9f7 | 232 | */ |
<> | 144:ef7eb2e8f9f7 | 233 | |
<> | 144:ef7eb2e8f9f7 | 234 | |
<> | 144:ef7eb2e8f9f7 | 235 | /** @addtogroup IWDG_Exported_Functions_Group2 |
<> | 144:ef7eb2e8f9f7 | 236 | * @brief IO operation functions |
<> | 144:ef7eb2e8f9f7 | 237 | * |
<> | 144:ef7eb2e8f9f7 | 238 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 239 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 240 | ##### IO operation functions ##### |
<> | 144:ef7eb2e8f9f7 | 241 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 242 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 243 | (+) Refresh the IWDG. |
<> | 144:ef7eb2e8f9f7 | 244 | |
<> | 144:ef7eb2e8f9f7 | 245 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 246 | * @{ |
<> | 144:ef7eb2e8f9f7 | 247 | */ |
<> | 144:ef7eb2e8f9f7 | 248 | |
<> | 144:ef7eb2e8f9f7 | 249 | |
<> | 144:ef7eb2e8f9f7 | 250 | /** |
<> | 144:ef7eb2e8f9f7 | 251 | * @brief Refresh the IWDG. |
<> | 144:ef7eb2e8f9f7 | 252 | * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 253 | * the configuration information for the specified IWDG module. |
<> | 144:ef7eb2e8f9f7 | 254 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 255 | */ |
<> | 144:ef7eb2e8f9f7 | 256 | HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) |
<> | 144:ef7eb2e8f9f7 | 257 | { |
<> | 144:ef7eb2e8f9f7 | 258 | /* Reload IWDG counter with value defined in the reload register */ |
<> | 144:ef7eb2e8f9f7 | 259 | __HAL_IWDG_RELOAD_COUNTER(hiwdg); |
<> | 144:ef7eb2e8f9f7 | 260 | |
<> | 144:ef7eb2e8f9f7 | 261 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 262 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 263 | } |
<> | 144:ef7eb2e8f9f7 | 264 | |
<> | 144:ef7eb2e8f9f7 | 265 | /** |
<> | 144:ef7eb2e8f9f7 | 266 | * @} |
<> | 144:ef7eb2e8f9f7 | 267 | */ |
<> | 144:ef7eb2e8f9f7 | 268 | |
<> | 144:ef7eb2e8f9f7 | 269 | /** |
<> | 144:ef7eb2e8f9f7 | 270 | * @} |
<> | 144:ef7eb2e8f9f7 | 271 | */ |
<> | 144:ef7eb2e8f9f7 | 272 | |
<> | 144:ef7eb2e8f9f7 | 273 | #endif /* HAL_IWDG_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 274 | /** |
<> | 144:ef7eb2e8f9f7 | 275 | * @} |
<> | 144:ef7eb2e8f9f7 | 276 | */ |
<> | 144:ef7eb2e8f9f7 | 277 | |
<> | 144:ef7eb2e8f9f7 | 278 | /** |
<> | 144:ef7eb2e8f9f7 | 279 | * @} |
<> | 144:ef7eb2e8f9f7 | 280 | */ |
<> | 144:ef7eb2e8f9f7 | 281 | |
<> | 144:ef7eb2e8f9f7 | 282 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |