Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c@181:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
181:96ed750bd169
Parent:
167:e84263d55307 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_gpio.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief GPIO HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the General Purpose Input/Output (GPIO) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### GPIO Peripheral features #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
<> 144:ef7eb2e8f9f7 19 configured by software in several modes:
<> 144:ef7eb2e8f9f7 20 (++) Input mode
<> 144:ef7eb2e8f9f7 21 (++) Analog mode
<> 144:ef7eb2e8f9f7 22 (++) Output mode
<> 144:ef7eb2e8f9f7 23 (++) Alternate function mode
<> 144:ef7eb2e8f9f7 24 (++) External interrupt/event lines
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 (+) During and just after reset, the alternate functions and external interrupt
<> 144:ef7eb2e8f9f7 27 lines are not active and the I/O ports are configured in input floating mode.
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
<> 144:ef7eb2e8f9f7 30 activated or not.
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
<> 144:ef7eb2e8f9f7 33 type and the IO speed can be selected depending on the VDD value.
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
<> 144:ef7eb2e8f9f7 36 multiplexer that allows only one peripheral alternate function (AF) connected
<> 144:ef7eb2e8f9f7 37 to an IO pin at a time. In this way, there can be no conflict between peripherals
<> 144:ef7eb2e8f9f7 38 sharing the same IO pin.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (+) All ports have external interrupt/event capability. To use external interrupt
<> 144:ef7eb2e8f9f7 41 lines, the port must be configured in input mode. All available GPIO pins are
<> 144:ef7eb2e8f9f7 42 connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (+) The external interrupt/event controller consists of up to 39 edge detectors
<> 144:ef7eb2e8f9f7 45 (16 lines are connected to GPIO) for generating event/interrupt requests (each
<> 144:ef7eb2e8f9f7 46 input line can be independently configured to select the type (interrupt or event)
<> 144:ef7eb2e8f9f7 47 and the corresponding trigger event (rising or falling or both). Each line can
<> 144:ef7eb2e8f9f7 48 also be masked independently.
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 51 ==============================================================================
<> 144:ef7eb2e8f9f7 52 [..]
<> 144:ef7eb2e8f9f7 53 (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
<> 144:ef7eb2e8f9f7 56 (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
<> 144:ef7eb2e8f9f7 57 (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
<> 144:ef7eb2e8f9f7 58 structure.
<> 144:ef7eb2e8f9f7 59 (++) In case of Output or alternate function mode selection: the speed is
<> 144:ef7eb2e8f9f7 60 configured through "Speed" member from GPIO_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 61 (++) In alternate mode is selection, the alternate function connected to the IO
<> 144:ef7eb2e8f9f7 62 is configured through "Alternate" member from GPIO_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 63 (++) Analog mode is required when a pin is to be used as ADC channel
<> 144:ef7eb2e8f9f7 64 or DAC output.
<> 144:ef7eb2e8f9f7 65 (++) In case of external interrupt/event selection the "Mode" member from
<> 144:ef7eb2e8f9f7 66 GPIO_InitTypeDef structure select the type (interrupt or event) and
<> 144:ef7eb2e8f9f7 67 the corresponding trigger event (rising or falling or both).
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
<> 144:ef7eb2e8f9f7 70 mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
<> 144:ef7eb2e8f9f7 71 HAL_NVIC_EnableIRQ().
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 (#) To set/reset the level of a pin configured in output mode use
<> 144:ef7eb2e8f9f7 76 HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 (#) During and just after reset, the alternate functions are not
<> 144:ef7eb2e8f9f7 81 active and the GPIO pins are configured in input floating mode (except JTAG
<> 144:ef7eb2e8f9f7 82 pins).
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
<> 144:ef7eb2e8f9f7 85 (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
<> 144:ef7eb2e8f9f7 86 priority over the GPIO function.
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
<> 144:ef7eb2e8f9f7 89 general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
<> 144:ef7eb2e8f9f7 90 The HSE has priority over the GPIO function.
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 @endverbatim
<> 144:ef7eb2e8f9f7 93 ******************************************************************************
<> 144:ef7eb2e8f9f7 94 * @attention
<> 144:ef7eb2e8f9f7 95 *
AnnaBridge 167:e84263d55307 96 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 97 *
<> 144:ef7eb2e8f9f7 98 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 99 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 100 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 101 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 102 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 103 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 104 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 105 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 106 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 107 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 108 *
<> 144:ef7eb2e8f9f7 109 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 110 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 111 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 112 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 113 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 114 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 115 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 116 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 117 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 118 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 119 *
<> 144:ef7eb2e8f9f7 120 ******************************************************************************
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 124 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 127 * @{
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @defgroup GPIO GPIO
<> 144:ef7eb2e8f9f7 131 * @brief GPIO HAL module driver
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 #ifdef HAL_GPIO_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 /* Private defines -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139 /** @defgroup GPIO_Private_Defines GPIO Private Defines
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142 #define GPIO_MODE ((uint32_t)0x00000003)
<> 144:ef7eb2e8f9f7 143 #define ANALOG_MODE ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 144 #define EXTI_MODE ((uint32_t)0x10000000)
<> 144:ef7eb2e8f9f7 145 #define GPIO_MODE_IT ((uint32_t)0x00010000)
<> 144:ef7eb2e8f9f7 146 #define GPIO_MODE_EVT ((uint32_t)0x00020000)
<> 144:ef7eb2e8f9f7 147 #define RISING_EDGE ((uint32_t)0x00100000)
<> 144:ef7eb2e8f9f7 148 #define FALLING_EDGE ((uint32_t)0x00200000)
<> 144:ef7eb2e8f9f7 149 #define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 #define GPIO_NUMBER ((uint32_t)16)
<> 144:ef7eb2e8f9f7 152 /**
<> 144:ef7eb2e8f9f7 153 * @}
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 157 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 158 /** @defgroup GPIO_Private_Macros GPIO Private Macros
<> 144:ef7eb2e8f9f7 159 * @{
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @}
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 165 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 166 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
<> 144:ef7eb2e8f9f7 169 * @{
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 173 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 174 *
<> 144:ef7eb2e8f9f7 175 @verbatim
<> 144:ef7eb2e8f9f7 176 ===============================================================================
<> 144:ef7eb2e8f9f7 177 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 178 ===============================================================================
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 @endverbatim
<> 144:ef7eb2e8f9f7 181 * @{
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /**
<> 144:ef7eb2e8f9f7 185 * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
<> 144:ef7eb2e8f9f7 186 * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
<> 144:ef7eb2e8f9f7 187 * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 188 * the configuration information for the specified GPIO peripheral.
<> 144:ef7eb2e8f9f7 189 * @retval None
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191 void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
<> 144:ef7eb2e8f9f7 192 {
<> 144:ef7eb2e8f9f7 193 uint32_t position = 0x00;
<> 144:ef7eb2e8f9f7 194 uint32_t iocurrent = 0x00;
<> 144:ef7eb2e8f9f7 195 uint32_t temp = 0x00;
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Check the parameters */
<> 144:ef7eb2e8f9f7 198 assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 199 assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
<> 144:ef7eb2e8f9f7 200 assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
<> 144:ef7eb2e8f9f7 201 assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Configure the port pins */
<> 144:ef7eb2e8f9f7 204 while (((GPIO_Init->Pin) >> position) != RESET)
<> 144:ef7eb2e8f9f7 205 {
<> 144:ef7eb2e8f9f7 206 /* Get current io position */
<> 144:ef7eb2e8f9f7 207 iocurrent = (GPIO_Init->Pin) & (1U << position);
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 if(iocurrent)
<> 144:ef7eb2e8f9f7 210 {
<> 144:ef7eb2e8f9f7 211 /*--------------------- GPIO Mode Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 212 /* In case of Alternate function mode selection */
<> 144:ef7eb2e8f9f7 213 if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 /* Check the Alternate function parameters */
<> 144:ef7eb2e8f9f7 216 assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 217 assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /* Configure Alternate function mapped with the current IO */
<> 144:ef7eb2e8f9f7 220 temp = GPIOx->AFR[position >> 3];
<> 144:ef7eb2e8f9f7 221 temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
<> 144:ef7eb2e8f9f7 222 temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
<> 144:ef7eb2e8f9f7 223 GPIOx->AFR[position >> 3] = temp;
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
<> 144:ef7eb2e8f9f7 227 temp = GPIOx->MODER;
<> 144:ef7eb2e8f9f7 228 temp &= ~(GPIO_MODER_MODE0 << (position * 2));
<> 144:ef7eb2e8f9f7 229 temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
<> 144:ef7eb2e8f9f7 230 GPIOx->MODER = temp;
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /* In case of Output or Alternate function mode selection */
<> 144:ef7eb2e8f9f7 233 if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
<> 144:ef7eb2e8f9f7 234 (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 /* Check the Speed parameter */
<> 144:ef7eb2e8f9f7 237 assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
<> 144:ef7eb2e8f9f7 238 /* Configure the IO Speed */
<> 144:ef7eb2e8f9f7 239 temp = GPIOx->OSPEEDR;
<> 144:ef7eb2e8f9f7 240 temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2));
<> 144:ef7eb2e8f9f7 241 temp |= (GPIO_Init->Speed << (position * 2));
<> 144:ef7eb2e8f9f7 242 GPIOx->OSPEEDR = temp;
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* Configure the IO Output Type */
<> 144:ef7eb2e8f9f7 245 temp = GPIOx->OTYPER;
<> 144:ef7eb2e8f9f7 246 temp &= ~(GPIO_OTYPER_OT0 << position) ;
<> 144:ef7eb2e8f9f7 247 temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
<> 144:ef7eb2e8f9f7 248 GPIOx->OTYPER = temp;
<> 144:ef7eb2e8f9f7 249 }
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* In case of Analog mode, check if ADC control mode is selected */
<> 144:ef7eb2e8f9f7 254 if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
<> 144:ef7eb2e8f9f7 255 {
<> 144:ef7eb2e8f9f7 256 /* Configure the IO Output Type */
<> 144:ef7eb2e8f9f7 257 temp = GPIOx->ASCR;
<> 144:ef7eb2e8f9f7 258 temp &= ~(GPIO_ASCR_ASC0 << position) ;
<> 144:ef7eb2e8f9f7 259 temp |= (((GPIO_Init->Mode & ANALOG_MODE) >> 3) << position);
<> 144:ef7eb2e8f9f7 260 GPIOx->ASCR = temp;
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Activate the Pull-up or Pull down resistor for the current IO */
<> 144:ef7eb2e8f9f7 266 temp = GPIOx->PUPDR;
<> 144:ef7eb2e8f9f7 267 temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
<> 144:ef7eb2e8f9f7 268 temp |= ((GPIO_Init->Pull) << (position * 2));
<> 144:ef7eb2e8f9f7 269 GPIOx->PUPDR = temp;
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /*--------------------- EXTI Mode Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 272 /* Configure the External Interrupt or event for the current IO */
<> 144:ef7eb2e8f9f7 273 if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 /* Enable SYSCFG Clock */
<> 144:ef7eb2e8f9f7 276 __HAL_RCC_SYSCFG_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 temp = SYSCFG->EXTICR[position >> 2];
<> 144:ef7eb2e8f9f7 279 temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
<> 144:ef7eb2e8f9f7 280 temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)));
<> 144:ef7eb2e8f9f7 281 SYSCFG->EXTICR[position >> 2] = temp;
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /* Clear EXTI line configuration */
<> 144:ef7eb2e8f9f7 284 temp = EXTI->IMR1;
<> 144:ef7eb2e8f9f7 285 temp &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 286 if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 temp |= iocurrent;
<> 144:ef7eb2e8f9f7 289 }
<> 144:ef7eb2e8f9f7 290 EXTI->IMR1 = temp;
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 temp = EXTI->EMR1;
<> 144:ef7eb2e8f9f7 293 temp &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 294 if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
<> 144:ef7eb2e8f9f7 295 {
<> 144:ef7eb2e8f9f7 296 temp |= iocurrent;
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298 EXTI->EMR1 = temp;
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Clear Rising Falling edge configuration */
<> 144:ef7eb2e8f9f7 301 temp = EXTI->RTSR1;
<> 144:ef7eb2e8f9f7 302 temp &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 303 if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 temp |= iocurrent;
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307 EXTI->RTSR1 = temp;
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 temp = EXTI->FTSR1;
<> 144:ef7eb2e8f9f7 310 temp &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 311 if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
<> 144:ef7eb2e8f9f7 312 {
<> 144:ef7eb2e8f9f7 313 temp |= iocurrent;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 EXTI->FTSR1 = temp;
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 position++;
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @brief De-initialize the GPIOx peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 325 * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
<> 144:ef7eb2e8f9f7 326 * @param GPIO_Pin: specifies the port bit to be written.
<> 144:ef7eb2e8f9f7 327 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 328 * @retval None
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330 void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 331 {
<> 144:ef7eb2e8f9f7 332 uint32_t position = 0x00;
<> 144:ef7eb2e8f9f7 333 uint32_t iocurrent = 0x00;
<> 144:ef7eb2e8f9f7 334 uint32_t tmp = 0x00;
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Check the parameters */
<> 144:ef7eb2e8f9f7 337 assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 338 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Configure the port pins */
<> 144:ef7eb2e8f9f7 341 while ((GPIO_Pin >> position) != RESET)
<> 144:ef7eb2e8f9f7 342 {
<> 144:ef7eb2e8f9f7 343 /* Get current io position */
<> 144:ef7eb2e8f9f7 344 iocurrent = (GPIO_Pin) & (1U << position);
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 if (iocurrent)
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 /*------------------------- GPIO Mode Configuration --------------------*/
<> 144:ef7eb2e8f9f7 349 /* Configure IO in Analog Mode */
<> 144:ef7eb2e8f9f7 350 GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2));
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Configure the default Alternate Function in current IO */
<> 144:ef7eb2e8f9f7 353 GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Configure the default value for IO Speed */
<> 144:ef7eb2e8f9f7 356 GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2));
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Configure the default value IO Output Type */
<> 144:ef7eb2e8f9f7 359 GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /* Deactivate the Pull-up and Pull-down resistor for the current IO */
<> 144:ef7eb2e8f9f7 362 GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Deactivate the Control bit of Analog mode for the current IO */
<> 144:ef7eb2e8f9f7 367 GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position);
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /*------------------------- EXTI Mode Configuration --------------------*/
<> 144:ef7eb2e8f9f7 372 /* Clear the External Interrupt or Event for the current IO */
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 tmp = SYSCFG->EXTICR[position >> 2];
<> 144:ef7eb2e8f9f7 375 tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
<> 144:ef7eb2e8f9f7 376 if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
<> 144:ef7eb2e8f9f7 377 {
<> 144:ef7eb2e8f9f7 378 tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
<> 144:ef7eb2e8f9f7 379 SYSCFG->EXTICR[position >> 2] &= ~tmp;
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /* Clear EXTI line configuration */
<> 144:ef7eb2e8f9f7 382 EXTI->IMR1 &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 383 EXTI->EMR1 &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* Clear Rising Falling edge configuration */
<> 144:ef7eb2e8f9f7 386 EXTI->RTSR1 &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 387 EXTI->FTSR1 &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389 }
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 position++;
<> 144:ef7eb2e8f9f7 392 }
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /**
<> 144:ef7eb2e8f9f7 396 * @}
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 400 * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
<> 144:ef7eb2e8f9f7 401 *
<> 144:ef7eb2e8f9f7 402 @verbatim
<> 144:ef7eb2e8f9f7 403 ===============================================================================
<> 144:ef7eb2e8f9f7 404 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 405 ===============================================================================
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 @endverbatim
<> 144:ef7eb2e8f9f7 408 * @{
<> 144:ef7eb2e8f9f7 409 */
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /**
<> 144:ef7eb2e8f9f7 412 * @brief Read the specified input port pin.
<> 144:ef7eb2e8f9f7 413 * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
<> 144:ef7eb2e8f9f7 414 * @param GPIO_Pin: specifies the port bit to read.
<> 144:ef7eb2e8f9f7 415 * This parameter can be GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 416 * @retval The input port pin value.
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 GPIO_PinState bitstatus;
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Check the parameters */
<> 144:ef7eb2e8f9f7 423 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 bitstatus = GPIO_PIN_SET;
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429 else
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 bitstatus = GPIO_PIN_RESET;
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433 return bitstatus;
<> 144:ef7eb2e8f9f7 434 }
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /**
<> 144:ef7eb2e8f9f7 437 * @brief Set or clear the selected data port bit.
<> 144:ef7eb2e8f9f7 438 *
<> 144:ef7eb2e8f9f7 439 * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
<> 144:ef7eb2e8f9f7 440 * accesses. In this way, there is no risk of an IRQ occurring between
<> 144:ef7eb2e8f9f7 441 * the read and the modify access.
<> 144:ef7eb2e8f9f7 442 *
<> 144:ef7eb2e8f9f7 443 * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
<> 144:ef7eb2e8f9f7 444 * @param GPIO_Pin: specifies the port bit to be written.
<> 144:ef7eb2e8f9f7 445 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 446 * @param PinState: specifies the value to be written to the selected bit.
<> 144:ef7eb2e8f9f7 447 * This parameter can be one of the GPIO_PinState enum values:
<> 144:ef7eb2e8f9f7 448 * @arg GPIO_PIN_RESET: to clear the port pin
<> 144:ef7eb2e8f9f7 449 * @arg GPIO_PIN_SET: to set the port pin
<> 144:ef7eb2e8f9f7 450 * @retval None
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
<> 144:ef7eb2e8f9f7 453 {
<> 144:ef7eb2e8f9f7 454 /* Check the parameters */
<> 144:ef7eb2e8f9f7 455 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 456 assert_param(IS_GPIO_PIN_ACTION(PinState));
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 if(PinState != GPIO_PIN_RESET)
<> 144:ef7eb2e8f9f7 459 {
<> 144:ef7eb2e8f9f7 460 GPIOx->BSRR = (uint32_t)GPIO_Pin;
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462 else
<> 144:ef7eb2e8f9f7 463 {
<> 144:ef7eb2e8f9f7 464 GPIOx->BRR = (uint32_t)GPIO_Pin;
<> 144:ef7eb2e8f9f7 465 }
<> 144:ef7eb2e8f9f7 466 }
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /**
<> 144:ef7eb2e8f9f7 469 * @brief Toggle the specified GPIO pin.
<> 144:ef7eb2e8f9f7 470 * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
<> 144:ef7eb2e8f9f7 471 * @param GPIO_Pin: specifies the pin to be toggled.
<> 144:ef7eb2e8f9f7 472 * @retval None
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 475 {
<> 144:ef7eb2e8f9f7 476 /* Check the parameters */
<> 144:ef7eb2e8f9f7 477 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 GPIOx->ODR ^= GPIO_Pin;
<> 144:ef7eb2e8f9f7 480 }
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /**
<> 144:ef7eb2e8f9f7 483 * @brief Lock GPIO Pins configuration registers.
<> 144:ef7eb2e8f9f7 484 * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
<> 144:ef7eb2e8f9f7 485 * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
<> 144:ef7eb2e8f9f7 486 * @note The configuration of the locked GPIO pins can no longer be modified
<> 144:ef7eb2e8f9f7 487 * until the next reset.
<> 144:ef7eb2e8f9f7 488 * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
<> 144:ef7eb2e8f9f7 489 * @param GPIO_Pin: specifies the port bits to be locked.
<> 144:ef7eb2e8f9f7 490 * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 491 * @retval None
<> 144:ef7eb2e8f9f7 492 */
<> 144:ef7eb2e8f9f7 493 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 494 {
<> 144:ef7eb2e8f9f7 495 __IO uint32_t tmp = GPIO_LCKR_LCKK;
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /* Check the parameters */
<> 144:ef7eb2e8f9f7 498 assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 499 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* Apply lock key write sequence */
<> 144:ef7eb2e8f9f7 502 tmp |= GPIO_Pin;
<> 144:ef7eb2e8f9f7 503 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 504 GPIOx->LCKR = tmp;
<> 144:ef7eb2e8f9f7 505 /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 506 GPIOx->LCKR = GPIO_Pin;
<> 144:ef7eb2e8f9f7 507 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 508 GPIOx->LCKR = tmp;
<> 144:ef7eb2e8f9f7 509 /* Read LCKK bit*/
<> 144:ef7eb2e8f9f7 510 tmp = GPIOx->LCKR;
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
<> 144:ef7eb2e8f9f7 513 {
<> 144:ef7eb2e8f9f7 514 return HAL_OK;
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516 else
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520 }
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /**
<> 144:ef7eb2e8f9f7 523 * @brief Handle EXTI interrupt request.
<> 144:ef7eb2e8f9f7 524 * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
<> 144:ef7eb2e8f9f7 525 * @retval None
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 /* EXTI line interrupt detected */
<> 144:ef7eb2e8f9f7 530 if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
<> 144:ef7eb2e8f9f7 533 HAL_GPIO_EXTI_Callback(GPIO_Pin);
<> 144:ef7eb2e8f9f7 534 }
<> 144:ef7eb2e8f9f7 535 }
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /**
<> 144:ef7eb2e8f9f7 538 * @brief EXTI line detection callback.
<> 144:ef7eb2e8f9f7 539 * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
<> 144:ef7eb2e8f9f7 540 * @retval None
<> 144:ef7eb2e8f9f7 541 */
<> 144:ef7eb2e8f9f7 542 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 543 {
<> 144:ef7eb2e8f9f7 544 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 545 UNUSED(GPIO_Pin);
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 548 the HAL_GPIO_EXTI_Callback could be implemented in the user file
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /**
<> 144:ef7eb2e8f9f7 553 * @}
<> 144:ef7eb2e8f9f7 554 */
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /**
<> 144:ef7eb2e8f9f7 558 * @}
<> 144:ef7eb2e8f9f7 559 */
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 #endif /* HAL_GPIO_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 562 /**
<> 144:ef7eb2e8f9f7 563 * @}
<> 144:ef7eb2e8f9f7 564 */
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /**
<> 144:ef7eb2e8f9f7 567 * @}
<> 144:ef7eb2e8f9f7 568 */
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/