Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c@181:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
181:96ed750bd169
Parent:
167:e84263d55307 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_dac_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief DAC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the extended
<> 144:ef7eb2e8f9f7 9 * functionalities of the DAC peripheral.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 @verbatim
<> 144:ef7eb2e8f9f7 13 ==============================================================================
<> 144:ef7eb2e8f9f7 14 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 [..]
<> 144:ef7eb2e8f9f7 17 (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
<> 144:ef7eb2e8f9f7 18 Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
<> 144:ef7eb2e8f9f7 19 HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
<> 144:ef7eb2e8f9f7 20 (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
<> 144:ef7eb2e8f9f7 21 (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
<> 144:ef7eb2e8f9f7 24 (+) HAL_DACEx_SetUserTrimming to set user trimming value.
<> 144:ef7eb2e8f9f7 25 (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
<> 144:ef7eb2e8f9f7 26 after reset, user setting if HAL_DACEx_SetUserTrimming have been used
<> 144:ef7eb2e8f9f7 27 at least one time after reset).
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 @endverbatim
<> 144:ef7eb2e8f9f7 30 ******************************************************************************
<> 144:ef7eb2e8f9f7 31 * @attention
<> 144:ef7eb2e8f9f7 32 *
AnnaBridge 167:e84263d55307 33 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 36 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 37 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 38 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 39 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 40 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 41 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 42 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 43 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 44 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 45 *
<> 144:ef7eb2e8f9f7 46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 47 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 49 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 52 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 53 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 54 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 55 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 56 *
<> 144:ef7eb2e8f9f7 57 ******************************************************************************
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 62 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 65 * @{
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /** @defgroup DACEx DACEx
<> 144:ef7eb2e8f9f7 69 * @brief DAC Extended HAL module driver
<> 144:ef7eb2e8f9f7 70 * @{
<> 144:ef7eb2e8f9f7 71 */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 #ifdef HAL_DAC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 76 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 77 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 78 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 79 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 80 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 87 * @brief Extended IO operation functions
<> 144:ef7eb2e8f9f7 88 *
<> 144:ef7eb2e8f9f7 89 @verbatim
<> 144:ef7eb2e8f9f7 90 ==============================================================================
<> 144:ef7eb2e8f9f7 91 ##### Extended features functions #####
<> 144:ef7eb2e8f9f7 92 ==============================================================================
<> 144:ef7eb2e8f9f7 93 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 94 (+) Start conversion.
<> 144:ef7eb2e8f9f7 95 (+) Stop conversion.
<> 144:ef7eb2e8f9f7 96 (+) Start conversion and enable DMA transfer.
<> 144:ef7eb2e8f9f7 97 (+) Stop conversion and disable DMA transfer.
<> 144:ef7eb2e8f9f7 98 (+) Get result of conversion.
<> 144:ef7eb2e8f9f7 99 (+) Get result of dual mode conversion.
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 @endverbatim
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /**
<> 144:ef7eb2e8f9f7 106 * @brief Enable or disable the selected DAC channel wave generation.
<> 144:ef7eb2e8f9f7 107 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 108 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 109 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 110 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 111 * DAC_CHANNEL_1 / DAC_CHANNEL_2
<> 144:ef7eb2e8f9f7 112 * @param Amplitude: Select max triangle amplitude.
<> 144:ef7eb2e8f9f7 113 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 114 * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
<> 144:ef7eb2e8f9f7 115 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
<> 144:ef7eb2e8f9f7 116 * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
<> 144:ef7eb2e8f9f7 117 * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
<> 144:ef7eb2e8f9f7 118 * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
<> 144:ef7eb2e8f9f7 119 * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
<> 144:ef7eb2e8f9f7 120 * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
<> 144:ef7eb2e8f9f7 121 * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
<> 144:ef7eb2e8f9f7 122 * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
<> 144:ef7eb2e8f9f7 123 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
<> 144:ef7eb2e8f9f7 124 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
<> 144:ef7eb2e8f9f7 125 * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
<> 144:ef7eb2e8f9f7 126 * @retval HAL status
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
<> 144:ef7eb2e8f9f7 129 {
<> 144:ef7eb2e8f9f7 130 /* Check the parameters */
<> 144:ef7eb2e8f9f7 131 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 132 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /* Process locked */
<> 144:ef7eb2e8f9f7 135 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* Change DAC state */
<> 144:ef7eb2e8f9f7 138 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /* Enable the triangle wave generation for the selected DAC channel */
<> 144:ef7eb2e8f9f7 141 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /* Change DAC state */
<> 144:ef7eb2e8f9f7 144 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /* Process unlocked */
<> 144:ef7eb2e8f9f7 147 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /* Return function status */
<> 144:ef7eb2e8f9f7 150 return HAL_OK;
<> 144:ef7eb2e8f9f7 151 }
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @brief Enable or disable the selected DAC channel wave generation.
<> 144:ef7eb2e8f9f7 155 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 156 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 157 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 158 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 159 * DAC_CHANNEL_1 / DAC_CHANNEL_2
<> 144:ef7eb2e8f9f7 160 * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
<> 144:ef7eb2e8f9f7 161 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 162 * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
<> 144:ef7eb2e8f9f7 163 * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
<> 144:ef7eb2e8f9f7 164 * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
<> 144:ef7eb2e8f9f7 165 * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
<> 144:ef7eb2e8f9f7 166 * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
<> 144:ef7eb2e8f9f7 167 * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
<> 144:ef7eb2e8f9f7 168 * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
<> 144:ef7eb2e8f9f7 169 * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
<> 144:ef7eb2e8f9f7 170 * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
<> 144:ef7eb2e8f9f7 171 * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
<> 144:ef7eb2e8f9f7 172 * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
<> 144:ef7eb2e8f9f7 173 * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
<> 144:ef7eb2e8f9f7 174 * @retval HAL status
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
<> 144:ef7eb2e8f9f7 177 {
<> 144:ef7eb2e8f9f7 178 /* Check the parameters */
<> 144:ef7eb2e8f9f7 179 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 180 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Process locked */
<> 144:ef7eb2e8f9f7 183 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Change DAC state */
<> 144:ef7eb2e8f9f7 186 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Enable the noise wave generation for the selected DAC channel */
<> 144:ef7eb2e8f9f7 189 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Change DAC state */
<> 144:ef7eb2e8f9f7 192 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Process unlocked */
<> 144:ef7eb2e8f9f7 195 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Return function status */
<> 144:ef7eb2e8f9f7 198 return HAL_OK;
<> 144:ef7eb2e8f9f7 199 }
<> 144:ef7eb2e8f9f7 200
AnnaBridge 167:e84263d55307 201 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
AnnaBridge 167:e84263d55307 202 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /**
<> 144:ef7eb2e8f9f7 205 * @brief Set the specified data holding register value for dual DAC channel.
<> 144:ef7eb2e8f9f7 206 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 207 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 208 * @param Alignment: Specifies the data alignment for dual channel DAC.
<> 144:ef7eb2e8f9f7 209 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 210 * DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 211 * DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 212 * DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 213 * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 214 * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 215 * @note In dual mode, a unique register access is required to write in both
<> 144:ef7eb2e8f9f7 216 * DAC channels at the same time.
<> 144:ef7eb2e8f9f7 217 * @retval HAL status
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 uint32_t data = 0, tmp = 0;
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Check the parameters */
<> 144:ef7eb2e8f9f7 224 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 225 assert_param(IS_DAC_DATA(Data1));
<> 144:ef7eb2e8f9f7 226 assert_param(IS_DAC_DATA(Data2));
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Calculate and set dual DAC data holding register value */
<> 144:ef7eb2e8f9f7 229 if (Alignment == DAC_ALIGN_8B_R)
<> 144:ef7eb2e8f9f7 230 {
<> 144:ef7eb2e8f9f7 231 data = ((uint32_t)Data2 << 8) | Data1;
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233 else
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 data = ((uint32_t)Data2 << 16) | Data1;
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 239 tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /* Set the dual DAC selected data holding register */
<> 144:ef7eb2e8f9f7 242 *(__IO uint32_t *)tmp = data;
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* Return function status */
<> 144:ef7eb2e8f9f7 245 return HAL_OK;
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /**
<> 144:ef7eb2e8f9f7 249 * @brief Conversion complete callback in non-blocking mode for Channel2.
<> 144:ef7eb2e8f9f7 250 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 251 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 252 * @retval None
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 255 {
<> 144:ef7eb2e8f9f7 256 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 257 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 260 the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
<> 144:ef7eb2e8f9f7 266 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 267 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 268 * @retval None
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 271 {
<> 144:ef7eb2e8f9f7 272 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 273 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 276 the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /**
<> 144:ef7eb2e8f9f7 281 * @brief Error DAC callback for Channel2.
<> 144:ef7eb2e8f9f7 282 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 283 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 284 * @retval None
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 289 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 292 the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @brief DMA underrun DAC callback for Channel2.
<> 144:ef7eb2e8f9f7 298 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 299 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 300 * @retval None
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 305 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 308 the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 }
AnnaBridge 167:e84263d55307 311 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
AnnaBridge 167:e84263d55307 312 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @brief Run the self calibration of one DAC channel.
<> 144:ef7eb2e8f9f7 316 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 317 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 318 * @param sConfig: DAC channel configuration structure.
<> 144:ef7eb2e8f9f7 319 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 320 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 321 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 322 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 323 * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
<> 144:ef7eb2e8f9f7 324 * @retval HAL status
<> 144:ef7eb2e8f9f7 325 * @note Calibration runs about 7 ms.
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 __IO uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 333 uint32_t trimmingvalue = 0;
<> 144:ef7eb2e8f9f7 334 uint32_t delta;
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* store/restore channel configuration structure purpose */
<> 144:ef7eb2e8f9f7 337 uint32_t oldmodeconfiguration = 0;
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Check the parameters */
<> 144:ef7eb2e8f9f7 340 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Check the DAC handle allocation */
<> 144:ef7eb2e8f9f7 343 /* Check if DAC running */
<> 144:ef7eb2e8f9f7 344 if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_BUSY))
<> 144:ef7eb2e8f9f7 345 {
<> 144:ef7eb2e8f9f7 346 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 347 }
<> 144:ef7eb2e8f9f7 348 else
<> 144:ef7eb2e8f9f7 349 {
AnnaBridge 167:e84263d55307 350 /* Process locked */
AnnaBridge 167:e84263d55307 351 __HAL_LOCK(hdac);
AnnaBridge 167:e84263d55307 352
AnnaBridge 167:e84263d55307 353 /* Store configuration */
AnnaBridge 167:e84263d55307 354 oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << Channel));
AnnaBridge 167:e84263d55307 355
AnnaBridge 167:e84263d55307 356 /* Disable the selected DAC channel */
AnnaBridge 167:e84263d55307 357 CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_EN1 << Channel));
AnnaBridge 167:e84263d55307 358
AnnaBridge 167:e84263d55307 359 /* Set mode in MCR for calibration */
AnnaBridge 167:e84263d55307 360 MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), 0);
AnnaBridge 167:e84263d55307 361
AnnaBridge 167:e84263d55307 362 /* Set DAC Channel1 DHR register to the middle value */
AnnaBridge 167:e84263d55307 363 tmp = (uint32_t)hdac->Instance;
AnnaBridge 167:e84263d55307 364
AnnaBridge 167:e84263d55307 365 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
AnnaBridge 167:e84263d55307 366 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 367 if(Channel == DAC_CHANNEL_1)
AnnaBridge 167:e84263d55307 368 {
AnnaBridge 167:e84263d55307 369 tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
AnnaBridge 167:e84263d55307 370 }
AnnaBridge 167:e84263d55307 371 else
<> 144:ef7eb2e8f9f7 372 {
AnnaBridge 167:e84263d55307 373 tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
AnnaBridge 167:e84263d55307 374 }
AnnaBridge 167:e84263d55307 375 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
AnnaBridge 167:e84263d55307 376 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
AnnaBridge 167:e84263d55307 377 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
AnnaBridge 167:e84263d55307 378 tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
AnnaBridge 167:e84263d55307 379 #endif /* STM32L451xx STM32L452xx STM32L462xx */
AnnaBridge 167:e84263d55307 380 *(__IO uint32_t *) tmp = 0x0800;
AnnaBridge 167:e84263d55307 381
AnnaBridge 167:e84263d55307 382 /* Enable the selected DAC channel calibration */
AnnaBridge 167:e84263d55307 383 /* i.e. set DAC_CR_CENx bit */
AnnaBridge 167:e84263d55307 384 SET_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
AnnaBridge 167:e84263d55307 385
AnnaBridge 167:e84263d55307 386 /* Init trimming counter */
AnnaBridge 167:e84263d55307 387 /* Medium value */
AnnaBridge 167:e84263d55307 388 trimmingvalue = 16;
AnnaBridge 167:e84263d55307 389 delta = 8;
AnnaBridge 167:e84263d55307 390 while (delta != 0)
AnnaBridge 167:e84263d55307 391 {
AnnaBridge 167:e84263d55307 392 /* Set candidate trimming */
AnnaBridge 167:e84263d55307 393 MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
AnnaBridge 167:e84263d55307 394
AnnaBridge 167:e84263d55307 395 /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
AnnaBridge 167:e84263d55307 396 /* i.e. minimum time needed between two calibration steps */
AnnaBridge 167:e84263d55307 397 HAL_Delay(1);
AnnaBridge 167:e84263d55307 398
AnnaBridge 167:e84263d55307 399 if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == (DAC_SR_CAL_FLAG1<<Channel))
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
AnnaBridge 167:e84263d55307 402 trimmingvalue -= delta;
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404 else
<> 144:ef7eb2e8f9f7 405 {
<> 144:ef7eb2e8f9f7 406 /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
AnnaBridge 167:e84263d55307 407 trimmingvalue += delta;
AnnaBridge 167:e84263d55307 408 }
AnnaBridge 167:e84263d55307 409 delta >>= 1;
<> 144:ef7eb2e8f9f7 410 }
AnnaBridge 167:e84263d55307 411
<> 144:ef7eb2e8f9f7 412 /* Still need to check if right calibration is current value or one step below */
<> 144:ef7eb2e8f9f7 413 /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */
<> 144:ef7eb2e8f9f7 414 /* Set candidate trimming */
<> 144:ef7eb2e8f9f7 415 MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
AnnaBridge 167:e84263d55307 416
<> 144:ef7eb2e8f9f7 417 /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
<> 144:ef7eb2e8f9f7 418 /* i.e. minimum time needed between two calibration steps */
<> 144:ef7eb2e8f9f7 419 HAL_Delay(1);
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == RESET)
AnnaBridge 167:e84263d55307 422 {
<> 144:ef7eb2e8f9f7 423 /* OPAMP_CSR_OUTCAL is actually one value more */
<> 144:ef7eb2e8f9f7 424 trimmingvalue++;
<> 144:ef7eb2e8f9f7 425 /* Set right trimming */
AnnaBridge 167:e84263d55307 426 MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
AnnaBridge 167:e84263d55307 427 }
AnnaBridge 167:e84263d55307 428
AnnaBridge 167:e84263d55307 429 /* Disable the selected DAC channel calibration */
AnnaBridge 167:e84263d55307 430 /* i.e. clear DAC_CR_CENx bit */
AnnaBridge 167:e84263d55307 431 CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
<> 144:ef7eb2e8f9f7 432
AnnaBridge 167:e84263d55307 433 sConfig->DAC_TrimmingValue = trimmingvalue;
AnnaBridge 167:e84263d55307 434 sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
AnnaBridge 167:e84263d55307 435
AnnaBridge 167:e84263d55307 436 /* Restore configuration */
AnnaBridge 167:e84263d55307 437 MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), oldmodeconfiguration);
AnnaBridge 167:e84263d55307 438
AnnaBridge 167:e84263d55307 439 /* Process unlocked */
AnnaBridge 167:e84263d55307 440 __HAL_UNLOCK(hdac);
AnnaBridge 167:e84263d55307 441 }
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 return status;
<> 144:ef7eb2e8f9f7 444 }
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /**
<> 144:ef7eb2e8f9f7 447 * @brief Set the trimming mode and trimming value (user trimming mode applied).
<> 144:ef7eb2e8f9f7 448 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 449 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 450 * @param sConfig: DAC configuration structure updated with new DAC trimming value.
<> 144:ef7eb2e8f9f7 451 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 452 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 453 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 454 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 455 * @param NewTrimmingValue: DAC new trimming value
<> 144:ef7eb2e8f9f7 456 * @retval HAL status
<> 144:ef7eb2e8f9f7 457 */
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Check the parameters */
<> 144:ef7eb2e8f9f7 464 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 465 assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /* Check the DAC handle allocation */
<> 144:ef7eb2e8f9f7 468 if(hdac == NULL)
<> 144:ef7eb2e8f9f7 469 {
<> 144:ef7eb2e8f9f7 470 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 471 }
AnnaBridge 167:e84263d55307 472 else
AnnaBridge 167:e84263d55307 473 {
AnnaBridge 167:e84263d55307 474 /* Process locked */
AnnaBridge 167:e84263d55307 475 __HAL_LOCK(hdac);
AnnaBridge 167:e84263d55307 476
AnnaBridge 167:e84263d55307 477 /* Set new trimming */
AnnaBridge 167:e84263d55307 478 MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (NewTrimmingValue<<Channel));
<> 144:ef7eb2e8f9f7 479
AnnaBridge 167:e84263d55307 480 /* Update trimming mode */
AnnaBridge 167:e84263d55307 481 sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
AnnaBridge 167:e84263d55307 482 sConfig->DAC_TrimmingValue = NewTrimmingValue;
AnnaBridge 167:e84263d55307 483
AnnaBridge 167:e84263d55307 484 /* Process unlocked */
AnnaBridge 167:e84263d55307 485 __HAL_UNLOCK(hdac);
AnnaBridge 167:e84263d55307 486 }
<> 144:ef7eb2e8f9f7 487 return status;
<> 144:ef7eb2e8f9f7 488 }
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /**
<> 144:ef7eb2e8f9f7 491 * @brief Return the DAC trimming value.
<> 144:ef7eb2e8f9f7 492 * @param hdac : DAC handle
<> 144:ef7eb2e8f9f7 493 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 494 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 495 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 496 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 497 * @retval Trimming value : range: 0->31
<> 144:ef7eb2e8f9f7 498 *
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 uint32_t trimmingvalue = 0;
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Check the DAC handle allocation */
<> 144:ef7eb2e8f9f7 506 /* And not in Reset state */
<> 144:ef7eb2e8f9f7 507 if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_RESET))
<> 144:ef7eb2e8f9f7 508 {
<> 144:ef7eb2e8f9f7 509 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511 else
<> 144:ef7eb2e8f9f7 512 {
<> 144:ef7eb2e8f9f7 513 /* Check the parameter */
<> 144:ef7eb2e8f9f7 514 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /* Retrieve trimming */
<> 144:ef7eb2e8f9f7 517 trimmingvalue = ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << Channel)) >> Channel);
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 return trimmingvalue;
<> 144:ef7eb2e8f9f7 520 }
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /**
<> 144:ef7eb2e8f9f7 523 * @}
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525
AnnaBridge 167:e84263d55307 526 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
AnnaBridge 167:e84263d55307 527 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 528
<> 144:ef7eb2e8f9f7 529 /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 530 * @brief Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 531 *
<> 144:ef7eb2e8f9f7 532 @verbatim
<> 144:ef7eb2e8f9f7 533 ==============================================================================
<> 144:ef7eb2e8f9f7 534 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 535 ==============================================================================
<> 144:ef7eb2e8f9f7 536 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 537 (+) Configure channels.
<> 144:ef7eb2e8f9f7 538 (+) Set the specified data holding register value for DAC channel.
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 @endverbatim
<> 144:ef7eb2e8f9f7 541 * @{
<> 144:ef7eb2e8f9f7 542 */
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /**
<> 144:ef7eb2e8f9f7 545 * @brief Return the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 546 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 547 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 548 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 551 {
<> 144:ef7eb2e8f9f7 552 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 tmp |= hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 tmp |= hdac->Instance->DOR2 << 16;
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 559 return tmp;
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /**
<> 144:ef7eb2e8f9f7 563 * @}
<> 144:ef7eb2e8f9f7 564 */
<> 144:ef7eb2e8f9f7 565
AnnaBridge 167:e84263d55307 566 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
AnnaBridge 167:e84263d55307 567 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
AnnaBridge 167:e84263d55307 568
<> 144:ef7eb2e8f9f7 569 /**
<> 144:ef7eb2e8f9f7 570 * @}
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572
AnnaBridge 167:e84263d55307 573 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
AnnaBridge 167:e84263d55307 574 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 575
<> 144:ef7eb2e8f9f7 576 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 577 /** @defgroup DACEx_Private_Functions DACEx private functions
<> 144:ef7eb2e8f9f7 578 * @brief Extended private functions
<> 144:ef7eb2e8f9f7 579 * @{
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /**
<> 144:ef7eb2e8f9f7 583 * @brief DMA conversion complete callback.
<> 144:ef7eb2e8f9f7 584 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 585 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 586 * @retval None
<> 144:ef7eb2e8f9f7 587 */
<> 144:ef7eb2e8f9f7 588 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 589 {
<> 144:ef7eb2e8f9f7 590 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 HAL_DACEx_ConvCpltCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /**
<> 144:ef7eb2e8f9f7 598 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 599 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 600 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 601 * @retval None
<> 144:ef7eb2e8f9f7 602 */
<> 144:ef7eb2e8f9f7 603 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 604 {
<> 144:ef7eb2e8f9f7 605 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 606 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 607 HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 608 }
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /**
<> 144:ef7eb2e8f9f7 611 * @brief DMA error callback.
<> 144:ef7eb2e8f9f7 612 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 613 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 614 * @retval None
<> 144:ef7eb2e8f9f7 615 */
<> 144:ef7eb2e8f9f7 616 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 617 {
<> 144:ef7eb2e8f9f7 618 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 621 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 HAL_DACEx_ErrorCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /**
<> 144:ef7eb2e8f9f7 629 * @}
<> 144:ef7eb2e8f9f7 630 */
AnnaBridge 167:e84263d55307 631 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
AnnaBridge 167:e84263d55307 632 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 #endif /* HAL_DAC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /**
<> 144:ef7eb2e8f9f7 637 * @}
<> 144:ef7eb2e8f9f7 638 */
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /**
<> 144:ef7eb2e8f9f7 641 * @}
<> 144:ef7eb2e8f9f7 642 */
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/