Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c@181:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
181:96ed750bd169
Parent:
167:e84263d55307 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_dac.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief DAC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Digital to Analog Converter (DAC) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 @verbatim
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 ##### DAC Peripheral features #####
<> 144:ef7eb2e8f9f7 19 ==============================================================================
<> 144:ef7eb2e8f9f7 20 [..]
<> 144:ef7eb2e8f9f7 21 *** DAC Channels ***
<> 144:ef7eb2e8f9f7 22 ====================
<> 144:ef7eb2e8f9f7 23 [..]
AnnaBridge 167:e84263d55307 24 STM32L4 devices integrate one or two 12-bit Digital Analog Converters
AnnaBridge 167:e84263d55307 25 (i.e. one or 2 channel(s))
AnnaBridge 167:e84263d55307 26 1 channel : STM32L451xx STM32L452xx STM32L462xx
AnnaBridge 167:e84263d55307 27 2 channels: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx
AnnaBridge 167:e84263d55307 28 STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx
<> 144:ef7eb2e8f9f7 29
AnnaBridge 167:e84263d55307 30 When 2 channels are available, the 2 converters (i.e. channel1 & channel2)
<> 144:ef7eb2e8f9f7 31 can be used independently or simultaneously (dual mode):
<> 144:ef7eb2e8f9f7 32 (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
<> 144:ef7eb2e8f9f7 33 peripherals (ex. OPAMPs, comparators).
AnnaBridge 167:e84263d55307 34 (#) Whenever present, DAC channel2 with DAC_OUT2 (PA5) as output
AnnaBridge 167:e84263d55307 35 or connected to on-chip peripherals (ex. OPAMPs, comparators).
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 *** DAC Triggers ***
<> 144:ef7eb2e8f9f7 38 ====================
<> 144:ef7eb2e8f9f7 39 [..]
<> 144:ef7eb2e8f9f7 40 Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
<> 144:ef7eb2e8f9f7 41 and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
<> 144:ef7eb2e8f9f7 42 [..]
<> 144:ef7eb2e8f9f7 43 Digital to Analog conversion can be triggered by:
<> 144:ef7eb2e8f9f7 44 (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
<> 144:ef7eb2e8f9f7 45 The used pin (GPIOx_PIN_9) must be configured in input mode.
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7
<> 144:ef7eb2e8f9f7 48 (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...)
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 (#) Software using DAC_TRIGGER_SOFTWARE
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 *** DAC Buffer mode feature ***
<> 144:ef7eb2e8f9f7 53 ===============================
<> 144:ef7eb2e8f9f7 54 [..]
<> 144:ef7eb2e8f9f7 55 Each DAC channel integrates an output buffer that can be used to
<> 144:ef7eb2e8f9f7 56 reduce the output impedance, and to drive external loads directly
<> 144:ef7eb2e8f9f7 57 without having to add an external operational amplifier.
<> 144:ef7eb2e8f9f7 58 To enable, the output buffer use
<> 144:ef7eb2e8f9f7 59 sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
<> 144:ef7eb2e8f9f7 60 [..]
<> 144:ef7eb2e8f9f7 61 (@) Refer to the device datasheet for more details about output
<> 144:ef7eb2e8f9f7 62 impedance value with and without output buffer.
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 *** DAC connect feature ***
<> 144:ef7eb2e8f9f7 65 ===============================
<> 144:ef7eb2e8f9f7 66 [..]
<> 144:ef7eb2e8f9f7 67 Each DAC channel can be connected internally.
<> 144:ef7eb2e8f9f7 68 To connect, use
<> 144:ef7eb2e8f9f7 69 sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 *** GPIO configurations guidelines ***
<> 144:ef7eb2e8f9f7 72 =====================
<> 144:ef7eb2e8f9f7 73 [..]
<> 144:ef7eb2e8f9f7 74 When a DAC channel is used (ex channel1 on PA4) and the other is not
<> 144:ef7eb2e8f9f7 75 (ex channel2 on PA5 is configured in Analog and disabled).
<> 144:ef7eb2e8f9f7 76 Channel1 may disturb channel2 as coupling effect.
<> 144:ef7eb2e8f9f7 77 Note that there is no coupling on channel2 as soon as channel2 is turned on.
<> 144:ef7eb2e8f9f7 78 Coupling on adjacent channel could be avoided as follows:
<> 144:ef7eb2e8f9f7 79 when unused PA5 is configured as INPUT PULL-UP or DOWN.
<> 144:ef7eb2e8f9f7 80 PA5 is configured in ANALOG just before it is turned on.
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 *** DAC Sample and Hold feature ***
<> 144:ef7eb2e8f9f7 83 ========================
<> 144:ef7eb2e8f9f7 84 [..]
<> 144:ef7eb2e8f9f7 85 For each converter, 2 modes are supported: normal mode and
<> 144:ef7eb2e8f9f7 86 "sample and hold" mode (i.e. low power mode).
<> 144:ef7eb2e8f9f7 87 In the sample and hold mode, the DAC core converts data, then holds the
<> 144:ef7eb2e8f9f7 88 converted voltage on a capacitor. When not converting, the DAC cores and
AnnaBridge 167:e84263d55307 89 buffer are completely turned off between samples and the DAC output is
<> 144:ef7eb2e8f9f7 90 tri-stated, therefore reducing the overall power consumption. A new
<> 144:ef7eb2e8f9f7 91 stabilization period is needed before each new conversion.
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 The sample and hold allow setting internal or external voltage @
<> 144:ef7eb2e8f9f7 94 low power consumption cost (output value can be at any given rate either
<> 144:ef7eb2e8f9f7 95 by CPU or DMA).
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 The Sample and hold block and registers uses either LSI & run in
<> 144:ef7eb2e8f9f7 98 several power modes: run mode, sleep mode, low power run, low power sleep
<> 144:ef7eb2e8f9f7 99 mode & stop1 mode.
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 Low power stop1 mode allows only static conversion.
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 To enable Sample and Hold mode
<> 144:ef7eb2e8f9f7 104 Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
<> 144:ef7eb2e8f9f7 105 RCC_LSI_ON parameters.
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
<> 144:ef7eb2e8f9f7 108 & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
<> 144:ef7eb2e8f9f7 109 DAC_HoldTime & DAC_RefreshTime;
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 *** DAC calibration feature ***
<> 144:ef7eb2e8f9f7 114 ===================================
<> 144:ef7eb2e8f9f7 115 [..]
<> 144:ef7eb2e8f9f7 116 (#) The 2 converters (channel1 & channel2) provide calibration capabilities.
<> 144:ef7eb2e8f9f7 117 (++) Calibration aims at correcting some offset of output buffer.
<> 144:ef7eb2e8f9f7 118 (++) The DAC uses either factory calibration settings OR user defined
<> 144:ef7eb2e8f9f7 119 calibration (trimming) settings (i.e. trimming mode).
<> 144:ef7eb2e8f9f7 120 (++) The user defined settings can be figured out using self calibration
<> 144:ef7eb2e8f9f7 121 handled by HAL_DACEx_SelfCalibrate.
<> 144:ef7eb2e8f9f7 122 (++) HAL_DACEx_SelfCalibrate:
<> 144:ef7eb2e8f9f7 123 (+++) Runs automatically the calibration.
<> 144:ef7eb2e8f9f7 124 (+++) Enables the user trimming mode
<> 144:ef7eb2e8f9f7 125 (+++) Updates a structure with trimming values with fresh calibration
<> 144:ef7eb2e8f9f7 126 results.
<> 144:ef7eb2e8f9f7 127 The user may store the calibration results for larger
<> 144:ef7eb2e8f9f7 128 (ex monitoring the trimming as a function of temperature
<> 144:ef7eb2e8f9f7 129 for instance)
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 *** DAC wave generation feature ***
<> 144:ef7eb2e8f9f7 132 ===================================
<> 144:ef7eb2e8f9f7 133 [..]
<> 144:ef7eb2e8f9f7 134 Both DAC channels can be used to generate
<> 144:ef7eb2e8f9f7 135 (#) Noise wave
<> 144:ef7eb2e8f9f7 136 (#) Triangle wave
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 *** DAC data format ***
<> 144:ef7eb2e8f9f7 139 =======================
<> 144:ef7eb2e8f9f7 140 [..]
<> 144:ef7eb2e8f9f7 141 The DAC data format can be:
<> 144:ef7eb2e8f9f7 142 (#) 8-bit right alignment using DAC_ALIGN_8B_R
<> 144:ef7eb2e8f9f7 143 (#) 12-bit left alignment using DAC_ALIGN_12B_L
<> 144:ef7eb2e8f9f7 144 (#) 12-bit right alignment using DAC_ALIGN_12B_R
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 *** DAC data value to voltage correspondence ***
<> 144:ef7eb2e8f9f7 147 ================================================
<> 144:ef7eb2e8f9f7 148 [..]
<> 144:ef7eb2e8f9f7 149 The analog output voltage on each DAC channel pin is determined
<> 144:ef7eb2e8f9f7 150 by the following equation:
<> 144:ef7eb2e8f9f7 151 [..]
<> 144:ef7eb2e8f9f7 152 DAC_OUTx = VREF+ * DOR / 4095
<> 144:ef7eb2e8f9f7 153 (+) with DOR is the Data Output Register
<> 144:ef7eb2e8f9f7 154 [..]
<> 144:ef7eb2e8f9f7 155 VEF+ is the input voltage reference (refer to the device datasheet)
<> 144:ef7eb2e8f9f7 156 [..]
<> 144:ef7eb2e8f9f7 157 e.g. To set DAC_OUT1 to 0.7V, use
<> 144:ef7eb2e8f9f7 158 (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 *** DMA requests ***
<> 144:ef7eb2e8f9f7 161 =====================
<> 144:ef7eb2e8f9f7 162 [..]
<> 144:ef7eb2e8f9f7 163 A DMA1 request can be generated when an external trigger (but not a software trigger)
<> 144:ef7eb2e8f9f7 164 occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
<> 144:ef7eb2e8f9f7 165 DMA requests are mapped as following:
<> 144:ef7eb2e8f9f7 166 (#) DAC channel1: mapped either on
<> 144:ef7eb2e8f9f7 167 (++) DMA1 request 6 channel3
<> 144:ef7eb2e8f9f7 168 (++) or DMA2 request channel4 which must be already configured
AnnaBridge 167:e84263d55307 169 (#) DAC channel2 (whenever present): mapped either on
<> 144:ef7eb2e8f9f7 170 (++) DMA1 request 5 channel4
<> 144:ef7eb2e8f9f7 171 (++) or DMA2 request 3 channel5 which must be already configured
<> 144:ef7eb2e8f9f7 172 [..]
<> 144:ef7eb2e8f9f7 173 (@) For Dual mode and specific signal (Triangle and noise) generation please
<> 144:ef7eb2e8f9f7 174 refer to Extended Features Driver description
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 177 ==============================================================================
<> 144:ef7eb2e8f9f7 178 [..]
<> 144:ef7eb2e8f9f7 179 (+) DAC APB clock must be enabled to get write access to DAC
<> 144:ef7eb2e8f9f7 180 registers using HAL_DAC_Init()
<> 144:ef7eb2e8f9f7 181 (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
<> 144:ef7eb2e8f9f7 182 (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
<> 144:ef7eb2e8f9f7 183 (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 *** Calibration mode IO operation ***
<> 144:ef7eb2e8f9f7 186 ======================================
<> 144:ef7eb2e8f9f7 187 [..]
<> 144:ef7eb2e8f9f7 188 (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
<> 144:ef7eb2e8f9f7 189 (+) Run the calibration using HAL_DACEx_SelfCalibrate()
<> 144:ef7eb2e8f9f7 190 (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 193 =================================
<> 144:ef7eb2e8f9f7 194 [..]
<> 144:ef7eb2e8f9f7 195 (+) Start the DAC peripheral using HAL_DAC_Start()
<> 144:ef7eb2e8f9f7 196 (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
<> 144:ef7eb2e8f9f7 197 (+) Stop the DAC peripheral using HAL_DAC_Stop()
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 200 ==============================
<> 144:ef7eb2e8f9f7 201 [..]
<> 144:ef7eb2e8f9f7 202 (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
<> 144:ef7eb2e8f9f7 203 of data to be transferred at each end of conversion
<> 144:ef7eb2e8f9f7 204 (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
<> 144:ef7eb2e8f9f7 205 function is executed and user can add his own code by customization of function pointer
<> 144:ef7eb2e8f9f7 206 HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
<> 144:ef7eb2e8f9f7 207 (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
<> 144:ef7eb2e8f9f7 208 function is executed and user can add his own code by customization of function pointer
<> 144:ef7eb2e8f9f7 209 HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
<> 144:ef7eb2e8f9f7 210 (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
<> 144:ef7eb2e8f9f7 211 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
<> 144:ef7eb2e8f9f7 212 (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
<> 144:ef7eb2e8f9f7 213 HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
<> 144:ef7eb2e8f9f7 214 function is executed and user can add his own code by customization of function pointer
<> 144:ef7eb2e8f9f7 215 HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
<> 144:ef7eb2e8f9f7 216 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
<> 144:ef7eb2e8f9f7 217 (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 *** DAC HAL driver macros list ***
<> 144:ef7eb2e8f9f7 220 =============================================
<> 144:ef7eb2e8f9f7 221 [..]
<> 144:ef7eb2e8f9f7 222 Below the list of most used macros in DAC HAL driver.
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
<> 144:ef7eb2e8f9f7 225 (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
<> 144:ef7eb2e8f9f7 226 (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
<> 144:ef7eb2e8f9f7 227 (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 [..]
<> 144:ef7eb2e8f9f7 230 (@) You can refer to the DAC HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 @endverbatim
<> 144:ef7eb2e8f9f7 233 ******************************************************************************
<> 144:ef7eb2e8f9f7 234 * @attention
<> 144:ef7eb2e8f9f7 235 *
AnnaBridge 167:e84263d55307 236 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 237 *
<> 144:ef7eb2e8f9f7 238 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 239 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 240 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 241 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 242 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 243 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 244 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 245 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 246 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 247 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 248 *
<> 144:ef7eb2e8f9f7 249 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 250 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 251 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 252 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 253 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 254 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 255 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 256 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 257 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 258 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 259 *
<> 144:ef7eb2e8f9f7 260 ******************************************************************************
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 265 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 268 * @{
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /** @defgroup DAC DAC
<> 144:ef7eb2e8f9f7 272 * @brief DAC driver modules
<> 144:ef7eb2e8f9f7 273 * @{
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 #ifdef HAL_DAC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 279 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 280 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 281 /** @addtogroup DAC_Private_Constants DAC Private Constants
<> 144:ef7eb2e8f9f7 282 * @{
<> 144:ef7eb2e8f9f7 283 */
AnnaBridge 167:e84263d55307 284 #define TIMEOUT_DAC_CALIBCONFIG ((uint32_t)1) /* 1 ms */
AnnaBridge 167:e84263d55307 285 #define HFSEL_ENABLE_THRESHOLD_80MHZ ((uint32_t)80000000) /* 80 mHz */
<> 144:ef7eb2e8f9f7 286 /**
<> 144:ef7eb2e8f9f7 287 * @}
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 291 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 292 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 293 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 294 /** @defgroup DAC_Private_Functions DAC Private Functions
<> 144:ef7eb2e8f9f7 295 * @{
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 298 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 299 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @}
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 /* Exported functions -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /** @defgroup DAC_Exported_Functions DAC Exported Functions
<> 144:ef7eb2e8f9f7 306 * @{
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 310 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 311 *
<> 144:ef7eb2e8f9f7 312 @verbatim
<> 144:ef7eb2e8f9f7 313 ==============================================================================
<> 144:ef7eb2e8f9f7 314 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 315 ==============================================================================
<> 144:ef7eb2e8f9f7 316 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 317 (+) Initialize and configure the DAC.
<> 144:ef7eb2e8f9f7 318 (+) De-initialize the DAC.
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 @endverbatim
<> 144:ef7eb2e8f9f7 321 * @{
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @brief Initialize the DAC peripheral according to the specified parameters
<> 144:ef7eb2e8f9f7 326 * in the DAC_InitStruct and initialize the associated handle.
<> 144:ef7eb2e8f9f7 327 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 328 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 329 * @retval HAL status
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 332 {
<> 144:ef7eb2e8f9f7 333 /* Check DAC handle */
<> 144:ef7eb2e8f9f7 334 if(hdac == NULL)
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 337 }
<> 144:ef7eb2e8f9f7 338 /* Check the parameters */
<> 144:ef7eb2e8f9f7 339 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 if(hdac->State == HAL_DAC_STATE_RESET)
<> 144:ef7eb2e8f9f7 342 {
<> 144:ef7eb2e8f9f7 343 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 344 hdac->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 347 HAL_DAC_MspInit(hdac);
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /* Initialize the DAC state*/
<> 144:ef7eb2e8f9f7 351 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /* Set DAC error code to none */
<> 144:ef7eb2e8f9f7 354 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Initialize the DAC state*/
<> 144:ef7eb2e8f9f7 357 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Return function status */
<> 144:ef7eb2e8f9f7 360 return HAL_OK;
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /**
<> 144:ef7eb2e8f9f7 364 * @brief Deinitialize the DAC peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 365 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 366 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 367 * @retval HAL status
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 370 {
<> 144:ef7eb2e8f9f7 371 /* Check DAC handle */
<> 144:ef7eb2e8f9f7 372 if(hdac == NULL)
<> 144:ef7eb2e8f9f7 373 {
<> 144:ef7eb2e8f9f7 374 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 375 }
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Check the parameters */
<> 144:ef7eb2e8f9f7 378 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Change DAC state */
<> 144:ef7eb2e8f9f7 381 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 384 HAL_DAC_MspDeInit(hdac);
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /* Set DAC error code to none */
<> 144:ef7eb2e8f9f7 387 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* Change DAC state */
<> 144:ef7eb2e8f9f7 390 hdac->State = HAL_DAC_STATE_RESET;
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* Release Lock */
<> 144:ef7eb2e8f9f7 393 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Return function status */
<> 144:ef7eb2e8f9f7 396 return HAL_OK;
<> 144:ef7eb2e8f9f7 397 }
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /**
<> 144:ef7eb2e8f9f7 400 * @brief Initialize the DAC MSP.
<> 144:ef7eb2e8f9f7 401 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 402 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 403 * @retval None
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 406 {
<> 144:ef7eb2e8f9f7 407 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 408 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 411 the HAL_DAC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /**
<> 144:ef7eb2e8f9f7 416 * @brief DeInitialize the DAC MSP.
<> 144:ef7eb2e8f9f7 417 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 418 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 419 * @retval None
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 422 {
<> 144:ef7eb2e8f9f7 423 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 424 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 427 the HAL_DAC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 428 */
<> 144:ef7eb2e8f9f7 429 }
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /**
<> 144:ef7eb2e8f9f7 432 * @}
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 436 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 437 *
<> 144:ef7eb2e8f9f7 438 @verbatim
<> 144:ef7eb2e8f9f7 439 ==============================================================================
<> 144:ef7eb2e8f9f7 440 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 441 ==============================================================================
<> 144:ef7eb2e8f9f7 442 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 443 (+) Start conversion.
<> 144:ef7eb2e8f9f7 444 (+) Stop conversion.
<> 144:ef7eb2e8f9f7 445 (+) Start conversion and enable DMA transfer.
<> 144:ef7eb2e8f9f7 446 (+) Stop conversion and disable DMA transfer.
<> 144:ef7eb2e8f9f7 447 (+) Get result of conversion.
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 @endverbatim
<> 144:ef7eb2e8f9f7 450 * @{
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /**
<> 144:ef7eb2e8f9f7 454 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 455 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 456 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 457 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 458 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 459 * @arg DAC_CHANNEL_1: DAC Channel1 selected
AnnaBridge 167:e84263d55307 460 * @arg DAC_CHANNEL_2: DAC Channel2 selected (when supported)
<> 144:ef7eb2e8f9f7 461 * @retval HAL status
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 464 {
<> 144:ef7eb2e8f9f7 465 /* Check the parameters */
<> 144:ef7eb2e8f9f7 466 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /* Process locked */
<> 144:ef7eb2e8f9f7 469 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /* Change DAC state */
<> 144:ef7eb2e8f9f7 472 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 475 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 476
AnnaBridge 167:e84263d55307 477 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
AnnaBridge 167:e84263d55307 478 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 479 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 480 {
<> 144:ef7eb2e8f9f7 481 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 482 if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 /* Enable the selected DAC software conversion */
<> 144:ef7eb2e8f9f7 485 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488 else
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 491 if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
<> 144:ef7eb2e8f9f7 492 {
<> 144:ef7eb2e8f9f7 493 /* Enable the selected DAC software conversion*/
<> 144:ef7eb2e8f9f7 494 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
<> 144:ef7eb2e8f9f7 495 }
<> 144:ef7eb2e8f9f7 496 }
AnnaBridge 167:e84263d55307 497 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
AnnaBridge 167:e84263d55307 498 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
AnnaBridge 167:e84263d55307 499
AnnaBridge 167:e84263d55307 500
AnnaBridge 167:e84263d55307 501 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
AnnaBridge 167:e84263d55307 502 /* Check if software trigger enabled */
AnnaBridge 167:e84263d55307 503 if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
AnnaBridge 167:e84263d55307 504 {
AnnaBridge 167:e84263d55307 505 /* Enable the selected DAC software conversion */
AnnaBridge 167:e84263d55307 506 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
AnnaBridge 167:e84263d55307 507 }
AnnaBridge 167:e84263d55307 508 #endif /* STM32L451xx STM32L452xx STM32L462xx */
<> 144:ef7eb2e8f9f7 509 /* Change DAC state */
<> 144:ef7eb2e8f9f7 510 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /* Process unlocked */
<> 144:ef7eb2e8f9f7 513 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /* Return function status */
<> 144:ef7eb2e8f9f7 516 return HAL_OK;
<> 144:ef7eb2e8f9f7 517 }
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /**
<> 144:ef7eb2e8f9f7 520 * @brief Disables DAC and stop conversion of channel.
<> 144:ef7eb2e8f9f7 521 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 522 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 523 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 524 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 525 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 526 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 527 * @retval HAL status
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 530 {
<> 144:ef7eb2e8f9f7 531 /* Check the parameters */
<> 144:ef7eb2e8f9f7 532 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 535 __HAL_DAC_DISABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Change DAC state */
<> 144:ef7eb2e8f9f7 538 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /* Return function status */
<> 144:ef7eb2e8f9f7 541 return HAL_OK;
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543
AnnaBridge 167:e84263d55307 544 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
AnnaBridge 167:e84263d55307 545 /**
AnnaBridge 167:e84263d55307 546 * @brief Enables DAC and starts conversion of channel.
AnnaBridge 167:e84263d55307 547 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
AnnaBridge 167:e84263d55307 548 * the configuration information for the specified DAC.
AnnaBridge 167:e84263d55307 549 * @param Channel: The selected DAC channel.
AnnaBridge 167:e84263d55307 550 * This parameter can be one of the following values:
AnnaBridge 167:e84263d55307 551 * @arg DAC_CHANNEL_1: DAC Channel1 selected
AnnaBridge 167:e84263d55307 552 * @param pData: The destination peripheral Buffer address.
AnnaBridge 167:e84263d55307 553 * @param Length: The length of data to be transferred from memory to DAC peripheral
AnnaBridge 167:e84263d55307 554 * @param Alignment: Specifies the data alignment for DAC channel.
AnnaBridge 167:e84263d55307 555 * This parameter can be one of the following values:
AnnaBridge 167:e84263d55307 556 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
AnnaBridge 167:e84263d55307 557 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
AnnaBridge 167:e84263d55307 558 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
AnnaBridge 167:e84263d55307 559 * @retval HAL status
AnnaBridge 167:e84263d55307 560 */
AnnaBridge 167:e84263d55307 561 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
AnnaBridge 167:e84263d55307 562 {
AnnaBridge 167:e84263d55307 563 uint32_t tmpreg = 0;
AnnaBridge 167:e84263d55307 564
AnnaBridge 167:e84263d55307 565 /* Check the parameters */
AnnaBridge 167:e84263d55307 566 assert_param(IS_DAC_CHANNEL(Channel));
AnnaBridge 167:e84263d55307 567 assert_param(IS_DAC_ALIGN(Alignment));
AnnaBridge 167:e84263d55307 568
AnnaBridge 167:e84263d55307 569 /* Process locked */
AnnaBridge 167:e84263d55307 570 __HAL_LOCK(hdac);
AnnaBridge 167:e84263d55307 571
AnnaBridge 167:e84263d55307 572 /* Change DAC state */
AnnaBridge 167:e84263d55307 573 hdac->State = HAL_DAC_STATE_BUSY;
AnnaBridge 167:e84263d55307 574
AnnaBridge 167:e84263d55307 575 /* Set the DMA transfer complete callback for channel1 */
AnnaBridge 167:e84263d55307 576 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
AnnaBridge 167:e84263d55307 577
AnnaBridge 167:e84263d55307 578 /* Set the DMA half transfer complete callback for channel1 */
AnnaBridge 167:e84263d55307 579 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
AnnaBridge 167:e84263d55307 580
AnnaBridge 167:e84263d55307 581 /* Set the DMA error callback for channel1 */
AnnaBridge 167:e84263d55307 582 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
AnnaBridge 167:e84263d55307 583
AnnaBridge 167:e84263d55307 584 /* Enable the selected DAC channel1 DMA request */
AnnaBridge 167:e84263d55307 585 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
AnnaBridge 167:e84263d55307 586
AnnaBridge 167:e84263d55307 587 /* Case of use of channel 1 */
AnnaBridge 167:e84263d55307 588 switch(Alignment)
AnnaBridge 167:e84263d55307 589 {
AnnaBridge 167:e84263d55307 590 case DAC_ALIGN_12B_R:
AnnaBridge 167:e84263d55307 591 /* Get DHR12R1 address */
AnnaBridge 167:e84263d55307 592 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
AnnaBridge 167:e84263d55307 593 break;
AnnaBridge 167:e84263d55307 594 case DAC_ALIGN_12B_L:
AnnaBridge 167:e84263d55307 595 /* Get DHR12L1 address */
AnnaBridge 167:e84263d55307 596 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
AnnaBridge 167:e84263d55307 597 break;
AnnaBridge 167:e84263d55307 598 case DAC_ALIGN_8B_R:
AnnaBridge 167:e84263d55307 599 /* Get DHR8R1 address */
AnnaBridge 167:e84263d55307 600 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
AnnaBridge 167:e84263d55307 601 break;
AnnaBridge 167:e84263d55307 602 default:
AnnaBridge 167:e84263d55307 603 break;
AnnaBridge 167:e84263d55307 604 }
AnnaBridge 167:e84263d55307 605
AnnaBridge 167:e84263d55307 606 /* Enable the DMA channel */
AnnaBridge 167:e84263d55307 607 /* Enable the DAC DMA underrun interrupt */
AnnaBridge 167:e84263d55307 608 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
AnnaBridge 167:e84263d55307 609
AnnaBridge 167:e84263d55307 610 /* Enable the DMA channel */
AnnaBridge 167:e84263d55307 611 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
AnnaBridge 167:e84263d55307 612
AnnaBridge 167:e84263d55307 613 /* Process Unlocked */
AnnaBridge 167:e84263d55307 614 __HAL_UNLOCK(hdac);
AnnaBridge 167:e84263d55307 615
AnnaBridge 167:e84263d55307 616 /* Enable the Peripheral */
AnnaBridge 167:e84263d55307 617 __HAL_DAC_ENABLE(hdac, Channel);
AnnaBridge 167:e84263d55307 618
AnnaBridge 167:e84263d55307 619 /* Return function status */
AnnaBridge 167:e84263d55307 620 return HAL_OK;
AnnaBridge 167:e84263d55307 621 }
AnnaBridge 167:e84263d55307 622 #endif /* STM32L451xx STM32L452xx STM32L462xx */
AnnaBridge 167:e84263d55307 623
AnnaBridge 167:e84263d55307 624 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
AnnaBridge 167:e84263d55307 625 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 626
<> 144:ef7eb2e8f9f7 627 /**
<> 144:ef7eb2e8f9f7 628 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 629 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 630 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 631 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 632 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 633 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 634 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 635 * @param pData: The destination peripheral Buffer address.
<> 144:ef7eb2e8f9f7 636 * @param Length: The length of data to be transferred from memory to DAC peripheral
<> 144:ef7eb2e8f9f7 637 * @param Alignment: Specifies the data alignment for DAC channel.
<> 144:ef7eb2e8f9f7 638 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 639 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 640 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 641 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 642 * @retval HAL status
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /* Check the parameters */
<> 144:ef7eb2e8f9f7 649 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 650 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /* Process locked */
<> 144:ef7eb2e8f9f7 653 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /* Change DAC state */
<> 144:ef7eb2e8f9f7 656 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 659 {
<> 144:ef7eb2e8f9f7 660 /* Set the DMA transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 661 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /* Set the DMA half transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 664 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /* Set the DMA error callback for channel1 */
<> 144:ef7eb2e8f9f7 667 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /* Enable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 670 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /* Case of use of channel 1 */
<> 144:ef7eb2e8f9f7 673 switch(Alignment)
<> 144:ef7eb2e8f9f7 674 {
<> 144:ef7eb2e8f9f7 675 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 676 /* Get DHR12R1 address */
<> 144:ef7eb2e8f9f7 677 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
<> 144:ef7eb2e8f9f7 678 break;
<> 144:ef7eb2e8f9f7 679 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 680 /* Get DHR12L1 address */
<> 144:ef7eb2e8f9f7 681 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
<> 144:ef7eb2e8f9f7 682 break;
<> 144:ef7eb2e8f9f7 683 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 684 /* Get DHR8R1 address */
<> 144:ef7eb2e8f9f7 685 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
<> 144:ef7eb2e8f9f7 686 break;
<> 144:ef7eb2e8f9f7 687 default:
<> 144:ef7eb2e8f9f7 688 break;
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690 }
<> 144:ef7eb2e8f9f7 691 else
<> 144:ef7eb2e8f9f7 692 {
<> 144:ef7eb2e8f9f7 693 /* Set the DMA transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 694 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /* Set the DMA half transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 697 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Set the DMA error callback for channel2 */
<> 144:ef7eb2e8f9f7 700 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Enable the selected DAC channel2 DMA request */
<> 144:ef7eb2e8f9f7 703 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* Case of use of channel 2 */
<> 144:ef7eb2e8f9f7 706 switch(Alignment)
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 709 /* Get DHR12R2 address */
<> 144:ef7eb2e8f9f7 710 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
<> 144:ef7eb2e8f9f7 711 break;
<> 144:ef7eb2e8f9f7 712 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 713 /* Get DHR12L2 address */
<> 144:ef7eb2e8f9f7 714 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
<> 144:ef7eb2e8f9f7 715 break;
<> 144:ef7eb2e8f9f7 716 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 717 /* Get DHR8R2 address */
<> 144:ef7eb2e8f9f7 718 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
<> 144:ef7eb2e8f9f7 719 break;
<> 144:ef7eb2e8f9f7 720 default:
<> 144:ef7eb2e8f9f7 721 break;
<> 144:ef7eb2e8f9f7 722 }
<> 144:ef7eb2e8f9f7 723 }
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 726 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 729 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 732 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 733 }
<> 144:ef7eb2e8f9f7 734 else
<> 144:ef7eb2e8f9f7 735 {
<> 144:ef7eb2e8f9f7 736 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 737 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 740 HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 741 }
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 744 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 747 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /* Return function status */
<> 144:ef7eb2e8f9f7 750 return HAL_OK;
<> 144:ef7eb2e8f9f7 751 }
AnnaBridge 167:e84263d55307 752 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
AnnaBridge 167:e84263d55307 753 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
AnnaBridge 167:e84263d55307 754
<> 144:ef7eb2e8f9f7 755 /**
<> 144:ef7eb2e8f9f7 756 * @brief Disables DAC and stop conversion of channel.
<> 144:ef7eb2e8f9f7 757 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 758 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 759 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 760 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 761 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 762 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 763 * @retval HAL status
<> 144:ef7eb2e8f9f7 764 */
<> 144:ef7eb2e8f9f7 765 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 766 {
<> 144:ef7eb2e8f9f7 767 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /* Check the parameters */
<> 144:ef7eb2e8f9f7 770 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /* Disable the selected DAC channel DMA request */
<> 144:ef7eb2e8f9f7 773 hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 776 __HAL_DAC_DISABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /* Disable the DMA channel */
AnnaBridge 167:e84263d55307 779 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
AnnaBridge 167:e84263d55307 780 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 781 /* Channel1 is used */
<> 144:ef7eb2e8f9f7 782 if (Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 783 {
<> 144:ef7eb2e8f9f7 784 /* Disable the DMA channel */
<> 144:ef7eb2e8f9f7 785 status = HAL_DMA_Abort(hdac->DMA_Handle1);
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /* Disable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 788 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790 else /* Channel2 is used for */
<> 144:ef7eb2e8f9f7 791 {
<> 144:ef7eb2e8f9f7 792 /* Disable the DMA channel */
<> 144:ef7eb2e8f9f7 793 status = HAL_DMA_Abort(hdac->DMA_Handle2);
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /* Disable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 796 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
<> 144:ef7eb2e8f9f7 797 }
AnnaBridge 167:e84263d55307 798 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
AnnaBridge 167:e84263d55307 799 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
AnnaBridge 167:e84263d55307 800
AnnaBridge 167:e84263d55307 801 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
AnnaBridge 167:e84263d55307 802 /* Disable the DMA channel */
AnnaBridge 167:e84263d55307 803 status = HAL_DMA_Abort(hdac->DMA_Handle1);
AnnaBridge 167:e84263d55307 804
AnnaBridge 167:e84263d55307 805 /* Disable the DAC DMA underrun interrupt */
AnnaBridge 167:e84263d55307 806 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
AnnaBridge 167:e84263d55307 807 #endif /* STM32L451xx STM32L452xx STM32L462xx */
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /* Check if DMA Channel effectively disabled */
<> 144:ef7eb2e8f9f7 810 if (status != HAL_OK)
<> 144:ef7eb2e8f9f7 811 {
<> 144:ef7eb2e8f9f7 812 /* Update DAC state machine to error */
<> 144:ef7eb2e8f9f7 813 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815 else
<> 144:ef7eb2e8f9f7 816 {
<> 144:ef7eb2e8f9f7 817 /* Change DAC state */
<> 144:ef7eb2e8f9f7 818 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /* Return function status */
<> 144:ef7eb2e8f9f7 822 return status;
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824
AnnaBridge 167:e84263d55307 825 /* DAC channel 2 is available on top of DAC channel 1 in */
AnnaBridge 167:e84263d55307 826 /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
AnnaBridge 167:e84263d55307 827 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /**
<> 144:ef7eb2e8f9f7 830 * @brief Handles DAC interrupt request
<> 144:ef7eb2e8f9f7 831 * This function uses the interruption of DMA
<> 144:ef7eb2e8f9f7 832 * underrun.
<> 144:ef7eb2e8f9f7 833 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 834 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 835 * @retval None
<> 144:ef7eb2e8f9f7 836 */
<> 144:ef7eb2e8f9f7 837 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 838 {
<> 144:ef7eb2e8f9f7 839 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
<> 144:ef7eb2e8f9f7 840 {
<> 144:ef7eb2e8f9f7 841 /* Check underrun flag of DAC channel 1 */
<> 144:ef7eb2e8f9f7 842 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
<> 144:ef7eb2e8f9f7 843 {
<> 144:ef7eb2e8f9f7 844 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 845 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* Set DAC error code to chanel1 DMA underrun error */
<> 144:ef7eb2e8f9f7 848 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 851 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 854 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* Error callback */
<> 144:ef7eb2e8f9f7 857 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 858 }
<> 144:ef7eb2e8f9f7 859 }
AnnaBridge 167:e84263d55307 860 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
AnnaBridge 167:e84263d55307 861 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 862 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
<> 144:ef7eb2e8f9f7 863 {
<> 144:ef7eb2e8f9f7 864 /* Check underrun flag of DAC channel 1 */
<> 144:ef7eb2e8f9f7 865 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
<> 144:ef7eb2e8f9f7 866 {
<> 144:ef7eb2e8f9f7 867 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 868 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 /* Set DAC error code to channel2 DMA underrun error */
<> 144:ef7eb2e8f9f7 871 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 874 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 877 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /* Error callback */
<> 144:ef7eb2e8f9f7 880 HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882 }
AnnaBridge 167:e84263d55307 883 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
AnnaBridge 167:e84263d55307 884 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
<> 144:ef7eb2e8f9f7 885 }
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 /**
<> 144:ef7eb2e8f9f7 888 * @brief Set the specified data holding register value for DAC channel.
<> 144:ef7eb2e8f9f7 889 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 890 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 891 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 892 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 893 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 894 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 895 * @param Alignment: Specifies the data alignment.
<> 144:ef7eb2e8f9f7 896 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 897 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 898 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 899 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 900 * @param Data: Data to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 901 * @retval HAL status
<> 144:ef7eb2e8f9f7 902 */
<> 144:ef7eb2e8f9f7 903 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
<> 144:ef7eb2e8f9f7 904 {
<> 144:ef7eb2e8f9f7 905 __IO uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /* Check the parameters */
<> 144:ef7eb2e8f9f7 908 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 909 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 910 assert_param(IS_DAC_DATA(Data));
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 913 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 914 {
<> 144:ef7eb2e8f9f7 915 tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
<> 144:ef7eb2e8f9f7 916 }
<> 144:ef7eb2e8f9f7 917 else
<> 144:ef7eb2e8f9f7 918 {
<> 144:ef7eb2e8f9f7 919 tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
<> 144:ef7eb2e8f9f7 920 }
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /* Set the DAC channel selected data holding register */
<> 144:ef7eb2e8f9f7 923 *(__IO uint32_t *) tmp = Data;
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /* Return function status */
<> 144:ef7eb2e8f9f7 926 return HAL_OK;
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /**
<> 144:ef7eb2e8f9f7 930 * @brief Conversion complete callback in non-blocking mode for Channel1
<> 144:ef7eb2e8f9f7 931 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 932 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 933 * @retval None
<> 144:ef7eb2e8f9f7 934 */
<> 144:ef7eb2e8f9f7 935 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 936 {
<> 144:ef7eb2e8f9f7 937 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 938 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 941 the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 942 */
<> 144:ef7eb2e8f9f7 943 }
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 /**
<> 144:ef7eb2e8f9f7 946 * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1
<> 144:ef7eb2e8f9f7 947 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 948 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 949 * @retval None
<> 144:ef7eb2e8f9f7 950 */
<> 144:ef7eb2e8f9f7 951 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 952 {
<> 144:ef7eb2e8f9f7 953 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 954 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 957 the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 958 */
<> 144:ef7eb2e8f9f7 959 }
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 /**
<> 144:ef7eb2e8f9f7 962 * @brief Error DAC callback for Channel1.
<> 144:ef7eb2e8f9f7 963 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 964 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 965 * @retval None
<> 144:ef7eb2e8f9f7 966 */
<> 144:ef7eb2e8f9f7 967 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 968 {
<> 144:ef7eb2e8f9f7 969 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 970 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 973 the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 974 */
<> 144:ef7eb2e8f9f7 975 }
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /**
<> 144:ef7eb2e8f9f7 978 * @brief DMA underrun DAC callback for channel1.
<> 144:ef7eb2e8f9f7 979 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 980 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 981 * @retval None
<> 144:ef7eb2e8f9f7 982 */
<> 144:ef7eb2e8f9f7 983 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 984 {
<> 144:ef7eb2e8f9f7 985 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 986 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 989 the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 990 */
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 /**
<> 144:ef7eb2e8f9f7 994 * @}
<> 144:ef7eb2e8f9f7 995 */
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 998 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 999 *
<> 144:ef7eb2e8f9f7 1000 @verbatim
<> 144:ef7eb2e8f9f7 1001 ==============================================================================
<> 144:ef7eb2e8f9f7 1002 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1003 ==============================================================================
<> 144:ef7eb2e8f9f7 1004 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1005 (+) Configure channels.
<> 144:ef7eb2e8f9f7 1006 (+) Set the specified data holding register value for DAC channel.
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 @endverbatim
<> 144:ef7eb2e8f9f7 1009 * @{
<> 144:ef7eb2e8f9f7 1010 */
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /**
<> 144:ef7eb2e8f9f7 1013 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 1014 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1015 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 1016 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 1017 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1018 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 1019 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 1020 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 1021 */
<> 144:ef7eb2e8f9f7 1022 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1023 {
<> 144:ef7eb2e8f9f7 1024 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1025 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /* Returns the DAC channel data output register value */
AnnaBridge 167:e84263d55307 1028 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
AnnaBridge 167:e84263d55307 1029 return hdac->Instance->DOR1;
AnnaBridge 167:e84263d55307 1030 #endif /* STM32L451xx STM32L452xx STM32L462xx */
AnnaBridge 167:e84263d55307 1031
AnnaBridge 167:e84263d55307 1032 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
AnnaBridge 167:e84263d55307 1033 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1034 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 1035 {
<> 144:ef7eb2e8f9f7 1036 return hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 1037 }
<> 144:ef7eb2e8f9f7 1038 else
<> 144:ef7eb2e8f9f7 1039 {
<> 144:ef7eb2e8f9f7 1040 return hdac->Instance->DOR2;
<> 144:ef7eb2e8f9f7 1041 }
AnnaBridge 167:e84263d55307 1042 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
AnnaBridge 167:e84263d55307 1043 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
<> 144:ef7eb2e8f9f7 1044 }
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /**
<> 144:ef7eb2e8f9f7 1047 * @brief Configures the selected DAC channel.
<> 144:ef7eb2e8f9f7 1048 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1049 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 1050 * @param sConfig: DAC configuration structure.
<> 144:ef7eb2e8f9f7 1051 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 1052 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1053 * @arg DAC_CHANNEL_1: DAC Channel1 selected
AnnaBridge 167:e84263d55307 1054 * @arg DAC_CHANNEL_2: DAC Channel2 selected (Whenever present)
<> 144:ef7eb2e8f9f7 1055 * @retval HAL status
<> 144:ef7eb2e8f9f7 1056 */
<> 144:ef7eb2e8f9f7 1057 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1058 {
<> 144:ef7eb2e8f9f7 1059 uint32_t tmpreg1 = 0, tmpreg2 = 0;
<> 144:ef7eb2e8f9f7 1060 uint32_t tickstart = 0;
AnnaBridge 167:e84263d55307 1061
<> 144:ef7eb2e8f9f7 1062 /* Check the DAC parameters */
AnnaBridge 167:e84263d55307 1063
<> 144:ef7eb2e8f9f7 1064 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
<> 144:ef7eb2e8f9f7 1065 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
<> 144:ef7eb2e8f9f7 1066 assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
<> 144:ef7eb2e8f9f7 1067 assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
<> 144:ef7eb2e8f9f7 1068 if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
<> 144:ef7eb2e8f9f7 1069 {
<> 144:ef7eb2e8f9f7 1070 assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
<> 144:ef7eb2e8f9f7 1071 }
<> 144:ef7eb2e8f9f7 1072 assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
<> 144:ef7eb2e8f9f7 1073 if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
<> 144:ef7eb2e8f9f7 1074 {
<> 144:ef7eb2e8f9f7 1075 assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
<> 144:ef7eb2e8f9f7 1076 assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
<> 144:ef7eb2e8f9f7 1077 assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
<> 144:ef7eb2e8f9f7 1078 }
<> 144:ef7eb2e8f9f7 1079 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 /* Process locked */
<> 144:ef7eb2e8f9f7 1082 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 1083
<> 144:ef7eb2e8f9f7 1084 /* Change DAC state */
<> 144:ef7eb2e8f9f7 1085 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
<> 144:ef7eb2e8f9f7 1088 /* Sample on old configuration */
<> 144:ef7eb2e8f9f7 1089 {
<> 144:ef7eb2e8f9f7 1090 /* SampleTime */
<> 144:ef7eb2e8f9f7 1091 if (Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 1092 {
<> 144:ef7eb2e8f9f7 1093 /* Get timeout */
<> 144:ef7eb2e8f9f7 1094 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 /* SHSR1 can be written when BWST1 equals RESET */
<> 144:ef7eb2e8f9f7 1097 while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET)
<> 144:ef7eb2e8f9f7 1098 {
<> 144:ef7eb2e8f9f7 1099 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1100 if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
<> 144:ef7eb2e8f9f7 1101 {
<> 144:ef7eb2e8f9f7 1102 /* Update error code */
<> 144:ef7eb2e8f9f7 1103 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
<> 144:ef7eb2e8f9f7 1104
<> 144:ef7eb2e8f9f7 1105 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 1106 hdac->State = HAL_DAC_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1109 }
<> 144:ef7eb2e8f9f7 1110 }
<> 144:ef7eb2e8f9f7 1111 HAL_Delay(1);
<> 144:ef7eb2e8f9f7 1112 hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
<> 144:ef7eb2e8f9f7 1113 }
AnnaBridge 167:e84263d55307 1114 #if !defined (STM32L451xx) & !defined (STM32L452xx) & !defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1115 else /* Channel 2 */
<> 144:ef7eb2e8f9f7 1116 {
<> 144:ef7eb2e8f9f7 1117 /* SHSR2 can be written when BWST2 equals RESET */
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET)
<> 144:ef7eb2e8f9f7 1120 {
<> 144:ef7eb2e8f9f7 1121 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1122 if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
<> 144:ef7eb2e8f9f7 1123 {
<> 144:ef7eb2e8f9f7 1124 /* Update error code */
<> 144:ef7eb2e8f9f7 1125 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
<> 144:ef7eb2e8f9f7 1126
<> 144:ef7eb2e8f9f7 1127 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 1128 hdac->State = HAL_DAC_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1131 }
<> 144:ef7eb2e8f9f7 1132 }
<> 144:ef7eb2e8f9f7 1133 HAL_Delay(1);
<> 144:ef7eb2e8f9f7 1134 hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
<> 144:ef7eb2e8f9f7 1135 }
AnnaBridge 167:e84263d55307 1136 #endif /* STM32L451xx STM32L452xx STM32L462xx */
AnnaBridge 167:e84263d55307 1137
<> 144:ef7eb2e8f9f7 1138 /* HoldTime */
AnnaBridge 167:e84263d55307 1139 MODIFY_REG (hdac->Instance->SHHR, DAC_SHHR_THOLD1<<Channel, (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<<Channel);
<> 144:ef7eb2e8f9f7 1140 /* RefreshTime */
AnnaBridge 167:e84263d55307 1141 MODIFY_REG (hdac->Instance->SHRR, DAC_SHRR_TREFRESH1<<Channel, (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<<Channel);
<> 144:ef7eb2e8f9f7 1142 }
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
<> 144:ef7eb2e8f9f7 1145 /* USER TRIMMING */
<> 144:ef7eb2e8f9f7 1146 {
<> 144:ef7eb2e8f9f7 1147 /* Get the DAC CCR value */
<> 144:ef7eb2e8f9f7 1148 tmpreg1 = hdac->Instance->CCR;
<> 144:ef7eb2e8f9f7 1149 /* Clear trimming value */
<> 144:ef7eb2e8f9f7 1150 tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel);
<> 144:ef7eb2e8f9f7 1151 /* Configure for the selected trimming offset */
<> 144:ef7eb2e8f9f7 1152 tmpreg2 = sConfig->DAC_TrimmingValue;
<> 144:ef7eb2e8f9f7 1153 /* Calculate CCR register value depending on DAC_Channel */
<> 144:ef7eb2e8f9f7 1154 tmpreg1 |= tmpreg2 << Channel;
<> 144:ef7eb2e8f9f7 1155 /* Write to DAC CCR */
<> 144:ef7eb2e8f9f7 1156 hdac->Instance->CCR = tmpreg1;
<> 144:ef7eb2e8f9f7 1157 }
<> 144:ef7eb2e8f9f7 1158 /* else factory trimming is used (factory setting are available at reset)*/
<> 144:ef7eb2e8f9f7 1159 /* SW Nothing has nothing to do */
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /* Get the DAC MCR value */
<> 144:ef7eb2e8f9f7 1162 tmpreg1 = hdac->Instance->MCR;
<> 144:ef7eb2e8f9f7 1163 /* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */
<> 144:ef7eb2e8f9f7 1164 tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel);
<> 144:ef7eb2e8f9f7 1165 /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
<> 144:ef7eb2e8f9f7 1166 tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral);
<> 144:ef7eb2e8f9f7 1167 /* Calculate MCR register value depending on DAC_Channel */
<> 144:ef7eb2e8f9f7 1168 tmpreg1 |= tmpreg2 << Channel;
<> 144:ef7eb2e8f9f7 1169 /* Write to DAC MCR */
<> 144:ef7eb2e8f9f7 1170 hdac->Instance->MCR = tmpreg1;
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172 /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
<> 144:ef7eb2e8f9f7 1173 CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel);
<> 144:ef7eb2e8f9f7 1174
<> 144:ef7eb2e8f9f7 1175 /* Get the DAC CR value */
<> 144:ef7eb2e8f9f7 1176 tmpreg1 = hdac->Instance->CR;
<> 144:ef7eb2e8f9f7 1177 /* Clear TENx, TSELx, WAVEx and MAMPx bits */
<> 144:ef7eb2e8f9f7 1178 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel);
<> 144:ef7eb2e8f9f7 1179 /* Configure for the selected DAC channel: trigger */
<> 144:ef7eb2e8f9f7 1180 /* Set TSELx and TENx bits according to DAC_Trigger value */
<> 144:ef7eb2e8f9f7 1181 tmpreg2 = (sConfig->DAC_Trigger);
<> 144:ef7eb2e8f9f7 1182 /* Calculate CR register value depending on DAC_Channel */
<> 144:ef7eb2e8f9f7 1183 tmpreg1 |= tmpreg2 << Channel;
AnnaBridge 167:e84263d55307 1184
<> 144:ef7eb2e8f9f7 1185 /* Write to DAC CR */
<> 144:ef7eb2e8f9f7 1186 hdac->Instance->CR = tmpreg1;
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 /* Disable wave generation */
<> 144:ef7eb2e8f9f7 1189 hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
<> 144:ef7eb2e8f9f7 1190
<> 144:ef7eb2e8f9f7 1191 /* Change DAC state */
<> 144:ef7eb2e8f9f7 1192 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1195 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 /* Return function status */
<> 144:ef7eb2e8f9f7 1198 return HAL_OK;
<> 144:ef7eb2e8f9f7 1199 }
<> 144:ef7eb2e8f9f7 1200
<> 144:ef7eb2e8f9f7 1201 /**
<> 144:ef7eb2e8f9f7 1202 * @}
<> 144:ef7eb2e8f9f7 1203 */
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1206 * @brief Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1207 *
<> 144:ef7eb2e8f9f7 1208 @verbatim
<> 144:ef7eb2e8f9f7 1209 ==============================================================================
<> 144:ef7eb2e8f9f7 1210 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1211 ==============================================================================
<> 144:ef7eb2e8f9f7 1212 [..]
<> 144:ef7eb2e8f9f7 1213 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 1214 (+) Check the DAC state.
<> 144:ef7eb2e8f9f7 1215 (+) Check the DAC Errors.
<> 144:ef7eb2e8f9f7 1216
<> 144:ef7eb2e8f9f7 1217 @endverbatim
<> 144:ef7eb2e8f9f7 1218 * @{
<> 144:ef7eb2e8f9f7 1219 */
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 /**
<> 144:ef7eb2e8f9f7 1222 * @brief return the DAC handle state
<> 144:ef7eb2e8f9f7 1223 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1224 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 1225 * @retval HAL state
<> 144:ef7eb2e8f9f7 1226 */
<> 144:ef7eb2e8f9f7 1227 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 1228 {
<> 144:ef7eb2e8f9f7 1229 /* Return DAC handle state */
<> 144:ef7eb2e8f9f7 1230 return hdac->State;
<> 144:ef7eb2e8f9f7 1231 }
<> 144:ef7eb2e8f9f7 1232
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234 /**
<> 144:ef7eb2e8f9f7 1235 * @brief Return the DAC error code
<> 144:ef7eb2e8f9f7 1236 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1237 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 1238 * @retval DAC Error Code
<> 144:ef7eb2e8f9f7 1239 */
<> 144:ef7eb2e8f9f7 1240 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 1241 {
<> 144:ef7eb2e8f9f7 1242 return hdac->ErrorCode;
<> 144:ef7eb2e8f9f7 1243 }
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 /**
<> 144:ef7eb2e8f9f7 1246 * @}
<> 144:ef7eb2e8f9f7 1247 */
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 /**
<> 144:ef7eb2e8f9f7 1250 * @}
<> 144:ef7eb2e8f9f7 1251 */
<> 144:ef7eb2e8f9f7 1252
<> 144:ef7eb2e8f9f7 1253 /** @addtogroup DAC_Private_Functions
<> 144:ef7eb2e8f9f7 1254 * @{
<> 144:ef7eb2e8f9f7 1255 */
<> 144:ef7eb2e8f9f7 1256
<> 144:ef7eb2e8f9f7 1257 /**
<> 144:ef7eb2e8f9f7 1258 * @brief DMA conversion complete callback.
<> 144:ef7eb2e8f9f7 1259 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1260 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1261 * @retval None
<> 144:ef7eb2e8f9f7 1262 */
<> 144:ef7eb2e8f9f7 1263 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1264 {
<> 144:ef7eb2e8f9f7 1265 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1266
<> 144:ef7eb2e8f9f7 1267 HAL_DAC_ConvCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 1268
<> 144:ef7eb2e8f9f7 1269 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 1270 }
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /**
<> 144:ef7eb2e8f9f7 1273 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 1274 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1275 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1276 * @retval None
<> 144:ef7eb2e8f9f7 1277 */
<> 144:ef7eb2e8f9f7 1278 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1279 {
<> 144:ef7eb2e8f9f7 1280 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1281 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 1282 HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 1283 }
<> 144:ef7eb2e8f9f7 1284
<> 144:ef7eb2e8f9f7 1285 /**
<> 144:ef7eb2e8f9f7 1286 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 1287 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1288 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1289 * @retval None
<> 144:ef7eb2e8f9f7 1290 */
<> 144:ef7eb2e8f9f7 1291 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1292 {
<> 144:ef7eb2e8f9f7 1293 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1294
<> 144:ef7eb2e8f9f7 1295 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 1296 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 HAL_DAC_ErrorCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 1299
<> 144:ef7eb2e8f9f7 1300 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 1301 }
<> 144:ef7eb2e8f9f7 1302
<> 144:ef7eb2e8f9f7 1303 /**
<> 144:ef7eb2e8f9f7 1304 * @}
<> 144:ef7eb2e8f9f7 1305 */
<> 144:ef7eb2e8f9f7 1306
<> 144:ef7eb2e8f9f7 1307 #endif /* HAL_DAC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 /**
<> 144:ef7eb2e8f9f7 1310 * @}
<> 144:ef7eb2e8f9f7 1311 */
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 /**
<> 144:ef7eb2e8f9f7 1314 * @}
<> 144:ef7eb2e8f9f7 1315 */
<> 144:ef7eb2e8f9f7 1316
<> 144:ef7eb2e8f9f7 1317 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/