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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h@181:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
181:96ed750bd169
Parent:
167:e84263d55307 
mbed-dev libray. Release version 158

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<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_adc_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of ADC HAL extended module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 167:e84263d55307 39 #ifndef __STM32L4xx_HAL_ADC_EX_H
AnnaBridge 167:e84263d55307 40 #define __STM32L4xx_HAL_ADC_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l4xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
AnnaBridge 167:e84263d55307 53 /** @addtogroup ADCEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
AnnaBridge 167:e84263d55307 63 * @brief ADC group injected contexts queue configuration
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
AnnaBridge 167:e84263d55307 67 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
AnnaBridge 167:e84263d55307 68 HAL_ADCEx_InjectedConfigChannel() call to finally initialize
AnnaBridge 167:e84263d55307 69 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
<> 144:ef7eb2e8f9f7 70
AnnaBridge 167:e84263d55307 71 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
AnnaBridge 167:e84263d55307 72 }ADC_InjectionConfigTypeDef;
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /**
<> 144:ef7eb2e8f9f7 75 * @brief ADC handle Structure definition
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77 typedef struct
<> 144:ef7eb2e8f9f7 78 {
<> 144:ef7eb2e8f9f7 79 ADC_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 HAL_LockTypeDef Lock; /*!< ADC locking object */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 __IO uint32_t State; /*!< ADC communication state (bit-map of ADC states) */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 __IO uint32_t ErrorCode; /*!< ADC Error code */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
<> 144:ef7eb2e8f9f7 92 }ADC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /**
<> 144:ef7eb2e8f9f7 95 * @brief ADC Injected Conversion Oversampling structure definition
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97 typedef struct
<> 144:ef7eb2e8f9f7 98 {
<> 144:ef7eb2e8f9f7 99 uint32_t Ratio; /*!< Configures the oversampling ratio.
<> 144:ef7eb2e8f9f7 100 This parameter can be a value of @ref ADCEx_Oversampling_Ratio */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
<> 144:ef7eb2e8f9f7 103 This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
<> 144:ef7eb2e8f9f7 104 }ADC_InjOversamplingTypeDef;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /**
AnnaBridge 167:e84263d55307 107 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
<> 144:ef7eb2e8f9f7 108 * @note Parameters of this structure are shared within 2 scopes:
<> 144:ef7eb2e8f9f7 109 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
AnnaBridge 167:e84263d55307 110 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
AnnaBridge 167:e84263d55307 111 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
AnnaBridge 167:e84263d55307 112 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 113 * ADC state can be either:
<> 144:ef7eb2e8f9f7 114 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
<> 144:ef7eb2e8f9f7 115 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
<> 144:ef7eb2e8f9f7 116 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
<> 144:ef7eb2e8f9f7 117 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
AnnaBridge 167:e84263d55307 118 * on ADC groups regular and injected.
<> 144:ef7eb2e8f9f7 119 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
AnnaBridge 167:e84263d55307 120 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 typedef struct
<> 144:ef7eb2e8f9f7 123 {
AnnaBridge 167:e84263d55307 124 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
<> 144:ef7eb2e8f9f7 125 This parameter can be a value of @ref ADC_channels
AnnaBridge 167:e84263d55307 126 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
AnnaBridge 167:e84263d55307 127
AnnaBridge 167:e84263d55307 128 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
<> 144:ef7eb2e8f9f7 129 This parameter must be a value of @ref ADCEx_injected_rank.
<> 144:ef7eb2e8f9f7 130 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
AnnaBridge 167:e84263d55307 131 the new channel setting (or parameter number of conversions adjusted) */
AnnaBridge 167:e84263d55307 132
<> 144:ef7eb2e8f9f7 133 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
<> 144:ef7eb2e8f9f7 134 Unit: ADC clock cycles.
AnnaBridge 167:e84263d55307 135 Conversion time is the addition of sampling time and processing time
AnnaBridge 167:e84263d55307 136 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
<> 144:ef7eb2e8f9f7 137 This parameter can be a value of @ref ADC_sampling_times.
<> 144:ef7eb2e8f9f7 138 Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
<> 144:ef7eb2e8f9f7 139 It overwrites the last setting.
<> 144:ef7eb2e8f9f7 140 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
AnnaBridge 167:e84263d55307 141 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
AnnaBridge 167:e84263d55307 142 Refer to device datasheet for timings values. */
AnnaBridge 167:e84263d55307 143
<> 144:ef7eb2e8f9f7 144 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
<> 144:ef7eb2e8f9f7 145 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
<> 144:ef7eb2e8f9f7 146 Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
<> 144:ef7eb2e8f9f7 147 This parameter must be a value of @ref ADCEx_SingleDifferential.
<> 144:ef7eb2e8f9f7 148 Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
<> 144:ef7eb2e8f9f7 149 It overwrites the last setting.
<> 144:ef7eb2e8f9f7 150 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
<> 144:ef7eb2e8f9f7 151 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
<> 144:ef7eb2e8f9f7 152 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
AnnaBridge 167:e84263d55307 153 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
<> 144:ef7eb2e8f9f7 154 of another parameter update on the fly) */
AnnaBridge 167:e84263d55307 155
<> 144:ef7eb2e8f9f7 156 uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
<> 144:ef7eb2e8f9f7 157 This parameter can be a value of @ref ADCEx_OffsetNumber.
<> 144:ef7eb2e8f9f7 158 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
AnnaBridge 167:e84263d55307 159
<> 144:ef7eb2e8f9f7 160 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
<> 144:ef7eb2e8f9f7 161 Offset value must be a positive number.
AnnaBridge 167:e84263d55307 162 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
AnnaBridge 167:e84263d55307 163 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
<> 144:ef7eb2e8f9f7 164 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
<> 144:ef7eb2e8f9f7 165 without continuous mode or external trigger that could launch a conversion). */
AnnaBridge 167:e84263d55307 166
AnnaBridge 167:e84263d55307 167 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
<> 144:ef7eb2e8f9f7 168 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<> 144:ef7eb2e8f9f7 169 This parameter must be a number between Min_Data = 1 and Max_Data = 4.
<> 144:ef7eb2e8f9f7 170 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 144:ef7eb2e8f9f7 171 configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge 167:e84263d55307 172
AnnaBridge 167:e84263d55307 173 uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
AnnaBridge 167:e84263d55307 174 (main sequence subdivided in successive parts).
<> 144:ef7eb2e8f9f7 175 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<> 144:ef7eb2e8f9f7 176 Discontinuous mode can be enabled only if continuous mode is disabled.
<> 144:ef7eb2e8f9f7 177 This parameter can be set to ENABLE or DISABLE.
<> 144:ef7eb2e8f9f7 178 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
AnnaBridge 167:e84263d55307 179 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
<> 144:ef7eb2e8f9f7 180 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 144:ef7eb2e8f9f7 181 configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge 167:e84263d55307 182
AnnaBridge 167:e84263d55307 183 uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
<> 144:ef7eb2e8f9f7 184 This parameter can be set to ENABLE or DISABLE.
<> 144:ef7eb2e8f9f7 185 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
AnnaBridge 167:e84263d55307 186 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 187 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
<> 144:ef7eb2e8f9f7 188 To maintain JAUTO always enabled, DMA must be configured in circular mode.
<> 144:ef7eb2e8f9f7 189 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 144:ef7eb2e8f9f7 190 configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge 167:e84263d55307 191
<> 144:ef7eb2e8f9f7 192 uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
<> 144:ef7eb2e8f9f7 193 This parameter can be set to ENABLE or DISABLE.
<> 144:ef7eb2e8f9f7 194 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
<> 144:ef7eb2e8f9f7 195 new injected context is set when queue is full, error is triggered by interruption and through function
<> 144:ef7eb2e8f9f7 196 'HAL_ADCEx_InjectedQueueOverflowCallback'.
<> 144:ef7eb2e8f9f7 197 Caution: This feature request that the sequence is fully configured before injected conversion start.
<> 144:ef7eb2e8f9f7 198 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
<> 144:ef7eb2e8f9f7 199 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 144:ef7eb2e8f9f7 200 configure a channel on injected group can impact the configuration of other channels previously set.
<> 144:ef7eb2e8f9f7 201 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
AnnaBridge 167:e84263d55307 202
<> 144:ef7eb2e8f9f7 203 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
<> 144:ef7eb2e8f9f7 204 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
AnnaBridge 167:e84263d55307 205 This parameter can be a value of @ref ADC_injected_external_trigger_source.
<> 144:ef7eb2e8f9f7 206 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 144:ef7eb2e8f9f7 207 configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge 167:e84263d55307 208
<> 144:ef7eb2e8f9f7 209 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
AnnaBridge 167:e84263d55307 210 This parameter can be a value of @ref ADC_injected_external_trigger_edge.
AnnaBridge 167:e84263d55307 211 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
<> 144:ef7eb2e8f9f7 212 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 144:ef7eb2e8f9f7 213 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 uint32_t InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
<> 144:ef7eb2e8f9f7 216 This parameter can be set to ENABLE or DISABLE.
<> 144:ef7eb2e8f9f7 217 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
<> 144:ef7eb2e8f9f7 220 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
<> 144:ef7eb2e8f9f7 221 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
<> 144:ef7eb2e8f9f7 222 }ADC_InjectionConfTypeDef;
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224
AnnaBridge 167:e84263d55307 225 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 226 /**
<> 144:ef7eb2e8f9f7 227 * @brief Structure definition of ADC multimode
<> 144:ef7eb2e8f9f7 228 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
<> 144:ef7eb2e8f9f7 229 * Both Master and Slave ADCs must be disabled.
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231 typedef struct
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode.
<> 144:ef7eb2e8f9f7 234 This parameter can be a value of @ref ADCEx_Common_mode. */
AnnaBridge 167:e84263d55307 235
<> 144:ef7eb2e8f9f7 236 uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC:
<> 144:ef7eb2e8f9f7 237 selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
<> 144:ef7eb2e8f9f7 238 This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode. */
AnnaBridge 167:e84263d55307 239
<> 144:ef7eb2e8f9f7 240 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
<> 144:ef7eb2e8f9f7 241 This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases.
<> 144:ef7eb2e8f9f7 242 Delay range depends on selected resolution:
<> 144:ef7eb2e8f9f7 243 from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
<> 144:ef7eb2e8f9f7 244 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */
<> 144:ef7eb2e8f9f7 245 }ADC_MultiModeTypeDef;
AnnaBridge 167:e84263d55307 246 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /**
<> 144:ef7eb2e8f9f7 249 * @}
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
<> 144:ef7eb2e8f9f7 255 * @{
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257
AnnaBridge 167:e84263d55307 258 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
AnnaBridge 167:e84263d55307 259 * @{
AnnaBridge 167:e84263d55307 260 */
AnnaBridge 167:e84263d55307 261 /* ADC group regular trigger sources for all ADC instances */
AnnaBridge 167:e84263d55307 262 #define ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) /*!< Event 0 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 263 #define ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) /*!< Event 1 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 264 #define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) /*!< Event 2 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 265 #define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 3 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 266 #define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) /*!< Event 4 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 267 #define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 5 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 268 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 6 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 269 #define ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 7 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 270 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) /*!< Event 8 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 271 #define ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) /*!< Event 9 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 272 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) /*!< Event 10 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 273 #define ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 11 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 274 #define ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) /*!< Event 12 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 275 #define ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 13 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 276 #define ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 14 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 277 #define ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) /*!< Event 15 triggers injected group conversion start */
AnnaBridge 167:e84263d55307 278 #define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001) /*!< Software triggers injected group conversion start */
AnnaBridge 167:e84263d55307 279 /**
AnnaBridge 167:e84263d55307 280 * @}
AnnaBridge 167:e84263d55307 281 */
AnnaBridge 167:e84263d55307 282
AnnaBridge 167:e84263d55307 283 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
AnnaBridge 167:e84263d55307 284 * @{
AnnaBridge 167:e84263d55307 285 */
AnnaBridge 167:e84263d55307 286 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) /*!< Injected conversions hardware trigger detection disabled */
AnnaBridge 167:e84263d55307 287 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */
AnnaBridge 167:e84263d55307 288 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */
AnnaBridge 167:e84263d55307 289 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
AnnaBridge 167:e84263d55307 290 /**
AnnaBridge 167:e84263d55307 291 * @}
AnnaBridge 167:e84263d55307 292 */
AnnaBridge 167:e84263d55307 293
<> 144:ef7eb2e8f9f7 294 /** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
<> 144:ef7eb2e8f9f7 295 * @{
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297 #define ADC_SINGLE_ENDED ((uint32_t)0x00000000) /*!< ADC channel set in single-ended input mode */
<> 144:ef7eb2e8f9f7 298 #define ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF) /*!< ADC channel set in differential mode */
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @}
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
<> 144:ef7eb2e8f9f7 304 * @{
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306 #define ADC_OFFSET_NONE ((uint32_t)0x00) /*!< No offset correction */
<> 144:ef7eb2e8f9f7 307 #define ADC_OFFSET_1 ((uint32_t)0x01) /*!< Offset correction to apply to a first channel */
<> 144:ef7eb2e8f9f7 308 #define ADC_OFFSET_2 ((uint32_t)0x02) /*!< Offset correction to apply to a second channel */
<> 144:ef7eb2e8f9f7 309 #define ADC_OFFSET_3 ((uint32_t)0x03) /*!< Offset correction to apply to a third channel */
<> 144:ef7eb2e8f9f7 310 #define ADC_OFFSET_4 ((uint32_t)0x04) /*!< Offset correction to apply to a fourth channel */
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @}
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
<> 144:ef7eb2e8f9f7 316 * @{
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318 #define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /*!< ADC injected conversion rank 1 */
<> 144:ef7eb2e8f9f7 319 #define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /*!< ADC injected conversion rank 2 */
<> 144:ef7eb2e8f9f7 320 #define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /*!< ADC injected conversion rank 3 */
<> 144:ef7eb2e8f9f7 321 #define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /*!< ADC injected conversion rank 4 */
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @}
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325
AnnaBridge 167:e84263d55307 326 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 327 /** @defgroup ADCEx_Common_mode ADC Extended multimode dual mode
<> 144:ef7eb2e8f9f7 328 * @{
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330 #define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /*!< Independent ADC conversions mode */
<> 144:ef7eb2e8f9f7 331 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0)) /*!< Combined regular simultaneous + injected simultaneous mode */
<> 144:ef7eb2e8f9f7 332 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1)) /*!< Combined regular simultaneous + alternate trigger mode */
<> 144:ef7eb2e8f9f7 333 #define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Combined Interleaved mode + injected simultaneous mode */
<> 144:ef7eb2e8f9f7 334 #define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)) /*!< Injected simultaneous mode only */
<> 144:ef7eb2e8f9f7 335 #define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1)) /*!< Regular simultaneous mode only */
<> 144:ef7eb2e8f9f7 336 #define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Interleaved mode only */
<> 144:ef7eb2e8f9f7 337 #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)) /*!< Alternate trigger mode only */
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @}
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341
AnnaBridge 167:e84263d55307 342 /** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA mode for multimode
<> 144:ef7eb2e8f9f7 343 * @{
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 #define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA multimode disabled: each ADC uses its own DMA channel */
<> 144:ef7eb2e8f9f7 346 #define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
<> 144:ef7eb2e8f9f7 347 #define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
<> 144:ef7eb2e8f9f7 348 /**
<> 144:ef7eb2e8f9f7 349 * @}
<> 144:ef7eb2e8f9f7 350 */
<> 144:ef7eb2e8f9f7 351
AnnaBridge 167:e84263d55307 352 /** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended delay between 2 sampling phases
<> 144:ef7eb2e8f9f7 353 * @{
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355 #define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000)) /*!< 1 ADC clock cycle delay */
<> 144:ef7eb2e8f9f7 356 #define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0)) /*!< 2 ADC clock cycles delay */
<> 144:ef7eb2e8f9f7 357 #define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1)) /*!< 3 ADC clock cycles delay */
<> 144:ef7eb2e8f9f7 358 #define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 4 ADC clock cycles delay */
<> 144:ef7eb2e8f9f7 359 #define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2)) /*!< 5 ADC clock cycles delay */
<> 144:ef7eb2e8f9f7 360 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) /*!< 6 ADC clock cycles delay */
<> 144:ef7eb2e8f9f7 361 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) /*!< 7 ADC clock cycles delay (lower for non 12-bit resolution) */
<> 144:ef7eb2e8f9f7 362 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 8 ADC clock cycles delay (lower for non 12-bit resolution) */
<> 144:ef7eb2e8f9f7 363 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3)) /*!< 9 ADC clock cycles delay (lower for non 12-bit resolution) */
<> 144:ef7eb2e8f9f7 364 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) /*!< 10 ADC clock cycles delay (lower for non 12-bit resolution) */
<> 144:ef7eb2e8f9f7 365 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) /*!< 11 ADC clock cycles delay (lower for non 12-bit resolution) */
<> 144:ef7eb2e8f9f7 366 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 12 ADC clock cycles delay (lower for non 12-bit resolution) */
<> 144:ef7eb2e8f9f7 367 /**
<> 144:ef7eb2e8f9f7 368 * @}
<> 144:ef7eb2e8f9f7 369 */
AnnaBridge 167:e84263d55307 370 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 371 /** @defgroup ADCEx_Common_mode ADC Extended Independent ADC Mode
<> 144:ef7eb2e8f9f7 372 * @{
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374 #define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /*!< Independent ADC conversions mode */
<> 144:ef7eb2e8f9f7 375 /**
<> 144:ef7eb2e8f9f7 376 * @}
<> 144:ef7eb2e8f9f7 377 */
<> 144:ef7eb2e8f9f7 378
AnnaBridge 167:e84263d55307 379 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
<> 144:ef7eb2e8f9f7 382 * @{
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384 #define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001) /*!< Analog watchdog 1 selection */
<> 144:ef7eb2e8f9f7 385 #define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002) /*!< Analog watchdog 2 selection */
<> 144:ef7eb2e8f9f7 386 #define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003) /*!< Analog watchdog 3 selection */
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @}
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
<> 144:ef7eb2e8f9f7 392 * @{
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) /*!< No analog watchdog selected */
<> 144:ef7eb2e8f9f7 395 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)) /*!< Analog watchdog applied to a regular group single channel */
<> 144:ef7eb2e8f9f7 396 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to an injected group single channel */
<> 144:ef7eb2e8f9f7 397 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to a regular and injected groups single channel */
<> 144:ef7eb2e8f9f7 398 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
<> 144:ef7eb2e8f9f7 399 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */
<> 144:ef7eb2e8f9f7 400 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to regular and injected groups all channels */
<> 144:ef7eb2e8f9f7 401 /**
<> 144:ef7eb2e8f9f7 402 * @}
<> 144:ef7eb2e8f9f7 403 */
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /** @defgroup ADCEx_conversion_group ADC Extended Conversion Group
<> 144:ef7eb2e8f9f7 406 * @{
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) /*!< ADC regular group selection */
<> 144:ef7eb2e8f9f7 409 #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC injected group selection */
<> 144:ef7eb2e8f9f7 410 #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC regular and injected groups selection */
<> 144:ef7eb2e8f9f7 411 /**
<> 144:ef7eb2e8f9f7 412 * @}
<> 144:ef7eb2e8f9f7 413 */
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /** @defgroup ADCEx_Event_type ADC Extended Event Type
<> 144:ef7eb2e8f9f7 416 * @{
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418 #define ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
AnnaBridge 167:e84263d55307 419 #define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
AnnaBridge 167:e84263d55307 420 #define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
AnnaBridge 167:e84263d55307 421 #define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
<> 144:ef7eb2e8f9f7 422 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
<> 144:ef7eb2e8f9f7 423 #define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
<> 144:ef7eb2e8f9f7 424 /**
<> 144:ef7eb2e8f9f7 425 * @}
<> 144:ef7eb2e8f9f7 426 */
AnnaBridge 167:e84263d55307 427 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
<> 144:ef7eb2e8f9f7 430 * @{
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432 #define ADC_IT_RDY ADC_IER_ADRDY /*!< ADC Ready (ADRDY) interrupt source */
<> 144:ef7eb2e8f9f7 433 #define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of sampling interrupt source */
<> 144:ef7eb2e8f9f7 434 #define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of regular conversion interrupt source */
<> 144:ef7eb2e8f9f7 435 #define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of regular sequence of conversions interrupt source */
<> 144:ef7eb2e8f9f7 436 #define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */
<> 144:ef7eb2e8f9f7 437 #define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of injected conversion interrupt source */
<> 144:ef7eb2e8f9f7 438 #define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of injected sequence of conversions interrupt source */
<> 144:ef7eb2e8f9f7 439 #define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
<> 144:ef7eb2e8f9f7 440 #define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
<> 144:ef7eb2e8f9f7 441 #define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
<> 144:ef7eb2e8f9f7 442 #define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /**
<> 144:ef7eb2e8f9f7 447 * @}
<> 144:ef7eb2e8f9f7 448 */
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
<> 144:ef7eb2e8f9f7 451 * @{
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready (ADRDY) flag */
<> 144:ef7eb2e8f9f7 454 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
<> 144:ef7eb2e8f9f7 455 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
<> 144:ef7eb2e8f9f7 456 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
<> 144:ef7eb2e8f9f7 457 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
<> 144:ef7eb2e8f9f7 458 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
<> 144:ef7eb2e8f9f7 459 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
<> 144:ef7eb2e8f9f7 460 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
<> 144:ef7eb2e8f9f7 461 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
<> 144:ef7eb2e8f9f7 462 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
<> 144:ef7eb2e8f9f7 463 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 #define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
<> 144:ef7eb2e8f9f7 468 ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
<> 144:ef7eb2e8f9f7 469 ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /*!< ADC all flags */
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */
<> 144:ef7eb2e8f9f7 472 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
<> 144:ef7eb2e8f9f7 473 ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
<> 144:ef7eb2e8f9f7 474 ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @}
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
<> 144:ef7eb2e8f9f7 482 * @{
<> 144:ef7eb2e8f9f7 483 */
<> 144:ef7eb2e8f9f7 484 #define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /*!< ADC injected conversion rank 1 */
<> 144:ef7eb2e8f9f7 485 #define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /*!< ADC injected conversion rank 2 */
<> 144:ef7eb2e8f9f7 486 #define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /*!< ADC injected conversion rank 3 */
<> 144:ef7eb2e8f9f7 487 #define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /*!< ADC injected conversion rank 4 */
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @}
<> 144:ef7eb2e8f9f7 490 */
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /** @defgroup ADCEx_Oversampling_Ratio ADC Extended Oversampling Ratio
<> 144:ef7eb2e8f9f7 495 * @{
<> 144:ef7eb2e8f9f7 496 */
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 #define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /*!< ADC Oversampling ratio 2x */
<> 144:ef7eb2e8f9f7 499 #define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)ADC_CFGR2_OVSR_0) /*!< ADC Oversampling ratio 4x */
<> 144:ef7eb2e8f9f7 500 #define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)ADC_CFGR2_OVSR_1) /*!< ADC Oversampling ratio 8x */
<> 144:ef7eb2e8f9f7 501 #define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)(ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)) /*!< ADC Oversampling ratio 16x */
<> 144:ef7eb2e8f9f7 502 #define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)ADC_CFGR2_OVSR_2) /*!< ADC Oversampling ratio 32x */
<> 144:ef7eb2e8f9f7 503 #define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)) /*!< ADC Oversampling ratio 64x */
<> 144:ef7eb2e8f9f7 504 #define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1)) /*!< ADC Oversampling ratio 128x */
<> 144:ef7eb2e8f9f7 505 #define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)(ADC_CFGR2_OVSR)) /*!< ADC Oversampling ratio 256x */
<> 144:ef7eb2e8f9f7 506 /**
<> 144:ef7eb2e8f9f7 507 * @}
<> 144:ef7eb2e8f9f7 508 */
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /** @defgroup ADCEx_Right_Bit_Shift ADC Extended Oversampling Right Shift
<> 144:ef7eb2e8f9f7 511 * @{
<> 144:ef7eb2e8f9f7 512 */
<> 144:ef7eb2e8f9f7 513 #define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */
<> 144:ef7eb2e8f9f7 514 #define ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0) /*!< ADC 1 bit shift for oversampling */
<> 144:ef7eb2e8f9f7 515 #define ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1) /*!< ADC 2 bits shift for oversampling */
<> 144:ef7eb2e8f9f7 516 #define ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!< ADC 3 bits shift for oversampling */
<> 144:ef7eb2e8f9f7 517 #define ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2) /*!< ADC 4 bits shift for oversampling */
<> 144:ef7eb2e8f9f7 518 #define ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)) /*!< ADC 5 bits shift for oversampling */
<> 144:ef7eb2e8f9f7 519 #define ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1)) /*!< ADC 6 bits shift for oversampling */
<> 144:ef7eb2e8f9f7 520 #define ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!< ADC 7 bits shift for oversampling */
<> 144:ef7eb2e8f9f7 521 #define ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3) /*!< ADC 8 bits shift for oversampling */
<> 144:ef7eb2e8f9f7 522 /**
<> 144:ef7eb2e8f9f7 523 * @}
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /** @defgroup ADCEx_Triggered_Oversampling_Mode ADC Extended Triggered Regular Oversampling
<> 144:ef7eb2e8f9f7 527 * @{
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /*!< A single trigger for all channel oversampled conversions */
<> 144:ef7eb2e8f9f7 530 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS) /*!< A trigger for each oversampled conversion */
<> 144:ef7eb2e8f9f7 531 /**
<> 144:ef7eb2e8f9f7 532 * @}
<> 144:ef7eb2e8f9f7 533 */
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /** @defgroup ADCEx_Regular_Oversampling_Mode ADC Extended Regular Oversampling Continued or Resumed Mode
<> 144:ef7eb2e8f9f7 536 * @{
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538 #define ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000) /*!< Oversampling buffer maintained during injection sequence */
<> 144:ef7eb2e8f9f7 539 #define ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM) /*!< Oversampling buffer zeroed during injection sequence */
<> 144:ef7eb2e8f9f7 540 /**
<> 144:ef7eb2e8f9f7 541 * @}
<> 144:ef7eb2e8f9f7 542 */
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /** @defgroup ADC_sampling_times ADC Sampling Times
<> 144:ef7eb2e8f9f7 545 * @{
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547 #define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)0x00000000) /*!< Sampling time 2.5 ADC clock cycle */
AnnaBridge 167:e84263d55307 548 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 549 #define ADC_SAMPLETIME_3CYCLES_5 ((uint32_t)ADC_SMPR1_SMPPLUS) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time
AnnaBridge 167:e84263d55307 550 replaces all sampling time 2.5 ADC clock cycles. These 2 sampling
AnnaBridge 167:e84263d55307 551 times cannot be used simultaneously. */
AnnaBridge 167:e84263d55307 552 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
<> 144:ef7eb2e8f9f7 553 #define ADC_SAMPLETIME_6CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 554 #define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 555 #define ADC_SAMPLETIME_24CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 24.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 556 #define ADC_SAMPLETIME_47CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 557 #define ADC_SAMPLETIME_92CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 92.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 558 #define ADC_SAMPLETIME_247CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 247.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 559 #define ADC_SAMPLETIME_640CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10) /*!< Sampling time 640.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 560 /**
<> 144:ef7eb2e8f9f7 561 * @}
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /** @defgroup ADC_CFGR_fields ADCx CFGR fields
<> 144:ef7eb2e8f9f7 565 * @{
<> 144:ef7eb2e8f9f7 566 */
AnnaBridge 167:e84263d55307 567 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 568 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\
AnnaBridge 167:e84263d55307 569 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\
AnnaBridge 167:e84263d55307 570 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\
AnnaBridge 167:e84263d55307 571 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
AnnaBridge 167:e84263d55307 572 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
AnnaBridge 167:e84263d55307 573 ADC_CFGR_RES | ADC_CFGR_DFSDMCFG | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)
AnnaBridge 167:e84263d55307 574 #else
<> 144:ef7eb2e8f9f7 575 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\
<> 144:ef7eb2e8f9f7 576 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\
<> 144:ef7eb2e8f9f7 577 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\
<> 144:ef7eb2e8f9f7 578 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
<> 144:ef7eb2e8f9f7 579 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
<> 144:ef7eb2e8f9f7 580 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
AnnaBridge 167:e84263d55307 581 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
<> 144:ef7eb2e8f9f7 582 /**
<> 144:ef7eb2e8f9f7 583 * @}
<> 144:ef7eb2e8f9f7 584 */
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
<> 144:ef7eb2e8f9f7 587 * @{
<> 144:ef7eb2e8f9f7 588 */
AnnaBridge 167:e84263d55307 589 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 590 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
AnnaBridge 167:e84263d55307 591 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
AnnaBridge 167:e84263d55307 592 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
AnnaBridge 167:e84263d55307 593 ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS)
AnnaBridge 167:e84263d55307 594 #else
<> 144:ef7eb2e8f9f7 595 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
<> 144:ef7eb2e8f9f7 596 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
<> 144:ef7eb2e8f9f7 597 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
<> 144:ef7eb2e8f9f7 598 ADC_SMPR1_SMP0)
AnnaBridge 167:e84263d55307 599 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
<> 144:ef7eb2e8f9f7 600 /**
<> 144:ef7eb2e8f9f7 601 * @}
<> 144:ef7eb2e8f9f7 602 */
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
<> 144:ef7eb2e8f9f7 605 * @{
<> 144:ef7eb2e8f9f7 606 */
<> 144:ef7eb2e8f9f7 607 /* ADC_CFGR fields of parameters that can be updated when no conversion
<> 144:ef7eb2e8f9f7 608 (neither regular nor injected) is on-going */
AnnaBridge 167:e84263d55307 609 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 610 #define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG))
AnnaBridge 167:e84263d55307 611 #else
<> 144:ef7eb2e8f9f7 612 #define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
AnnaBridge 167:e84263d55307 613 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
<> 144:ef7eb2e8f9f7 614 /**
<> 144:ef7eb2e8f9f7 615 * @}
<> 144:ef7eb2e8f9f7 616 */
<> 144:ef7eb2e8f9f7 617
AnnaBridge 167:e84263d55307 618 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 619 /** @defgroup ADCEx_DFSDM_Mode_Configuration ADC Extended DFSDM mode configuration
AnnaBridge 167:e84263d55307 620 * @{
AnnaBridge 167:e84263d55307 621 */
AnnaBridge 167:e84263d55307 622 #define ADC_DFSDM_MODE_DISABLE ((uint32_t)0x00000000) /*!< DFSDM mode configuration disabled */
AnnaBridge 167:e84263d55307 623 #define ADC_DFSDM_MODE_ENABLE ((uint32_t)ADC_CFGR_DFSDMCFG) /*!< DFSDM mode configuration enabled */
AnnaBridge 167:e84263d55307 624 /**
AnnaBridge 167:e84263d55307 625 * @}
AnnaBridge 167:e84263d55307 626 */
AnnaBridge 167:e84263d55307 627 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
AnnaBridge 167:e84263d55307 628
<> 144:ef7eb2e8f9f7 629 /**
<> 144:ef7eb2e8f9f7 630 * @}
<> 144:ef7eb2e8f9f7 631 */
<> 144:ef7eb2e8f9f7 632
AnnaBridge 167:e84263d55307 633 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 634
AnnaBridge 167:e84263d55307 635 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 636 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
AnnaBridge 167:e84263d55307 637 * @{
AnnaBridge 167:e84263d55307 638 */
AnnaBridge 167:e84263d55307 639
AnnaBridge 167:e84263d55307 640 /** @brief Force ADC instance in multimode mode independant (multimode disable).
AnnaBridge 167:e84263d55307 641 * @note This macro must be used only in case of transition from multimode
AnnaBridge 167:e84263d55307 642 * to mode independent and in case of unknown previous state,
AnnaBridge 167:e84263d55307 643 * to ensure ADC configuration is in mode independent.
AnnaBridge 167:e84263d55307 644 * @note Standard way of multimode configuration change is done from
AnnaBridge 167:e84263d55307 645 * HAL ADC handle of ADC master using function
AnnaBridge 167:e84263d55307 646 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
AnnaBridge 167:e84263d55307 647 * Usage of this macro is not the Standard way of multimode
AnnaBridge 167:e84263d55307 648 * configuration and can lead to have HAL ADC handles status
AnnaBridge 167:e84263d55307 649 * misaligned. Usage of this macro must be limited to cases
AnnaBridge 167:e84263d55307 650 * mentionned above.
AnnaBridge 167:e84263d55307 651 * @param __HANDLE__: ADC handle.
AnnaBridge 167:e84263d55307 652 * @retval None
AnnaBridge 167:e84263d55307 653 */
AnnaBridge 167:e84263d55307 654 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \
AnnaBridge 167:e84263d55307 655 CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_DUAL)
AnnaBridge 167:e84263d55307 656
AnnaBridge 167:e84263d55307 657 /**
AnnaBridge 167:e84263d55307 658 * @}
AnnaBridge 167:e84263d55307 659 */
AnnaBridge 167:e84263d55307 660 #endif
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* Private macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
<> 144:ef7eb2e8f9f7 665 * @{
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /**
<> 144:ef7eb2e8f9f7 669 * @brief Test if conversion trigger of injected group is software start
<> 144:ef7eb2e8f9f7 670 * or external trigger.
<> 144:ef7eb2e8f9f7 671 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 672 * @retval SET (software start) or RESET (external trigger).
<> 144:ef7eb2e8f9f7 673 */
<> 144:ef7eb2e8f9f7 674 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
<> 144:ef7eb2e8f9f7 675 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /**
<> 144:ef7eb2e8f9f7 678 * @brief Check if conversion is on going on regular or injected groups.
<> 144:ef7eb2e8f9f7 679 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 680 * @retval SET (conversion is on going) or RESET (no conversion is on going).
<> 144:ef7eb2e8f9f7 681 */
<> 144:ef7eb2e8f9f7 682 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
<> 144:ef7eb2e8f9f7 683 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \
<> 144:ef7eb2e8f9f7 684 ) ? RESET : SET)
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /**
<> 144:ef7eb2e8f9f7 687 * @brief Check if conversion is on going on injected group.
<> 144:ef7eb2e8f9f7 688 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 689 * @retval SET (conversion is on going) or RESET (no conversion is on going).
<> 144:ef7eb2e8f9f7 690 */
<> 144:ef7eb2e8f9f7 691 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
<> 144:ef7eb2e8f9f7 692 (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \
<> 144:ef7eb2e8f9f7 693 ) ? RESET : SET)
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /**
<> 144:ef7eb2e8f9f7 696 * @brief Check whether or not ADC is independent.
<> 144:ef7eb2e8f9f7 697 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 698 * @note When multimode feature is not available, the macro always returns SET.
<> 144:ef7eb2e8f9f7 699 * @retval SET (ADC is independent) or RESET (ADC is not).
<> 144:ef7eb2e8f9f7 700 */
AnnaBridge 167:e84263d55307 701 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 702 #define ADC_IS_INDEPENDENT(__HANDLE__) \
<> 144:ef7eb2e8f9f7 703 ( ( ( ((__HANDLE__)->Instance) == ADC3) \
<> 144:ef7eb2e8f9f7 704 )? \
<> 144:ef7eb2e8f9f7 705 SET \
<> 144:ef7eb2e8f9f7 706 : \
<> 144:ef7eb2e8f9f7 707 RESET \
<> 144:ef7eb2e8f9f7 708 )
AnnaBridge 167:e84263d55307 709 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 710 #define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
<> 144:ef7eb2e8f9f7 711 #endif
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /**
<> 144:ef7eb2e8f9f7 714 * @brief Set the sample time for Channels numbers between 0 and 9.
<> 144:ef7eb2e8f9f7 715 * @param __SAMPLETIME__: Sample time parameter.
<> 144:ef7eb2e8f9f7 716 * @param __CHANNELNB__: Channel number.
<> 144:ef7eb2e8f9f7 717 * @retval None
<> 144:ef7eb2e8f9f7 718 */
<> 144:ef7eb2e8f9f7 719 #define ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /**
<> 144:ef7eb2e8f9f7 722 * @brief Set the sample time for Channels numbers between 10 and 18.
<> 144:ef7eb2e8f9f7 723 * @param __SAMPLETIME__: Sample time parameter.
<> 144:ef7eb2e8f9f7 724 * @param __CHANNELNB__: Channel number.
<> 144:ef7eb2e8f9f7 725 * @retval None
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727 #define ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /**
<> 144:ef7eb2e8f9f7 730 * @brief Write SMPR1 register.
<> 144:ef7eb2e8f9f7 731 * @param __HANDLE__ : ADC handle.
<> 144:ef7eb2e8f9f7 732 * @param __SAMPLETIME__: Sample time parameter.
<> 144:ef7eb2e8f9f7 733 * @param __CHANNELNB__ : Channel number.
<> 144:ef7eb2e8f9f7 734 * @retval None
<> 144:ef7eb2e8f9f7 735 */
AnnaBridge 167:e84263d55307 736 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 737 #define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \
AnnaBridge 167:e84263d55307 738 do { \
AnnaBridge 167:e84263d55307 739 if((__SAMPLETIME__) == ADC_SAMPLETIME_3CYCLES_5) \
AnnaBridge 167:e84263d55307 740 { \
AnnaBridge 167:e84263d55307 741 SET_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \
AnnaBridge 167:e84263d55307 742 } \
AnnaBridge 167:e84263d55307 743 else if ((__SAMPLETIME__) == ADC_SAMPLETIME_2CYCLES_5) \
AnnaBridge 167:e84263d55307 744 { \
AnnaBridge 167:e84263d55307 745 CLEAR_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \
AnnaBridge 167:e84263d55307 746 } \
AnnaBridge 167:e84263d55307 747 MODIFY_REG((__HANDLE__)->Instance->SMPR1, \
AnnaBridge 167:e84263d55307 748 ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)), \
AnnaBridge 167:e84263d55307 749 ADC_SMPR1((__SAMPLETIME__) & 0x7FFFFFFF, (__CHANNELNB__))); \
AnnaBridge 167:e84263d55307 750 } while(0)
AnnaBridge 167:e84263d55307 751 #else
<> 144:ef7eb2e8f9f7 752 #define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \
<> 144:ef7eb2e8f9f7 753 MODIFY_REG((__HANDLE__)->Instance->SMPR1, \
<> 144:ef7eb2e8f9f7 754 ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)), \
<> 144:ef7eb2e8f9f7 755 ADC_SMPR1((__SAMPLETIME__), (__CHANNELNB__)))
AnnaBridge 167:e84263d55307 756 #endif
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /**
<> 144:ef7eb2e8f9f7 759 * @brief Write SMPR2 register.
<> 144:ef7eb2e8f9f7 760 * @param __HANDLE__ : ADC handle.
<> 144:ef7eb2e8f9f7 761 * @param __SAMPLETIME__: Sample time parameter.
<> 144:ef7eb2e8f9f7 762 * @param __CHANNELNB__ : Channel number.
<> 144:ef7eb2e8f9f7 763 * @retval None
<> 144:ef7eb2e8f9f7 764 */
AnnaBridge 167:e84263d55307 765 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 766 #define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \
AnnaBridge 167:e84263d55307 767 do { \
AnnaBridge 167:e84263d55307 768 if((__SAMPLETIME__) == ADC_SAMPLETIME_3CYCLES_5) \
AnnaBridge 167:e84263d55307 769 { \
AnnaBridge 167:e84263d55307 770 SET_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \
AnnaBridge 167:e84263d55307 771 } \
AnnaBridge 167:e84263d55307 772 else if ((__SAMPLETIME__) == ADC_SAMPLETIME_2CYCLES_5) \
AnnaBridge 167:e84263d55307 773 { \
AnnaBridge 167:e84263d55307 774 CLEAR_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \
AnnaBridge 167:e84263d55307 775 } \
AnnaBridge 167:e84263d55307 776 MODIFY_REG((__HANDLE__)->Instance->SMPR2, \
AnnaBridge 167:e84263d55307 777 ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)), \
AnnaBridge 167:e84263d55307 778 ADC_SMPR2((__SAMPLETIME__) & 0x7FFFFFFF, (__CHANNELNB__))); \
AnnaBridge 167:e84263d55307 779 } while(0)
AnnaBridge 167:e84263d55307 780 #else
<> 144:ef7eb2e8f9f7 781 #define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \
<> 144:ef7eb2e8f9f7 782 MODIFY_REG((__HANDLE__)->Instance->SMPR2, \
<> 144:ef7eb2e8f9f7 783 ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)), \
<> 144:ef7eb2e8f9f7 784 ADC_SMPR2((__SAMPLETIME__), (__CHANNELNB__)))
AnnaBridge 167:e84263d55307 785 #endif
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /**
<> 144:ef7eb2e8f9f7 789 * @brief Set the selected regular Channel rank for rank between 1 and 4.
<> 144:ef7eb2e8f9f7 790 * @param __CHANNELNB__: Channel number.
<> 144:ef7eb2e8f9f7 791 * @param __RANKNB__: Rank number.
<> 144:ef7eb2e8f9f7 792 * @retval None
<> 144:ef7eb2e8f9f7 793 */
<> 144:ef7eb2e8f9f7 794 #define ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /**
<> 144:ef7eb2e8f9f7 797 * @brief Set the selected regular Channel rank for rank between 5 and 9.
<> 144:ef7eb2e8f9f7 798 * @param __CHANNELNB__: Channel number.
<> 144:ef7eb2e8f9f7 799 * @param __RANKNB__: Rank number.
<> 144:ef7eb2e8f9f7 800 * @retval None
<> 144:ef7eb2e8f9f7 801 */
<> 144:ef7eb2e8f9f7 802 #define ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /**
<> 144:ef7eb2e8f9f7 805 * @brief Set the selected regular Channel rank for rank between 10 and 14.
<> 144:ef7eb2e8f9f7 806 * @param __CHANNELNB__: Channel number.
<> 144:ef7eb2e8f9f7 807 * @param __RANKNB__: Rank number.
<> 144:ef7eb2e8f9f7 808 * @retval None
<> 144:ef7eb2e8f9f7 809 */
<> 144:ef7eb2e8f9f7 810 #define ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /**
<> 144:ef7eb2e8f9f7 813 * @brief Set the selected regular Channel rank for rank between 15 and 16.
<> 144:ef7eb2e8f9f7 814 * @param __CHANNELNB__: Channel number.
<> 144:ef7eb2e8f9f7 815 * @param __RANKNB__: Rank number.
<> 144:ef7eb2e8f9f7 816 * @retval None
<> 144:ef7eb2e8f9f7 817 */
<> 144:ef7eb2e8f9f7 818 #define ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /**
<> 144:ef7eb2e8f9f7 821 * @brief Set the selected injected Channel rank.
<> 144:ef7eb2e8f9f7 822 * @param __CHANNELNB__: Channel number.
<> 144:ef7eb2e8f9f7 823 * @param __RANKNB__: Rank number.
<> 144:ef7eb2e8f9f7 824 * @retval None
<> 144:ef7eb2e8f9f7 825 */
<> 144:ef7eb2e8f9f7 826 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-2) * (__RANKNB__) +2))
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /**
<> 144:ef7eb2e8f9f7 830 * @brief Set the Analog Watchdog 1 channel.
<> 144:ef7eb2e8f9f7 831 * @param __CHANNEL__: channel to be monitored by Analog Watchdog 1.
<> 144:ef7eb2e8f9f7 832 * @retval None
<> 144:ef7eb2e8f9f7 833 */
<> 144:ef7eb2e8f9f7 834 #define ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /**
<> 144:ef7eb2e8f9f7 837 * @brief Configure the channel number in Analog Watchdog 2 or 3.
<> 144:ef7eb2e8f9f7 838 * @param __CHANNEL__: ADC Channel
<> 144:ef7eb2e8f9f7 839 * @retval None
<> 144:ef7eb2e8f9f7 840 */
<> 144:ef7eb2e8f9f7 841 #define ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__))
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /**
<> 144:ef7eb2e8f9f7 844 * @brief Configure ADC injected context queue
<> 144:ef7eb2e8f9f7 845 * @param __INJECT_CONTEXT_QUEUE_MODE__: Injected context queue mode.
<> 144:ef7eb2e8f9f7 846 * @retval None
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /**
<> 144:ef7eb2e8f9f7 851 * @brief Configure ADC discontinuous conversion mode for injected group
<> 144:ef7eb2e8f9f7 852 * @param __INJECT_DISCONTINUOUS_MODE__: Injected discontinuous mode.
<> 144:ef7eb2e8f9f7 853 * @retval None
<> 144:ef7eb2e8f9f7 854 */
<> 144:ef7eb2e8f9f7 855 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_JDISCEN))
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /**
<> 144:ef7eb2e8f9f7 858 * @brief Configure ADC discontinuous conversion mode for regular group
<> 144:ef7eb2e8f9f7 859 * @param __REG_DISCONTINUOUS_MODE__: Regular discontinuous mode.
<> 144:ef7eb2e8f9f7 860 * @retval None
<> 144:ef7eb2e8f9f7 861 */
<> 144:ef7eb2e8f9f7 862 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))
<> 144:ef7eb2e8f9f7 863 /**
<> 144:ef7eb2e8f9f7 864 * @brief Configure the number of discontinuous conversions for regular group.
<> 144:ef7eb2e8f9f7 865 * @param __NBR_DISCONTINUOUS_CONV__: Number of discontinuous conversions.
<> 144:ef7eb2e8f9f7 866 * @retval None
<> 144:ef7eb2e8f9f7 867 */
<> 144:ef7eb2e8f9f7 868 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 /**
<> 144:ef7eb2e8f9f7 871 * @brief Configure the ADC auto delay mode.
<> 144:ef7eb2e8f9f7 872 * @param __AUTOWAIT__: Auto delay bit enable or disable.
<> 144:ef7eb2e8f9f7 873 * @retval None
<> 144:ef7eb2e8f9f7 874 */
<> 144:ef7eb2e8f9f7 875 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /**
<> 144:ef7eb2e8f9f7 878 * @brief Configure ADC continuous conversion mode.
<> 144:ef7eb2e8f9f7 879 * @param __CONTINUOUS_MODE__: Continuous mode.
<> 144:ef7eb2e8f9f7 880 * @retval None
<> 144:ef7eb2e8f9f7 881 */
<> 144:ef7eb2e8f9f7 882 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /**
<> 144:ef7eb2e8f9f7 885 * @brief Configure the ADC DMA continuous request.
<> 144:ef7eb2e8f9f7 886 * @param __DMACONTREQ_MODE__: DMA continuous request mode.
<> 144:ef7eb2e8f9f7 887 * @retval None
<> 144:ef7eb2e8f9f7 888 */
<> 144:ef7eb2e8f9f7 889 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CFGR_DMACFG))
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /**
<> 144:ef7eb2e8f9f7 893 * @brief Configure the channel number into offset OFRx register.
<> 144:ef7eb2e8f9f7 894 * @param __CHANNEL__: ADC Channel.
<> 144:ef7eb2e8f9f7 895 * @retval None
<> 144:ef7eb2e8f9f7 896 */
<> 144:ef7eb2e8f9f7 897 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 /**
<> 144:ef7eb2e8f9f7 900 * @brief Configure the channel number into differential mode selection register.
<> 144:ef7eb2e8f9f7 901 * @param __CHANNEL__: ADC Channel.
<> 144:ef7eb2e8f9f7 902 * @retval None
<> 144:ef7eb2e8f9f7 903 */
<> 144:ef7eb2e8f9f7 904 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__))
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 /**
<> 144:ef7eb2e8f9f7 907 * @brief Configure calibration factor in differential mode to be set into calibration register.
<> 144:ef7eb2e8f9f7 908 * @param __CALIBRATION_FACTOR__: Calibration factor value.
<> 144:ef7eb2e8f9f7 909 * @retval None
<> 144:ef7eb2e8f9f7 910 */
<> 144:ef7eb2e8f9f7 911 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))
<> 144:ef7eb2e8f9f7 912 /**
<> 144:ef7eb2e8f9f7 913 * @brief Calibration factor in differential mode to be retrieved from calibration register.
<> 144:ef7eb2e8f9f7 914 * @param __CALIBRATION_FACTOR__: Calibration factor value.
<> 144:ef7eb2e8f9f7 915 * @retval None
<> 144:ef7eb2e8f9f7 916 */
<> 144:ef7eb2e8f9f7 917 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /**
<> 144:ef7eb2e8f9f7 920 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
<> 144:ef7eb2e8f9f7 921 * @param __THRESHOLD__: Threshold value.
<> 144:ef7eb2e8f9f7 922 * @retval None
<> 144:ef7eb2e8f9f7 923 */
<> 144:ef7eb2e8f9f7 924 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
<> 144:ef7eb2e8f9f7 925
AnnaBridge 167:e84263d55307 926 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 927 /**
<> 144:ef7eb2e8f9f7 928 * @brief Configure the ADC DMA continuous request for ADC multimode.
<> 144:ef7eb2e8f9f7 929 * @param __DMACONTREQ_MODE__: DMA continuous request mode.
<> 144:ef7eb2e8f9f7 930 * @retval None
<> 144:ef7eb2e8f9f7 931 */
<> 144:ef7eb2e8f9f7 932 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))
AnnaBridge 167:e84263d55307 933 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /**
<> 144:ef7eb2e8f9f7 936 * @brief Enable the ADC peripheral.
<> 144:ef7eb2e8f9f7 937 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 938 * @retval None
<> 144:ef7eb2e8f9f7 939 */
<> 144:ef7eb2e8f9f7 940 #define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 /**
<> 144:ef7eb2e8f9f7 943 * @brief Verification of hardware constraints before ADC can be enabled.
<> 144:ef7eb2e8f9f7 944 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 945 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
<> 144:ef7eb2e8f9f7 946 */
<> 144:ef7eb2e8f9f7 947 #define ADC_ENABLING_CONDITIONS(__HANDLE__) \
<> 144:ef7eb2e8f9f7 948 (( ( ((__HANDLE__)->Instance->CR) & \
<> 144:ef7eb2e8f9f7 949 (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | \
<> 144:ef7eb2e8f9f7 950 ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \
<> 144:ef7eb2e8f9f7 951 ) == RESET \
<> 144:ef7eb2e8f9f7 952 ) ? SET : RESET)
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /**
<> 144:ef7eb2e8f9f7 955 * @brief Disable the ADC peripheral.
<> 144:ef7eb2e8f9f7 956 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 957 * @retval None
<> 144:ef7eb2e8f9f7 958 */
<> 144:ef7eb2e8f9f7 959 #define ADC_DISABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 960 do{ \
<> 144:ef7eb2e8f9f7 961 (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \
<> 144:ef7eb2e8f9f7 962 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
<> 144:ef7eb2e8f9f7 963 } while(0)
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 /**
<> 144:ef7eb2e8f9f7 966 * @brief Verification of hardware constraints before ADC can be disabled.
<> 144:ef7eb2e8f9f7 967 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 968 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
<> 144:ef7eb2e8f9f7 969 */
<> 144:ef7eb2e8f9f7 970 #define ADC_DISABLING_CONDITIONS(__HANDLE__) \
<> 144:ef7eb2e8f9f7 971 (( ( ((__HANDLE__)->Instance->CR) & \
<> 144:ef7eb2e8f9f7 972 (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
<> 144:ef7eb2e8f9f7 973 ) ? SET : RESET)
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 /**
<> 144:ef7eb2e8f9f7 976 * @brief Shift the offset with respect to the selected ADC resolution.
<> 144:ef7eb2e8f9f7 977 * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
<> 144:ef7eb2e8f9f7 978 * If resolution 12 bits, no shift.
<> 144:ef7eb2e8f9f7 979 * If resolution 10 bits, shift of 2 ranks on the left.
<> 144:ef7eb2e8f9f7 980 * If resolution 8 bits, shift of 4 ranks on the left.
<> 144:ef7eb2e8f9f7 981 * If resolution 6 bits, shift of 6 ranks on the left.
<> 144:ef7eb2e8f9f7 982 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
<> 144:ef7eb2e8f9f7 983 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 984 * @param __OFFSET__: Value to be shifted
<> 144:ef7eb2e8f9f7 985 * @retval None
<> 144:ef7eb2e8f9f7 986 */
<> 144:ef7eb2e8f9f7 987 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
<> 144:ef7eb2e8f9f7 988 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /**
<> 144:ef7eb2e8f9f7 992 * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
<> 144:ef7eb2e8f9f7 993 * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
<> 144:ef7eb2e8f9f7 994 * If resolution 12 bits, no shift.
<> 144:ef7eb2e8f9f7 995 * If resolution 10 bits, shift of 2 ranks on the left.
<> 144:ef7eb2e8f9f7 996 * If resolution 8 bits, shift of 4 ranks on the left.
<> 144:ef7eb2e8f9f7 997 * If resolution 6 bits, shift of 6 ranks on the left.
<> 144:ef7eb2e8f9f7 998 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
<> 144:ef7eb2e8f9f7 999 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 1000 * @param __THRESHOLD__: Value to be shifted
<> 144:ef7eb2e8f9f7 1001 * @retval None
<> 144:ef7eb2e8f9f7 1002 */
<> 144:ef7eb2e8f9f7 1003 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
<> 144:ef7eb2e8f9f7 1004 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 /**
<> 144:ef7eb2e8f9f7 1007 * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
<> 144:ef7eb2e8f9f7 1008 * @note Thresholds have to be left-aligned on bit 7.
<> 144:ef7eb2e8f9f7 1009 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
<> 144:ef7eb2e8f9f7 1010 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
<> 144:ef7eb2e8f9f7 1011 * If resolution 8 bits, no shift.
<> 144:ef7eb2e8f9f7 1012 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
<> 144:ef7eb2e8f9f7 1013 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 1014 * @param __THRESHOLD__: Value to be shifted
<> 144:ef7eb2e8f9f7 1015 * @retval None
<> 144:ef7eb2e8f9f7 1016 */
<> 144:ef7eb2e8f9f7 1017 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
<> 144:ef7eb2e8f9f7 1018 ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \
<> 144:ef7eb2e8f9f7 1019 ((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
<> 144:ef7eb2e8f9f7 1020 (__THRESHOLD__) << 2 )
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 /**
<> 144:ef7eb2e8f9f7 1023 * @brief Report ADC common register.
<> 144:ef7eb2e8f9f7 1024 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1025 * @retval Common control register
<> 144:ef7eb2e8f9f7 1026 */
AnnaBridge 167:e84263d55307 1027 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1028 #define ADC_COMMON_REGISTER(__HANDLE__) (ADC123_COMMON)
AnnaBridge 167:e84263d55307 1029 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1030 #define ADC_COMMON_REGISTER(__HANDLE__) (ADC1_COMMON)
<> 144:ef7eb2e8f9f7 1031 #endif
<> 144:ef7eb2e8f9f7 1032
<> 144:ef7eb2e8f9f7 1033 /**
<> 144:ef7eb2e8f9f7 1034 * @brief Report Master Instance.
<> 144:ef7eb2e8f9f7 1035 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1036 * @note Return same instance if ADC of input handle is independent ADC or if
<> 144:ef7eb2e8f9f7 1037 * multimode feature is not available.
<> 144:ef7eb2e8f9f7 1038 * @retval Master Instance
<> 144:ef7eb2e8f9f7 1039 */
AnnaBridge 167:e84263d55307 1040 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1041 #define ADC_MASTER_REGISTER(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1042 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
<> 144:ef7eb2e8f9f7 1043 )? \
<> 144:ef7eb2e8f9f7 1044 ((__HANDLE__)->Instance) \
<> 144:ef7eb2e8f9f7 1045 : \
<> 144:ef7eb2e8f9f7 1046 (ADC1) \
<> 144:ef7eb2e8f9f7 1047 )
AnnaBridge 167:e84263d55307 1048 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1049 #define ADC_MASTER_REGISTER(__HANDLE__) ((__HANDLE__)->Instance)
<> 144:ef7eb2e8f9f7 1050 #endif
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 /**
<> 144:ef7eb2e8f9f7 1053 * @brief Clear Common Control Register.
<> 144:ef7eb2e8f9f7 1054 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1055 * @retval None
<> 144:ef7eb2e8f9f7 1056 */
AnnaBridge 167:e84263d55307 1057 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1058 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \
<> 144:ef7eb2e8f9f7 1059 ADC_CCR_PRESC | \
<> 144:ef7eb2e8f9f7 1060 ADC_CCR_VBATEN | \
<> 144:ef7eb2e8f9f7 1061 ADC_CCR_TSEN | \
<> 144:ef7eb2e8f9f7 1062 ADC_CCR_VREFEN | \
<> 144:ef7eb2e8f9f7 1063 ADC_CCR_MDMA | \
<> 144:ef7eb2e8f9f7 1064 ADC_CCR_DMACFG | \
<> 144:ef7eb2e8f9f7 1065 ADC_CCR_DELAY | \
<> 144:ef7eb2e8f9f7 1066 ADC_CCR_DUAL )
AnnaBridge 167:e84263d55307 1067 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1068 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \
<> 144:ef7eb2e8f9f7 1069 ADC_CCR_PRESC | \
<> 144:ef7eb2e8f9f7 1070 ADC_CCR_VBATEN | \
<> 144:ef7eb2e8f9f7 1071 ADC_CCR_TSEN | \
<> 144:ef7eb2e8f9f7 1072 ADC_CCR_VREFEN )
<> 144:ef7eb2e8f9f7 1073 #endif
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 /**
<> 144:ef7eb2e8f9f7 1077 * @brief Check whether or not dual conversions are enabled.
<> 144:ef7eb2e8f9f7 1078 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1079 * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.
<> 144:ef7eb2e8f9f7 1080 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
<> 144:ef7eb2e8f9f7 1081 */
AnnaBridge 167:e84263d55307 1082 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1083 #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1084 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
<> 144:ef7eb2e8f9f7 1085 )? \
<> 144:ef7eb2e8f9f7 1086 ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) ) \
<> 144:ef7eb2e8f9f7 1087 : \
<> 144:ef7eb2e8f9f7 1088 RESET \
<> 144:ef7eb2e8f9f7 1089 )
AnnaBridge 167:e84263d55307 1090 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1091 #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) (RESET)
<> 144:ef7eb2e8f9f7 1092 #endif
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 /**
<> 144:ef7eb2e8f9f7 1095 * @brief Check whether or not dual regular conversions are enabled.
<> 144:ef7eb2e8f9f7 1096 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1097 * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.
<> 144:ef7eb2e8f9f7 1098 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
<> 144:ef7eb2e8f9f7 1099 */
AnnaBridge 167:e84263d55307 1100 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1101 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1102 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
<> 144:ef7eb2e8f9f7 1103 )? \
<> 144:ef7eb2e8f9f7 1104 ( (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
<> 144:ef7eb2e8f9f7 1105 (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
<> 144:ef7eb2e8f9f7 1106 (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
<> 144:ef7eb2e8f9f7 1107 : \
<> 144:ef7eb2e8f9f7 1108 RESET \
<> 144:ef7eb2e8f9f7 1109 )
AnnaBridge 167:e84263d55307 1110 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1111 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) (RESET)
<> 144:ef7eb2e8f9f7 1112 #endif
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /**
<> 144:ef7eb2e8f9f7 1116 * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master.
<> 144:ef7eb2e8f9f7 1117 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1118 * @note Return SET if multimode feature is not available.
<> 144:ef7eb2e8f9f7 1119 * @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode)
<> 144:ef7eb2e8f9f7 1120 */
AnnaBridge 167:e84263d55307 1121 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1122 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1123 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
<> 144:ef7eb2e8f9f7 1124 )? \
<> 144:ef7eb2e8f9f7 1125 SET \
<> 144:ef7eb2e8f9f7 1126 : \
<> 144:ef7eb2e8f9f7 1127 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
<> 144:ef7eb2e8f9f7 1128 )
AnnaBridge 167:e84263d55307 1129 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1130 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (SET)
<> 144:ef7eb2e8f9f7 1131 #endif
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 /**
<> 144:ef7eb2e8f9f7 1134 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
<> 144:ef7eb2e8f9f7 1135 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1136 * @note Return SET if multimode feature is not available.
<> 144:ef7eb2e8f9f7 1137 * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
<> 144:ef7eb2e8f9f7 1138 */
AnnaBridge 167:e84263d55307 1139 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1140 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1141 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
<> 144:ef7eb2e8f9f7 1142 )? \
<> 144:ef7eb2e8f9f7 1143 SET \
<> 144:ef7eb2e8f9f7 1144 : \
<> 144:ef7eb2e8f9f7 1145 ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
<> 144:ef7eb2e8f9f7 1146 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
<> 144:ef7eb2e8f9f7 1147 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
AnnaBridge 167:e84263d55307 1148 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1149 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) (SET)
<> 144:ef7eb2e8f9f7 1150 #endif
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 /**
<> 144:ef7eb2e8f9f7 1153 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
<> 144:ef7eb2e8f9f7 1154 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1155 * @note Return SET if multimode feature is not available.
<> 144:ef7eb2e8f9f7 1156 * @retval SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
<> 144:ef7eb2e8f9f7 1157 */
AnnaBridge 167:e84263d55307 1158 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1159 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1160 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
<> 144:ef7eb2e8f9f7 1161 )? \
<> 144:ef7eb2e8f9f7 1162 SET \
<> 144:ef7eb2e8f9f7 1163 : \
<> 144:ef7eb2e8f9f7 1164 ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
<> 144:ef7eb2e8f9f7 1165 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
<> 144:ef7eb2e8f9f7 1166 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
AnnaBridge 167:e84263d55307 1167 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1168 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) (SET)
<> 144:ef7eb2e8f9f7 1169 #endif
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /**
<> 144:ef7eb2e8f9f7 1172 * @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.
<> 144:ef7eb2e8f9f7 1173 * @param __INSTANCE__: ADC instance.
<> 144:ef7eb2e8f9f7 1174 * @retval SET (ADC enabled) or RESET (ADC disabled)
<> 144:ef7eb2e8f9f7 1175 */
<> 144:ef7eb2e8f9f7 1176 #define ADC_INSTANCE_IS_ENABLED(__INSTANCE__) \
<> 144:ef7eb2e8f9f7 1177 (( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
<> 144:ef7eb2e8f9f7 1178 ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
<> 144:ef7eb2e8f9f7 1179 ) ? SET : RESET)
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 /**
<> 144:ef7eb2e8f9f7 1182 * @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.
<> 144:ef7eb2e8f9f7 1183 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1184 * @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled)
<> 144:ef7eb2e8f9f7 1185 */
AnnaBridge 167:e84263d55307 1186 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1187 #define ADC_ANY_OTHER_ENABLED(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1188 ( ( ((__HANDLE__)->Instance == ADC1) \
<> 144:ef7eb2e8f9f7 1189 )? \
<> 144:ef7eb2e8f9f7 1190 (ADC_INSTANCE_IS_ENABLED(ADC2)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \
<> 144:ef7eb2e8f9f7 1191 : \
<> 144:ef7eb2e8f9f7 1192 ( ( ((__HANDLE__)->Instance == ADC2) \
<> 144:ef7eb2e8f9f7 1193 )? \
<> 144:ef7eb2e8f9f7 1194 (ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \
<> 144:ef7eb2e8f9f7 1195 : \
<> 144:ef7eb2e8f9f7 1196 ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2)) \
<> 144:ef7eb2e8f9f7 1197 )
AnnaBridge 167:e84263d55307 1198 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1199 #define ADC_ANY_OTHER_ENABLED(__HANDLE__) (RESET)
<> 144:ef7eb2e8f9f7 1200 #endif
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202
AnnaBridge 167:e84263d55307 1203 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1204 /**
<> 144:ef7eb2e8f9f7 1205 * @brief Set handle instance of the ADC slave associated to the ADC master.
<> 144:ef7eb2e8f9f7 1206 * @param __HANDLE_MASTER__: ADC master handle.
<> 144:ef7eb2e8f9f7 1207 * @param __HANDLE_SLAVE__: ADC slave handle.
<> 144:ef7eb2e8f9f7 1208 * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC (ADC3), __HANDLE_SLAVE__ instance is set to NULL.
<> 144:ef7eb2e8f9f7 1209 * @retval None
<> 144:ef7eb2e8f9f7 1210 */
<> 144:ef7eb2e8f9f7 1211 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
<> 144:ef7eb2e8f9f7 1212 ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
<> 144:ef7eb2e8f9f7 1213 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215
<> 144:ef7eb2e8f9f7 1216 /**
<> 144:ef7eb2e8f9f7 1217 * @brief Check whether or not multimode is configured in DMA mode.
<> 144:ef7eb2e8f9f7 1218 * @note Return RESET if multimode feature is not available.
<> 144:ef7eb2e8f9f7 1219 * @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled)
<> 144:ef7eb2e8f9f7 1220 */
AnnaBridge 167:e84263d55307 1221 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1222 #define ADC_MULTIMODE_DMA_ENABLED() \
<> 144:ef7eb2e8f9f7 1223 ((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \
<> 144:ef7eb2e8f9f7 1224 || (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS))
AnnaBridge 167:e84263d55307 1225 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1226 #define ADC_MULTIMODE_DMA_ENABLED() (RESET)
<> 144:ef7eb2e8f9f7 1227 #endif
<> 144:ef7eb2e8f9f7 1228
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230 /**
<> 144:ef7eb2e8f9f7 1231 * @brief Verify the ADC instance connected to the temperature sensor.
<> 144:ef7eb2e8f9f7 1232 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1233 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
<> 144:ef7eb2e8f9f7 1234 */
AnnaBridge 167:e84263d55307 1235 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1236 /* The temperature sensor measurement path (channel 17) is available on ADC1 */
<> 144:ef7eb2e8f9f7 1237 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
AnnaBridge 167:e84263d55307 1238 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1239 /* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */
<> 144:ef7eb2e8f9f7 1240 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
<> 144:ef7eb2e8f9f7 1241 #endif
<> 144:ef7eb2e8f9f7 1242
<> 144:ef7eb2e8f9f7 1243 /**
<> 144:ef7eb2e8f9f7 1244 * @brief Verify the ADC instance connected to the battery voltage VBAT.
<> 144:ef7eb2e8f9f7 1245 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1246 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
<> 144:ef7eb2e8f9f7 1247 */
AnnaBridge 167:e84263d55307 1248 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1249 /* The battery voltage measurement path (channel 18) is available on ADC1 */
<> 144:ef7eb2e8f9f7 1250 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
AnnaBridge 167:e84263d55307 1251 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1252 /* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */
<> 144:ef7eb2e8f9f7 1253 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
<> 144:ef7eb2e8f9f7 1254 #endif
<> 144:ef7eb2e8f9f7 1255
<> 144:ef7eb2e8f9f7 1256 /**
<> 144:ef7eb2e8f9f7 1257 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
<> 144:ef7eb2e8f9f7 1258 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1259 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
<> 144:ef7eb2e8f9f7 1260 */
<> 144:ef7eb2e8f9f7 1261 /* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */
<> 144:ef7eb2e8f9f7 1262 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
<> 144:ef7eb2e8f9f7 1263
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 /**
<> 144:ef7eb2e8f9f7 1266 * @brief Verify the length of scheduled injected conversions group.
<> 144:ef7eb2e8f9f7 1267 * @param __LENGTH__: number of programmed conversions.
<> 144:ef7eb2e8f9f7 1268 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
<> 144:ef7eb2e8f9f7 1269 */
<> 144:ef7eb2e8f9f7 1270 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272
<> 144:ef7eb2e8f9f7 1273 /**
<> 144:ef7eb2e8f9f7 1274 * @brief Calibration factor size verification (7 bits maximum).
<> 144:ef7eb2e8f9f7 1275 * @param __CALIBRATION_FACTOR__: Calibration factor value.
<> 144:ef7eb2e8f9f7 1276 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
<> 144:ef7eb2e8f9f7 1277 */
<> 144:ef7eb2e8f9f7 1278 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= ((uint32_t)0x7F))
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 /**
<> 144:ef7eb2e8f9f7 1282 * @brief Verify the ADC channel setting.
<> 144:ef7eb2e8f9f7 1283 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1284 * @param __CHANNEL__: programmed ADC channel.
<> 144:ef7eb2e8f9f7 1285 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
<> 144:ef7eb2e8f9f7 1286 */
AnnaBridge 167:e84263d55307 1287 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1288 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \
<> 144:ef7eb2e8f9f7 1289 (((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
<> 144:ef7eb2e8f9f7 1290 ((__CHANNEL__) == ADC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1291 ((__CHANNEL__) == ADC_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 1292 ((__CHANNEL__) == ADC_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 1293 ((__CHANNEL__) == ADC_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 1294 ((__CHANNEL__) == ADC_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 1295 ((__CHANNEL__) == ADC_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 1296 ((__CHANNEL__) == ADC_CHANNEL_7) || \
<> 144:ef7eb2e8f9f7 1297 ((__CHANNEL__) == ADC_CHANNEL_8) || \
<> 144:ef7eb2e8f9f7 1298 ((__CHANNEL__) == ADC_CHANNEL_9) || \
<> 144:ef7eb2e8f9f7 1299 ((__CHANNEL__) == ADC_CHANNEL_10) || \
<> 144:ef7eb2e8f9f7 1300 ((__CHANNEL__) == ADC_CHANNEL_11) || \
<> 144:ef7eb2e8f9f7 1301 ((__CHANNEL__) == ADC_CHANNEL_12) || \
<> 144:ef7eb2e8f9f7 1302 ((__CHANNEL__) == ADC_CHANNEL_13) || \
<> 144:ef7eb2e8f9f7 1303 ((__CHANNEL__) == ADC_CHANNEL_14) || \
<> 144:ef7eb2e8f9f7 1304 ((__CHANNEL__) == ADC_CHANNEL_15) || \
<> 144:ef7eb2e8f9f7 1305 ((__CHANNEL__) == ADC_CHANNEL_16) || \
<> 144:ef7eb2e8f9f7 1306 ((__CHANNEL__) == ADC_CHANNEL_17) || \
<> 144:ef7eb2e8f9f7 1307 ((__CHANNEL__) == ADC_CHANNEL_18) || \
<> 144:ef7eb2e8f9f7 1308 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
<> 144:ef7eb2e8f9f7 1309 ((__CHANNEL__) == ADC_CHANNEL_VBAT)))
AnnaBridge 167:e84263d55307 1310 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1311 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \
<> 144:ef7eb2e8f9f7 1312 (((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
<> 144:ef7eb2e8f9f7 1313 ((__CHANNEL__) == ADC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1314 ((__CHANNEL__) == ADC_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 1315 ((__CHANNEL__) == ADC_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 1316 ((__CHANNEL__) == ADC_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 1317 ((__CHANNEL__) == ADC_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 1318 ((__CHANNEL__) == ADC_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 1319 ((__CHANNEL__) == ADC_CHANNEL_7) || \
<> 144:ef7eb2e8f9f7 1320 ((__CHANNEL__) == ADC_CHANNEL_8) || \
<> 144:ef7eb2e8f9f7 1321 ((__CHANNEL__) == ADC_CHANNEL_9) || \
<> 144:ef7eb2e8f9f7 1322 ((__CHANNEL__) == ADC_CHANNEL_10) || \
<> 144:ef7eb2e8f9f7 1323 ((__CHANNEL__) == ADC_CHANNEL_11) || \
<> 144:ef7eb2e8f9f7 1324 ((__CHANNEL__) == ADC_CHANNEL_12) || \
<> 144:ef7eb2e8f9f7 1325 ((__CHANNEL__) == ADC_CHANNEL_13) || \
<> 144:ef7eb2e8f9f7 1326 ((__CHANNEL__) == ADC_CHANNEL_14) || \
<> 144:ef7eb2e8f9f7 1327 ((__CHANNEL__) == ADC_CHANNEL_15) || \
<> 144:ef7eb2e8f9f7 1328 ((__CHANNEL__) == ADC_CHANNEL_16) || \
<> 144:ef7eb2e8f9f7 1329 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
<> 144:ef7eb2e8f9f7 1330 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \
<> 144:ef7eb2e8f9f7 1331 ((((__HANDLE__)->Instance) == ADC2) && \
<> 144:ef7eb2e8f9f7 1332 (((__CHANNEL__) == ADC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1333 ((__CHANNEL__) == ADC_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 1334 ((__CHANNEL__) == ADC_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 1335 ((__CHANNEL__) == ADC_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 1336 ((__CHANNEL__) == ADC_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 1337 ((__CHANNEL__) == ADC_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 1338 ((__CHANNEL__) == ADC_CHANNEL_7) || \
<> 144:ef7eb2e8f9f7 1339 ((__CHANNEL__) == ADC_CHANNEL_8) || \
<> 144:ef7eb2e8f9f7 1340 ((__CHANNEL__) == ADC_CHANNEL_9) || \
<> 144:ef7eb2e8f9f7 1341 ((__CHANNEL__) == ADC_CHANNEL_10) || \
<> 144:ef7eb2e8f9f7 1342 ((__CHANNEL__) == ADC_CHANNEL_11) || \
<> 144:ef7eb2e8f9f7 1343 ((__CHANNEL__) == ADC_CHANNEL_12) || \
<> 144:ef7eb2e8f9f7 1344 ((__CHANNEL__) == ADC_CHANNEL_13) || \
<> 144:ef7eb2e8f9f7 1345 ((__CHANNEL__) == ADC_CHANNEL_14) || \
<> 144:ef7eb2e8f9f7 1346 ((__CHANNEL__) == ADC_CHANNEL_15) || \
<> 144:ef7eb2e8f9f7 1347 ((__CHANNEL__) == ADC_CHANNEL_16) || \
<> 144:ef7eb2e8f9f7 1348 ((__CHANNEL__) == ADC_CHANNEL_17) || \
<> 144:ef7eb2e8f9f7 1349 ((__CHANNEL__) == ADC_CHANNEL_18))) || \
<> 144:ef7eb2e8f9f7 1350 ((((__HANDLE__)->Instance) == ADC3) && \
<> 144:ef7eb2e8f9f7 1351 (((__CHANNEL__) == ADC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1352 ((__CHANNEL__) == ADC_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 1353 ((__CHANNEL__) == ADC_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 1354 ((__CHANNEL__) == ADC_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 1355 ((__CHANNEL__) == ADC_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 1356 ((__CHANNEL__) == ADC_CHANNEL_7) || \
<> 144:ef7eb2e8f9f7 1357 ((__CHANNEL__) == ADC_CHANNEL_8) || \
<> 144:ef7eb2e8f9f7 1358 ((__CHANNEL__) == ADC_CHANNEL_9) || \
<> 144:ef7eb2e8f9f7 1359 ((__CHANNEL__) == ADC_CHANNEL_10) || \
<> 144:ef7eb2e8f9f7 1360 ((__CHANNEL__) == ADC_CHANNEL_11) || \
<> 144:ef7eb2e8f9f7 1361 ((__CHANNEL__) == ADC_CHANNEL_12) || \
<> 144:ef7eb2e8f9f7 1362 ((__CHANNEL__) == ADC_CHANNEL_13) || \
<> 144:ef7eb2e8f9f7 1363 ((__CHANNEL__) == ADC_CHANNEL_14) || \
<> 144:ef7eb2e8f9f7 1364 ((__CHANNEL__) == ADC_CHANNEL_15) || \
<> 144:ef7eb2e8f9f7 1365 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
<> 144:ef7eb2e8f9f7 1366 ((__CHANNEL__) == ADC_CHANNEL_VBAT) )))
<> 144:ef7eb2e8f9f7 1367 #endif
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 /**
<> 144:ef7eb2e8f9f7 1370 * @brief Verify the ADC channel setting in differential mode.
<> 144:ef7eb2e8f9f7 1371 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1372 * @param __CHANNEL__: programmed ADC channel.
<> 144:ef7eb2e8f9f7 1373 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
<> 144:ef7eb2e8f9f7 1374 */
AnnaBridge 167:e84263d55307 1375 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
<> 144:ef7eb2e8f9f7 1376 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1377 ((__CHANNEL__) == ADC_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 1378 ((__CHANNEL__) == ADC_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 1379 ((__CHANNEL__) == ADC_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 1380 ((__CHANNEL__) == ADC_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 1381 ((__CHANNEL__) == ADC_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 1382 ((__CHANNEL__) == ADC_CHANNEL_7) || \
<> 144:ef7eb2e8f9f7 1383 ((__CHANNEL__) == ADC_CHANNEL_8) || \
<> 144:ef7eb2e8f9f7 1384 ((__CHANNEL__) == ADC_CHANNEL_9) || \
<> 144:ef7eb2e8f9f7 1385 ((__CHANNEL__) == ADC_CHANNEL_10) || \
<> 144:ef7eb2e8f9f7 1386 ((__CHANNEL__) == ADC_CHANNEL_11) || \
<> 144:ef7eb2e8f9f7 1387 ((__CHANNEL__) == ADC_CHANNEL_12) || \
<> 144:ef7eb2e8f9f7 1388 ((__CHANNEL__) == ADC_CHANNEL_13) || \
<> 144:ef7eb2e8f9f7 1389 ((__CHANNEL__) == ADC_CHANNEL_14) || \
<> 144:ef7eb2e8f9f7 1390 ((__CHANNEL__) == ADC_CHANNEL_15) )
AnnaBridge 167:e84263d55307 1391 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1392 /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode,
<> 144:ef7eb2e8f9f7 1393 channels 0, 16 to 18 can be only used in single-ended mode.
<> 144:ef7eb2e8f9f7 1394 For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode,
<> 144:ef7eb2e8f9f7 1395 channels 4, 5 and 13 to 18 can only be used in single-ended mode. */
<> 144:ef7eb2e8f9f7 1396 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ((((((__HANDLE__)->Instance) == ADC1) || \
<> 144:ef7eb2e8f9f7 1397 (((__HANDLE__)->Instance) == ADC2)) && \
<> 144:ef7eb2e8f9f7 1398 (((__CHANNEL__) == ADC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1399 ((__CHANNEL__) == ADC_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 1400 ((__CHANNEL__) == ADC_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 1401 ((__CHANNEL__) == ADC_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 1402 ((__CHANNEL__) == ADC_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 1403 ((__CHANNEL__) == ADC_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 1404 ((__CHANNEL__) == ADC_CHANNEL_7) || \
<> 144:ef7eb2e8f9f7 1405 ((__CHANNEL__) == ADC_CHANNEL_8) || \
<> 144:ef7eb2e8f9f7 1406 ((__CHANNEL__) == ADC_CHANNEL_9) || \
<> 144:ef7eb2e8f9f7 1407 ((__CHANNEL__) == ADC_CHANNEL_10) || \
<> 144:ef7eb2e8f9f7 1408 ((__CHANNEL__) == ADC_CHANNEL_11) || \
<> 144:ef7eb2e8f9f7 1409 ((__CHANNEL__) == ADC_CHANNEL_12) || \
<> 144:ef7eb2e8f9f7 1410 ((__CHANNEL__) == ADC_CHANNEL_13) || \
<> 144:ef7eb2e8f9f7 1411 ((__CHANNEL__) == ADC_CHANNEL_14) || \
<> 144:ef7eb2e8f9f7 1412 ((__CHANNEL__) == ADC_CHANNEL_15))) || \
<> 144:ef7eb2e8f9f7 1413 ((((__HANDLE__)->Instance) == ADC3) && \
<> 144:ef7eb2e8f9f7 1414 (((__CHANNEL__) == ADC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1415 ((__CHANNEL__) == ADC_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 1416 ((__CHANNEL__) == ADC_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 1417 ((__CHANNEL__) == ADC_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 1418 ((__CHANNEL__) == ADC_CHANNEL_7) || \
<> 144:ef7eb2e8f9f7 1419 ((__CHANNEL__) == ADC_CHANNEL_8) || \
<> 144:ef7eb2e8f9f7 1420 ((__CHANNEL__) == ADC_CHANNEL_9) || \
<> 144:ef7eb2e8f9f7 1421 ((__CHANNEL__) == ADC_CHANNEL_10) || \
<> 144:ef7eb2e8f9f7 1422 ((__CHANNEL__) == ADC_CHANNEL_11) || \
<> 144:ef7eb2e8f9f7 1423 ((__CHANNEL__) == ADC_CHANNEL_12) )))
<> 144:ef7eb2e8f9f7 1424 #endif
<> 144:ef7eb2e8f9f7 1425
<> 144:ef7eb2e8f9f7 1426 /**
<> 144:ef7eb2e8f9f7 1427 * @brief Verify the ADC single-ended input or differential mode setting.
<> 144:ef7eb2e8f9f7 1428 * @param __SING_DIFF__: programmed channel setting.
<> 144:ef7eb2e8f9f7 1429 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
<> 144:ef7eb2e8f9f7 1430 */
<> 144:ef7eb2e8f9f7 1431 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
<> 144:ef7eb2e8f9f7 1432 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
<> 144:ef7eb2e8f9f7 1433
<> 144:ef7eb2e8f9f7 1434 /**
<> 144:ef7eb2e8f9f7 1435 * @brief Verify the ADC offset management setting.
<> 144:ef7eb2e8f9f7 1436 * @param __OFFSET_NUMBER__: ADC offset management.
<> 144:ef7eb2e8f9f7 1437 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
<> 144:ef7eb2e8f9f7 1438 */
<> 144:ef7eb2e8f9f7 1439 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
<> 144:ef7eb2e8f9f7 1440 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
<> 144:ef7eb2e8f9f7 1441 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
<> 144:ef7eb2e8f9f7 1442 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
<> 144:ef7eb2e8f9f7 1443 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
<> 144:ef7eb2e8f9f7 1444
<> 144:ef7eb2e8f9f7 1445 /**
<> 144:ef7eb2e8f9f7 1446 * @brief Verify the ADC injected channel setting.
<> 144:ef7eb2e8f9f7 1447 * @param __CHANNEL__: programmed ADC injected channel.
<> 144:ef7eb2e8f9f7 1448 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
<> 144:ef7eb2e8f9f7 1449 */
<> 144:ef7eb2e8f9f7 1450 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
<> 144:ef7eb2e8f9f7 1451 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
<> 144:ef7eb2e8f9f7 1452 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
<> 144:ef7eb2e8f9f7 1453 ((__CHANNEL__) == ADC_INJECTED_RANK_4) )
<> 144:ef7eb2e8f9f7 1454
<> 144:ef7eb2e8f9f7 1455 /**
<> 144:ef7eb2e8f9f7 1456 * @brief Verify the ADC injected conversions external trigger.
<> 144:ef7eb2e8f9f7 1457 * @param __INJTRIG__: programmed ADC injected conversions external trigger.
<> 144:ef7eb2e8f9f7 1458 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
<> 144:ef7eb2e8f9f7 1459 */
<> 144:ef7eb2e8f9f7 1460 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
<> 144:ef7eb2e8f9f7 1461 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
<> 144:ef7eb2e8f9f7 1462 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
<> 144:ef7eb2e8f9f7 1463 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
<> 144:ef7eb2e8f9f7 1464 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
<> 144:ef7eb2e8f9f7 1465 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
<> 144:ef7eb2e8f9f7 1466 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
<> 144:ef7eb2e8f9f7 1467 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
<> 144:ef7eb2e8f9f7 1468 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
<> 144:ef7eb2e8f9f7 1469 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
<> 144:ef7eb2e8f9f7 1470 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
<> 144:ef7eb2e8f9f7 1471 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
<> 144:ef7eb2e8f9f7 1472 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
<> 144:ef7eb2e8f9f7 1473 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
<> 144:ef7eb2e8f9f7 1474 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
<> 144:ef7eb2e8f9f7 1475 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
<> 144:ef7eb2e8f9f7 1476 \
<> 144:ef7eb2e8f9f7 1477 ((__INJTRIG__) == ADC_SOFTWARE_START) )
<> 144:ef7eb2e8f9f7 1478
AnnaBridge 167:e84263d55307 1479 /**
AnnaBridge 167:e84263d55307 1480 * @brief Verify the ADC edge trigger setting for injected group.
AnnaBridge 167:e84263d55307 1481 * @param __EDGE__: programmed ADC edge trigger setting.
AnnaBridge 167:e84263d55307 1482 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
AnnaBridge 167:e84263d55307 1483 */
AnnaBridge 167:e84263d55307 1484 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
AnnaBridge 167:e84263d55307 1485 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
AnnaBridge 167:e84263d55307 1486 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
AnnaBridge 167:e84263d55307 1487 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
<> 144:ef7eb2e8f9f7 1488
AnnaBridge 167:e84263d55307 1489 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1490 /**
<> 144:ef7eb2e8f9f7 1491 * @brief Verify the ADC multimode setting.
<> 144:ef7eb2e8f9f7 1492 * @param __MODE__: programmed ADC multimode setting.
<> 144:ef7eb2e8f9f7 1493 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<> 144:ef7eb2e8f9f7 1494 */
<> 144:ef7eb2e8f9f7 1495 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
<> 144:ef7eb2e8f9f7 1496 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
<> 144:ef7eb2e8f9f7 1497 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
<> 144:ef7eb2e8f9f7 1498 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
<> 144:ef7eb2e8f9f7 1499 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
<> 144:ef7eb2e8f9f7 1500 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
<> 144:ef7eb2e8f9f7 1501 ((__MODE__) == ADC_DUALMODE_INTERL) || \
<> 144:ef7eb2e8f9f7 1502 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
<> 144:ef7eb2e8f9f7 1503
<> 144:ef7eb2e8f9f7 1504 /**
<> 144:ef7eb2e8f9f7 1505 * @brief Verify the ADC multimode DMA access setting.
<> 144:ef7eb2e8f9f7 1506 * @param __MODE__: programmed ADC multimode DMA access setting.
<> 144:ef7eb2e8f9f7 1507 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<> 144:ef7eb2e8f9f7 1508 */
<> 144:ef7eb2e8f9f7 1509 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \
<> 144:ef7eb2e8f9f7 1510 ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
<> 144:ef7eb2e8f9f7 1511 ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) )
<> 144:ef7eb2e8f9f7 1512
<> 144:ef7eb2e8f9f7 1513 /**
<> 144:ef7eb2e8f9f7 1514 * @brief Verify the ADC multimode delay setting.
<> 144:ef7eb2e8f9f7 1515 * @param __DELAY__: programmed ADC multimode delay setting.
<> 144:ef7eb2e8f9f7 1516 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
<> 144:ef7eb2e8f9f7 1517 */
<> 144:ef7eb2e8f9f7 1518 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
<> 144:ef7eb2e8f9f7 1519 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
<> 144:ef7eb2e8f9f7 1520 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
<> 144:ef7eb2e8f9f7 1521 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
<> 144:ef7eb2e8f9f7 1522 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
<> 144:ef7eb2e8f9f7 1523 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
<> 144:ef7eb2e8f9f7 1524 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
<> 144:ef7eb2e8f9f7 1525 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
<> 144:ef7eb2e8f9f7 1526 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
<> 144:ef7eb2e8f9f7 1527 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
<> 144:ef7eb2e8f9f7 1528 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
<> 144:ef7eb2e8f9f7 1529 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) )
AnnaBridge 167:e84263d55307 1530 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
<> 144:ef7eb2e8f9f7 1531
<> 144:ef7eb2e8f9f7 1532 /**
<> 144:ef7eb2e8f9f7 1533 * @brief Verify the ADC analog watchdog setting.
<> 144:ef7eb2e8f9f7 1534 * @param __WATCHDOG__: programmed ADC analog watchdog setting.
<> 144:ef7eb2e8f9f7 1535 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
<> 144:ef7eb2e8f9f7 1536 */
<> 144:ef7eb2e8f9f7 1537 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
<> 144:ef7eb2e8f9f7 1538 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
<> 144:ef7eb2e8f9f7 1539 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
<> 144:ef7eb2e8f9f7 1540
<> 144:ef7eb2e8f9f7 1541 /**
<> 144:ef7eb2e8f9f7 1542 * @brief Verify the ADC analog watchdog mode setting.
<> 144:ef7eb2e8f9f7 1543 * @param __WATCHDOG_MODE__: programmed ADC analog watchdog mode setting.
<> 144:ef7eb2e8f9f7 1544 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
<> 144:ef7eb2e8f9f7 1545 */
<> 144:ef7eb2e8f9f7 1546 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
<> 144:ef7eb2e8f9f7 1547 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
<> 144:ef7eb2e8f9f7 1548 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
<> 144:ef7eb2e8f9f7 1549 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
<> 144:ef7eb2e8f9f7 1550 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
<> 144:ef7eb2e8f9f7 1551 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
<> 144:ef7eb2e8f9f7 1552 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
<> 144:ef7eb2e8f9f7 1553
<> 144:ef7eb2e8f9f7 1554 /**
<> 144:ef7eb2e8f9f7 1555 * @brief Verify the ADC conversion (regular or injected or both).
<> 144:ef7eb2e8f9f7 1556 * @param __CONVERSION__: ADC conversion group.
<> 144:ef7eb2e8f9f7 1557 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
<> 144:ef7eb2e8f9f7 1558 */
<> 144:ef7eb2e8f9f7 1559 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
<> 144:ef7eb2e8f9f7 1560 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \
<> 144:ef7eb2e8f9f7 1561 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
<> 144:ef7eb2e8f9f7 1562
<> 144:ef7eb2e8f9f7 1563 /**
<> 144:ef7eb2e8f9f7 1564 * @brief Verify the ADC event type.
<> 144:ef7eb2e8f9f7 1565 * @param __EVENT__: ADC event.
<> 144:ef7eb2e8f9f7 1566 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
<> 144:ef7eb2e8f9f7 1567 */
<> 144:ef7eb2e8f9f7 1568 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
<> 144:ef7eb2e8f9f7 1569 ((__EVENT__) == ADC_AWD_EVENT) || \
<> 144:ef7eb2e8f9f7 1570 ((__EVENT__) == ADC_AWD2_EVENT) || \
<> 144:ef7eb2e8f9f7 1571 ((__EVENT__) == ADC_AWD3_EVENT) || \
<> 144:ef7eb2e8f9f7 1572 ((__EVENT__) == ADC_OVR_EVENT) || \
<> 144:ef7eb2e8f9f7 1573 ((__EVENT__) == ADC_JQOVF_EVENT) )
<> 144:ef7eb2e8f9f7 1574
<> 144:ef7eb2e8f9f7 1575 /**
<> 144:ef7eb2e8f9f7 1576 * @brief Verify the ADC oversampling ratio.
<> 144:ef7eb2e8f9f7 1577 * @param __RATIO__: programmed ADC oversampling ratio.
<> 144:ef7eb2e8f9f7 1578 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
<> 144:ef7eb2e8f9f7 1579 */
<> 144:ef7eb2e8f9f7 1580 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \
<> 144:ef7eb2e8f9f7 1581 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \
<> 144:ef7eb2e8f9f7 1582 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \
<> 144:ef7eb2e8f9f7 1583 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \
<> 144:ef7eb2e8f9f7 1584 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \
<> 144:ef7eb2e8f9f7 1585 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
<> 144:ef7eb2e8f9f7 1586 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
<> 144:ef7eb2e8f9f7 1587 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
<> 144:ef7eb2e8f9f7 1588
<> 144:ef7eb2e8f9f7 1589 /**
<> 144:ef7eb2e8f9f7 1590 * @brief Verify the ADC oversampling shift.
<> 144:ef7eb2e8f9f7 1591 * @param __SHIFT__: programmed ADC oversampling shift.
<> 144:ef7eb2e8f9f7 1592 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
<> 144:ef7eb2e8f9f7 1593 */
<> 144:ef7eb2e8f9f7 1594 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
<> 144:ef7eb2e8f9f7 1595 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
<> 144:ef7eb2e8f9f7 1596 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
<> 144:ef7eb2e8f9f7 1597 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
<> 144:ef7eb2e8f9f7 1598 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
<> 144:ef7eb2e8f9f7 1599 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
<> 144:ef7eb2e8f9f7 1600 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
<> 144:ef7eb2e8f9f7 1601 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
<> 144:ef7eb2e8f9f7 1602 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
<> 144:ef7eb2e8f9f7 1603
<> 144:ef7eb2e8f9f7 1604 /**
<> 144:ef7eb2e8f9f7 1605 * @brief Verify the ADC oversampling triggered mode.
<> 144:ef7eb2e8f9f7 1606 * @param __MODE__: programmed ADC oversampling triggered mode.
<> 144:ef7eb2e8f9f7 1607 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<> 144:ef7eb2e8f9f7 1608 */
<> 144:ef7eb2e8f9f7 1609 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
<> 144:ef7eb2e8f9f7 1610 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 /**
<> 144:ef7eb2e8f9f7 1613 * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
<> 144:ef7eb2e8f9f7 1614 * @param __MODE__: programmed ADC oversampling regular conversion resumed or continued mode.
<> 144:ef7eb2e8f9f7 1615 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<> 144:ef7eb2e8f9f7 1616 */
<> 144:ef7eb2e8f9f7 1617 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
<> 144:ef7eb2e8f9f7 1618 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
<> 144:ef7eb2e8f9f7 1619
<> 144:ef7eb2e8f9f7 1620
<> 144:ef7eb2e8f9f7 1621 /**
<> 144:ef7eb2e8f9f7 1622 * @brief Verify the DFSDM mode configuration.
<> 144:ef7eb2e8f9f7 1623 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1624 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
<> 144:ef7eb2e8f9f7 1625 * this reason, the input parameter is the ADC handle and not the configuration parameter
<> 144:ef7eb2e8f9f7 1626 * directly.
<> 144:ef7eb2e8f9f7 1627 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
<> 144:ef7eb2e8f9f7 1628 */
AnnaBridge 167:e84263d55307 1629 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 1630 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \
AnnaBridge 167:e84263d55307 1631 ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) )
AnnaBridge 167:e84263d55307 1632 #else
<> 144:ef7eb2e8f9f7 1633 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
AnnaBridge 167:e84263d55307 1634 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
<> 144:ef7eb2e8f9f7 1635
<> 144:ef7eb2e8f9f7 1636 /**
<> 144:ef7eb2e8f9f7 1637 * @brief Return the DFSDM configuration mode.
<> 144:ef7eb2e8f9f7 1638 * @param __HANDLE__: ADC handle.
<> 144:ef7eb2e8f9f7 1639 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
<> 144:ef7eb2e8f9f7 1640 * For this reason, the input parameter is the ADC handle and not the configuration parameter
<> 144:ef7eb2e8f9f7 1641 * directly.
<> 144:ef7eb2e8f9f7 1642 * @retval DFSDM configuration mode
<> 144:ef7eb2e8f9f7 1643 */
AnnaBridge 167:e84263d55307 1644 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 167:e84263d55307 1645 #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig)
AnnaBridge 167:e84263d55307 1646 #else
<> 144:ef7eb2e8f9f7 1647 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0)
AnnaBridge 167:e84263d55307 1648 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
<> 144:ef7eb2e8f9f7 1649
<> 144:ef7eb2e8f9f7 1650 /**
<> 144:ef7eb2e8f9f7 1651 * @}
<> 144:ef7eb2e8f9f7 1652 */
<> 144:ef7eb2e8f9f7 1653
<> 144:ef7eb2e8f9f7 1654
<> 144:ef7eb2e8f9f7 1655 /* Exported functions --------------------------------------------------------*/
AnnaBridge 167:e84263d55307 1656 /** @addtogroup ADCEx_Exported_Functions
<> 144:ef7eb2e8f9f7 1657 * @{
<> 144:ef7eb2e8f9f7 1658 */
<> 144:ef7eb2e8f9f7 1659
AnnaBridge 167:e84263d55307 1660 /** @addtogroup ADCEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 1661 * @{
<> 144:ef7eb2e8f9f7 1662 */
AnnaBridge 167:e84263d55307 1663 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 1664
<> 144:ef7eb2e8f9f7 1665 /* ADC calibration */
<> 144:ef7eb2e8f9f7 1666 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
<> 144:ef7eb2e8f9f7 1667 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
<> 144:ef7eb2e8f9f7 1668 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
<> 144:ef7eb2e8f9f7 1669
<> 144:ef7eb2e8f9f7 1670 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1671 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1672 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1673 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 1674
<> 144:ef7eb2e8f9f7 1675 /* Non-blocking mode: Interruption */
<> 144:ef7eb2e8f9f7 1676 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1677 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1678
AnnaBridge 167:e84263d55307 1679 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1680 /* ADC multimode */
<> 144:ef7eb2e8f9f7 1681 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
<> 144:ef7eb2e8f9f7 1682 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 1683 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
AnnaBridge 167:e84263d55307 1684 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
<> 144:ef7eb2e8f9f7 1685
<> 144:ef7eb2e8f9f7 1686 /* ADC retrieve conversion value intended to be used with polling or interruption */
<> 144:ef7eb2e8f9f7 1687 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
<> 144:ef7eb2e8f9f7 1688
<> 144:ef7eb2e8f9f7 1689 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
<> 144:ef7eb2e8f9f7 1690 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1691 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1692 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1693 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1694 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1695
<> 144:ef7eb2e8f9f7 1696 /* ADC Regular conversions stop */
<> 144:ef7eb2e8f9f7 1697 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1698 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1699 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);
AnnaBridge 167:e84263d55307 1700 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1701 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc);
AnnaBridge 167:e84263d55307 1702 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
<> 144:ef7eb2e8f9f7 1703
<> 144:ef7eb2e8f9f7 1704 /**
<> 144:ef7eb2e8f9f7 1705 * @}
<> 144:ef7eb2e8f9f7 1706 */
<> 144:ef7eb2e8f9f7 1707
AnnaBridge 167:e84263d55307 1708 /** @addtogroup ADCEx_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 1709 * @{
<> 144:ef7eb2e8f9f7 1710 */
<> 144:ef7eb2e8f9f7 1711 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 1712 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
AnnaBridge 167:e84263d55307 1713 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 1714 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
AnnaBridge 167:e84263d55307 1715 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
<> 144:ef7eb2e8f9f7 1716 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1717 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1718 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1719 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 1720
<> 144:ef7eb2e8f9f7 1721 /**
<> 144:ef7eb2e8f9f7 1722 * @}
<> 144:ef7eb2e8f9f7 1723 */
<> 144:ef7eb2e8f9f7 1724
<> 144:ef7eb2e8f9f7 1725 /**
<> 144:ef7eb2e8f9f7 1726 * @}
<> 144:ef7eb2e8f9f7 1727 */
<> 144:ef7eb2e8f9f7 1728
<> 144:ef7eb2e8f9f7 1729 /**
<> 144:ef7eb2e8f9f7 1730 * @}
<> 144:ef7eb2e8f9f7 1731 */
<> 144:ef7eb2e8f9f7 1732
<> 144:ef7eb2e8f9f7 1733 /**
<> 144:ef7eb2e8f9f7 1734 * @}
<> 144:ef7eb2e8f9f7 1735 */
<> 144:ef7eb2e8f9f7 1736
<> 144:ef7eb2e8f9f7 1737 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1738 }
<> 144:ef7eb2e8f9f7 1739 #endif
<> 144:ef7eb2e8f9f7 1740
AnnaBridge 167:e84263d55307 1741 #endif /* __STM32L4xx_HAL_ADC_EX_H */
<> 144:ef7eb2e8f9f7 1742
<> 144:ef7eb2e8f9f7 1743
<> 144:ef7eb2e8f9f7 1744 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/