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mbed library sources. Supersedes mbed-src.

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c@181:96ed750bd169, 2018-01-17 (annotated)

Committer:: Anna Bridge
Date:: Wed Jan 17 15:23:54 2018 +0000
Revision:: 181:96ed750bd169
Parent:: 167:e84263d55307

mbed-dev libray. Release version 158

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_hal_adc.c
AnnaBridge	167:e84263d55307	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.7.1
AnnaBridge	167:e84263d55307	6	* @date 21-April-2017
<>	144:ef7eb2e8f9f7	7	* @brief This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	8	* functionalities of the Analog to Digital Convertor (ADC)
<>	144:ef7eb2e8f9f7	9	* peripheral:
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
AnnaBridge	167:e84263d55307	11	* ++ Initialization and Configuration of ADC
<>	144:ef7eb2e8f9f7	12	* + Operation functions
AnnaBridge	167:e84263d55307	13	* ++ Start, stop, get result of conversions of regular
AnnaBridge	167:e84263d55307	14	* group, using 3 possible modes: polling, interruption or DMA.
<>	144:ef7eb2e8f9f7	15	* + Control functions
AnnaBridge	167:e84263d55307	16	* ++ Channels configuration on regular group
<>	144:ef7eb2e8f9f7	17	* ++ Analog Watchdog configuration
<>	144:ef7eb2e8f9f7	18	* + State functions
<>	144:ef7eb2e8f9f7	19	* ++ ADC state machine management
<>	144:ef7eb2e8f9f7	20	* ++ Interrupts and flags management
AnnaBridge	167:e84263d55307	21	* Other functions (extended functions) are available in file
AnnaBridge	167:e84263d55307	22	* "stm32l4xx_hal_adc_ex.c".
AnnaBridge	167:e84263d55307	23	*
AnnaBridge	167:e84263d55307	24	@verbatim
<>	144:ef7eb2e8f9f7	25	==============================================================================
AnnaBridge	167:e84263d55307	26	##### ADC peripheral features #####
<>	144:ef7eb2e8f9f7	27	==============================================================================
AnnaBridge	167:e84263d55307	28	[..]
AnnaBridge	167:e84263d55307	29	(+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
<>	144:ef7eb2e8f9f7	30
AnnaBridge	167:e84263d55307	31	(+) Interrupt generation at the end of regular conversion and in case of
AnnaBridge	167:e84263d55307	32	analog watchdog or overrun events.
<>	144:ef7eb2e8f9f7	33
AnnaBridge	167:e84263d55307	34	(+) Single and continuous conversion modes.
<>	144:ef7eb2e8f9f7	35
AnnaBridge	167:e84263d55307	36	(+) Scan mode for conversion of several channels sequentially.
<>	144:ef7eb2e8f9f7	37
AnnaBridge	167:e84263d55307	38	(+) Data alignment with in-built data coherency.
<>	144:ef7eb2e8f9f7	39
AnnaBridge	167:e84263d55307	40	(+) Programmable sampling time (channel wise)
AnnaBridge	167:e84263d55307	41
AnnaBridge	167:e84263d55307	42	(+) External trigger (timer or EXTI) with configurable polarity
AnnaBridge	167:e84263d55307	43
AnnaBridge	167:e84263d55307	44	(+) DMA request generation for transfer of conversions data of regular group.
<>	144:ef7eb2e8f9f7	45
AnnaBridge	167:e84263d55307	46	(+) Configurable delay between conversions in Dual interleaved mode.
AnnaBridge	167:e84263d55307	47
AnnaBridge	167:e84263d55307	48	(+) ADC channels selectable single/differential input.
AnnaBridge	167:e84263d55307	49
AnnaBridge	167:e84263d55307	50	(+) ADC offset on regular groups.
<>	144:ef7eb2e8f9f7	51
AnnaBridge	167:e84263d55307	52	(+) ADC calibration
AnnaBridge	167:e84263d55307	53
AnnaBridge	167:e84263d55307	54	(+) ADC conversion of regular group.
<>	144:ef7eb2e8f9f7	55
AnnaBridge	167:e84263d55307	56	(+) ADC supply requirements: 1.62 V to 3.6 V.
AnnaBridge	167:e84263d55307	57
AnnaBridge	167:e84263d55307	58	(+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
<>	144:ef7eb2e8f9f7	59	Vdda or to an external voltage reference).
<>	144:ef7eb2e8f9f7	60
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	63	==============================================================================
<>	144:ef7eb2e8f9f7	64	[..]
<>	144:ef7eb2e8f9f7	65
AnnaBridge	167:e84263d55307	66	* Configuration of top level parameters related to ADC *
AnnaBridge	167:e84263d55307	67	============================================================
AnnaBridge	167:e84263d55307	68	[..]
AnnaBridge	167:e84263d55307	69
AnnaBridge	167:e84263d55307	70	(#) Enable the ADC interface
AnnaBridge	167:e84263d55307	71	(++) As prerequisite, ADC clock must be configured at RCC top level.
AnnaBridge	167:e84263d55307	72
AnnaBridge	167:e84263d55307	73	(++) Two clock settings are mandatory:
AnnaBridge	167:e84263d55307	74	(+++) ADC clock (core clock, also possibly conversion clock).
<>	144:ef7eb2e8f9f7	75
AnnaBridge	167:e84263d55307	76	(+++) ADC clock (conversions clock).
AnnaBridge	167:e84263d55307	77	Two possible clock sources: synchronous clock derived from APB clock
AnnaBridge	167:e84263d55307	78	or asynchronous clock derived from system clock, PLLSAI1 or the PLLSAI2
AnnaBridge	167:e84263d55307	79	running up to 80MHz.
<>	144:ef7eb2e8f9f7	80
AnnaBridge	167:e84263d55307	81	(+++) Example:
AnnaBridge	167:e84263d55307	82	Into HAL_ADC_MspInit() (recommended code location) or with
AnnaBridge	167:e84263d55307	83	other device clock parameters configuration:
AnnaBridge	167:e84263d55307	84	(+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
<>	144:ef7eb2e8f9f7	85
AnnaBridge	167:e84263d55307	86	RCC_ADCCLKSOURCE_PLLSAI2 enable: (optional: if asynchronous clock selected)
AnnaBridge	167:e84263d55307	87	(+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
AnnaBridge	167:e84263d55307	88	(+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
AnnaBridge	167:e84263d55307	89	(+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI2;
AnnaBridge	167:e84263d55307	90	(+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
AnnaBridge	167:e84263d55307	91
AnnaBridge	167:e84263d55307	92	(++) ADC clock source and clock prescaler are configured at ADC level with
AnnaBridge	167:e84263d55307	93	parameter "ClockPrescaler" using function HAL_ADC_Init().
AnnaBridge	167:e84263d55307	94
AnnaBridge	167:e84263d55307	95	(#) ADC pins configuration
AnnaBridge	167:e84263d55307	96	(++) Enable the clock for the ADC GPIOs
AnnaBridge	167:e84263d55307	97	using macro __HAL_RCC_GPIOx_CLK_ENABLE()
AnnaBridge	167:e84263d55307	98	(++) Configure these ADC pins in analog mode
AnnaBridge	167:e84263d55307	99	using function HAL_GPIO_Init()
<>	144:ef7eb2e8f9f7	100
AnnaBridge	167:e84263d55307	101	(#) Optionally, in case of usage of ADC with interruptions:
AnnaBridge	167:e84263d55307	102	(++) Configure the NVIC for ADC
AnnaBridge	167:e84263d55307	103	using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
AnnaBridge	167:e84263d55307	104	(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
AnnaBridge	167:e84263d55307	105	into the function of corresponding ADC interruption vector
AnnaBridge	167:e84263d55307	106	ADCx_IRQHandler().
AnnaBridge	167:e84263d55307	107
AnnaBridge	167:e84263d55307	108	(#) Optionally, in case of usage of DMA:
AnnaBridge	167:e84263d55307	109	(++) Configure the DMA (DMA channel, mode normal or circular, ...)
AnnaBridge	167:e84263d55307	110	using function HAL_DMA_Init().
AnnaBridge	167:e84263d55307	111	(++) Configure the NVIC for DMA
AnnaBridge	167:e84263d55307	112	using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
AnnaBridge	167:e84263d55307	113	(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
AnnaBridge	167:e84263d55307	114	into the function of corresponding DMA interruption vector
AnnaBridge	167:e84263d55307	115	DMAx_Channelx_IRQHandler().
<>	144:ef7eb2e8f9f7	116
AnnaBridge	167:e84263d55307	117	* Configuration of ADC, group regular, channels parameters *
AnnaBridge	167:e84263d55307	118	================================================================
AnnaBridge	167:e84263d55307	119	[..]
AnnaBridge	167:e84263d55307	120
AnnaBridge	167:e84263d55307	121	(#) Configure the ADC parameters (resolution, data alignment, ...)
AnnaBridge	167:e84263d55307	122	and regular group parameters (conversion trigger, sequencer, ...)
AnnaBridge	167:e84263d55307	123	using function HAL_ADC_Init().
AnnaBridge	167:e84263d55307	124
AnnaBridge	167:e84263d55307	125	(#) Configure the channels for regular group parameters (channel number,
AnnaBridge	167:e84263d55307	126	channel rank into sequencer, ..., into regular group)
AnnaBridge	167:e84263d55307	127	using function HAL_ADC_ConfigChannel().
AnnaBridge	167:e84263d55307	128
AnnaBridge	167:e84263d55307	129	(#) Optionally, configure the analog watchdog parameters (channels
AnnaBridge	167:e84263d55307	130	monitored, thresholds, ...)
AnnaBridge	167:e84263d55307	131	using function HAL_ADC_AnalogWDGConfig().
AnnaBridge	167:e84263d55307	132
AnnaBridge	167:e84263d55307	133	* Execution of ADC conversions *
AnnaBridge	167:e84263d55307	134	====================================
AnnaBridge	167:e84263d55307	135	[..]
AnnaBridge	167:e84263d55307	136
<>	144:ef7eb2e8f9f7	137	(#) Optionally, perform an automatic ADC calibration to improve the
AnnaBridge	167:e84263d55307	138	conversion accuracy
AnnaBridge	167:e84263d55307	139	using function HAL_ADCEx_Calibration_Start().
AnnaBridge	167:e84263d55307	140
AnnaBridge	167:e84263d55307	141	(#) ADC driver can be used among three modes: polling, interruption,
AnnaBridge	167:e84263d55307	142	transfer by DMA.
AnnaBridge	167:e84263d55307	143
AnnaBridge	167:e84263d55307	144	(++) ADC conversion by polling:
AnnaBridge	167:e84263d55307	145	(+++) Activate the ADC peripheral and start conversions
AnnaBridge	167:e84263d55307	146	using function HAL_ADC_Start()
AnnaBridge	167:e84263d55307	147	(+++) Wait for ADC conversion completion
AnnaBridge	167:e84263d55307	148	using function HAL_ADC_PollForConversion()
AnnaBridge	167:e84263d55307	149	(+++) Retrieve conversion results
AnnaBridge	167:e84263d55307	150	using function HAL_ADC_GetValue()
AnnaBridge	167:e84263d55307	151	(+++) Stop conversion and disable the ADC peripheral
AnnaBridge	167:e84263d55307	152	using function HAL_ADC_Stop()
AnnaBridge	167:e84263d55307	153
AnnaBridge	167:e84263d55307	154	(++) ADC conversion by interruption:
AnnaBridge	167:e84263d55307	155	(+++) Activate the ADC peripheral and start conversions
AnnaBridge	167:e84263d55307	156	using function HAL_ADC_Start_IT()
AnnaBridge	167:e84263d55307	157	(+++) Wait for ADC conversion completion by call of function
AnnaBridge	167:e84263d55307	158	HAL_ADC_ConvCpltCallback()
AnnaBridge	167:e84263d55307	159	(this function must be implemented in user program)
AnnaBridge	167:e84263d55307	160	(+++) Retrieve conversion results
AnnaBridge	167:e84263d55307	161	using function HAL_ADC_GetValue()
AnnaBridge	167:e84263d55307	162	(+++) Stop conversion and disable the ADC peripheral
AnnaBridge	167:e84263d55307	163	using function HAL_ADC_Stop_IT()
<>	144:ef7eb2e8f9f7	164
AnnaBridge	167:e84263d55307	165	(++) ADC conversion with transfer by DMA:
AnnaBridge	167:e84263d55307	166	(+++) Activate the ADC peripheral and start conversions
AnnaBridge	167:e84263d55307	167	using function HAL_ADC_Start_DMA()
AnnaBridge	167:e84263d55307	168	(+++) Wait for ADC conversion completion by call of function
AnnaBridge	167:e84263d55307	169	HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
AnnaBridge	167:e84263d55307	170	(these functions must be implemented in user program)
AnnaBridge	167:e84263d55307	171	(+++) Conversion results are automatically transferred by DMA into
AnnaBridge	167:e84263d55307	172	destination variable address.
AnnaBridge	167:e84263d55307	173	(+++) Stop conversion and disable the ADC peripheral
AnnaBridge	167:e84263d55307	174	using function HAL_ADC_Stop_DMA()
AnnaBridge	167:e84263d55307	175
AnnaBridge	167:e84263d55307	176	[..]
AnnaBridge	167:e84263d55307	177
AnnaBridge	167:e84263d55307	178	(@) Callback functions must be implemented in user program:
AnnaBridge	167:e84263d55307	179	(+@) HAL_ADC_ErrorCallback()
AnnaBridge	167:e84263d55307	180	(+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
AnnaBridge	167:e84263d55307	181	(+@) HAL_ADC_ConvCpltCallback()
AnnaBridge	167:e84263d55307	182	(+@) HAL_ADC_ConvHalfCpltCallback
AnnaBridge	167:e84263d55307	183
AnnaBridge	167:e84263d55307	184	* Deinitialization of ADC *
AnnaBridge	167:e84263d55307	185	============================================================
<>	144:ef7eb2e8f9f7	186	[..]
AnnaBridge	167:e84263d55307	187
AnnaBridge	167:e84263d55307	188	(#) Disable the ADC interface
AnnaBridge	167:e84263d55307	189	(++) ADC clock can be hard reset and disabled at RCC top level.
AnnaBridge	167:e84263d55307	190	(++) Hard reset of ADC peripherals
AnnaBridge	167:e84263d55307	191	using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
AnnaBridge	167:e84263d55307	192	(++) ADC clock disable
AnnaBridge	167:e84263d55307	193	using the equivalent macro/functions as configuration step.
AnnaBridge	167:e84263d55307	194	(+++) Example:
AnnaBridge	167:e84263d55307	195	Into HAL_ADC_MspDeInit() (recommended code location) or with
AnnaBridge	167:e84263d55307	196	other device clock parameters configuration:
AnnaBridge	167:e84263d55307	197	(+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
AnnaBridge	167:e84263d55307	198	(+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
AnnaBridge	167:e84263d55307	199	(+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
<>	144:ef7eb2e8f9f7	200
AnnaBridge	167:e84263d55307	201	(#) ADC pins configuration
AnnaBridge	167:e84263d55307	202	(++) Disable the clock for the ADC GPIOs
AnnaBridge	167:e84263d55307	203	using macro __HAL_RCC_GPIOx_CLK_DISABLE()
AnnaBridge	167:e84263d55307	204
AnnaBridge	167:e84263d55307	205	(#) Optionally, in case of usage of ADC with interruptions:
AnnaBridge	167:e84263d55307	206	(++) Disable the NVIC for ADC
AnnaBridge	167:e84263d55307	207	using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
AnnaBridge	167:e84263d55307	208
AnnaBridge	167:e84263d55307	209	(#) Optionally, in case of usage of DMA:
AnnaBridge	167:e84263d55307	210	(++) Deinitialize the DMA
AnnaBridge	167:e84263d55307	211	using function HAL_DMA_Init().
AnnaBridge	167:e84263d55307	212	(++) Disable the NVIC for DMA
AnnaBridge	167:e84263d55307	213	using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
AnnaBridge	167:e84263d55307	214
AnnaBridge	167:e84263d55307	215	[..]
<>	144:ef7eb2e8f9f7	216
<>	144:ef7eb2e8f9f7	217	@endverbatim
<>	144:ef7eb2e8f9f7	218	******************************************************************************
<>	144:ef7eb2e8f9f7	219	* @attention
<>	144:ef7eb2e8f9f7	220	*
AnnaBridge	167:e84263d55307	221	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	222	*
<>	144:ef7eb2e8f9f7	223	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	224	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	225	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	226	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	227	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	228	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	229	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	230	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	231	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	232	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	233	*
<>	144:ef7eb2e8f9f7	234	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	235	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	236	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	237	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	238	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	239	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	240	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	241	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	242	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	243	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	244	*
<>	144:ef7eb2e8f9f7	245	******************************************************************************
<>	144:ef7eb2e8f9f7	246	*/
<>	144:ef7eb2e8f9f7	247
<>	144:ef7eb2e8f9f7	248	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	249	#include "stm32l4xx_hal.h"
<>	144:ef7eb2e8f9f7	250
<>	144:ef7eb2e8f9f7	251	/** @addtogroup STM32L4xx_HAL_Driver
<>	144:ef7eb2e8f9f7	252	* @{
<>	144:ef7eb2e8f9f7	253	*/
<>	144:ef7eb2e8f9f7	254
<>	144:ef7eb2e8f9f7	255	/** @defgroup ADC ADC
<>	144:ef7eb2e8f9f7	256	* @brief ADC HAL module driver
<>	144:ef7eb2e8f9f7	257	* @{
AnnaBridge	167:e84263d55307	258	*/
<>	144:ef7eb2e8f9f7	259
<>	144:ef7eb2e8f9f7	260	#ifdef HAL_ADC_MODULE_ENABLED
AnnaBridge	167:e84263d55307	261
<>	144:ef7eb2e8f9f7	262	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	263	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	264
<>	144:ef7eb2e8f9f7	265	/** @defgroup ADC_Private_Constants ADC Private Constants
AnnaBridge	167:e84263d55307	266	* @{
<>	144:ef7eb2e8f9f7	267	*/
AnnaBridge	167:e84263d55307	268
<>	144:ef7eb2e8f9f7	269	#define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR_RES \| ADC_CFGR_ALIGN \|\
<>	144:ef7eb2e8f9f7	270	ADC_CFGR_CONT \| ADC_CFGR_OVRMOD \|\
<>	144:ef7eb2e8f9f7	271	ADC_CFGR_DISCEN \| ADC_CFGR_DISCNUM \|\
<>	144:ef7eb2e8f9f7	272	ADC_CFGR_EXTEN \| ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
<>	144:ef7eb2e8f9f7	273	when no regular conversion is on-going */
<>	144:ef7eb2e8f9f7	274
<>	144:ef7eb2e8f9f7	275	#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE \| ADC_CFGR2_OVSR \|\
<>	144:ef7eb2e8f9f7	276	ADC_CFGR2_OVSS \| ADC_CFGR2_TROVS \|\
<>	144:ef7eb2e8f9f7	277	ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
<>	144:ef7eb2e8f9f7	278	(neither regular nor injected) is on-going */
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	#define ADC_CFGR_WD_FIELDS ((uint32_t)(ADC_CFGR_AWD1SGL \| ADC_CFGR_JAWD1EN \| \
<>	144:ef7eb2e8f9f7	281	ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1CH)) /*!< ADC_CFGR fields of Analog Watchdog parameters that can be updated when no
<>	144:ef7eb2e8f9f7	282	conversion (neither regular nor injected) is on-going */
<>	144:ef7eb2e8f9f7	283
<>	144:ef7eb2e8f9f7	284	#define ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 \| ADC_OFR1_OFFSET1_CH \| ADC_OFR1_OFFSET1_EN)) /*!< ADC_OFR fields of parameters that can be updated when no conversion
<>	144:ef7eb2e8f9f7	285	(neither regular nor injected) is on-going */
<>	144:ef7eb2e8f9f7	286
<>	144:ef7eb2e8f9f7	287
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	/* Delay to wait before setting ADEN once ADCAL has been reset
<>	144:ef7eb2e8f9f7	290	must be at least 4 ADC clock cycles.
<>	144:ef7eb2e8f9f7	291	Assuming lowest ADC clock (140 KHz according to DS), this
<>	144:ef7eb2e8f9f7	292	4 ADC clock cycles duration is equal to
<>	144:ef7eb2e8f9f7	293	4 / 140,000 = 0.028 ms.
<>	144:ef7eb2e8f9f7	294	ADC_ENABLE_TIMEOUT set to 2 is a margin large enough to ensure
<>	144:ef7eb2e8f9f7	295	the 4 ADC clock cycles have elapsed while waiting for ADRDY
<>	144:ef7eb2e8f9f7	296	to become 1 */
<>	144:ef7eb2e8f9f7	297	#define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /!< ADC enable time-out value /
<>	144:ef7eb2e8f9f7	298	#define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /!< ADC disable time-out value /
<>	144:ef7eb2e8f9f7	299
<>	144:ef7eb2e8f9f7	300
<>	144:ef7eb2e8f9f7	301
<>	144:ef7eb2e8f9f7	302	/* Delay for ADC voltage regulator startup time */
<>	144:ef7eb2e8f9f7	303	/* Maximum delay is 10 microseconds */
<>	144:ef7eb2e8f9f7	304	/* (refer device RM, parameter Tadcvreg_stup). */
<>	144:ef7eb2e8f9f7	305	#define ADC_STAB_DELAY_US ((uint32_t) 10) /!< ADC voltage regulator startup time /
<>	144:ef7eb2e8f9f7	306
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	/* Timeout to wait for current conversion on going to be completed. */
<>	144:ef7eb2e8f9f7	309	/* Timeout fixed to worst case, for 1 channel. */
<>	144:ef7eb2e8f9f7	310	/* - maximum sampling time (640.5 adc_clk) */
<>	144:ef7eb2e8f9f7	311	/* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
<>	144:ef7eb2e8f9f7	312	/* - ADC clock with prescaler 256 */
<>	144:ef7eb2e8f9f7	313	/* 653 * 256 = 167168 clock cycles max */
<>	144:ef7eb2e8f9f7	314	/* Unit: cycles of CPU clock. */
<>	144:ef7eb2e8f9f7	315	#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 167168) /!< ADC conversion completion time-out value /
AnnaBridge	167:e84263d55307	316
<>	144:ef7eb2e8f9f7	317
AnnaBridge	167:e84263d55307	318
AnnaBridge	167:e84263d55307	319
<>	144:ef7eb2e8f9f7	320	/**
<>	144:ef7eb2e8f9f7	321	* @}
AnnaBridge	167:e84263d55307	322	*/
AnnaBridge	167:e84263d55307	323
<>	144:ef7eb2e8f9f7	324	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	325	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	326	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	327	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	328
<>	144:ef7eb2e8f9f7	329	/** @defgroup ADC_Exported_Functions ADC Exported Functions
<>	144:ef7eb2e8f9f7	330	* @{
AnnaBridge	167:e84263d55307	331	*/
<>	144:ef7eb2e8f9f7	332
<>	144:ef7eb2e8f9f7	333	/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge	167:e84263d55307	334	* @brief ADC Initialization and Configuration functions
AnnaBridge	167:e84263d55307	335	*
<>	144:ef7eb2e8f9f7	336	@verbatim
<>	144:ef7eb2e8f9f7	337	===============================================================================
<>	144:ef7eb2e8f9f7	338	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	339	===============================================================================
<>	144:ef7eb2e8f9f7	340	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	341	(+) Initialize and configure the ADC.
AnnaBridge	167:e84263d55307	342	(+) De-initialize the ADC.
<>	144:ef7eb2e8f9f7	343	@endverbatim
<>	144:ef7eb2e8f9f7	344	* @{
<>	144:ef7eb2e8f9f7	345	*/
<>	144:ef7eb2e8f9f7	346
<>	144:ef7eb2e8f9f7	347	/**
<>	144:ef7eb2e8f9f7	348	* @brief Initialize the ADC peripheral and regular group according to
<>	144:ef7eb2e8f9f7	349	* parameters specified in structure "ADC_InitTypeDef".
<>	144:ef7eb2e8f9f7	350	* @note As prerequisite, ADC clock must be configured at RCC top level
<>	144:ef7eb2e8f9f7	351	* depending on possible clock sources: System/PLLSAI1/PLLSAI2 clocks
<>	144:ef7eb2e8f9f7	352	* or AHB clock.
<>	144:ef7eb2e8f9f7	353	* @note Possibility to update parameters on the fly:
AnnaBridge	167:e84263d55307	354	* This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
<>	144:ef7eb2e8f9f7	355	* coming from ADC state reset. Following calls to this function can
<>	144:ef7eb2e8f9f7	356	* be used to reconfigure some parameters of ADC_InitTypeDef
<>	144:ef7eb2e8f9f7	357	* structure on the fly, without modifying MSP configuration. If ADC
<>	144:ef7eb2e8f9f7	358	* MSP has to be modified again, HAL_ADC_DeInit() must be called
<>	144:ef7eb2e8f9f7	359	* before HAL_ADC_Init().
AnnaBridge	167:e84263d55307	360	* The setting of these parameters is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	361	* For parameters constraints, see comments of structure
<>	144:ef7eb2e8f9f7	362	* "ADC_InitTypeDef".
<>	144:ef7eb2e8f9f7	363	* @note This function configures the ADC within 2 scopes: scope of entire
<>	144:ef7eb2e8f9f7	364	* ADC and scope of regular group. For parameters details, see comments
<>	144:ef7eb2e8f9f7	365	* of structure "ADC_InitTypeDef".
<>	144:ef7eb2e8f9f7	366	* @note Parameters related to common ADC registers (ADC clock mode) are set
<>	144:ef7eb2e8f9f7	367	* only if all ADCs are disabled.
<>	144:ef7eb2e8f9f7	368	* If this is not the case, these common parameters setting are
<>	144:ef7eb2e8f9f7	369	* bypassed without error reporting: it can be the intended behaviour in
<>	144:ef7eb2e8f9f7	370	* case of update of a parameter of ADC_InitTypeDef on the fly,
<>	144:ef7eb2e8f9f7	371	* without disabling the other ADCs.
<>	144:ef7eb2e8f9f7	372	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	373	* @retval HAL status
<>	144:ef7eb2e8f9f7	374	*/
<>	144:ef7eb2e8f9f7	375	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	376	{
AnnaBridge	167:e84263d55307	377	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
AnnaBridge	167:e84263d55307	378
<>	144:ef7eb2e8f9f7	379	ADC_Common_TypeDef *tmpADC_Common;
<>	144:ef7eb2e8f9f7	380	uint32_t tmpCFGR = 0;
<>	144:ef7eb2e8f9f7	381	__IO uint32_t wait_loop_index = 0;
<>	144:ef7eb2e8f9f7	382
<>	144:ef7eb2e8f9f7	383	/* Check ADC handle */
<>	144:ef7eb2e8f9f7	384	if(hadc == NULL)
<>	144:ef7eb2e8f9f7	385	{
<>	144:ef7eb2e8f9f7	386	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	387	}
<>	144:ef7eb2e8f9f7	388
<>	144:ef7eb2e8f9f7	389	/* Check the parameters */
<>	144:ef7eb2e8f9f7	390	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
AnnaBridge	167:e84263d55307	391	assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
<>	144:ef7eb2e8f9f7	392	assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
AnnaBridge	167:e84263d55307	393	assert_param(IS_ADC_DFSDMCFG_MODE(hadc));
<>	144:ef7eb2e8f9f7	394	assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
<>	144:ef7eb2e8f9f7	395	assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
<>	144:ef7eb2e8f9f7	396	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<>	144:ef7eb2e8f9f7	397	assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
<>	144:ef7eb2e8f9f7	398	assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
<>	144:ef7eb2e8f9f7	399	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
<>	144:ef7eb2e8f9f7	400	assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
<>	144:ef7eb2e8f9f7	401	assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
<>	144:ef7eb2e8f9f7	402	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
<>	144:ef7eb2e8f9f7	403	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
<>	144:ef7eb2e8f9f7	404
<>	144:ef7eb2e8f9f7	405	if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
<>	144:ef7eb2e8f9f7	406	{
<>	144:ef7eb2e8f9f7	407	assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
<>	144:ef7eb2e8f9f7	408	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
<>	144:ef7eb2e8f9f7	409
<>	144:ef7eb2e8f9f7	410	if (hadc->Init.DiscontinuousConvMode == ENABLE)
AnnaBridge	167:e84263d55307	411	{
<>	144:ef7eb2e8f9f7	412	assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
<>	144:ef7eb2e8f9f7	413	}
<>	144:ef7eb2e8f9f7	414	}
AnnaBridge	167:e84263d55307	415
<>	144:ef7eb2e8f9f7	416
AnnaBridge	167:e84263d55307	417	/* DISCEN and CONT bits cannot be set at the same time */
<>	144:ef7eb2e8f9f7	418	assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
<>	144:ef7eb2e8f9f7	419
<>	144:ef7eb2e8f9f7	420
<>	144:ef7eb2e8f9f7	421	/* Actions performed only if ADC is coming from state reset: */
<>	144:ef7eb2e8f9f7	422	/* - Initialization of ADC MSP */
<>	144:ef7eb2e8f9f7	423	if (hadc->State == HAL_ADC_STATE_RESET)
<>	144:ef7eb2e8f9f7	424	{
<>	144:ef7eb2e8f9f7	425	/* Init the low level hardware */
<>	144:ef7eb2e8f9f7	426	HAL_ADC_MspInit(hadc);
<>	144:ef7eb2e8f9f7	427
<>	144:ef7eb2e8f9f7	428	/* Set ADC error code to none */
<>	144:ef7eb2e8f9f7	429	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	430
<>	144:ef7eb2e8f9f7	431	/* Initialize Lock */
<>	144:ef7eb2e8f9f7	432	hadc->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	433	}
AnnaBridge	167:e84263d55307	434
AnnaBridge	167:e84263d55307	435
AnnaBridge	167:e84263d55307	436	/* - Exit from deep-power-down mode and ADC voltage regulator enable */
<>	144:ef7eb2e8f9f7	437	/* Exit deep power down mode if still in that state */
<>	144:ef7eb2e8f9f7	438	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
<>	144:ef7eb2e8f9f7	439	{
<>	144:ef7eb2e8f9f7	440	/* Exit deep power down mode */
<>	144:ef7eb2e8f9f7	441	CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
<>	144:ef7eb2e8f9f7	442
<>	144:ef7eb2e8f9f7	443	/* System was in deep power down mode, calibration must
<>	144:ef7eb2e8f9f7	444	be relaunched or a previously saved calibration factor
<>	144:ef7eb2e8f9f7	445	re-applied once the ADC voltage regulator is enabled */
<>	144:ef7eb2e8f9f7	446	}
<>	144:ef7eb2e8f9f7	447
<>	144:ef7eb2e8f9f7	448	if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
<>	144:ef7eb2e8f9f7	449	{
<>	144:ef7eb2e8f9f7	450	/* Enable ADC internal voltage regulator */
<>	144:ef7eb2e8f9f7	451	SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
<>	144:ef7eb2e8f9f7	452
<>	144:ef7eb2e8f9f7	453	/* Delay for ADC stabilization time */
<>	144:ef7eb2e8f9f7	454	/* Wait loop initialization and execution */
<>	144:ef7eb2e8f9f7	455	/* Note: Variable divided by 2 to compensate partially */
<>	144:ef7eb2e8f9f7	456	/* CPU processing cycles. */
<>	144:ef7eb2e8f9f7	457	wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000 * 2)));
<>	144:ef7eb2e8f9f7	458	while(wait_loop_index != 0)
<>	144:ef7eb2e8f9f7	459	{
<>	144:ef7eb2e8f9f7	460	wait_loop_index--;
<>	144:ef7eb2e8f9f7	461	}
<>	144:ef7eb2e8f9f7	462	}
<>	144:ef7eb2e8f9f7	463
<>	144:ef7eb2e8f9f7	464	/* Verification that ADC voltage regulator is correctly enabled, whether */
<>	144:ef7eb2e8f9f7	465	/* or not ADC is coming from state reset (if any potential problem of */
<>	144:ef7eb2e8f9f7	466	/* clocking, voltage regulator would not be enabled). */
<>	144:ef7eb2e8f9f7	467	if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
<>	144:ef7eb2e8f9f7	468	{
<>	144:ef7eb2e8f9f7	469	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	470	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	471
<>	144:ef7eb2e8f9f7	472	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	473	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	474
AnnaBridge	167:e84263d55307	475	tmp_hal_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	476	}
AnnaBridge	167:e84263d55307	477
<>	144:ef7eb2e8f9f7	478	/* Configuration of ADC parameters if previous preliminary actions are */
<>	144:ef7eb2e8f9f7	479	/* correctly completed and if there is no conversion on going on regular */
<>	144:ef7eb2e8f9f7	480	/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
<>	144:ef7eb2e8f9f7	481	/* called to update a parameter on the fly). */
<>	144:ef7eb2e8f9f7	482	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
<>	144:ef7eb2e8f9f7	483	(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
<>	144:ef7eb2e8f9f7	484	{
<>	144:ef7eb2e8f9f7	485
<>	144:ef7eb2e8f9f7	486	/* Initialize the ADC state */
<>	144:ef7eb2e8f9f7	487	SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
<>	144:ef7eb2e8f9f7	488
<>	144:ef7eb2e8f9f7	489	/* Configuration of common ADC parameters */
<>	144:ef7eb2e8f9f7	490
<>	144:ef7eb2e8f9f7	491	/* Pointer to the common control register */
<>	144:ef7eb2e8f9f7	492	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	493
AnnaBridge	167:e84263d55307	494
<>	144:ef7eb2e8f9f7	495	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	496	/* Parameters that can be updated only when ADC is disabled: */
<>	144:ef7eb2e8f9f7	497	/* - clock configuration */
<>	144:ef7eb2e8f9f7	498	if ((ADC_IS_ENABLE(hadc) == RESET) &&
AnnaBridge	167:e84263d55307	499	(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
<>	144:ef7eb2e8f9f7	500	{
<>	144:ef7eb2e8f9f7	501	/* Reset configuration of ADC common register CCR: */
<>	144:ef7eb2e8f9f7	502	/* */
<>	144:ef7eb2e8f9f7	503	/* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
<>	144:ef7eb2e8f9f7	504	/* according to adc->Init.ClockPrescaler. It selects the clock */
<>	144:ef7eb2e8f9f7	505	/* source and sets the clock division factor. */
<>	144:ef7eb2e8f9f7	506	/* */
<>	144:ef7eb2e8f9f7	507	/* Some parameters of this register are not reset, since they are set */
<>	144:ef7eb2e8f9f7	508	/* by other functions and must be kept in case of usage of this */
<>	144:ef7eb2e8f9f7	509	/* function on the fly (update of a parameter of ADC_InitTypeDef */
<>	144:ef7eb2e8f9f7	510	/* without needing to reconfigure all other ADC groups/channels */
<>	144:ef7eb2e8f9f7	511	/* parameters): */
<>	144:ef7eb2e8f9f7	512	/* - when multimode feature is available, multimode-related */
<>	144:ef7eb2e8f9f7	513	/* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
<>	144:ef7eb2e8f9f7	514	/* HAL_ADCEx_MultiModeConfigChannel() ) */
<>	144:ef7eb2e8f9f7	515	/* - internal measurement paths: Vbat, temperature sensor, Vref */
<>	144:ef7eb2e8f9f7	516	/* (set into HAL_ADC_ConfigChannel() or */
<>	144:ef7eb2e8f9f7	517	/* HAL_ADCEx_InjectedConfigChannel() ) */
<>	144:ef7eb2e8f9f7	518
<>	144:ef7eb2e8f9f7	519	MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_PRESC\|ADC_CCR_CKMODE, hadc->Init.ClockPrescaler);
<>	144:ef7eb2e8f9f7	520	}
AnnaBridge	167:e84263d55307	521
<>	144:ef7eb2e8f9f7	522	/* Configuration of ADC: */
<>	144:ef7eb2e8f9f7	523	/* - resolution Init.Resolution */
<>	144:ef7eb2e8f9f7	524	/* - data alignment Init.DataAlign */
<>	144:ef7eb2e8f9f7	525	/* - external trigger to start conversion Init.ExternalTrigConv */
<>	144:ef7eb2e8f9f7	526	/* - external trigger polarity Init.ExternalTrigConvEdge */
<>	144:ef7eb2e8f9f7	527	/* - continuous conversion mode Init.ContinuousConvMode */
<>	144:ef7eb2e8f9f7	528	/* - overrun Init.Overrun */
<>	144:ef7eb2e8f9f7	529	/* - discontinuous mode Init.DiscontinuousConvMode */
AnnaBridge	167:e84263d55307	530	/* - discontinuous mode channel count Init.NbrOfDiscConversion */
AnnaBridge	167:e84263d55307	531	tmpCFGR = (ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) \|
AnnaBridge	167:e84263d55307	532	hadc->Init.Overrun \|
AnnaBridge	167:e84263d55307	533	hadc->Init.DataAlign \|
AnnaBridge	167:e84263d55307	534	hadc->Init.Resolution \|
AnnaBridge	167:e84263d55307	535	ADC_CFGR_REG_DISCONTINUOUS(hadc->Init.DiscontinuousConvMode) );
AnnaBridge	167:e84263d55307	536
AnnaBridge	167:e84263d55307	537	if (hadc->Init.DiscontinuousConvMode == ENABLE)
AnnaBridge	167:e84263d55307	538	{
AnnaBridge	167:e84263d55307	539	tmpCFGR \|= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
AnnaBridge	167:e84263d55307	540	}
AnnaBridge	167:e84263d55307	541
<>	144:ef7eb2e8f9f7	542	/* Enable external trigger if trigger selection is different of software */
<>	144:ef7eb2e8f9f7	543	/* start. */
<>	144:ef7eb2e8f9f7	544	/* - external trigger to start conversion Init.ExternalTrigConv */
AnnaBridge	167:e84263d55307	545	/* - external trigger polarity Init.ExternalTrigConvEdge */
<>	144:ef7eb2e8f9f7	546	/* Note: parameter ExternalTrigConvEdge set to "trigger edge none" is */
<>	144:ef7eb2e8f9f7	547	/* equivalent to software start. */
<>	144:ef7eb2e8f9f7	548	if ((hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
<>	144:ef7eb2e8f9f7	549	&& (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE))
<>	144:ef7eb2e8f9f7	550	{
<>	144:ef7eb2e8f9f7	551	tmpCFGR \|= ( hadc->Init.ExternalTrigConv \| hadc->Init.ExternalTrigConvEdge);
<>	144:ef7eb2e8f9f7	552	}
<>	144:ef7eb2e8f9f7	553
<>	144:ef7eb2e8f9f7	554	/* Update Configuration Register CFGR */
<>	144:ef7eb2e8f9f7	555	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
<>	144:ef7eb2e8f9f7	556
<>	144:ef7eb2e8f9f7	557	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	558	/* Parameters that can be updated when ADC is disabled or enabled without */
<>	144:ef7eb2e8f9f7	559	/* conversion on going on regular and injected groups: */
<>	144:ef7eb2e8f9f7	560	/* - DMA continuous request Init.DMAContinuousRequests */
<>	144:ef7eb2e8f9f7	561	/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
AnnaBridge	167:e84263d55307	562	/* - Oversampling parameters Init.Oversampling */
<>	144:ef7eb2e8f9f7	563	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
<>	144:ef7eb2e8f9f7	564	{
<>	144:ef7eb2e8f9f7	565	tmpCFGR = ( ADC_CFGR_DFSDM(hadc) \|
<>	144:ef7eb2e8f9f7	566	ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) \|
<>	144:ef7eb2e8f9f7	567	ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
<>	144:ef7eb2e8f9f7	568
<>	144:ef7eb2e8f9f7	569	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
<>	144:ef7eb2e8f9f7	570
<>	144:ef7eb2e8f9f7	571
<>	144:ef7eb2e8f9f7	572	if (hadc->Init.OversamplingMode == ENABLE)
<>	144:ef7eb2e8f9f7	573	{
<>	144:ef7eb2e8f9f7	574	assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
<>	144:ef7eb2e8f9f7	575	assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
<>	144:ef7eb2e8f9f7	576	assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
<>	144:ef7eb2e8f9f7	577	assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
<>	144:ef7eb2e8f9f7	578
<>	144:ef7eb2e8f9f7	579	if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
<>	144:ef7eb2e8f9f7	580	\|\| (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
<>	144:ef7eb2e8f9f7	581	{
<>	144:ef7eb2e8f9f7	582	/* Multi trigger is not applicable to software-triggered conversions */
<>	144:ef7eb2e8f9f7	583	assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
AnnaBridge	167:e84263d55307	584	}
<>	144:ef7eb2e8f9f7	585
<>	144:ef7eb2e8f9f7	586
<>	144:ef7eb2e8f9f7	587	/* Configuration of Oversampler: */
<>	144:ef7eb2e8f9f7	588	/* - Oversampling Ratio */
<>	144:ef7eb2e8f9f7	589	/* - Right bit shift */
<>	144:ef7eb2e8f9f7	590	/* - Triggered mode */
AnnaBridge	167:e84263d55307	591	/* - Oversampling mode (continued/resumed) */
<>	144:ef7eb2e8f9f7	592	MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
<>	144:ef7eb2e8f9f7	593	ADC_CFGR2_ROVSE \|
<>	144:ef7eb2e8f9f7	594	hadc->Init.Oversampling.Ratio \|
<>	144:ef7eb2e8f9f7	595	hadc->Init.Oversampling.RightBitShift \|
<>	144:ef7eb2e8f9f7	596	hadc->Init.Oversampling.TriggeredMode \|
<>	144:ef7eb2e8f9f7	597	hadc->Init.Oversampling.OversamplingStopReset);
AnnaBridge	167:e84263d55307	598	}
<>	144:ef7eb2e8f9f7	599	else
<>	144:ef7eb2e8f9f7	600	{
<>	144:ef7eb2e8f9f7	601	/* Disable Regular OverSampling */
<>	144:ef7eb2e8f9f7	602	CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
AnnaBridge	167:e84263d55307	603	}
AnnaBridge	167:e84263d55307	604
<>	144:ef7eb2e8f9f7	605	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
<>	144:ef7eb2e8f9f7	606
<>	144:ef7eb2e8f9f7	607
<>	144:ef7eb2e8f9f7	608
<>	144:ef7eb2e8f9f7	609	/* Configuration of regular group sequencer: */
<>	144:ef7eb2e8f9f7	610	/* - if scan mode is disabled, regular channels sequence length is set to */
<>	144:ef7eb2e8f9f7	611	/* 0x00: 1 channel converted (channel on regular rank 1) */
<>	144:ef7eb2e8f9f7	612	/* Parameter "NbrOfConversion" is discarded. */
<>	144:ef7eb2e8f9f7	613	/* Note: Scan mode is not present by hardware on this device, but */
<>	144:ef7eb2e8f9f7	614	/* emulated by software for alignment over all STM32 devices. */
<>	144:ef7eb2e8f9f7	615	/* - if scan mode is enabled, regular channels sequence length is set to */
<>	144:ef7eb2e8f9f7	616	/* parameter "NbrOfConversion" */
<>	144:ef7eb2e8f9f7	617
<>	144:ef7eb2e8f9f7	618	if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
<>	144:ef7eb2e8f9f7	619	{
<>	144:ef7eb2e8f9f7	620	/* Set number of ranks in regular group sequencer */
<>	144:ef7eb2e8f9f7	621	MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
AnnaBridge	167:e84263d55307	622	}
<>	144:ef7eb2e8f9f7	623	else
<>	144:ef7eb2e8f9f7	624	{
<>	144:ef7eb2e8f9f7	625	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
<>	144:ef7eb2e8f9f7	626	}
<>	144:ef7eb2e8f9f7	627
<>	144:ef7eb2e8f9f7	628	/* Initialize the ADC state */
<>	144:ef7eb2e8f9f7	629	/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
<>	144:ef7eb2e8f9f7	630	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	631	}
<>	144:ef7eb2e8f9f7	632	else
<>	144:ef7eb2e8f9f7	633	{
<>	144:ef7eb2e8f9f7	634	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	635	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
AnnaBridge	167:e84263d55307	636
AnnaBridge	167:e84263d55307	637	tmp_hal_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	638	} /* if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) */
<>	144:ef7eb2e8f9f7	639
<>	144:ef7eb2e8f9f7	640	/* Return function status */
AnnaBridge	167:e84263d55307	641	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	642	}
<>	144:ef7eb2e8f9f7	643
<>	144:ef7eb2e8f9f7	644	/**
<>	144:ef7eb2e8f9f7	645	* @brief Deinitialize the ADC peripheral registers to their default reset
<>	144:ef7eb2e8f9f7	646	* values, with deinitialization of the ADC MSP.
<>	144:ef7eb2e8f9f7	647	* @note Keep in mind that all ADCs use the same clock: disabling
<>	144:ef7eb2e8f9f7	648	* the clock will reset all ADCs.
<>	144:ef7eb2e8f9f7	649	* @note By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by
<>	144:ef7eb2e8f9f7	650	* reducing the leakage currents and is particularly interesting before
AnnaBridge	167:e84263d55307	651	* entering STOP 1 or STOP 2 modes.
<>	144:ef7eb2e8f9f7	652	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	653	* @retval HAL status
<>	144:ef7eb2e8f9f7	654	*/
<>	144:ef7eb2e8f9f7	655	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
AnnaBridge	167:e84263d55307	656	{
<>	144:ef7eb2e8f9f7	657	/* Check ADC handle */
<>	144:ef7eb2e8f9f7	658	if(hadc == NULL)
<>	144:ef7eb2e8f9f7	659	{
AnnaBridge	167:e84263d55307	660	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	661	}
<>	144:ef7eb2e8f9f7	662
<>	144:ef7eb2e8f9f7	663	/* Check the parameters */
<>	144:ef7eb2e8f9f7	664	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	665
AnnaBridge	167:e84263d55307	666	/* Set ADC state */
<>	144:ef7eb2e8f9f7	667	SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
<>	144:ef7eb2e8f9f7	668
<>	144:ef7eb2e8f9f7	669	/* Stop potential conversion on going, on regular and injected groups */
AnnaBridge	167:e84263d55307	670	/* Note: No check on ADC_ConversionStop() return status, */
AnnaBridge	167:e84263d55307	671	/* if the conversion stop failed, it is up to */
AnnaBridge	167:e84263d55307	672	/* HAL_ADC_MspDeInit() to reset the ADC IP. */
<>	144:ef7eb2e8f9f7	673	ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<>	144:ef7eb2e8f9f7	674
<>	144:ef7eb2e8f9f7	675	/* Disable ADC peripheral if conversions are effectively stopped */
<>	144:ef7eb2e8f9f7	676	/* Flush register JSQR: reset the queue sequencer when injected */
<>	144:ef7eb2e8f9f7	677	/* queue sequencer is enabled and ADC disabled. */
<>	144:ef7eb2e8f9f7	678	/* The software and hardware triggers of the injected sequence are both */
<>	144:ef7eb2e8f9f7	679	/* internally disabled just after the completion of the last valid */
<>	144:ef7eb2e8f9f7	680	/* injected sequence. */
<>	144:ef7eb2e8f9f7	681	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
AnnaBridge	167:e84263d55307	682
<>	144:ef7eb2e8f9f7	683	/* Disable the ADC peripheral */
<>	144:ef7eb2e8f9f7	684	/* No check on ADC_Disable() return status, if the ADC disabling process
<>	144:ef7eb2e8f9f7	685	failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
<>	144:ef7eb2e8f9f7	686	ADC_Disable(hadc);
AnnaBridge	167:e84263d55307	687
AnnaBridge	167:e84263d55307	688
<>	144:ef7eb2e8f9f7	689	/* ========== Reset ADC registers ========== */
<>	144:ef7eb2e8f9f7	690	/* Reset register IER */
<>	144:ef7eb2e8f9f7	691	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 \| ADC_IT_AWD2 \| ADC_IT_AWD1 \|
<>	144:ef7eb2e8f9f7	692	ADC_IT_JQOVF \| ADC_IT_OVR \|
<>	144:ef7eb2e8f9f7	693	ADC_IT_JEOS \| ADC_IT_JEOC \|
<>	144:ef7eb2e8f9f7	694	ADC_IT_EOS \| ADC_IT_EOC \|
<>	144:ef7eb2e8f9f7	695	ADC_IT_EOSMP \| ADC_IT_RDY ) );
<>	144:ef7eb2e8f9f7	696
<>	144:ef7eb2e8f9f7	697	/* Reset register ISR */
<>	144:ef7eb2e8f9f7	698	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 \| ADC_FLAG_AWD2 \| ADC_FLAG_AWD1 \|
<>	144:ef7eb2e8f9f7	699	ADC_FLAG_JQOVF \| ADC_FLAG_OVR \|
<>	144:ef7eb2e8f9f7	700	ADC_FLAG_JEOS \| ADC_FLAG_JEOC \|
<>	144:ef7eb2e8f9f7	701	ADC_FLAG_EOS \| ADC_FLAG_EOC \|
<>	144:ef7eb2e8f9f7	702	ADC_FLAG_EOSMP \| ADC_FLAG_RDY ) );
<>	144:ef7eb2e8f9f7	703
<>	144:ef7eb2e8f9f7	704	/* Reset register CR */
<>	144:ef7eb2e8f9f7	705	/* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
<>	144:ef7eb2e8f9f7	706	ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
<>	144:ef7eb2e8f9f7	707	no direct reset applicable.
<>	144:ef7eb2e8f9f7	708	Update CR register to reset value where doable by software */
<>	144:ef7eb2e8f9f7	709	CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN \| ADC_CR_ADCALDIF);
<>	144:ef7eb2e8f9f7	710	SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
<>	144:ef7eb2e8f9f7	711
<>	144:ef7eb2e8f9f7	712	/* Reset register CFGR */
<>	144:ef7eb2e8f9f7	713	CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
<>	144:ef7eb2e8f9f7	714	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
<>	144:ef7eb2e8f9f7	715
<>	144:ef7eb2e8f9f7	716	/* Reset register CFGR2 */
<>	144:ef7eb2e8f9f7	717	CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM \| ADC_CFGR2_TROVS \| ADC_CFGR2_OVSS \|
<>	144:ef7eb2e8f9f7	718	ADC_CFGR2_OVSR \| ADC_CFGR2_JOVSE \| ADC_CFGR2_ROVSE );
<>	144:ef7eb2e8f9f7	719
<>	144:ef7eb2e8f9f7	720	/* Reset register SMPR1 */
<>	144:ef7eb2e8f9f7	721	CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	/* Reset register SMPR2 */
<>	144:ef7eb2e8f9f7	724	CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 \| ADC_SMPR2_SMP17 \| ADC_SMPR2_SMP16 \|
<>	144:ef7eb2e8f9f7	725	ADC_SMPR2_SMP15 \| ADC_SMPR2_SMP14 \| ADC_SMPR2_SMP13 \|
<>	144:ef7eb2e8f9f7	726	ADC_SMPR2_SMP12 \| ADC_SMPR2_SMP11 \| ADC_SMPR2_SMP10 );
<>	144:ef7eb2e8f9f7	727
<>	144:ef7eb2e8f9f7	728	/* Reset register TR1 */
<>	144:ef7eb2e8f9f7	729	CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 \| ADC_TR1_LT1);
<>	144:ef7eb2e8f9f7	730
<>	144:ef7eb2e8f9f7	731	/* Reset register TR2 */
<>	144:ef7eb2e8f9f7	732	CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 \| ADC_TR2_LT2);
<>	144:ef7eb2e8f9f7	733
<>	144:ef7eb2e8f9f7	734	/* Reset register TR3 */
<>	144:ef7eb2e8f9f7	735	CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 \| ADC_TR3_LT3);
<>	144:ef7eb2e8f9f7	736
<>	144:ef7eb2e8f9f7	737	/* Reset register SQR1 */
<>	144:ef7eb2e8f9f7	738	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 \| ADC_SQR1_SQ3 \| ADC_SQR1_SQ2 \|
<>	144:ef7eb2e8f9f7	739	ADC_SQR1_SQ1 \| ADC_SQR1_L);
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	/* Reset register SQR2 */
<>	144:ef7eb2e8f9f7	742	CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 \| ADC_SQR2_SQ8 \| ADC_SQR2_SQ7 \|
<>	144:ef7eb2e8f9f7	743	ADC_SQR2_SQ6 \| ADC_SQR2_SQ5);
<>	144:ef7eb2e8f9f7	744
<>	144:ef7eb2e8f9f7	745	/* Reset register SQR3 */
<>	144:ef7eb2e8f9f7	746	CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 \| ADC_SQR3_SQ13 \| ADC_SQR3_SQ12 \|
<>	144:ef7eb2e8f9f7	747	ADC_SQR3_SQ11 \| ADC_SQR3_SQ10);
<>	144:ef7eb2e8f9f7	748
<>	144:ef7eb2e8f9f7	749	/* Reset register SQR4 */
<>	144:ef7eb2e8f9f7	750	CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 \| ADC_SQR4_SQ15);
<>	144:ef7eb2e8f9f7	751
<>	144:ef7eb2e8f9f7	752	/* Register JSQR was reset when the ADC was disabled */
<>	144:ef7eb2e8f9f7	753
<>	144:ef7eb2e8f9f7	754	/* Reset register DR */
<>	144:ef7eb2e8f9f7	755	/* bits in access mode read only, no direct reset applicable*/
<>	144:ef7eb2e8f9f7	756
<>	144:ef7eb2e8f9f7	757	/* Reset register OFR1 */
<>	144:ef7eb2e8f9f7	758	CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN \| ADC_OFR1_OFFSET1_CH \| ADC_OFR1_OFFSET1);
<>	144:ef7eb2e8f9f7	759	/* Reset register OFR2 */
<>	144:ef7eb2e8f9f7	760	CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN \| ADC_OFR2_OFFSET2_CH \| ADC_OFR2_OFFSET2);
<>	144:ef7eb2e8f9f7	761	/* Reset register OFR3 */
<>	144:ef7eb2e8f9f7	762	CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN \| ADC_OFR3_OFFSET3_CH \| ADC_OFR3_OFFSET3);
<>	144:ef7eb2e8f9f7	763	/* Reset register OFR4 */
<>	144:ef7eb2e8f9f7	764	CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN \| ADC_OFR4_OFFSET4_CH \| ADC_OFR4_OFFSET4);
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	/* Reset registers JDR1, JDR2, JDR3, JDR4 */
<>	144:ef7eb2e8f9f7	767	/* bits in access mode read only, no direct reset applicable*/
<>	144:ef7eb2e8f9f7	768
<>	144:ef7eb2e8f9f7	769	/* Reset register AWD2CR */
<>	144:ef7eb2e8f9f7	770	CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
<>	144:ef7eb2e8f9f7	771
<>	144:ef7eb2e8f9f7	772	/* Reset register AWD3CR */
<>	144:ef7eb2e8f9f7	773	CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
<>	144:ef7eb2e8f9f7	774
<>	144:ef7eb2e8f9f7	775	/* Reset register DIFSEL */
<>	144:ef7eb2e8f9f7	776	CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
<>	144:ef7eb2e8f9f7	777
<>	144:ef7eb2e8f9f7	778	/* Reset register CALFACT */
<>	144:ef7eb2e8f9f7	779	CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D \| ADC_CALFACT_CALFACT_S);
<>	144:ef7eb2e8f9f7	780
<>	144:ef7eb2e8f9f7	781
<>	144:ef7eb2e8f9f7	782	/* ========== Reset common ADC registers ========== */
<>	144:ef7eb2e8f9f7	783
<>	144:ef7eb2e8f9f7	784	/* Software is allowed to change common parameters only when all the other
<>	144:ef7eb2e8f9f7	785	ADCs are disabled. */
<>	144:ef7eb2e8f9f7	786	if ((ADC_IS_ENABLE(hadc) == RESET) &&
<>	144:ef7eb2e8f9f7	787	(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
<>	144:ef7eb2e8f9f7	788	{
<>	144:ef7eb2e8f9f7	789	/* Reset configuration of ADC common register CCR:
<>	144:ef7eb2e8f9f7	790	- clock mode: CKMODE, PRESCEN
<>	144:ef7eb2e8f9f7	791	- multimode related parameters (when this feature is available): MDMA,
<>	144:ef7eb2e8f9f7	792	DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
<>	144:ef7eb2e8f9f7	793	- internal measurement paths: Vbat, temperature sensor, Vref (set into
<>	144:ef7eb2e8f9f7	794	HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
<>	144:ef7eb2e8f9f7	795	*/
<>	144:ef7eb2e8f9f7	796	ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	797	}
<>	144:ef7eb2e8f9f7	798
<>	144:ef7eb2e8f9f7	799	/* DeInit the low level hardware.
<>	144:ef7eb2e8f9f7	800
<>	144:ef7eb2e8f9f7	801	For example:
<>	144:ef7eb2e8f9f7	802	__HAL_RCC_ADC_FORCE_RESET();
<>	144:ef7eb2e8f9f7	803	__HAL_RCC_ADC_RELEASE_RESET();
<>	144:ef7eb2e8f9f7	804	__HAL_RCC_ADC_CLK_DISABLE();
<>	144:ef7eb2e8f9f7	805
<>	144:ef7eb2e8f9f7	806	Keep in mind that all ADCs use the same clock: disabling
<>	144:ef7eb2e8f9f7	807	the clock will reset all ADCs.
<>	144:ef7eb2e8f9f7	808
AnnaBridge	167:e84263d55307	809	*/
<>	144:ef7eb2e8f9f7	810	HAL_ADC_MspDeInit(hadc);
<>	144:ef7eb2e8f9f7	811
<>	144:ef7eb2e8f9f7	812	/* Set ADC error code to none */
<>	144:ef7eb2e8f9f7	813	ADC_CLEAR_ERRORCODE(hadc);
AnnaBridge	167:e84263d55307	814
<>	144:ef7eb2e8f9f7	815	/* Reset injected channel configuration parameters */
<>	144:ef7eb2e8f9f7	816	hadc->InjectionConfig.ContextQueue = 0;
<>	144:ef7eb2e8f9f7	817	hadc->InjectionConfig.ChannelCount = 0;
<>	144:ef7eb2e8f9f7	818
AnnaBridge	167:e84263d55307	819	/* Set ADC state */
<>	144:ef7eb2e8f9f7	820	hadc->State = HAL_ADC_STATE_RESET;
<>	144:ef7eb2e8f9f7	821
<>	144:ef7eb2e8f9f7	822	/* Process unlocked */
<>	144:ef7eb2e8f9f7	823	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	824
<>	144:ef7eb2e8f9f7	825	/* Return function status */
<>	144:ef7eb2e8f9f7	826	return HAL_OK;
AnnaBridge	167:e84263d55307	827	}
<>	144:ef7eb2e8f9f7	828
<>	144:ef7eb2e8f9f7	829	/**
<>	144:ef7eb2e8f9f7	830	* @brief Initialize the ADC MSP.
<>	144:ef7eb2e8f9f7	831	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	832	* @retval None
<>	144:ef7eb2e8f9f7	833	*/
<>	144:ef7eb2e8f9f7	834	__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	835	{
<>	144:ef7eb2e8f9f7	836	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	837	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	838
<>	144:ef7eb2e8f9f7	839	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	840	function HAL_ADC_MspInit must be implemented in the user file.
<>	144:ef7eb2e8f9f7	841	*/
<>	144:ef7eb2e8f9f7	842	}
<>	144:ef7eb2e8f9f7	843
<>	144:ef7eb2e8f9f7	844	/**
<>	144:ef7eb2e8f9f7	845	* @brief DeInitialize the ADC MSP.
<>	144:ef7eb2e8f9f7	846	* @param hadc: ADC handle
AnnaBridge	167:e84263d55307	847	* @note All ADCs use the same clock: disabling the clock will reset all ADCs.
<>	144:ef7eb2e8f9f7	848	* @retval None
<>	144:ef7eb2e8f9f7	849	*/
<>	144:ef7eb2e8f9f7	850	__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	851	{
<>	144:ef7eb2e8f9f7	852	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	853	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	854
<>	144:ef7eb2e8f9f7	855	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	856	function HAL_ADC_MspDeInit must be implemented in the user file.
<>	144:ef7eb2e8f9f7	857	*/
<>	144:ef7eb2e8f9f7	858	}
<>	144:ef7eb2e8f9f7	859
<>	144:ef7eb2e8f9f7	860	/**
<>	144:ef7eb2e8f9f7	861	* @}
<>	144:ef7eb2e8f9f7	862	*/
<>	144:ef7eb2e8f9f7	863
AnnaBridge	167:e84263d55307	864	/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
AnnaBridge	167:e84263d55307	865	* @brief ADC IO operation functions
<>	144:ef7eb2e8f9f7	866	*
<>	144:ef7eb2e8f9f7	867	@verbatim
<>	144:ef7eb2e8f9f7	868	===============================================================================
AnnaBridge	167:e84263d55307	869	##### IO operation functions #####
AnnaBridge	167:e84263d55307	870	===============================================================================
<>	144:ef7eb2e8f9f7	871	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	872	(+) Start conversion of regular group.
<>	144:ef7eb2e8f9f7	873	(+) Stop conversion of regular group.
<>	144:ef7eb2e8f9f7	874	(+) Poll for conversion complete on regular group.
<>	144:ef7eb2e8f9f7	875	(+) Poll for conversion event.
<>	144:ef7eb2e8f9f7	876	(+) Get result of regular channel conversion.
<>	144:ef7eb2e8f9f7	877	(+) Start conversion of regular group and enable interruptions.
<>	144:ef7eb2e8f9f7	878	(+) Stop conversion of regular group and disable interruptions.
<>	144:ef7eb2e8f9f7	879	(+) Handle ADC interrupt request
<>	144:ef7eb2e8f9f7	880	(+) Start conversion of regular group and enable DMA transfer.
<>	144:ef7eb2e8f9f7	881	(+) Stop conversion of regular group and disable ADC DMA transfer.
<>	144:ef7eb2e8f9f7	882	@endverbatim
<>	144:ef7eb2e8f9f7	883	* @{
<>	144:ef7eb2e8f9f7	884	*/
AnnaBridge	167:e84263d55307	885
<>	144:ef7eb2e8f9f7	886	/**
<>	144:ef7eb2e8f9f7	887	* @brief Enable ADC, start conversion of regular group.
<>	144:ef7eb2e8f9f7	888	* @note Interruptions enabled in this function: None.
<>	144:ef7eb2e8f9f7	889	* @note Case of multimode enabled (when multimode feature is available):
<>	144:ef7eb2e8f9f7	890	* if ADC is Slave, ADC is enabled but conversion is not started,
<>	144:ef7eb2e8f9f7	891	* if ADC is master, ADC is enabled and multimode conversion is started.
<>	144:ef7eb2e8f9f7	892	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	893	* @retval HAL status
<>	144:ef7eb2e8f9f7	894	*/
<>	144:ef7eb2e8f9f7	895	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	896	{
AnnaBridge	167:e84263d55307	897	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
AnnaBridge	167:e84263d55307	898	ADC_TypeDef *tmpADC_Master;
<>	144:ef7eb2e8f9f7	899	/* Check the parameters */
<>	144:ef7eb2e8f9f7	900	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	901
AnnaBridge	167:e84263d55307	902	/* Perform ADC enable and conversion start if no conversion is on going */
AnnaBridge	167:e84263d55307	903	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	904	{
<>	144:ef7eb2e8f9f7	905	/* Process locked */
<>	144:ef7eb2e8f9f7	906	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	907
<>	144:ef7eb2e8f9f7	908	/* Enable the ADC peripheral */
AnnaBridge	167:e84263d55307	909	tmp_hal_status = ADC_Enable(hadc);
<>	144:ef7eb2e8f9f7	910
<>	144:ef7eb2e8f9f7	911	/* Start conversion if ADC is effectively enabled */
AnnaBridge	167:e84263d55307	912	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	913	{
<>	144:ef7eb2e8f9f7	914	/* State machine update: Check if an injected conversion is ongoing */
<>	144:ef7eb2e8f9f7	915	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	916	{
<>	144:ef7eb2e8f9f7	917	/* Reset ADC error code fields related to regular conversions only */
<>	144:ef7eb2e8f9f7	918	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR\|HAL_ADC_ERROR_DMA));
<>	144:ef7eb2e8f9f7	919	}
<>	144:ef7eb2e8f9f7	920	else
<>	144:ef7eb2e8f9f7	921	{
<>	144:ef7eb2e8f9f7	922	/* Set ADC error code to none */
<>	144:ef7eb2e8f9f7	923	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	924	}
<>	144:ef7eb2e8f9f7	925	/* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
<>	144:ef7eb2e8f9f7	926	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_REG_EOC\|HAL_ADC_STATE_REG_OVR\|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	927
<>	144:ef7eb2e8f9f7	928	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
<>	144:ef7eb2e8f9f7	929	- by default if ADC is Master or Independent or if multimode feature is not available
<>	144:ef7eb2e8f9f7	930	- if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
<>	144:ef7eb2e8f9f7	931	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<>	144:ef7eb2e8f9f7	932	{
<>	144:ef7eb2e8f9f7	933	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<>	144:ef7eb2e8f9f7	934	}
<>	144:ef7eb2e8f9f7	935
<>	144:ef7eb2e8f9f7	936	/* Clear regular group conversion flag and overrun flag */
<>	144:ef7eb2e8f9f7	937	/* (To ensure of no unknown state from potential previous ADC operations) */
<>	144:ef7eb2e8f9f7	938	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
AnnaBridge	167:e84263d55307	939
<>	144:ef7eb2e8f9f7	940	/* Enable conversion of regular group. */
<>	144:ef7eb2e8f9f7	941	/* If software start has been selected, conversion starts immediately. */
AnnaBridge	167:e84263d55307	942	/* If external trigger has been selected, conversion will start at next */
<>	144:ef7eb2e8f9f7	943	/* trigger event. */
AnnaBridge	167:e84263d55307	944	/* Case of multimode enabled (when multimode feature is available): */
<>	144:ef7eb2e8f9f7	945	/* - if ADC is slave and dual regular conversions are enabled, ADC is */
<>	144:ef7eb2e8f9f7	946	/* enabled only (conversion is not started), */
<>	144:ef7eb2e8f9f7	947	/* - if ADC is master, ADC is enabled and conversion is started. */
<>	144:ef7eb2e8f9f7	948	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
<>	144:ef7eb2e8f9f7	949	{
<>	144:ef7eb2e8f9f7	950	/* Multimode feature is not available or ADC Instance is Independent or Master,
<>	144:ef7eb2e8f9f7	951	or is not Slave ADC with dual regular conversions enabled.
<>	144:ef7eb2e8f9f7	952	Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */
<>	144:ef7eb2e8f9f7	953	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
<>	144:ef7eb2e8f9f7	954	{
<>	144:ef7eb2e8f9f7	955	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<>	144:ef7eb2e8f9f7	956	}
<>	144:ef7eb2e8f9f7	957	/* Process unlocked */
<>	144:ef7eb2e8f9f7	958	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	959	/* Start ADC */
<>	144:ef7eb2e8f9f7	960	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
<>	144:ef7eb2e8f9f7	961	}
<>	144:ef7eb2e8f9f7	962	else
<>	144:ef7eb2e8f9f7	963	{
<>	144:ef7eb2e8f9f7	964	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<>	144:ef7eb2e8f9f7	965	/* if Master ADC JAUTO bit is set, update Slave State in setting
<>	144:ef7eb2e8f9f7	966	HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
<>	144:ef7eb2e8f9f7	967	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	968	if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
<>	144:ef7eb2e8f9f7	969	{
<>	144:ef7eb2e8f9f7	970	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<>	144:ef7eb2e8f9f7	971
<>	144:ef7eb2e8f9f7	972	} /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
<>	144:ef7eb2e8f9f7	973	/* Process unlocked */
<>	144:ef7eb2e8f9f7	974	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	975	} /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) */
<>	144:ef7eb2e8f9f7	976	}
<>	144:ef7eb2e8f9f7	977	else
<>	144:ef7eb2e8f9f7	978	{
<>	144:ef7eb2e8f9f7	979	/* Process unlocked */
AnnaBridge	167:e84263d55307	980	__HAL_UNLOCK(hadc);
AnnaBridge	167:e84263d55307	981	}
AnnaBridge	167:e84263d55307	982	}
AnnaBridge	167:e84263d55307	983	else
AnnaBridge	167:e84263d55307	984	{
AnnaBridge	167:e84263d55307	985	tmp_hal_status = HAL_BUSY;
AnnaBridge	167:e84263d55307	986	}
<>	144:ef7eb2e8f9f7	987
<>	144:ef7eb2e8f9f7	988	/* Return function status */
AnnaBridge	167:e84263d55307	989	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	990	}
<>	144:ef7eb2e8f9f7	991
AnnaBridge	167:e84263d55307	992	/**
AnnaBridge	167:e84263d55307	993	* @brief Stop ADC conversion of regular group (and injected channels in
AnnaBridge	167:e84263d55307	994	* case of auto_injection mode), disable ADC peripheral.
AnnaBridge	167:e84263d55307	995	* @note: ADC peripheral disable is forcing stop of potential
AnnaBridge	167:e84263d55307	996	* conversion on injected group. If injected group is under use, it
AnnaBridge	167:e84263d55307	997	* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
<>	144:ef7eb2e8f9f7	998	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	999	* @retval HAL status.
<>	144:ef7eb2e8f9f7	1000	*/
<>	144:ef7eb2e8f9f7	1001	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
AnnaBridge	167:e84263d55307	1002	{
AnnaBridge	167:e84263d55307	1003	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	1004
<>	144:ef7eb2e8f9f7	1005	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1006	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1007
<>	144:ef7eb2e8f9f7	1008	/* Process locked */
<>	144:ef7eb2e8f9f7	1009	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	1010
AnnaBridge	167:e84263d55307	1011	/* 1. Stop potential conversion on going, on ADC groups regular and injected */
AnnaBridge	167:e84263d55307	1012	tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<>	144:ef7eb2e8f9f7	1013
<>	144:ef7eb2e8f9f7	1014	/* Disable ADC peripheral if conversions are effectively stopped */
AnnaBridge	167:e84263d55307	1015	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1016	{
<>	144:ef7eb2e8f9f7	1017	/* 2. Disable the ADC peripheral */
AnnaBridge	167:e84263d55307	1018	tmp_hal_status = ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	1019
<>	144:ef7eb2e8f9f7	1020	/* Check if ADC is effectively disabled */
AnnaBridge	167:e84263d55307	1021	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1022	{
AnnaBridge	167:e84263d55307	1023	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1024	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
<>	144:ef7eb2e8f9f7	1025	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1026	}
<>	144:ef7eb2e8f9f7	1027	}
AnnaBridge	167:e84263d55307	1028
<>	144:ef7eb2e8f9f7	1029	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1030	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	/* Return function status */
AnnaBridge	167:e84263d55307	1033	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	1034	}
<>	144:ef7eb2e8f9f7	1035
<>	144:ef7eb2e8f9f7	1036	/**
<>	144:ef7eb2e8f9f7	1037	* @brief Wait for regular group conversion to be completed.
<>	144:ef7eb2e8f9f7	1038	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1039	* @param Timeout: Timeout value in millisecond.
<>	144:ef7eb2e8f9f7	1040	* @note Depending on hadc->Init.EOCSelection, EOS or EOC is
<>	144:ef7eb2e8f9f7	1041	* checked and cleared depending on AUTDLY bit status.
<>	144:ef7eb2e8f9f7	1042	* @note HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a
<>	144:ef7eb2e8f9f7	1043	* DMA-managed conversions configuration: indeed, EOC is immediately
<>	144:ef7eb2e8f9f7	1044	* reset by the DMA reading the DR register when the converted data is
<>	144:ef7eb2e8f9f7	1045	* available. Therefore, EOC is set for a too short period to be
AnnaBridge	167:e84263d55307	1046	* reliably polled.
<>	144:ef7eb2e8f9f7	1047	* @retval HAL status
<>	144:ef7eb2e8f9f7	1048	*/
<>	144:ef7eb2e8f9f7	1049	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1050	{
AnnaBridge	167:e84263d55307	1051	uint32_t tickstart = 0;
AnnaBridge	167:e84263d55307	1052	uint32_t tmp_Flag_EOC = 0x00;
AnnaBridge	167:e84263d55307	1053	uint32_t tmp_cfgr = 0x00;
AnnaBridge	167:e84263d55307	1054	uint32_t tmp_eos_raised = 0x01; /* by default, assume that EOS is set,
AnnaBridge	167:e84263d55307	1055	tmp_eos_raised will be corrected
AnnaBridge	167:e84263d55307	1056	accordingly during API execution */
AnnaBridge	167:e84263d55307	1057	ADC_TypeDef *tmpADC_Master;
AnnaBridge	167:e84263d55307	1058
<>	144:ef7eb2e8f9f7	1059	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1060	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
AnnaBridge	167:e84263d55307	1061
AnnaBridge	167:e84263d55307	1062	/* If end of conversion selected to end of sequence conversions */
<>	144:ef7eb2e8f9f7	1063	if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
<>	144:ef7eb2e8f9f7	1064	{
AnnaBridge	167:e84263d55307	1065	tmp_Flag_EOC = ADC_FLAG_EOS;
<>	144:ef7eb2e8f9f7	1066	}
AnnaBridge	167:e84263d55307	1067	/* If end of conversion selected to end of unitary conversion */
AnnaBridge	167:e84263d55307	1068	else /* ADC_EOC_SINGLE_CONV */
<>	144:ef7eb2e8f9f7	1069	{
<>	144:ef7eb2e8f9f7	1070	/* Check that the ADC is not in a DMA-based configuration. Otherwise,
AnnaBridge	167:e84263d55307	1071	returns an error. */
<>	144:ef7eb2e8f9f7	1072
<>	144:ef7eb2e8f9f7	1073	/* Check whether dual regular conversions are disabled or unavailable. */
<>	144:ef7eb2e8f9f7	1074	if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1075	{
<>	144:ef7eb2e8f9f7	1076	/* Check DMAEN bit in handle ADC CFGR register */
<>	144:ef7eb2e8f9f7	1077	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET)
<>	144:ef7eb2e8f9f7	1078	{
<>	144:ef7eb2e8f9f7	1079	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	1080	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1081	}
<>	144:ef7eb2e8f9f7	1082	}
<>	144:ef7eb2e8f9f7	1083	else
<>	144:ef7eb2e8f9f7	1084	{
<>	144:ef7eb2e8f9f7	1085	/* Else need to check Common register CCR MDMA bit field. */
<>	144:ef7eb2e8f9f7	1086	if (ADC_MULTIMODE_DMA_ENABLED())
<>	144:ef7eb2e8f9f7	1087	{
AnnaBridge	167:e84263d55307	1088	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
AnnaBridge	167:e84263d55307	1089	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1090	}
AnnaBridge	167:e84263d55307	1091	}
<>	144:ef7eb2e8f9f7	1092
AnnaBridge	167:e84263d55307	1093	/* no DMA transfer detected, polling ADC_FLAG_EOC is possible */
AnnaBridge	167:e84263d55307	1094	tmp_Flag_EOC = ADC_FLAG_EOC;
<>	144:ef7eb2e8f9f7	1095	}
AnnaBridge	167:e84263d55307	1096
AnnaBridge	167:e84263d55307	1097	/* Get tick count */
AnnaBridge	167:e84263d55307	1098	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	1099
AnnaBridge	167:e84263d55307	1100	/* Wait until End of unitary conversion or sequence conversions flag is raised */
AnnaBridge	167:e84263d55307	1101	while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
<>	144:ef7eb2e8f9f7	1102	{
<>	144:ef7eb2e8f9f7	1103	/* Check if timeout is disabled (set to infinite wait) */
<>	144:ef7eb2e8f9f7	1104	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	1105	{
<>	144:ef7eb2e8f9f7	1106	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
AnnaBridge	167:e84263d55307	1107	{
AnnaBridge	167:e84263d55307	1108	/* Update ADC state machine to timeout */
AnnaBridge	167:e84263d55307	1109	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
AnnaBridge	167:e84263d55307	1110
AnnaBridge	167:e84263d55307	1111	/* Process unlocked */
AnnaBridge	167:e84263d55307	1112	__HAL_UNLOCK(hadc);
AnnaBridge	167:e84263d55307	1113
<>	144:ef7eb2e8f9f7	1114	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1115	}
<>	144:ef7eb2e8f9f7	1116	}
<>	144:ef7eb2e8f9f7	1117	}
<>	144:ef7eb2e8f9f7	1118
<>	144:ef7eb2e8f9f7	1119	/* Next, to clear the polled flag as well as to update the handle State,
<>	144:ef7eb2e8f9f7	1120	EOS is checked and the relevant configuration register is retrieved. */
<>	144:ef7eb2e8f9f7	1121	/* 1. Check whether or not EOS is set */
<>	144:ef7eb2e8f9f7	1122	if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_EOS))
<>	144:ef7eb2e8f9f7	1123	{
AnnaBridge	167:e84263d55307	1124	tmp_eos_raised = 0;
<>	144:ef7eb2e8f9f7	1125	}
<>	144:ef7eb2e8f9f7	1126	/* 2. Check whether or not hadc is the handle of a Slave ADC with dual
<>	144:ef7eb2e8f9f7	1127	regular conversions enabled. */
<>	144:ef7eb2e8f9f7	1128	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
<>	144:ef7eb2e8f9f7	1129	{
<>	144:ef7eb2e8f9f7	1130	/* Retrieve handle ADC CFGR register */
<>	144:ef7eb2e8f9f7	1131	tmp_cfgr = READ_REG(hadc->Instance->CFGR);
<>	144:ef7eb2e8f9f7	1132	}
<>	144:ef7eb2e8f9f7	1133	else
<>	144:ef7eb2e8f9f7	1134	{
<>	144:ef7eb2e8f9f7	1135	/* Retrieve Master ADC CFGR register */
<>	144:ef7eb2e8f9f7	1136	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	1137	tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
AnnaBridge	167:e84263d55307	1138	}
<>	144:ef7eb2e8f9f7	1139
AnnaBridge	167:e84263d55307	1140	/* Clear polled flag */
AnnaBridge	167:e84263d55307	1141	if (tmp_Flag_EOC == ADC_FLAG_EOS)
<>	144:ef7eb2e8f9f7	1142	{
<>	144:ef7eb2e8f9f7	1143	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
<>	144:ef7eb2e8f9f7	1144	}
<>	144:ef7eb2e8f9f7	1145	else
AnnaBridge	167:e84263d55307	1146	{
<>	144:ef7eb2e8f9f7	1147
<>	144:ef7eb2e8f9f7	1148	/* Clear end of conversion EOC flag of regular group if low power feature */
<>	144:ef7eb2e8f9f7	1149	/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
<>	144:ef7eb2e8f9f7	1150	/* until data register is read using function HAL_ADC_GetValue(). */
<>	144:ef7eb2e8f9f7	1151	/* For regular groups, no new conversion will start before EOC is cleared.*/
<>	144:ef7eb2e8f9f7	1152	/* Note that 1. reading DR clears EOC. */
<>	144:ef7eb2e8f9f7	1153	/* 2. in multimode with dual regular conversions enabled (when */
<>	144:ef7eb2e8f9f7	1154	/* multimode feature is available), Master AUTDLY bit is */
<>	144:ef7eb2e8f9f7	1155	/* checked. */
<>	144:ef7eb2e8f9f7	1156	if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
<>	144:ef7eb2e8f9f7	1157	{
<>	144:ef7eb2e8f9f7	1158	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
<>	144:ef7eb2e8f9f7	1159	}
<>	144:ef7eb2e8f9f7	1160	}
<>	144:ef7eb2e8f9f7	1161
<>	144:ef7eb2e8f9f7	1162	/* Update ADC state machine */
<>	144:ef7eb2e8f9f7	1163	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<>	144:ef7eb2e8f9f7	1164	/* If 1. EOS is set
<>	144:ef7eb2e8f9f7	1165	2. conversions are software-triggered
<>	144:ef7eb2e8f9f7	1166	3. CONT bit is reset (that of handle ADC or Master ADC if applicable)
<>	144:ef7eb2e8f9f7	1167	Then regular conversions are over and HAL_ADC_STATE_REG_BUSY can be reset.
<>	144:ef7eb2e8f9f7	1168	4. additionally, if no injected conversions are on-going, HAL_ADC_STATE_READY
<>	144:ef7eb2e8f9f7	1169	can be set */
<>	144:ef7eb2e8f9f7	1170	if ((tmp_eos_raised)
<>	144:ef7eb2e8f9f7	1171	&& (ADC_IS_SOFTWARE_START_REGULAR(hadc))
<>	144:ef7eb2e8f9f7	1172	&& (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET))
<>	144:ef7eb2e8f9f7	1173	{
<>	144:ef7eb2e8f9f7	1174	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	1175	/* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
<>	144:ef7eb2e8f9f7	1176	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	1177	{
<>	144:ef7eb2e8f9f7	1178	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1179	}
AnnaBridge	167:e84263d55307	1180	}
<>	144:ef7eb2e8f9f7	1181
AnnaBridge	167:e84263d55307	1182	/* Return function status */
<>	144:ef7eb2e8f9f7	1183	return HAL_OK;
<>	144:ef7eb2e8f9f7	1184	}
<>	144:ef7eb2e8f9f7	1185
<>	144:ef7eb2e8f9f7	1186	/**
<>	144:ef7eb2e8f9f7	1187	* @brief Poll for ADC event.
<>	144:ef7eb2e8f9f7	1188	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1189	* @param EventType: the ADC event type.
<>	144:ef7eb2e8f9f7	1190	* This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1191	* @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
AnnaBridge	167:e84263d55307	1192	* @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
AnnaBridge	167:e84263d55307	1193	* @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
AnnaBridge	167:e84263d55307	1194	* @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
<>	144:ef7eb2e8f9f7	1195	* @arg @ref ADC_OVR_EVENT ADC Overrun event
<>	144:ef7eb2e8f9f7	1196	* @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
<>	144:ef7eb2e8f9f7	1197	* @param Timeout: Timeout value in millisecond.
<>	144:ef7eb2e8f9f7	1198	* @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
<>	144:ef7eb2e8f9f7	1199	* Indeed, the latter is reset only if hadc->Init.Overrun field is set
AnnaBridge	167:e84263d55307	1200	* to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
<>	144:ef7eb2e8f9f7	1201	* by a new converted data as soon as OVR is cleared.
<>	144:ef7eb2e8f9f7	1202	* To reset OVR flag once the preserved data is retrieved, the user can resort
<>	144:ef7eb2e8f9f7	1203	* to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<>	144:ef7eb2e8f9f7	1204	* @retval HAL status
<>	144:ef7eb2e8f9f7	1205	*/
<>	144:ef7eb2e8f9f7	1206	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1207	{
AnnaBridge	167:e84263d55307	1208	uint32_t tickstart = 0;
AnnaBridge	167:e84263d55307	1209
<>	144:ef7eb2e8f9f7	1210	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1211	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1212	assert_param(IS_ADC_EVENT_TYPE(EventType));
<>	144:ef7eb2e8f9f7	1213
AnnaBridge	167:e84263d55307	1214	/* Get tick count */
<>	144:ef7eb2e8f9f7	1215	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	1216
<>	144:ef7eb2e8f9f7	1217	/* Check selected event flag */
<>	144:ef7eb2e8f9f7	1218	while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
<>	144:ef7eb2e8f9f7	1219	{
<>	144:ef7eb2e8f9f7	1220	/* Check if timeout is disabled (set to infinite wait) */
<>	144:ef7eb2e8f9f7	1221	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	1222	{
<>	144:ef7eb2e8f9f7	1223	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	1224	{
<>	144:ef7eb2e8f9f7	1225	/* Update ADC state machine to timeout */
<>	144:ef7eb2e8f9f7	1226	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<>	144:ef7eb2e8f9f7	1227
<>	144:ef7eb2e8f9f7	1228	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1229	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1230
<>	144:ef7eb2e8f9f7	1231	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1232	}
<>	144:ef7eb2e8f9f7	1233	}
<>	144:ef7eb2e8f9f7	1234	}
<>	144:ef7eb2e8f9f7	1235
<>	144:ef7eb2e8f9f7	1236	switch(EventType)
<>	144:ef7eb2e8f9f7	1237	{
<>	144:ef7eb2e8f9f7	1238	/* End Of Sampling event */
<>	144:ef7eb2e8f9f7	1239	case ADC_EOSMP_EVENT:
AnnaBridge	167:e84263d55307	1240	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1241	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
<>	144:ef7eb2e8f9f7	1242
<>	144:ef7eb2e8f9f7	1243	/* Clear the End Of Sampling flag */
<>	144:ef7eb2e8f9f7	1244	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
<>	144:ef7eb2e8f9f7	1245
<>	144:ef7eb2e8f9f7	1246	break;
<>	144:ef7eb2e8f9f7	1247
<>	144:ef7eb2e8f9f7	1248	/* Analog watchdog (level out of window) event */
<>	144:ef7eb2e8f9f7	1249	/* Note: In case of several analog watchdog enabled, if needed to know */
<>	144:ef7eb2e8f9f7	1250	/* which one triggered and on which ADCx, test ADC state of Analog Watchdog */
<>	144:ef7eb2e8f9f7	1251	/* flags HAL_ADC_STATE_AWD/2/3 function. */
<>	144:ef7eb2e8f9f7	1252	/* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) " */
<>	144:ef7eb2e8f9f7	1253	/* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)" */
<>	144:ef7eb2e8f9f7	1254	/* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)" */
<>	144:ef7eb2e8f9f7	1255	case ADC_AWD_EVENT:
AnnaBridge	167:e84263d55307	1256	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1257	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
AnnaBridge	167:e84263d55307	1258
<>	144:ef7eb2e8f9f7	1259	/* Clear ADC analog watchdog flag */
<>	144:ef7eb2e8f9f7	1260	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
AnnaBridge	167:e84263d55307	1261
<>	144:ef7eb2e8f9f7	1262	break;
<>	144:ef7eb2e8f9f7	1263
<>	144:ef7eb2e8f9f7	1264	/* Check analog watchdog 2 flag */
<>	144:ef7eb2e8f9f7	1265	case ADC_AWD2_EVENT:
AnnaBridge	167:e84263d55307	1266	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1267	SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
<>	144:ef7eb2e8f9f7	1268
<>	144:ef7eb2e8f9f7	1269	/* Clear ADC analog watchdog flag */
<>	144:ef7eb2e8f9f7	1270	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
AnnaBridge	167:e84263d55307	1271
<>	144:ef7eb2e8f9f7	1272	break;
<>	144:ef7eb2e8f9f7	1273
<>	144:ef7eb2e8f9f7	1274	/* Check analog watchdog 3 flag */
<>	144:ef7eb2e8f9f7	1275	case ADC_AWD3_EVENT:
AnnaBridge	167:e84263d55307	1276	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1277	SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
<>	144:ef7eb2e8f9f7	1278
<>	144:ef7eb2e8f9f7	1279	/* Clear ADC analog watchdog flag */
<>	144:ef7eb2e8f9f7	1280	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
AnnaBridge	167:e84263d55307	1281
<>	144:ef7eb2e8f9f7	1282	break;
<>	144:ef7eb2e8f9f7	1283
<>	144:ef7eb2e8f9f7	1284	/* Injected context queue overflow event */
<>	144:ef7eb2e8f9f7	1285	case ADC_JQOVF_EVENT:
AnnaBridge	167:e84263d55307	1286	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1287	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
AnnaBridge	167:e84263d55307	1288
<>	144:ef7eb2e8f9f7	1289	/* Set ADC error code to Injected context queue overflow */
<>	144:ef7eb2e8f9f7	1290	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
<>	144:ef7eb2e8f9f7	1291
<>	144:ef7eb2e8f9f7	1292	/* Clear ADC Injected context queue overflow flag */
<>	144:ef7eb2e8f9f7	1293	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
<>	144:ef7eb2e8f9f7	1294
<>	144:ef7eb2e8f9f7	1295	break;
AnnaBridge	167:e84263d55307	1296
<>	144:ef7eb2e8f9f7	1297	/* Overrun event */
<>	144:ef7eb2e8f9f7	1298	default: /* Case ADC_OVR_EVENT */
<>	144:ef7eb2e8f9f7	1299	/* If overrun is set to overwrite previous data, overrun event is not */
<>	144:ef7eb2e8f9f7	1300	/* considered as an error. */
<>	144:ef7eb2e8f9f7	1301	/* (cf ref manual "Managing conversions without using the DMA and without */
<>	144:ef7eb2e8f9f7	1302	/* overrun ") */
<>	144:ef7eb2e8f9f7	1303	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
<>	144:ef7eb2e8f9f7	1304	{
AnnaBridge	167:e84263d55307	1305	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1306	SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
<>	144:ef7eb2e8f9f7	1307
<>	144:ef7eb2e8f9f7	1308	/* Set ADC error code to overrun */
<>	144:ef7eb2e8f9f7	1309	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<>	144:ef7eb2e8f9f7	1310	}
<>	144:ef7eb2e8f9f7	1311	else
<>	144:ef7eb2e8f9f7	1312	{
<>	144:ef7eb2e8f9f7	1313	/* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
AnnaBridge	167:e84263d55307	1314	otherwise, data register is potentially overwritten by new converted data as soon
<>	144:ef7eb2e8f9f7	1315	as OVR is cleared. */
<>	144:ef7eb2e8f9f7	1316	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<>	144:ef7eb2e8f9f7	1317	}
<>	144:ef7eb2e8f9f7	1318	break;
<>	144:ef7eb2e8f9f7	1319	}
<>	144:ef7eb2e8f9f7	1320
AnnaBridge	167:e84263d55307	1321	/* Return function status */
<>	144:ef7eb2e8f9f7	1322	return HAL_OK;
<>	144:ef7eb2e8f9f7	1323	}
<>	144:ef7eb2e8f9f7	1324
<>	144:ef7eb2e8f9f7	1325	/**
<>	144:ef7eb2e8f9f7	1326	* @brief Enable ADC, start conversion of regular group with interruption.
<>	144:ef7eb2e8f9f7	1327	* @note Interruptions enabled in this function according to initialization
<>	144:ef7eb2e8f9f7	1328	* setting : EOC (end of conversion), EOS (end of sequence),
<>	144:ef7eb2e8f9f7	1329	* OVR overrun.
<>	144:ef7eb2e8f9f7	1330	* Each of these interruptions has its dedicated callback function.
<>	144:ef7eb2e8f9f7	1331	* @note Case of multimode enabled (when multimode feature is available):
<>	144:ef7eb2e8f9f7	1332	* HAL_ADC_Start_IT() must be called for ADC Slave first, then for
AnnaBridge	167:e84263d55307	1333	* ADC Master.
<>	144:ef7eb2e8f9f7	1334	* For ADC Slave, ADC is enabled only (conversion is not started).
<>	144:ef7eb2e8f9f7	1335	* For ADC Master, ADC is enabled and multimode conversion is started.
<>	144:ef7eb2e8f9f7	1336	* @note To guarantee a proper reset of all interruptions once all the needed
<>	144:ef7eb2e8f9f7	1337	* conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
AnnaBridge	167:e84263d55307	1338	* a correct stop of the IT-based conversions.
<>	144:ef7eb2e8f9f7	1339	* @note By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling
<>	144:ef7eb2e8f9f7	1340	* interruption. If required (e.g. in case of oversampling with trigger
AnnaBridge	167:e84263d55307	1341	* mode), the user must:
<>	144:ef7eb2e8f9f7	1342	* 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
<>	144:ef7eb2e8f9f7	1343	* 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
AnnaBridge	167:e84263d55307	1344	* before calling HAL_ADC_Start_IT().
<>	144:ef7eb2e8f9f7	1345	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1346	* @retval HAL status
<>	144:ef7eb2e8f9f7	1347	*/
<>	144:ef7eb2e8f9f7	1348	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1349	{
AnnaBridge	167:e84263d55307	1350	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
AnnaBridge	167:e84263d55307	1351	ADC_TypeDef *tmpADC_Master;
<>	144:ef7eb2e8f9f7	1352
<>	144:ef7eb2e8f9f7	1353	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1354	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1355
AnnaBridge	167:e84263d55307	1356	/* Perform ADC enable and conversion start if no conversion is on going */
AnnaBridge	167:e84263d55307	1357	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1358	{
<>	144:ef7eb2e8f9f7	1359	/* Process locked */
<>	144:ef7eb2e8f9f7	1360	__HAL_LOCK(hadc);
AnnaBridge	167:e84263d55307	1361
<>	144:ef7eb2e8f9f7	1362	/* Enable the ADC peripheral */
AnnaBridge	167:e84263d55307	1363	tmp_hal_status = ADC_Enable(hadc);
<>	144:ef7eb2e8f9f7	1364
<>	144:ef7eb2e8f9f7	1365	/* Start conversion if ADC is effectively enabled */
AnnaBridge	167:e84263d55307	1366	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1367	{
<>	144:ef7eb2e8f9f7	1368	/* State machine update: Check if an injected conversion is ongoing */
<>	144:ef7eb2e8f9f7	1369	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	1370	{
<>	144:ef7eb2e8f9f7	1371	/* Reset ADC error code fields related to regular conversions only */
<>	144:ef7eb2e8f9f7	1372	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR\|HAL_ADC_ERROR_DMA));
<>	144:ef7eb2e8f9f7	1373	}
<>	144:ef7eb2e8f9f7	1374	else
<>	144:ef7eb2e8f9f7	1375	{
<>	144:ef7eb2e8f9f7	1376	/* Set ADC error code to none */
<>	144:ef7eb2e8f9f7	1377	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	1378	}
<>	144:ef7eb2e8f9f7	1379	/* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
<>	144:ef7eb2e8f9f7	1380	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_REG_EOC\|HAL_ADC_STATE_REG_OVR\|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	1381
<>	144:ef7eb2e8f9f7	1382	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
<>	144:ef7eb2e8f9f7	1383	- by default if ADC is Master or Independent or if multimode feature is not available
<>	144:ef7eb2e8f9f7	1384	- if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
<>	144:ef7eb2e8f9f7	1385	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<>	144:ef7eb2e8f9f7	1386	{
<>	144:ef7eb2e8f9f7	1387	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
AnnaBridge	167:e84263d55307	1388	}
AnnaBridge	167:e84263d55307	1389
<>	144:ef7eb2e8f9f7	1390	/* Clear regular group conversion flag and overrun flag */
<>	144:ef7eb2e8f9f7	1391	/* (To ensure of no unknown state from potential previous ADC operations) */
<>	144:ef7eb2e8f9f7	1392	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
<>	144:ef7eb2e8f9f7	1393
<>	144:ef7eb2e8f9f7	1394	/* By default, disable all interruptions before enabling the desired ones */
<>	144:ef7eb2e8f9f7	1395	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_EOS \| ADC_IT_OVR));
AnnaBridge	167:e84263d55307	1396
AnnaBridge	167:e84263d55307	1397	/* Enable required interruptions */
<>	144:ef7eb2e8f9f7	1398	switch(hadc->Init.EOCSelection)
<>	144:ef7eb2e8f9f7	1399	{
<>	144:ef7eb2e8f9f7	1400	case ADC_EOC_SEQ_CONV:
<>	144:ef7eb2e8f9f7	1401	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
<>	144:ef7eb2e8f9f7	1402	break;
<>	144:ef7eb2e8f9f7	1403	/* case ADC_EOC_SINGLE_CONV */
<>	144:ef7eb2e8f9f7	1404	default:
<>	144:ef7eb2e8f9f7	1405	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
<>	144:ef7eb2e8f9f7	1406	break;
<>	144:ef7eb2e8f9f7	1407	}
<>	144:ef7eb2e8f9f7	1408
<>	144:ef7eb2e8f9f7	1409	/* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
<>	144:ef7eb2e8f9f7	1410	ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
<>	144:ef7eb2e8f9f7	1411	behavior and no CPU time is lost for a non-processed interruption */
<>	144:ef7eb2e8f9f7	1412	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
<>	144:ef7eb2e8f9f7	1413	{
<>	144:ef7eb2e8f9f7	1414	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
<>	144:ef7eb2e8f9f7	1415	}
<>	144:ef7eb2e8f9f7	1416
<>	144:ef7eb2e8f9f7	1417	/* Enable conversion of regular group. */
<>	144:ef7eb2e8f9f7	1418	/* If software start has been selected, conversion starts immediately. */
<>	144:ef7eb2e8f9f7	1419	/* If external trigger has been selected, conversion starts at next */
<>	144:ef7eb2e8f9f7	1420	/* trigger event. */
<>	144:ef7eb2e8f9f7	1421	/* Case of multimode enabled (when multimode feature is available): */
<>	144:ef7eb2e8f9f7	1422	/* - if ADC is slave and dual regular conversions are enabled, ADC is */
<>	144:ef7eb2e8f9f7	1423	/* enabled only (conversion is not started), */
<>	144:ef7eb2e8f9f7	1424	/* - if ADC is master, ADC is enabled and conversion is started. */
<>	144:ef7eb2e8f9f7	1425	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) )
<>	144:ef7eb2e8f9f7	1426	{
<>	144:ef7eb2e8f9f7	1427	/* Multimode feature is not available or ADC Instance is Independent or Master,
<>	144:ef7eb2e8f9f7	1428	or is not Slave ADC with dual regular conversions enabled.
<>	144:ef7eb2e8f9f7	1429	Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */
<>	144:ef7eb2e8f9f7	1430	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
<>	144:ef7eb2e8f9f7	1431	{
<>	144:ef7eb2e8f9f7	1432	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<>	144:ef7eb2e8f9f7	1433
<>	144:ef7eb2e8f9f7	1434	/* Enable as well injected interruptions in case
<>	144:ef7eb2e8f9f7	1435	HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
<>	144:ef7eb2e8f9f7	1436	allows to start regular and injected conversions when JAUTO is
<>	144:ef7eb2e8f9f7	1437	set with a single call to HAL_ADC_Start_IT() */
<>	144:ef7eb2e8f9f7	1438	switch(hadc->Init.EOCSelection)
<>	144:ef7eb2e8f9f7	1439	{
<>	144:ef7eb2e8f9f7	1440	case ADC_EOC_SEQ_CONV:
<>	144:ef7eb2e8f9f7	1441	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
<>	144:ef7eb2e8f9f7	1442	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
<>	144:ef7eb2e8f9f7	1443	break;
<>	144:ef7eb2e8f9f7	1444	/* case ADC_EOC_SINGLE_CONV */
<>	144:ef7eb2e8f9f7	1445	default:
<>	144:ef7eb2e8f9f7	1446	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
<>	144:ef7eb2e8f9f7	1447	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
<>	144:ef7eb2e8f9f7	1448	break;
<>	144:ef7eb2e8f9f7	1449	}
<>	144:ef7eb2e8f9f7	1450	} /* if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) */
<>	144:ef7eb2e8f9f7	1451	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1452	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1453	/* Start ADC */
<>	144:ef7eb2e8f9f7	1454	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
<>	144:ef7eb2e8f9f7	1455	}
<>	144:ef7eb2e8f9f7	1456	else
<>	144:ef7eb2e8f9f7	1457	{
<>	144:ef7eb2e8f9f7	1458	/* hadc is the handle of a Slave ADC with dual regular conversions
<>	144:ef7eb2e8f9f7	1459	enabled. Therefore, ADC_CR_ADSTART is NOT set */
<>	144:ef7eb2e8f9f7	1460	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<>	144:ef7eb2e8f9f7	1461	/* if Master ADC JAUTO bit is set, Slave injected interruptions
<>	144:ef7eb2e8f9f7	1462	are enabled nevertheless (for same reason as above) */
<>	144:ef7eb2e8f9f7	1463	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	1464	if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
<>	144:ef7eb2e8f9f7	1465	{
<>	144:ef7eb2e8f9f7	1466	/* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
<>	144:ef7eb2e8f9f7	1467	and in resetting HAL_ADC_STATE_INJ_EOC bit */
<>	144:ef7eb2e8f9f7	1468	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<>	144:ef7eb2e8f9f7	1469	/* Next, set Slave injected interruptions */
<>	144:ef7eb2e8f9f7	1470	switch(hadc->Init.EOCSelection)
<>	144:ef7eb2e8f9f7	1471	{
<>	144:ef7eb2e8f9f7	1472	case ADC_EOC_SEQ_CONV:
<>	144:ef7eb2e8f9f7	1473	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
<>	144:ef7eb2e8f9f7	1474	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
<>	144:ef7eb2e8f9f7	1475	break;
<>	144:ef7eb2e8f9f7	1476	/* case ADC_EOC_SINGLE_CONV */
<>	144:ef7eb2e8f9f7	1477	default:
<>	144:ef7eb2e8f9f7	1478	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
<>	144:ef7eb2e8f9f7	1479	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
<>	144:ef7eb2e8f9f7	1480	break;
<>	144:ef7eb2e8f9f7	1481	}
<>	144:ef7eb2e8f9f7	1482	} /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
<>	144:ef7eb2e8f9f7	1483	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1484	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1485	} /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) ) */
AnnaBridge	167:e84263d55307	1486	} /* if (tmp_hal_status == HAL_OK) */
<>	144:ef7eb2e8f9f7	1487	else
<>	144:ef7eb2e8f9f7	1488	{
<>	144:ef7eb2e8f9f7	1489	/* Process unlocked */
AnnaBridge	167:e84263d55307	1490	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1491	}
AnnaBridge	167:e84263d55307	1492
AnnaBridge	167:e84263d55307	1493	}
AnnaBridge	167:e84263d55307	1494	else
AnnaBridge	167:e84263d55307	1495	{
AnnaBridge	167:e84263d55307	1496	tmp_hal_status = HAL_BUSY;
AnnaBridge	167:e84263d55307	1497	}
AnnaBridge	167:e84263d55307	1498
AnnaBridge	167:e84263d55307	1499	/* Return function status */
AnnaBridge	167:e84263d55307	1500	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	1501	}
<>	144:ef7eb2e8f9f7	1502
AnnaBridge	167:e84263d55307	1503	/**
AnnaBridge	167:e84263d55307	1504	* @brief Stop ADC conversion of regular group (and injected group in
AnnaBridge	167:e84263d55307	1505	* case of auto_injection mode), disable interrution of
AnnaBridge	167:e84263d55307	1506	* end-of-conversion, disable ADC peripheral.
<>	144:ef7eb2e8f9f7	1507	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1508	* @retval HAL status.
AnnaBridge	167:e84263d55307	1509	*/
<>	144:ef7eb2e8f9f7	1510	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1511	{
AnnaBridge	167:e84263d55307	1512	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	1513
<>	144:ef7eb2e8f9f7	1514	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1515	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1516
<>	144:ef7eb2e8f9f7	1517	/* Process locked */
<>	144:ef7eb2e8f9f7	1518	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	1519
AnnaBridge	167:e84263d55307	1520	/* 1. Stop potential conversion on going, on ADC groups regular and injected */
AnnaBridge	167:e84263d55307	1521	tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<>	144:ef7eb2e8f9f7	1522
<>	144:ef7eb2e8f9f7	1523	/* Disable ADC peripheral if conversions are effectively stopped */
AnnaBridge	167:e84263d55307	1524	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1525	{
AnnaBridge	167:e84263d55307	1526	/* Disable ADC end of conversion interrupt for regular group */
AnnaBridge	167:e84263d55307	1527	/* Disable ADC overrun interrupt */
<>	144:ef7eb2e8f9f7	1528	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_EOS \| ADC_IT_OVR));
<>	144:ef7eb2e8f9f7	1529
<>	144:ef7eb2e8f9f7	1530	/* 2. Disable the ADC peripheral */
AnnaBridge	167:e84263d55307	1531	tmp_hal_status = ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	1532
<>	144:ef7eb2e8f9f7	1533	/* Check if ADC is effectively disabled */
AnnaBridge	167:e84263d55307	1534	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1535	{
AnnaBridge	167:e84263d55307	1536	/* Set ADC state */
AnnaBridge	167:e84263d55307	1537	ADC_STATE_CLR_SET(hadc->State,
AnnaBridge	167:e84263d55307	1538	(HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY),
AnnaBridge	167:e84263d55307	1539	HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1540	}
<>	144:ef7eb2e8f9f7	1541	}
AnnaBridge	167:e84263d55307	1542
<>	144:ef7eb2e8f9f7	1543	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1544	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1545
<>	144:ef7eb2e8f9f7	1546	/* Return function status */
AnnaBridge	167:e84263d55307	1547	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	1548	}
<>	144:ef7eb2e8f9f7	1549
<>	144:ef7eb2e8f9f7	1550	/**
<>	144:ef7eb2e8f9f7	1551	* @brief Enable ADC, start conversion of regular group and transfer result through DMA.
<>	144:ef7eb2e8f9f7	1552	* @note Interruptions enabled in this function:
<>	144:ef7eb2e8f9f7	1553	* overrun (if applicable), DMA half transfer, DMA transfer complete.
<>	144:ef7eb2e8f9f7	1554	* Each of these interruptions has its dedicated callback function.
<>	144:ef7eb2e8f9f7	1555	* @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
<>	144:ef7eb2e8f9f7	1556	* is designed for single-ADC mode only. For multimode, the dedicated
<>	144:ef7eb2e8f9f7	1557	* HAL_ADCEx_MultiModeStart_DMA() function must be used.
<>	144:ef7eb2e8f9f7	1558	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1559	* @param pData: Destination Buffer address.
<>	144:ef7eb2e8f9f7	1560	* @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes)
AnnaBridge	167:e84263d55307	1561	* @retval HAL status.
<>	144:ef7eb2e8f9f7	1562	*/
<>	144:ef7eb2e8f9f7	1563	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
<>	144:ef7eb2e8f9f7	1564	{
AnnaBridge	167:e84263d55307	1565	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	1566
<>	144:ef7eb2e8f9f7	1567	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1568	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1569
AnnaBridge	167:e84263d55307	1570	/* Perform ADC enable and conversion start if no conversion is on going */
AnnaBridge	167:e84263d55307	1571	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1572	{
<>	144:ef7eb2e8f9f7	1573	/* Process locked */
<>	144:ef7eb2e8f9f7	1574	__HAL_LOCK(hadc);
AnnaBridge	167:e84263d55307	1575
<>	144:ef7eb2e8f9f7	1576	/* Ensure that dual regular conversions are not enabled or unavailable. */
<>	144:ef7eb2e8f9f7	1577	/* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
<>	144:ef7eb2e8f9f7	1578	if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1579	{
<>	144:ef7eb2e8f9f7	1580	/* Enable the ADC peripheral */
AnnaBridge	167:e84263d55307	1581	tmp_hal_status = ADC_Enable(hadc);
<>	144:ef7eb2e8f9f7	1582
<>	144:ef7eb2e8f9f7	1583	/* Start conversion if ADC is effectively enabled */
AnnaBridge	167:e84263d55307	1584	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1585	{
<>	144:ef7eb2e8f9f7	1586	/* State machine update: Check if an injected conversion is ongoing */
<>	144:ef7eb2e8f9f7	1587	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	1588	{
<>	144:ef7eb2e8f9f7	1589	/* Reset ADC error code fields related to regular conversions only */
AnnaBridge	167:e84263d55307	1590	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR \| HAL_ADC_ERROR_DMA));
<>	144:ef7eb2e8f9f7	1591	}
<>	144:ef7eb2e8f9f7	1592	else
<>	144:ef7eb2e8f9f7	1593	{
<>	144:ef7eb2e8f9f7	1594	/* Set ADC error code to none */
AnnaBridge	167:e84263d55307	1595	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	1596	}
<>	144:ef7eb2e8f9f7	1597	/* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
AnnaBridge	167:e84263d55307	1598	ADC_STATE_CLR_SET(hadc->State,
AnnaBridge	167:e84263d55307	1599	(HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR \| HAL_ADC_STATE_REG_EOSMP),
AnnaBridge	167:e84263d55307	1600	HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	1601
<>	144:ef7eb2e8f9f7	1602	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
<>	144:ef7eb2e8f9f7	1603	- by default if ADC is Master or Independent or if multimode feature is not available
<>	144:ef7eb2e8f9f7	1604	- if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
<>	144:ef7eb2e8f9f7	1605	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<>	144:ef7eb2e8f9f7	1606	{
<>	144:ef7eb2e8f9f7	1607	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<>	144:ef7eb2e8f9f7	1608	}
<>	144:ef7eb2e8f9f7	1609
<>	144:ef7eb2e8f9f7	1610	/* Set the DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1611	hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
AnnaBridge	167:e84263d55307	1612
<>	144:ef7eb2e8f9f7	1613	/* Set the DMA half transfer complete callback */
<>	144:ef7eb2e8f9f7	1614	hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
AnnaBridge	167:e84263d55307	1615
<>	144:ef7eb2e8f9f7	1616	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1617	hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
AnnaBridge	167:e84263d55307	1618
AnnaBridge	167:e84263d55307	1619
<>	144:ef7eb2e8f9f7	1620	/* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
<>	144:ef7eb2e8f9f7	1621	/* ADC start (in case of SW start): */
AnnaBridge	167:e84263d55307	1622
<>	144:ef7eb2e8f9f7	1623	/* Clear regular group conversion flag and overrun flag */
<>	144:ef7eb2e8f9f7	1624	/* (To ensure of no unknown state from potential previous ADC */
<>	144:ef7eb2e8f9f7	1625	/* operations) */
<>	144:ef7eb2e8f9f7	1626	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
AnnaBridge	167:e84263d55307	1627
<>	144:ef7eb2e8f9f7	1628	/* With DMA, overrun event is always considered as an error even if
<>	144:ef7eb2e8f9f7	1629	hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
<>	144:ef7eb2e8f9f7	1630	ADC_IT_OVR is enabled. */
<>	144:ef7eb2e8f9f7	1631	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
AnnaBridge	167:e84263d55307	1632
AnnaBridge	167:e84263d55307	1633
<>	144:ef7eb2e8f9f7	1634	/* Enable ADC DMA mode */
<>	144:ef7eb2e8f9f7	1635	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
<>	144:ef7eb2e8f9f7	1636
<>	144:ef7eb2e8f9f7	1637	/* Start the DMA channel */
<>	144:ef7eb2e8f9f7	1638	HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
AnnaBridge	167:e84263d55307	1639
<>	144:ef7eb2e8f9f7	1640	/* Enable conversion of regular group. */
<>	144:ef7eb2e8f9f7	1641	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1642	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1643	/* If software start has been selected, conversion starts immediately. */
<>	144:ef7eb2e8f9f7	1644	/* If external trigger has been selected, conversion will start at next */
<>	144:ef7eb2e8f9f7	1645	/* trigger event. */
<>	144:ef7eb2e8f9f7	1646	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
<>	144:ef7eb2e8f9f7	1647
AnnaBridge	167:e84263d55307	1648	}
<>	144:ef7eb2e8f9f7	1649	else
<>	144:ef7eb2e8f9f7	1650	{
<>	144:ef7eb2e8f9f7	1651	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1652	__HAL_UNLOCK(hadc);
AnnaBridge	167:e84263d55307	1653	} /* if (tmp_hal_status == HAL_OK) */
<>	144:ef7eb2e8f9f7	1654	}
<>	144:ef7eb2e8f9f7	1655	else
<>	144:ef7eb2e8f9f7	1656	{
AnnaBridge	167:e84263d55307	1657	tmp_hal_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1658	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1659	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1660	} /* if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) */
AnnaBridge	167:e84263d55307	1661
AnnaBridge	167:e84263d55307	1662	}
AnnaBridge	167:e84263d55307	1663	else
AnnaBridge	167:e84263d55307	1664	{
AnnaBridge	167:e84263d55307	1665	tmp_hal_status = HAL_BUSY;
AnnaBridge	167:e84263d55307	1666	}
AnnaBridge	167:e84263d55307	1667
<>	144:ef7eb2e8f9f7	1668	/* Return function status */
AnnaBridge	167:e84263d55307	1669	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	1670	}
<>	144:ef7eb2e8f9f7	1671
<>	144:ef7eb2e8f9f7	1672	/**
AnnaBridge	167:e84263d55307	1673	* @brief Stop ADC conversion of regular group (and injected group in
AnnaBridge	167:e84263d55307	1674	* case of auto_injection mode), disable ADC DMA transfer, disable
AnnaBridge	167:e84263d55307	1675	* ADC peripheral.
AnnaBridge	167:e84263d55307	1676	* @note: ADC peripheral disable is forcing stop of potential
AnnaBridge	167:e84263d55307	1677	* conversion on injected group. If injected group is under use, it
AnnaBridge	167:e84263d55307	1678	* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
<>	144:ef7eb2e8f9f7	1679	* @note Case of multimode enabled (when multimode feature is available):
<>	144:ef7eb2e8f9f7	1680	* HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
<>	144:ef7eb2e8f9f7	1681	* For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
<>	144:ef7eb2e8f9f7	1682	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1683	* @retval HAL status.
<>	144:ef7eb2e8f9f7	1684	*/
<>	144:ef7eb2e8f9f7	1685	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
AnnaBridge	167:e84263d55307	1686	{
AnnaBridge	167:e84263d55307	1687	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	1688
<>	144:ef7eb2e8f9f7	1689	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1690	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
AnnaBridge	167:e84263d55307	1691
<>	144:ef7eb2e8f9f7	1692	/* Process locked */
<>	144:ef7eb2e8f9f7	1693	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	1694
AnnaBridge	167:e84263d55307	1695	/* 1. Stop potential ADC group regular conversion on going */
AnnaBridge	167:e84263d55307	1696	tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<>	144:ef7eb2e8f9f7	1697
<>	144:ef7eb2e8f9f7	1698	/* Disable ADC peripheral if conversions are effectively stopped */
AnnaBridge	167:e84263d55307	1699	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1700	{
<>	144:ef7eb2e8f9f7	1701	/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
AnnaBridge	167:e84263d55307	1702	CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
<>	144:ef7eb2e8f9f7	1703
AnnaBridge	167:e84263d55307	1704	/* Disable the DMA channel (in case of DMA in circular mode or stop */
<>	144:ef7eb2e8f9f7	1705	/* while DMA transfer is on going) */
AnnaBridge	167:e84263d55307	1706	tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
<>	144:ef7eb2e8f9f7	1707
<>	144:ef7eb2e8f9f7	1708	/* Check if DMA channel effectively disabled */
AnnaBridge	167:e84263d55307	1709	if (tmp_hal_status != HAL_OK)
<>	144:ef7eb2e8f9f7	1710	{
<>	144:ef7eb2e8f9f7	1711	/* Update ADC state machine to error */
AnnaBridge	167:e84263d55307	1712	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1713	}
<>	144:ef7eb2e8f9f7	1714
<>	144:ef7eb2e8f9f7	1715	/* Disable ADC overrun interrupt */
<>	144:ef7eb2e8f9f7	1716	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<>	144:ef7eb2e8f9f7	1717
<>	144:ef7eb2e8f9f7	1718	/* 2. Disable the ADC peripheral */
AnnaBridge	167:e84263d55307	1719	/* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */
AnnaBridge	167:e84263d55307	1720	/* in memory a potential failing status. */
AnnaBridge	167:e84263d55307	1721	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1722	{
AnnaBridge	167:e84263d55307	1723	tmp_hal_status = ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	1724	}
<>	144:ef7eb2e8f9f7	1725	else
<>	144:ef7eb2e8f9f7	1726	{
<>	144:ef7eb2e8f9f7	1727	ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	1728	}
<>	144:ef7eb2e8f9f7	1729
<>	144:ef7eb2e8f9f7	1730	/* Check if ADC is effectively disabled */
AnnaBridge	167:e84263d55307	1731	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1732	{
AnnaBridge	167:e84263d55307	1733	/* Set ADC state */
AnnaBridge	167:e84263d55307	1734	ADC_STATE_CLR_SET(hadc->State,
AnnaBridge	167:e84263d55307	1735	(HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY),
AnnaBridge	167:e84263d55307	1736	HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1737	}
<>	144:ef7eb2e8f9f7	1738
<>	144:ef7eb2e8f9f7	1739	}
AnnaBridge	167:e84263d55307	1740
<>	144:ef7eb2e8f9f7	1741	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1742	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1743
<>	144:ef7eb2e8f9f7	1744	/* Return function status */
AnnaBridge	167:e84263d55307	1745	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	1746	}
<>	144:ef7eb2e8f9f7	1747
<>	144:ef7eb2e8f9f7	1748	/**
<>	144:ef7eb2e8f9f7	1749	* @brief Get ADC regular group conversion result.
AnnaBridge	167:e84263d55307	1750	* @note Reading register DR automatically clears ADC flag EOC
AnnaBridge	167:e84263d55307	1751	* (ADC group regular end of unitary conversion).
AnnaBridge	167:e84263d55307	1752	* @note This function does not clear ADC flag EOS
AnnaBridge	167:e84263d55307	1753	* (ADC group regular end of sequence conversion).
AnnaBridge	167:e84263d55307	1754	* Occurrence of flag EOS rising:
AnnaBridge	167:e84263d55307	1755	* - If sequencer is composed of 1 rank, flag EOS is equivalent
AnnaBridge	167:e84263d55307	1756	* to flag EOC.
AnnaBridge	167:e84263d55307	1757	* - If sequencer is composed of several ranks, during the scan
AnnaBridge	167:e84263d55307	1758	* sequence flag EOC only is raised, at the end of the scan sequence
AnnaBridge	167:e84263d55307	1759	* both flags EOC and EOS are raised.
AnnaBridge	167:e84263d55307	1760	* To clear this flag, either use function:
AnnaBridge	167:e84263d55307	1761	* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
AnnaBridge	167:e84263d55307	1762	* model polling: @ref HAL_ADC_PollForConversion()
AnnaBridge	167:e84263d55307	1763	* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
<>	144:ef7eb2e8f9f7	1764	* @param hadc: ADC handle
AnnaBridge	167:e84263d55307	1765	* @retval ADC group regular conversion data
<>	144:ef7eb2e8f9f7	1766	*/
<>	144:ef7eb2e8f9f7	1767	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1768	{
<>	144:ef7eb2e8f9f7	1769	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1770	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
AnnaBridge	167:e84263d55307	1771
AnnaBridge	167:e84263d55307	1772	/* Note: EOC flag is not cleared here by software because automatically */
AnnaBridge	167:e84263d55307	1773	/* cleared by hardware when reading register DR. */
<>	144:ef7eb2e8f9f7	1774
<>	144:ef7eb2e8f9f7	1775	/* Return ADC converted value */
<>	144:ef7eb2e8f9f7	1776	return hadc->Instance->DR;
<>	144:ef7eb2e8f9f7	1777	}
<>	144:ef7eb2e8f9f7	1778
<>	144:ef7eb2e8f9f7	1779	/**
AnnaBridge	167:e84263d55307	1780	* @brief Handle ADC interrupt request.
<>	144:ef7eb2e8f9f7	1781	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1782	* @retval None
<>	144:ef7eb2e8f9f7	1783	*/
<>	144:ef7eb2e8f9f7	1784	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1785	{
<>	144:ef7eb2e8f9f7	1786	uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */
<>	144:ef7eb2e8f9f7	1787	ADC_TypeDef *tmpADC_Master;
<>	144:ef7eb2e8f9f7	1788	uint32_t tmp_isr = hadc->Instance->ISR;
<>	144:ef7eb2e8f9f7	1789	uint32_t tmp_ier = hadc->Instance->IER;
<>	144:ef7eb2e8f9f7	1790	uint32_t tmp_cfgr = 0x0;
AnnaBridge	167:e84263d55307	1791	uint32_t tmp_cfgr_jqm = 0x0;
<>	144:ef7eb2e8f9f7	1792
<>	144:ef7eb2e8f9f7	1793	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1794	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1795	assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
<>	144:ef7eb2e8f9f7	1796
<>	144:ef7eb2e8f9f7	1797	/* ====== Check End of Sampling flag for regular group ===== */
<>	144:ef7eb2e8f9f7	1798	if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
<>	144:ef7eb2e8f9f7	1799	{
<>	144:ef7eb2e8f9f7	1800	/* Update state machine on end of sampling status if not in error state */
<>	144:ef7eb2e8f9f7	1801	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<>	144:ef7eb2e8f9f7	1802	{
AnnaBridge	167:e84263d55307	1803	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1804	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
<>	144:ef7eb2e8f9f7	1805	}
<>	144:ef7eb2e8f9f7	1806
<>	144:ef7eb2e8f9f7	1807	/* End Of Sampling callback */
<>	144:ef7eb2e8f9f7	1808	HAL_ADCEx_EndOfSamplingCallback(hadc);
<>	144:ef7eb2e8f9f7	1809
<>	144:ef7eb2e8f9f7	1810	/* Clear regular group conversion flag */
<>	144:ef7eb2e8f9f7	1811	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP );
<>	144:ef7eb2e8f9f7	1812	}
<>	144:ef7eb2e8f9f7	1813
<>	144:ef7eb2e8f9f7	1814	/* ====== Check End of Conversion or Sequence flags for regular group ===== */
<>	144:ef7eb2e8f9f7	1815	if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) \|\|
<>	144:ef7eb2e8f9f7	1816	(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) )
<>	144:ef7eb2e8f9f7	1817	{
<>	144:ef7eb2e8f9f7	1818	/* Update state machine on conversion status if not in error state */
<>	144:ef7eb2e8f9f7	1819	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<>	144:ef7eb2e8f9f7	1820	{
AnnaBridge	167:e84263d55307	1821	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1822	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<>	144:ef7eb2e8f9f7	1823	}
<>	144:ef7eb2e8f9f7	1824
<>	144:ef7eb2e8f9f7	1825	/* Disable interruption if no further conversion upcoming by regular */
<>	144:ef7eb2e8f9f7	1826	/* external trigger or by continuous mode, */
<>	144:ef7eb2e8f9f7	1827	/* and if scan sequence if completed. */
<>	144:ef7eb2e8f9f7	1828	if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
<>	144:ef7eb2e8f9f7	1829	{
<>	144:ef7eb2e8f9f7	1830	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
<>	144:ef7eb2e8f9f7	1831	{
<>	144:ef7eb2e8f9f7	1832	/* check CONT bit directly in handle ADC CFGR register */
<>	144:ef7eb2e8f9f7	1833	tmp_cfgr = READ_REG(hadc->Instance->CFGR);
<>	144:ef7eb2e8f9f7	1834	}
<>	144:ef7eb2e8f9f7	1835	else
<>	144:ef7eb2e8f9f7	1836	{
<>	144:ef7eb2e8f9f7	1837	/* else need to check Master ADC CONT bit */
<>	144:ef7eb2e8f9f7	1838	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	1839	tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
<>	144:ef7eb2e8f9f7	1840	}
<>	144:ef7eb2e8f9f7	1841
<>	144:ef7eb2e8f9f7	1842	/* Carry on if continuous mode is disabled */
<>	144:ef7eb2e8f9f7	1843	if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
<>	144:ef7eb2e8f9f7	1844	{
<>	144:ef7eb2e8f9f7	1845	/* If End of Sequence is reached, disable interrupts */
<>	144:ef7eb2e8f9f7	1846	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
<>	144:ef7eb2e8f9f7	1847	{
<>	144:ef7eb2e8f9f7	1848	/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
<>	144:ef7eb2e8f9f7	1849	/* ADSTART==0 (no conversion on going) */
<>	144:ef7eb2e8f9f7	1850	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1851	{
<>	144:ef7eb2e8f9f7	1852	/* Disable ADC end of sequence conversion interrupt */
<>	144:ef7eb2e8f9f7	1853	/* Note: if Overrun interrupt was enabled with EOC or EOS interrupt */
<>	144:ef7eb2e8f9f7	1854	/* in HAL_Start_IT(), it isn't disabled here because it can be used */
<>	144:ef7eb2e8f9f7	1855	/* by overrun IRQ process below. */
<>	144:ef7eb2e8f9f7	1856	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC \| ADC_IT_EOS);
<>	144:ef7eb2e8f9f7	1857	/* Clear HAL_ADC_STATE_REG_BUSY bit */
<>	144:ef7eb2e8f9f7	1858	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	1859	/* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
<>	144:ef7eb2e8f9f7	1860	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	1861	{
<>	144:ef7eb2e8f9f7	1862	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1863	}
<>	144:ef7eb2e8f9f7	1864	}
<>	144:ef7eb2e8f9f7	1865	else
<>	144:ef7eb2e8f9f7	1866	{
<>	144:ef7eb2e8f9f7	1867	/* Change ADC state to error state */
<>	144:ef7eb2e8f9f7	1868	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1869
<>	144:ef7eb2e8f9f7	1870	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	1871	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1872	}
<>	144:ef7eb2e8f9f7	1873	}
<>	144:ef7eb2e8f9f7	1874	} /* if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) */
<>	144:ef7eb2e8f9f7	1875	} /* if(ADC_IS_SOFTWARE_START_REGULAR(hadc) */
<>	144:ef7eb2e8f9f7	1876
<>	144:ef7eb2e8f9f7	1877	/* Conversion complete callback */
<>	144:ef7eb2e8f9f7	1878	/* Note: HAL_ADC_ConvCpltCallback can resort to
<>	144:ef7eb2e8f9f7	1879	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) or
<>	144:ef7eb2e8f9f7	1880	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOC)) to determine whether
<>	144:ef7eb2e8f9f7	1881	interruption has been triggered by end of conversion or end of
<>	144:ef7eb2e8f9f7	1882	sequence. */
<>	144:ef7eb2e8f9f7	1883	HAL_ADC_ConvCpltCallback(hadc);
<>	144:ef7eb2e8f9f7	1884
<>	144:ef7eb2e8f9f7	1885
<>	144:ef7eb2e8f9f7	1886	/* Clear regular group conversion flag */
<>	144:ef7eb2e8f9f7	1887	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS) );
<>	144:ef7eb2e8f9f7	1888	}
<>	144:ef7eb2e8f9f7	1889
<>	144:ef7eb2e8f9f7	1890
<>	144:ef7eb2e8f9f7	1891	/* ========== Check End of Conversion flag for injected group ========== */
<>	144:ef7eb2e8f9f7	1892	if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) \|\|
<>	144:ef7eb2e8f9f7	1893	(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) )
<>	144:ef7eb2e8f9f7	1894	{
<>	144:ef7eb2e8f9f7	1895	/* Update state machine on conversion status if not in error state */
<>	144:ef7eb2e8f9f7	1896	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<>	144:ef7eb2e8f9f7	1897	{
AnnaBridge	167:e84263d55307	1898	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1899	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
<>	144:ef7eb2e8f9f7	1900	}
<>	144:ef7eb2e8f9f7	1901
<>	144:ef7eb2e8f9f7	1902
<>	144:ef7eb2e8f9f7	1903	/* Check whether interruptions can be disabled only if
<>	144:ef7eb2e8f9f7	1904	- injected conversions are software-triggered when injected queue management is disabled
<>	144:ef7eb2e8f9f7	1905	OR
<>	144:ef7eb2e8f9f7	1906	- auto-injection is enabled, continuous mode is disabled (CONT = 0)
<>	144:ef7eb2e8f9f7	1907	and regular conversions are software-triggered */
<>	144:ef7eb2e8f9f7	1908	/* If End of Sequence is reached, disable interrupts */
<>	144:ef7eb2e8f9f7	1909	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
<>	144:ef7eb2e8f9f7	1910	{
<>	144:ef7eb2e8f9f7	1911
<>	144:ef7eb2e8f9f7	1912	/* First, retrieve proper registers to check */
AnnaBridge	167:e84263d55307	1913	/* 1a. Are injected conversions that of a dual Slave ? */
<>	144:ef7eb2e8f9f7	1914	if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
<>	144:ef7eb2e8f9f7	1915	{
<>	144:ef7eb2e8f9f7	1916	/* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
<>	144:ef7eb2e8f9f7	1917	check JQM bit directly in ADC CFGR register */
<>	144:ef7eb2e8f9f7	1918	tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
<>	144:ef7eb2e8f9f7	1919	}
<>	144:ef7eb2e8f9f7	1920	else
<>	144:ef7eb2e8f9f7	1921	{
<>	144:ef7eb2e8f9f7	1922	/* hadc is the handle of a Slave ADC with dual injected conversions enabled:
<>	144:ef7eb2e8f9f7	1923	need to check JQM bit of Master ADC CFGR register */
<>	144:ef7eb2e8f9f7	1924	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	1925	tmp_cfgr_jqm = READ_REG(tmpADC_Master->CFGR);
<>	144:ef7eb2e8f9f7	1926	}
<>	144:ef7eb2e8f9f7	1927	/* 1b. Is hadc the handle of a Slave ADC with regular conversions enabled? */
<>	144:ef7eb2e8f9f7	1928	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
<>	144:ef7eb2e8f9f7	1929	{
<>	144:ef7eb2e8f9f7	1930	/* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
<>	144:ef7eb2e8f9f7	1931	check JAUTO and CONT bits directly in ADC CFGR register */
<>	144:ef7eb2e8f9f7	1932	tmp_cfgr = READ_REG(hadc->Instance->CFGR);
<>	144:ef7eb2e8f9f7	1933	}
<>	144:ef7eb2e8f9f7	1934	else
<>	144:ef7eb2e8f9f7	1935	{
<>	144:ef7eb2e8f9f7	1936	/* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
<>	144:ef7eb2e8f9f7	1937	check JAUTO and CONT bits of Master ADC CFGR register */
<>	144:ef7eb2e8f9f7	1938	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	1939	tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
<>	144:ef7eb2e8f9f7	1940	}
<>	144:ef7eb2e8f9f7	1941
<>	144:ef7eb2e8f9f7	1942	/* Secondly, check whether JEOC and JEOS interruptions can be disabled */
<>	144:ef7eb2e8f9f7	1943	if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) != ADC_CFGR_JQM))
<>	144:ef7eb2e8f9f7	1944	&& (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO\|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO\|ADC_CFGR_CONT)) &&
<>	144:ef7eb2e8f9f7	1945	(ADC_IS_SOFTWARE_START_REGULAR(hadc)))) )
<>	144:ef7eb2e8f9f7	1946	{
<>	144:ef7eb2e8f9f7	1947	/* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
<>	144:ef7eb2e8f9f7	1948	/* JADSTART==0 (no conversion on going) */
<>	144:ef7eb2e8f9f7	1949	if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1950	{
<>	144:ef7eb2e8f9f7	1951	/* Disable ADC end of sequence conversion interrupt */
<>	144:ef7eb2e8f9f7	1952	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC \| ADC_IT_JEOS);
<>	144:ef7eb2e8f9f7	1953	/* Clear HAL_ADC_STATE_INJ_BUSY bit */
<>	144:ef7eb2e8f9f7	1954	CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<>	144:ef7eb2e8f9f7	1955	/* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */
<>	144:ef7eb2e8f9f7	1956	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<>	144:ef7eb2e8f9f7	1957	{
<>	144:ef7eb2e8f9f7	1958	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1959	}
<>	144:ef7eb2e8f9f7	1960	}
<>	144:ef7eb2e8f9f7	1961	else
<>	144:ef7eb2e8f9f7	1962	{
<>	144:ef7eb2e8f9f7	1963	/* Change ADC state to error state */
<>	144:ef7eb2e8f9f7	1964	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1965
<>	144:ef7eb2e8f9f7	1966	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	1967	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1968	}
<>	144:ef7eb2e8f9f7	1969	}
<>	144:ef7eb2e8f9f7	1970	} /* if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) */
<>	144:ef7eb2e8f9f7	1971
<>	144:ef7eb2e8f9f7	1972	/* Injected Conversion complete callback */
<>	144:ef7eb2e8f9f7	1973	/* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
<>	144:ef7eb2e8f9f7	1974	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
AnnaBridge	167:e84263d55307	1975	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
<>	144:ef7eb2e8f9f7	1976	interruption has been triggered by end of conversion or end of
<>	144:ef7eb2e8f9f7	1977	sequence. */
<>	144:ef7eb2e8f9f7	1978	HAL_ADCEx_InjectedConvCpltCallback(hadc);
<>	144:ef7eb2e8f9f7	1979
<>	144:ef7eb2e8f9f7	1980	/* Clear injected group conversion flag */
<>	144:ef7eb2e8f9f7	1981	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC \| ADC_FLAG_JEOS);
<>	144:ef7eb2e8f9f7	1982	}
<>	144:ef7eb2e8f9f7	1983
<>	144:ef7eb2e8f9f7	1984	/* ========== Check Analog watchdog flags =================================================== */
<>	144:ef7eb2e8f9f7	1985
AnnaBridge	167:e84263d55307	1986	/* ========== Check Analog watchdog 1 flag ========== */
<>	144:ef7eb2e8f9f7	1987	if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
<>	144:ef7eb2e8f9f7	1988	{
AnnaBridge	167:e84263d55307	1989	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1990	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<>	144:ef7eb2e8f9f7	1991
<>	144:ef7eb2e8f9f7	1992	/* Level out of window 1 callback */
<>	144:ef7eb2e8f9f7	1993	HAL_ADC_LevelOutOfWindowCallback(hadc);
AnnaBridge	167:e84263d55307	1994	/* Clear ADC analog watchdog flag */
<>	144:ef7eb2e8f9f7	1995	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
<>	144:ef7eb2e8f9f7	1996	}
<>	144:ef7eb2e8f9f7	1997
AnnaBridge	167:e84263d55307	1998	/* ========== Check analog watchdog 2 flag ========== */
<>	144:ef7eb2e8f9f7	1999	if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
<>	144:ef7eb2e8f9f7	2000	{
AnnaBridge	167:e84263d55307	2001	/* Set ADC state */
<>	144:ef7eb2e8f9f7	2002	SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
<>	144:ef7eb2e8f9f7	2003
<>	144:ef7eb2e8f9f7	2004	/* Level out of window 2 callback */
<>	144:ef7eb2e8f9f7	2005	HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
AnnaBridge	167:e84263d55307	2006	/* Clear ADC analog watchdog flag */
<>	144:ef7eb2e8f9f7	2007	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
<>	144:ef7eb2e8f9f7	2008	}
<>	144:ef7eb2e8f9f7	2009
AnnaBridge	167:e84263d55307	2010	/* ========== Check analog watchdog 3 flag ========== */
<>	144:ef7eb2e8f9f7	2011	if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
<>	144:ef7eb2e8f9f7	2012	{
AnnaBridge	167:e84263d55307	2013	/* Set ADC state */
<>	144:ef7eb2e8f9f7	2014	SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
<>	144:ef7eb2e8f9f7	2015
<>	144:ef7eb2e8f9f7	2016	/* Level out of window 3 callback */
<>	144:ef7eb2e8f9f7	2017	HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
AnnaBridge	167:e84263d55307	2018	/* Clear ADC analog watchdog flag */
<>	144:ef7eb2e8f9f7	2019	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
AnnaBridge	167:e84263d55307	2020	}
<>	144:ef7eb2e8f9f7	2021
<>	144:ef7eb2e8f9f7	2022	/* ========== Check Overrun flag ========== */
<>	144:ef7eb2e8f9f7	2023	if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
<>	144:ef7eb2e8f9f7	2024	{
<>	144:ef7eb2e8f9f7	2025	/* If overrun is set to overwrite previous data (default setting), */
<>	144:ef7eb2e8f9f7	2026	/* overrun event is not considered as an error. */
<>	144:ef7eb2e8f9f7	2027	/* (cf ref manual "Managing conversions without using the DMA and without */
<>	144:ef7eb2e8f9f7	2028	/* overrun ") */
<>	144:ef7eb2e8f9f7	2029	/* Exception for usage with DMA overrun event always considered as an */
<>	144:ef7eb2e8f9f7	2030	/* error. */
<>	144:ef7eb2e8f9f7	2031
<>	144:ef7eb2e8f9f7	2032	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
<>	144:ef7eb2e8f9f7	2033	{
<>	144:ef7eb2e8f9f7	2034	overrun_error = 1;
<>	144:ef7eb2e8f9f7	2035	}
<>	144:ef7eb2e8f9f7	2036	else
<>	144:ef7eb2e8f9f7	2037	{
<>	144:ef7eb2e8f9f7	2038	/* check DMA configuration, depending on multimode set or not,
<>	144:ef7eb2e8f9f7	2039	or whether or not multimode feature is available */
<>	144:ef7eb2e8f9f7	2040	if (ADC_IS_DUAL_CONVERSION_ENABLE(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2041	{
<>	144:ef7eb2e8f9f7	2042	/* Multimode not set or feature not available or ADC independent */
<>	144:ef7eb2e8f9f7	2043	if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
<>	144:ef7eb2e8f9f7	2044	{
<>	144:ef7eb2e8f9f7	2045	overrun_error = 1;
<>	144:ef7eb2e8f9f7	2046	}
<>	144:ef7eb2e8f9f7	2047	}
<>	144:ef7eb2e8f9f7	2048	else
<>	144:ef7eb2e8f9f7	2049	{
<>	144:ef7eb2e8f9f7	2050	/* Multimode (when feature is available) is enabled,
<>	144:ef7eb2e8f9f7	2051	Common Control Register MDMA bits must be checked. */
<>	144:ef7eb2e8f9f7	2052	if (ADC_MULTIMODE_DMA_ENABLED())
<>	144:ef7eb2e8f9f7	2053	{
<>	144:ef7eb2e8f9f7	2054	overrun_error = 1;
<>	144:ef7eb2e8f9f7	2055	}
<>	144:ef7eb2e8f9f7	2056	}
<>	144:ef7eb2e8f9f7	2057	}
<>	144:ef7eb2e8f9f7	2058
<>	144:ef7eb2e8f9f7	2059	if (overrun_error == 1)
<>	144:ef7eb2e8f9f7	2060	{
<>	144:ef7eb2e8f9f7	2061	/* Change ADC state to error state */
<>	144:ef7eb2e8f9f7	2062	SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
<>	144:ef7eb2e8f9f7	2063
<>	144:ef7eb2e8f9f7	2064	/* Set ADC error code to overrun */
<>	144:ef7eb2e8f9f7	2065	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<>	144:ef7eb2e8f9f7	2066
<>	144:ef7eb2e8f9f7	2067	/* Error callback */
<>	144:ef7eb2e8f9f7	2068	HAL_ADC_ErrorCallback(hadc);
<>	144:ef7eb2e8f9f7	2069	}
<>	144:ef7eb2e8f9f7	2070
<>	144:ef7eb2e8f9f7	2071	/* Clear the Overrun flag, to be done AFTER HAL_ADC_ErrorCallback() since
<>	144:ef7eb2e8f9f7	2072	old data is preserved until OVR is reset */
<>	144:ef7eb2e8f9f7	2073	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<>	144:ef7eb2e8f9f7	2074
<>	144:ef7eb2e8f9f7	2075	}
<>	144:ef7eb2e8f9f7	2076
<>	144:ef7eb2e8f9f7	2077
<>	144:ef7eb2e8f9f7	2078	/* ========== Check Injected context queue overflow flag ========== */
<>	144:ef7eb2e8f9f7	2079	if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
<>	144:ef7eb2e8f9f7	2080	{
<>	144:ef7eb2e8f9f7	2081	/* Change ADC state to overrun state */
<>	144:ef7eb2e8f9f7	2082	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
<>	144:ef7eb2e8f9f7	2083
<>	144:ef7eb2e8f9f7	2084	/* Set ADC error code to Injected context queue overflow */
<>	144:ef7eb2e8f9f7	2085	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
<>	144:ef7eb2e8f9f7	2086
<>	144:ef7eb2e8f9f7	2087	/* Clear the Injected context queue overflow flag */
<>	144:ef7eb2e8f9f7	2088	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
<>	144:ef7eb2e8f9f7	2089
AnnaBridge	167:e84263d55307	2090	/* Error callback */
<>	144:ef7eb2e8f9f7	2091	HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
<>	144:ef7eb2e8f9f7	2092	}
<>	144:ef7eb2e8f9f7	2093
<>	144:ef7eb2e8f9f7	2094	}
<>	144:ef7eb2e8f9f7	2095
<>	144:ef7eb2e8f9f7	2096	/**
<>	144:ef7eb2e8f9f7	2097	* @brief Conversion complete callback in non-blocking mode.
<>	144:ef7eb2e8f9f7	2098	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2099	* @retval None
<>	144:ef7eb2e8f9f7	2100	*/
<>	144:ef7eb2e8f9f7	2101	__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	2102	{
<>	144:ef7eb2e8f9f7	2103	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2104	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	2105
<>	144:ef7eb2e8f9f7	2106	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	2107	function HAL_ADC_ConvCpltCallback must be implemented in the user file.
<>	144:ef7eb2e8f9f7	2108	*/
<>	144:ef7eb2e8f9f7	2109	}
<>	144:ef7eb2e8f9f7	2110
<>	144:ef7eb2e8f9f7	2111	/**
<>	144:ef7eb2e8f9f7	2112	* @brief Conversion DMA half-transfer callback in non-blocking mode.
<>	144:ef7eb2e8f9f7	2113	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2114	* @retval None
<>	144:ef7eb2e8f9f7	2115	*/
<>	144:ef7eb2e8f9f7	2116	__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	2117	{
<>	144:ef7eb2e8f9f7	2118	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2119	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	2120
<>	144:ef7eb2e8f9f7	2121	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	2122	function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
<>	144:ef7eb2e8f9f7	2123	*/
<>	144:ef7eb2e8f9f7	2124	}
<>	144:ef7eb2e8f9f7	2125
<>	144:ef7eb2e8f9f7	2126	/**
AnnaBridge	167:e84263d55307	2127	* @brief Analog watchdog 1 callback in non-blocking mode.
<>	144:ef7eb2e8f9f7	2128	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2129	* @retval None
<>	144:ef7eb2e8f9f7	2130	*/
<>	144:ef7eb2e8f9f7	2131	__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	2132	{
<>	144:ef7eb2e8f9f7	2133	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2134	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	2135
<>	144:ef7eb2e8f9f7	2136	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	2137	function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
<>	144:ef7eb2e8f9f7	2138	*/
<>	144:ef7eb2e8f9f7	2139	}
<>	144:ef7eb2e8f9f7	2140
<>	144:ef7eb2e8f9f7	2141	/**
<>	144:ef7eb2e8f9f7	2142	* @brief ADC error callback in non-blocking mode
AnnaBridge	167:e84263d55307	2143	* (ADC conversion with interruption or transfer by DMA).
AnnaBridge	167:e84263d55307	2144	* @note In case of error due to overrun when using ADC with DMA transfer
AnnaBridge	167:e84263d55307	2145	* (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
AnnaBridge	167:e84263d55307	2146	* - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
AnnaBridge	167:e84263d55307	2147	* - If needed, restart a new ADC conversion using function
AnnaBridge	167:e84263d55307	2148	* "HAL_ADC_Start_DMA()"
AnnaBridge	167:e84263d55307	2149	* (this function is also clearing overrun flag)
<>	144:ef7eb2e8f9f7	2150	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2151	* @retval None
<>	144:ef7eb2e8f9f7	2152	*/
<>	144:ef7eb2e8f9f7	2153	__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
<>	144:ef7eb2e8f9f7	2154	{
<>	144:ef7eb2e8f9f7	2155	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2156	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	2157
<>	144:ef7eb2e8f9f7	2158	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	2159	function HAL_ADC_ErrorCallback must be implemented in the user file.
<>	144:ef7eb2e8f9f7	2160	*/
<>	144:ef7eb2e8f9f7	2161	}
<>	144:ef7eb2e8f9f7	2162
<>	144:ef7eb2e8f9f7	2163	/**
<>	144:ef7eb2e8f9f7	2164	* @}
<>	144:ef7eb2e8f9f7	2165	*/
<>	144:ef7eb2e8f9f7	2166
<>	144:ef7eb2e8f9f7	2167	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
<>	144:ef7eb2e8f9f7	2168	* @brief Peripheral Control functions
<>	144:ef7eb2e8f9f7	2169	*
<>	144:ef7eb2e8f9f7	2170	@verbatim
<>	144:ef7eb2e8f9f7	2171	===============================================================================
<>	144:ef7eb2e8f9f7	2172	##### Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	2173	===============================================================================
<>	144:ef7eb2e8f9f7	2174	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	2175	(+) Configure channels on regular group
<>	144:ef7eb2e8f9f7	2176	(+) Configure the analog watchdog
<>	144:ef7eb2e8f9f7	2177
<>	144:ef7eb2e8f9f7	2178	@endverbatim
<>	144:ef7eb2e8f9f7	2179	* @{
<>	144:ef7eb2e8f9f7	2180	*/
<>	144:ef7eb2e8f9f7	2181
<>	144:ef7eb2e8f9f7	2182	/**
AnnaBridge	167:e84263d55307	2183	* @brief Configure a channel to be assigned to ADC group regular.
AnnaBridge	167:e84263d55307	2184	* @note In case of usage of internal measurement channels:
AnnaBridge	167:e84263d55307	2185	* Vbat/VrefInt/TempSensor.
<>	144:ef7eb2e8f9f7	2186	* These internal paths can be disabled using function
<>	144:ef7eb2e8f9f7	2187	* HAL_ADC_DeInit().
<>	144:ef7eb2e8f9f7	2188	* @note Possibility to update parameters on the fly:
AnnaBridge	167:e84263d55307	2189	* This function initializes channel into ADC group regular,
AnnaBridge	167:e84263d55307	2190	* following calls to this function can be used to reconfigure
AnnaBridge	167:e84263d55307	2191	* some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
AnnaBridge	167:e84263d55307	2192	* without resetting the ADC.
AnnaBridge	167:e84263d55307	2193	* The setting of these parameters is conditioned to ADC state:
AnnaBridge	167:e84263d55307	2194	* Refer to comments of structure "ADC_ChannelConfTypeDef".
<>	144:ef7eb2e8f9f7	2195	* @param hadc: ADC handle
AnnaBridge	167:e84263d55307	2196	* @param sConfig: Structure of ADC channel assigned to ADC group regular.
<>	144:ef7eb2e8f9f7	2197	* @retval HAL status
<>	144:ef7eb2e8f9f7	2198	*/
<>	144:ef7eb2e8f9f7	2199	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
<>	144:ef7eb2e8f9f7	2200	{
AnnaBridge	167:e84263d55307	2201	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	2202	ADC_Common_TypeDef *tmpADC_Common;
<>	144:ef7eb2e8f9f7	2203	uint32_t tmpOffsetShifted;
<>	144:ef7eb2e8f9f7	2204	__IO uint32_t wait_loop_index = 0;
<>	144:ef7eb2e8f9f7	2205
<>	144:ef7eb2e8f9f7	2206	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2207	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	2208	assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
<>	144:ef7eb2e8f9f7	2209	assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
<>	144:ef7eb2e8f9f7	2210	assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
<>	144:ef7eb2e8f9f7	2211	assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
<>	144:ef7eb2e8f9f7	2212	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
AnnaBridge	167:e84263d55307	2213
<>	144:ef7eb2e8f9f7	2214	/* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
<>	144:ef7eb2e8f9f7	2215	ignored (considered as reset) */
<>	144:ef7eb2e8f9f7	2216	assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
<>	144:ef7eb2e8f9f7	2217
<>	144:ef7eb2e8f9f7	2218	/* Verification of channel number */
<>	144:ef7eb2e8f9f7	2219	if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
<>	144:ef7eb2e8f9f7	2220	{
<>	144:ef7eb2e8f9f7	2221	assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
<>	144:ef7eb2e8f9f7	2222	}
<>	144:ef7eb2e8f9f7	2223	else
<>	144:ef7eb2e8f9f7	2224	{
<>	144:ef7eb2e8f9f7	2225	assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
<>	144:ef7eb2e8f9f7	2226	}
<>	144:ef7eb2e8f9f7	2227
<>	144:ef7eb2e8f9f7	2228	/* Process locked */
<>	144:ef7eb2e8f9f7	2229	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	2230
<>	144:ef7eb2e8f9f7	2231	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	2232	/* Parameters that can be updated when ADC is disabled or enabled without */
<>	144:ef7eb2e8f9f7	2233	/* conversion on going on regular group: */
<>	144:ef7eb2e8f9f7	2234	/* - Channel number */
<>	144:ef7eb2e8f9f7	2235	/* - Channel rank */
<>	144:ef7eb2e8f9f7	2236	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2237	{
<>	144:ef7eb2e8f9f7	2238
<>	144:ef7eb2e8f9f7	2239	/* Regular sequence configuration */
<>	144:ef7eb2e8f9f7	2240	/* Clear the old SQx bits then set the new ones for the selected rank */
<>	144:ef7eb2e8f9f7	2241	/* For Rank 1 to 4 */
<>	144:ef7eb2e8f9f7	2242	if (sConfig->Rank < 5)
<>	144:ef7eb2e8f9f7	2243	{
<>	144:ef7eb2e8f9f7	2244	MODIFY_REG(hadc->Instance->SQR1,
<>	144:ef7eb2e8f9f7	2245	ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank),
AnnaBridge	167:e84263d55307	2246	ADC_SQR1_RK(sConfig->Channel, sConfig->Rank));
<>	144:ef7eb2e8f9f7	2247	}
<>	144:ef7eb2e8f9f7	2248	/* For Rank 5 to 9 */
<>	144:ef7eb2e8f9f7	2249	else if (sConfig->Rank < 10)
<>	144:ef7eb2e8f9f7	2250	{
<>	144:ef7eb2e8f9f7	2251	MODIFY_REG(hadc->Instance->SQR2,
<>	144:ef7eb2e8f9f7	2252	ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank),
AnnaBridge	167:e84263d55307	2253	ADC_SQR2_RK(sConfig->Channel, sConfig->Rank));
<>	144:ef7eb2e8f9f7	2254	}
<>	144:ef7eb2e8f9f7	2255	/* For Rank 10 to 14 */
<>	144:ef7eb2e8f9f7	2256	else if (sConfig->Rank < 15)
<>	144:ef7eb2e8f9f7	2257	{
<>	144:ef7eb2e8f9f7	2258	MODIFY_REG(hadc->Instance->SQR3,
<>	144:ef7eb2e8f9f7	2259	ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank),
AnnaBridge	167:e84263d55307	2260	ADC_SQR3_RK(sConfig->Channel, sConfig->Rank));
<>	144:ef7eb2e8f9f7	2261	}
<>	144:ef7eb2e8f9f7	2262	/* For Rank 15 to 16 */
<>	144:ef7eb2e8f9f7	2263	else
<>	144:ef7eb2e8f9f7	2264	{
<>	144:ef7eb2e8f9f7	2265	MODIFY_REG(hadc->Instance->SQR4,
<>	144:ef7eb2e8f9f7	2266	ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank),
AnnaBridge	167:e84263d55307	2267	ADC_SQR4_RK(sConfig->Channel, sConfig->Rank));
<>	144:ef7eb2e8f9f7	2268	}
<>	144:ef7eb2e8f9f7	2269
<>	144:ef7eb2e8f9f7	2270
<>	144:ef7eb2e8f9f7	2271	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	2272	/* Parameters that can be updated when ADC is disabled or enabled without */
<>	144:ef7eb2e8f9f7	2273	/* conversion on going on regular group: */
<>	144:ef7eb2e8f9f7	2274	/* - Channel sampling time */
<>	144:ef7eb2e8f9f7	2275	/* - Channel offset */
<>	144:ef7eb2e8f9f7	2276	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2277	{
<>	144:ef7eb2e8f9f7	2278
<>	144:ef7eb2e8f9f7	2279	/* Channel sampling time configuration */
AnnaBridge	167:e84263d55307	2280	/* Clear the old sample time then set the new one for the selected channel */
<>	144:ef7eb2e8f9f7	2281	/* For channels 10 to 18 */
<>	144:ef7eb2e8f9f7	2282	if (sConfig->Channel >= ADC_CHANNEL_10)
<>	144:ef7eb2e8f9f7	2283	{
AnnaBridge	167:e84263d55307	2284	ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);
<>	144:ef7eb2e8f9f7	2285	}
<>	144:ef7eb2e8f9f7	2286	else /* For channels 0 to 9 */
<>	144:ef7eb2e8f9f7	2287	{
AnnaBridge	167:e84263d55307	2288	ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);
<>	144:ef7eb2e8f9f7	2289	}
<>	144:ef7eb2e8f9f7	2290
<>	144:ef7eb2e8f9f7	2291
<>	144:ef7eb2e8f9f7	2292	/* Configure the offset: offset enable/disable, channel, offset value */
<>	144:ef7eb2e8f9f7	2293
<>	144:ef7eb2e8f9f7	2294	/* Shift the offset with respect to the selected ADC resolution. */
<>	144:ef7eb2e8f9f7	2295	/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
<>	144:ef7eb2e8f9f7	2296	tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
<>	144:ef7eb2e8f9f7	2297
<>	144:ef7eb2e8f9f7	2298	switch (sConfig->OffsetNumber)
<>	144:ef7eb2e8f9f7	2299	{
<>	144:ef7eb2e8f9f7	2300	/* Configure offset register i when applicable: */
<>	144:ef7eb2e8f9f7	2301	/* - Enable offset */
<>	144:ef7eb2e8f9f7	2302	/* - Set channel number */
AnnaBridge	167:e84263d55307	2303	/* - Set offset value */
AnnaBridge	167:e84263d55307	2304	case ADC_OFFSET_1:
AnnaBridge	167:e84263d55307	2305	MODIFY_REG(hadc->Instance->OFR1,
AnnaBridge	167:e84263d55307	2306	ADC_OFR_FIELDS,
<>	144:ef7eb2e8f9f7	2307	ADC_OFR1_OFFSET1_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
<>	144:ef7eb2e8f9f7	2308	break;
<>	144:ef7eb2e8f9f7	2309
<>	144:ef7eb2e8f9f7	2310	case ADC_OFFSET_2:
AnnaBridge	167:e84263d55307	2311	MODIFY_REG(hadc->Instance->OFR2,
<>	144:ef7eb2e8f9f7	2312	ADC_OFR_FIELDS,
<>	144:ef7eb2e8f9f7	2313	ADC_OFR2_OFFSET2_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
<>	144:ef7eb2e8f9f7	2314	break;
<>	144:ef7eb2e8f9f7	2315
<>	144:ef7eb2e8f9f7	2316	case ADC_OFFSET_3:
AnnaBridge	167:e84263d55307	2317	MODIFY_REG(hadc->Instance->OFR3,
AnnaBridge	167:e84263d55307	2318	ADC_OFR_FIELDS,
<>	144:ef7eb2e8f9f7	2319	ADC_OFR3_OFFSET3_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
<>	144:ef7eb2e8f9f7	2320	break;
<>	144:ef7eb2e8f9f7	2321
<>	144:ef7eb2e8f9f7	2322	case ADC_OFFSET_4:
AnnaBridge	167:e84263d55307	2323	MODIFY_REG(hadc->Instance->OFR4,
AnnaBridge	167:e84263d55307	2324	ADC_OFR_FIELDS,
<>	144:ef7eb2e8f9f7	2325	ADC_OFR4_OFFSET4_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
<>	144:ef7eb2e8f9f7	2326	break;
AnnaBridge	167:e84263d55307	2327
<>	144:ef7eb2e8f9f7	2328	/* Case ADC_OFFSET_NONE */
<>	144:ef7eb2e8f9f7	2329	default :
AnnaBridge	167:e84263d55307	2330	/* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
AnnaBridge	167:e84263d55307	2331	If this is the case, offset OFRx is disabled since
<>	144:ef7eb2e8f9f7	2332	sConfig->OffsetNumber = ADC_OFFSET_NONE. */
<>	144:ef7eb2e8f9f7	2333	if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
<>	144:ef7eb2e8f9f7	2334	{
<>	144:ef7eb2e8f9f7	2335	CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
<>	144:ef7eb2e8f9f7	2336	}
<>	144:ef7eb2e8f9f7	2337	if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
<>	144:ef7eb2e8f9f7	2338	{
AnnaBridge	167:e84263d55307	2339	CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
<>	144:ef7eb2e8f9f7	2340	}
<>	144:ef7eb2e8f9f7	2341	if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
<>	144:ef7eb2e8f9f7	2342	{
AnnaBridge	167:e84263d55307	2343	CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
<>	144:ef7eb2e8f9f7	2344	}
<>	144:ef7eb2e8f9f7	2345	if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
<>	144:ef7eb2e8f9f7	2346	{
<>	144:ef7eb2e8f9f7	2347	CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
<>	144:ef7eb2e8f9f7	2348	}
<>	144:ef7eb2e8f9f7	2349	break;
<>	144:ef7eb2e8f9f7	2350	} /* switch (sConfig->OffsetNumber) */
AnnaBridge	167:e84263d55307	2351
<>	144:ef7eb2e8f9f7	2352	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
AnnaBridge	167:e84263d55307	2353
<>	144:ef7eb2e8f9f7	2354	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	2355	/* Parameters that can be updated only when ADC is disabled: */
<>	144:ef7eb2e8f9f7	2356	/* - Single or differential mode */
<>	144:ef7eb2e8f9f7	2357	/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
<>	144:ef7eb2e8f9f7	2358	if (ADC_IS_ENABLE(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2359	{
<>	144:ef7eb2e8f9f7	2360	/* Configuration of differential mode */
<>	144:ef7eb2e8f9f7	2361	if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
<>	144:ef7eb2e8f9f7	2362	{
<>	144:ef7eb2e8f9f7	2363	/* Disable differential mode (default mode: single-ended) */
<>	144:ef7eb2e8f9f7	2364	CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
<>	144:ef7eb2e8f9f7	2365	}
<>	144:ef7eb2e8f9f7	2366	else
<>	144:ef7eb2e8f9f7	2367	{
<>	144:ef7eb2e8f9f7	2368	/* Enable differential mode */
<>	144:ef7eb2e8f9f7	2369	SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
<>	144:ef7eb2e8f9f7	2370
<>	144:ef7eb2e8f9f7	2371	/* Sampling time configuration of channel ADC_IN+1 (negative input) */
<>	144:ef7eb2e8f9f7	2372	/* Clear the old sample time then set the new one for the selected */
AnnaBridge	167:e84263d55307	2373	/* channel. */
<>	144:ef7eb2e8f9f7	2374	/* Starting from channel 9, SMPR2 register must be configured */
<>	144:ef7eb2e8f9f7	2375	if (sConfig->Channel >= ADC_CHANNEL_9)
<>	144:ef7eb2e8f9f7	2376	{
AnnaBridge	167:e84263d55307	2377	ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);
<>	144:ef7eb2e8f9f7	2378	}
<>	144:ef7eb2e8f9f7	2379	else /* For channels 0 to 8, SMPR1 must be configured */
<>	144:ef7eb2e8f9f7	2380	{
AnnaBridge	167:e84263d55307	2381	ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);
<>	144:ef7eb2e8f9f7	2382	}
<>	144:ef7eb2e8f9f7	2383	}
<>	144:ef7eb2e8f9f7	2384
<>	144:ef7eb2e8f9f7	2385
<>	144:ef7eb2e8f9f7	2386
<>	144:ef7eb2e8f9f7	2387	/* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
<>	144:ef7eb2e8f9f7	2388	/* If internal channel selected, enable dedicated internal buffers and */
<>	144:ef7eb2e8f9f7	2389	/* paths. */
<>	144:ef7eb2e8f9f7	2390	/* Note: these internal measurement paths can be disabled using */
<>	144:ef7eb2e8f9f7	2391	/* HAL_ADC_DeInit(). */
<>	144:ef7eb2e8f9f7	2392
<>	144:ef7eb2e8f9f7	2393	/* Configuration of common ADC parameters */
<>	144:ef7eb2e8f9f7	2394	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	2395
<>	144:ef7eb2e8f9f7	2396
<>	144:ef7eb2e8f9f7	2397	/* If the requested internal measurement path has already been enabled, */
<>	144:ef7eb2e8f9f7	2398	/* bypass the configuration processing. */
<>	144:ef7eb2e8f9f7	2399	if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
<>	144:ef7eb2e8f9f7	2400	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) \|\|
<>	144:ef7eb2e8f9f7	2401	( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
<>	144:ef7eb2e8f9f7	2402	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) \|\|
<>	144:ef7eb2e8f9f7	2403	( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
<>	144:ef7eb2e8f9f7	2404	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
<>	144:ef7eb2e8f9f7	2405	)
<>	144:ef7eb2e8f9f7	2406	{
<>	144:ef7eb2e8f9f7	2407	/* Configuration of common ADC parameters (continuation) */
<>	144:ef7eb2e8f9f7	2408
<>	144:ef7eb2e8f9f7	2409	/* Software is allowed to change common parameters only when all ADCs */
<>	144:ef7eb2e8f9f7	2410	/* of the common group are disabled. */
<>	144:ef7eb2e8f9f7	2411	if ((ADC_IS_ENABLE(hadc) == RESET) &&
AnnaBridge	167:e84263d55307	2412	(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
<>	144:ef7eb2e8f9f7	2413	{
<>	144:ef7eb2e8f9f7	2414	if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
<>	144:ef7eb2e8f9f7	2415	{
<>	144:ef7eb2e8f9f7	2416	if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
<>	144:ef7eb2e8f9f7	2417	{
<>	144:ef7eb2e8f9f7	2418	SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
<>	144:ef7eb2e8f9f7	2419
<>	144:ef7eb2e8f9f7	2420	/* Delay for temperature sensor stabilization time */
<>	144:ef7eb2e8f9f7	2421	/* Wait loop initialization and execution */
<>	144:ef7eb2e8f9f7	2422	/* Note: Variable divided by 2 to compensate partially */
<>	144:ef7eb2e8f9f7	2423	/* CPU processing cycles. */
<>	144:ef7eb2e8f9f7	2424	wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / (1000000 * 2)));
<>	144:ef7eb2e8f9f7	2425	while(wait_loop_index != 0)
<>	144:ef7eb2e8f9f7	2426	{
<>	144:ef7eb2e8f9f7	2427	wait_loop_index--;
<>	144:ef7eb2e8f9f7	2428	}
<>	144:ef7eb2e8f9f7	2429	}
<>	144:ef7eb2e8f9f7	2430	}
<>	144:ef7eb2e8f9f7	2431	else if (sConfig->Channel == ADC_CHANNEL_VBAT)
<>	144:ef7eb2e8f9f7	2432	{
<>	144:ef7eb2e8f9f7	2433	if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
<>	144:ef7eb2e8f9f7	2434	{
<>	144:ef7eb2e8f9f7	2435	SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
<>	144:ef7eb2e8f9f7	2436	}
<>	144:ef7eb2e8f9f7	2437	}
<>	144:ef7eb2e8f9f7	2438	else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
<>	144:ef7eb2e8f9f7	2439	{
<>	144:ef7eb2e8f9f7	2440	if (ADC_VREFINT_INSTANCE(hadc))
<>	144:ef7eb2e8f9f7	2441	{
<>	144:ef7eb2e8f9f7	2442	SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
<>	144:ef7eb2e8f9f7	2443	}
<>	144:ef7eb2e8f9f7	2444	}
<>	144:ef7eb2e8f9f7	2445	}
<>	144:ef7eb2e8f9f7	2446	/* If the requested internal measurement path has already been */
<>	144:ef7eb2e8f9f7	2447	/* enabled and other ADC of the common group are enabled, internal */
<>	144:ef7eb2e8f9f7	2448	/* measurement paths cannot be enabled. */
<>	144:ef7eb2e8f9f7	2449	else
<>	144:ef7eb2e8f9f7	2450	{
<>	144:ef7eb2e8f9f7	2451	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2452	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	2453
AnnaBridge	167:e84263d55307	2454	tmp_hal_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	2455	}
<>	144:ef7eb2e8f9f7	2456	}
AnnaBridge	167:e84263d55307	2457
<>	144:ef7eb2e8f9f7	2458	} /* if (ADC_IS_ENABLE(hadc) == RESET) */
AnnaBridge	167:e84263d55307	2459
<>	144:ef7eb2e8f9f7	2460	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) */
<>	144:ef7eb2e8f9f7	2461
<>	144:ef7eb2e8f9f7	2462	/* If a conversion is on going on regular group, no update on regular */
<>	144:ef7eb2e8f9f7	2463	/* channel could be done on neither of the channel configuration structure */
<>	144:ef7eb2e8f9f7	2464	/* parameters. */
<>	144:ef7eb2e8f9f7	2465	else
<>	144:ef7eb2e8f9f7	2466	{
<>	144:ef7eb2e8f9f7	2467	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2468	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	2469
AnnaBridge	167:e84263d55307	2470	tmp_hal_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	2471	}
<>	144:ef7eb2e8f9f7	2472
<>	144:ef7eb2e8f9f7	2473	/* Process unlocked */
<>	144:ef7eb2e8f9f7	2474	__HAL_UNLOCK(hadc);
AnnaBridge	167:e84263d55307	2475
<>	144:ef7eb2e8f9f7	2476	/* Return function status */
AnnaBridge	167:e84263d55307	2477	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	2478	}
<>	144:ef7eb2e8f9f7	2479
<>	144:ef7eb2e8f9f7	2480	/**
<>	144:ef7eb2e8f9f7	2481	* @brief Configure the analog watchdog.
<>	144:ef7eb2e8f9f7	2482	* @note Possibility to update parameters on the fly:
<>	144:ef7eb2e8f9f7	2483	* This function initializes the selected analog watchdog, successive
<>	144:ef7eb2e8f9f7	2484	* calls to this function can be used to reconfigure some parameters
<>	144:ef7eb2e8f9f7	2485	* of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
AnnaBridge	167:e84263d55307	2486	* the ADC.
<>	144:ef7eb2e8f9f7	2487	* The setting of these parameters is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	2488	* For parameters constraints, see comments of structure
<>	144:ef7eb2e8f9f7	2489	* "ADC_AnalogWDGConfTypeDef".
AnnaBridge	167:e84263d55307	2490	* @note Analog watchdog thresholds can be modified while ADC conversion
AnnaBridge	167:e84263d55307	2491	* is on going.
AnnaBridge	167:e84263d55307	2492	* In this case, some constraints must be taken into account:
AnnaBridge	167:e84263d55307	2493	* the programmed threshold values are effective from the next
AnnaBridge	167:e84263d55307	2494	* ADC EOC (end of unitary conversion).
AnnaBridge	167:e84263d55307	2495	* Considering that registers write delay may happen due to
AnnaBridge	167:e84263d55307	2496	* bus activity, this might cause an uncertainty on the
AnnaBridge	167:e84263d55307	2497	* effective timing of the new programmed threshold values.
<>	144:ef7eb2e8f9f7	2498	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2499	* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
<>	144:ef7eb2e8f9f7	2500	* @retval HAL status
<>	144:ef7eb2e8f9f7	2501	*/
<>	144:ef7eb2e8f9f7	2502	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
<>	144:ef7eb2e8f9f7	2503	{
AnnaBridge	167:e84263d55307	2504	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	2505
<>	144:ef7eb2e8f9f7	2506	uint32_t tmpAWDHighThresholdShifted;
<>	144:ef7eb2e8f9f7	2507	uint32_t tmpAWDLowThresholdShifted;
<>	144:ef7eb2e8f9f7	2508
<>	144:ef7eb2e8f9f7	2509	uint32_t tmpADCFlagAWD2orAWD3;
<>	144:ef7eb2e8f9f7	2510	uint32_t tmpADCITAWD2orAWD3;
<>	144:ef7eb2e8f9f7	2511
<>	144:ef7eb2e8f9f7	2512	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2513	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	2514	assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
<>	144:ef7eb2e8f9f7	2515	assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
<>	144:ef7eb2e8f9f7	2516	assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
<>	144:ef7eb2e8f9f7	2517
<>	144:ef7eb2e8f9f7	2518	if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\|
<>	144:ef7eb2e8f9f7	2519	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\|
<>	144:ef7eb2e8f9f7	2520	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
<>	144:ef7eb2e8f9f7	2521	{
<>	144:ef7eb2e8f9f7	2522	assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
<>	144:ef7eb2e8f9f7	2523	}
<>	144:ef7eb2e8f9f7	2524
<>	144:ef7eb2e8f9f7	2525	/* Verify if threshold is within the selected ADC resolution */
<>	144:ef7eb2e8f9f7	2526	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
<>	144:ef7eb2e8f9f7	2527	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
<>	144:ef7eb2e8f9f7	2528
<>	144:ef7eb2e8f9f7	2529	/* Process locked */
<>	144:ef7eb2e8f9f7	2530	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	2531
<>	144:ef7eb2e8f9f7	2532	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	2533	/* Parameters that can be updated when ADC is disabled or enabled without */
<>	144:ef7eb2e8f9f7	2534	/* conversion on going on regular and injected groups: */
<>	144:ef7eb2e8f9f7	2535	/* - Analog watchdog channels */
<>	144:ef7eb2e8f9f7	2536	/* - Analog watchdog thresholds */
<>	144:ef7eb2e8f9f7	2537	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2538	{
AnnaBridge	167:e84263d55307	2539
<>	144:ef7eb2e8f9f7	2540	/* Analog watchdogs configuration */
<>	144:ef7eb2e8f9f7	2541	if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
<>	144:ef7eb2e8f9f7	2542	{
<>	144:ef7eb2e8f9f7	2543	/* Configuration of analog watchdog: */
<>	144:ef7eb2e8f9f7	2544	/* - Set the analog watchdog enable mode: regular and/or injected */
<>	144:ef7eb2e8f9f7	2545	/* groups, one or overall group of channels. */
<>	144:ef7eb2e8f9f7	2546	/* - Set the Analog watchdog channel (is not used if watchdog */
<>	144:ef7eb2e8f9f7	2547	/* mode "all channels": ADC_CFGR_AWD1SGL=0). */
<>	144:ef7eb2e8f9f7	2548	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_WD_FIELDS,
<>	144:ef7eb2e8f9f7	2549	AnalogWDGConfig->WatchdogMode \| ADC_CFGR_SET_AWD1CH(AnalogWDGConfig->Channel) );
<>	144:ef7eb2e8f9f7	2550
<>	144:ef7eb2e8f9f7	2551	/* Shift the offset with respect to the selected ADC resolution: */
<>	144:ef7eb2e8f9f7	2552	/* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
<>	144:ef7eb2e8f9f7	2553	/* are set to 0 */
<>	144:ef7eb2e8f9f7	2554	tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
<>	144:ef7eb2e8f9f7	2555	tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
<>	144:ef7eb2e8f9f7	2556
AnnaBridge	167:e84263d55307	2557	/* Set the high and low thresholds */
AnnaBridge	167:e84263d55307	2558	MODIFY_REG(hadc->Instance->TR1,
AnnaBridge	167:e84263d55307	2559	ADC_TR1_HT1 \| ADC_TR1_LT1,
AnnaBridge	167:e84263d55307	2560	ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) \| tmpAWDLowThresholdShifted );
<>	144:ef7eb2e8f9f7	2561
AnnaBridge	167:e84263d55307	2562	/* Clear the ADC Analog watchdog flag (in case of left enabled by */
AnnaBridge	167:e84263d55307	2563	/* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
AnnaBridge	167:e84263d55307	2564	/* or HAL_ADC_PollForEvent(). */
<>	144:ef7eb2e8f9f7	2565	__HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
<>	144:ef7eb2e8f9f7	2566
<>	144:ef7eb2e8f9f7	2567	/* Configure ADC Analog watchdog interrupt */
<>	144:ef7eb2e8f9f7	2568	if(AnalogWDGConfig->ITMode == ENABLE)
<>	144:ef7eb2e8f9f7	2569	{
<>	144:ef7eb2e8f9f7	2570	/* Enable the ADC Analog watchdog interrupt */
<>	144:ef7eb2e8f9f7	2571	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
<>	144:ef7eb2e8f9f7	2572	}
<>	144:ef7eb2e8f9f7	2573	else
<>	144:ef7eb2e8f9f7	2574	{
<>	144:ef7eb2e8f9f7	2575	/* Disable the ADC Analog watchdog interrupt */
<>	144:ef7eb2e8f9f7	2576	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
<>	144:ef7eb2e8f9f7	2577	}
<>	144:ef7eb2e8f9f7	2578
<>	144:ef7eb2e8f9f7	2579	/* Update state, clear previous result related to AWD1 */
<>	144:ef7eb2e8f9f7	2580	CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<>	144:ef7eb2e8f9f7	2581	}
<>	144:ef7eb2e8f9f7	2582	/* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
<>	144:ef7eb2e8f9f7	2583	else
<>	144:ef7eb2e8f9f7	2584	{
<>	144:ef7eb2e8f9f7	2585	/* Shift the threshold with respect to the selected ADC resolution */
<>	144:ef7eb2e8f9f7	2586	/* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
<>	144:ef7eb2e8f9f7	2587	tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
<>	144:ef7eb2e8f9f7	2588	tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
<>	144:ef7eb2e8f9f7	2589
<>	144:ef7eb2e8f9f7	2590	if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
<>	144:ef7eb2e8f9f7	2591	{
<>	144:ef7eb2e8f9f7	2592	/* Set the Analog watchdog channel or group of channels. This also */
<>	144:ef7eb2e8f9f7	2593	/* enables the watchdog. */
AnnaBridge	167:e84263d55307	2594	/* Note: Conditional register reset, because several channels can be */
<>	144:ef7eb2e8f9f7	2595	/* set by successive calls of this function. */
AnnaBridge	167:e84263d55307	2596	if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
<>	144:ef7eb2e8f9f7	2597	{
<>	144:ef7eb2e8f9f7	2598	SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
<>	144:ef7eb2e8f9f7	2599	}
<>	144:ef7eb2e8f9f7	2600	else
<>	144:ef7eb2e8f9f7	2601	{
AnnaBridge	167:e84263d55307	2602	CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
<>	144:ef7eb2e8f9f7	2603	}
<>	144:ef7eb2e8f9f7	2604
<>	144:ef7eb2e8f9f7	2605	/* Set the high and low thresholds */
<>	144:ef7eb2e8f9f7	2606	MODIFY_REG(hadc->Instance->TR2, ADC_TR2_HT2 \| ADC_TR2_LT2,
AnnaBridge	167:e84263d55307	2607	ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) \| tmpAWDLowThresholdShifted );
<>	144:ef7eb2e8f9f7	2608
<>	144:ef7eb2e8f9f7	2609	/* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
<>	144:ef7eb2e8f9f7	2610	/* settings. */
<>	144:ef7eb2e8f9f7	2611	tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
<>	144:ef7eb2e8f9f7	2612	tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
<>	144:ef7eb2e8f9f7	2613
<>	144:ef7eb2e8f9f7	2614	/* Update state, clear previous result related to AWD2 */
<>	144:ef7eb2e8f9f7	2615	CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
<>	144:ef7eb2e8f9f7	2616	}
<>	144:ef7eb2e8f9f7	2617	/* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
<>	144:ef7eb2e8f9f7	2618	else
<>	144:ef7eb2e8f9f7	2619	{
<>	144:ef7eb2e8f9f7	2620	/* Set the Analog watchdog channel or group of channels. This also */
<>	144:ef7eb2e8f9f7	2621	/* enables the watchdog. */
<>	144:ef7eb2e8f9f7	2622	/* Note: Conditional register reset, because several channels can be */
<>	144:ef7eb2e8f9f7	2623	/* set by successive calls of this function. */
<>	144:ef7eb2e8f9f7	2624	if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
<>	144:ef7eb2e8f9f7	2625	{
<>	144:ef7eb2e8f9f7	2626	SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
<>	144:ef7eb2e8f9f7	2627	}
<>	144:ef7eb2e8f9f7	2628	else
<>	144:ef7eb2e8f9f7	2629	{
AnnaBridge	167:e84263d55307	2630	CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
<>	144:ef7eb2e8f9f7	2631	}
<>	144:ef7eb2e8f9f7	2632
<>	144:ef7eb2e8f9f7	2633	/* Set the high and low thresholds */
<>	144:ef7eb2e8f9f7	2634	MODIFY_REG(hadc->Instance->TR3, ADC_TR3_HT3 \| ADC_TR3_LT3,
AnnaBridge	167:e84263d55307	2635	ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) \| tmpAWDLowThresholdShifted );
<>	144:ef7eb2e8f9f7	2636
<>	144:ef7eb2e8f9f7	2637	/* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
<>	144:ef7eb2e8f9f7	2638	/* settings. */
<>	144:ef7eb2e8f9f7	2639	tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
<>	144:ef7eb2e8f9f7	2640	tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
<>	144:ef7eb2e8f9f7	2641
<>	144:ef7eb2e8f9f7	2642	/* Update state, clear previous result related to AWD3 */
<>	144:ef7eb2e8f9f7	2643	CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
<>	144:ef7eb2e8f9f7	2644	}
AnnaBridge	167:e84263d55307	2645
<>	144:ef7eb2e8f9f7	2646	/* Clear the ADC Analog watchdog flag (in case left enabled by */
<>	144:ef7eb2e8f9f7	2647	/* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
<>	144:ef7eb2e8f9f7	2648	/* or HAL_ADC_PollForEvent(). */
<>	144:ef7eb2e8f9f7	2649	__HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
<>	144:ef7eb2e8f9f7	2650
<>	144:ef7eb2e8f9f7	2651	/* Configure ADC Analog watchdog interrupt */
<>	144:ef7eb2e8f9f7	2652	if(AnalogWDGConfig->ITMode == ENABLE)
<>	144:ef7eb2e8f9f7	2653	{
<>	144:ef7eb2e8f9f7	2654	__HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
<>	144:ef7eb2e8f9f7	2655	}
<>	144:ef7eb2e8f9f7	2656	else
<>	144:ef7eb2e8f9f7	2657	{
<>	144:ef7eb2e8f9f7	2658	__HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
<>	144:ef7eb2e8f9f7	2659	}
<>	144:ef7eb2e8f9f7	2660	}
AnnaBridge	167:e84263d55307	2661
<>	144:ef7eb2e8f9f7	2662	}
<>	144:ef7eb2e8f9f7	2663	/* If a conversion is on going on regular or injected groups, no update */
<>	144:ef7eb2e8f9f7	2664	/* could be done on neither of the AWD configuration structure parameters. */
<>	144:ef7eb2e8f9f7	2665	else
<>	144:ef7eb2e8f9f7	2666	{
<>	144:ef7eb2e8f9f7	2667	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2668	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	2669
AnnaBridge	167:e84263d55307	2670	tmp_hal_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	2671	}
<>	144:ef7eb2e8f9f7	2672
<>	144:ef7eb2e8f9f7	2673	/* Process unlocked */
<>	144:ef7eb2e8f9f7	2674	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	2675
<>	144:ef7eb2e8f9f7	2676	/* Return function status */
AnnaBridge	167:e84263d55307	2677	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	2678	}
<>	144:ef7eb2e8f9f7	2679
<>	144:ef7eb2e8f9f7	2680
<>	144:ef7eb2e8f9f7	2681	/**
<>	144:ef7eb2e8f9f7	2682	* @}
<>	144:ef7eb2e8f9f7	2683	*/
<>	144:ef7eb2e8f9f7	2684
<>	144:ef7eb2e8f9f7	2685	/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
AnnaBridge	167:e84263d55307	2686	* @brief ADC Peripheral State functions
<>	144:ef7eb2e8f9f7	2687	*
AnnaBridge	167:e84263d55307	2688	@verbatim
<>	144:ef7eb2e8f9f7	2689	===============================================================================
<>	144:ef7eb2e8f9f7	2690	##### Peripheral state and errors functions #####
<>	144:ef7eb2e8f9f7	2691	===============================================================================
<>	144:ef7eb2e8f9f7	2692	[..]
<>	144:ef7eb2e8f9f7	2693	This subsection provides functions to get in run-time the status of the
<>	144:ef7eb2e8f9f7	2694	peripheral.
<>	144:ef7eb2e8f9f7	2695	(+) Check the ADC state
<>	144:ef7eb2e8f9f7	2696	(+) Check the ADC error code
AnnaBridge	167:e84263d55307	2697
<>	144:ef7eb2e8f9f7	2698	@endverbatim
<>	144:ef7eb2e8f9f7	2699	* @{
<>	144:ef7eb2e8f9f7	2700	*/
AnnaBridge	167:e84263d55307	2701
<>	144:ef7eb2e8f9f7	2702	/**
<>	144:ef7eb2e8f9f7	2703	* @brief Return the ADC handle state.
AnnaBridge	167:e84263d55307	2704	* @note ADC state machine is managed by bitfields, ADC status must be
AnnaBridge	167:e84263d55307	2705	* compared with states bits.
AnnaBridge	167:e84263d55307	2706	* For example:
AnnaBridge	167:e84263d55307	2707	* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
AnnaBridge	167:e84263d55307	2708	* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
<>	144:ef7eb2e8f9f7	2709	* @param hadc: ADC handle
AnnaBridge	167:e84263d55307	2710	* @retval ADC handle state (bitfield on 32 bits)
<>	144:ef7eb2e8f9f7	2711	*/
<>	144:ef7eb2e8f9f7	2712	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	2713	{
<>	144:ef7eb2e8f9f7	2714	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2715	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	2716
<>	144:ef7eb2e8f9f7	2717	/* Return ADC handle state */
<>	144:ef7eb2e8f9f7	2718	return hadc->State;
<>	144:ef7eb2e8f9f7	2719	}
<>	144:ef7eb2e8f9f7	2720
<>	144:ef7eb2e8f9f7	2721	/**
<>	144:ef7eb2e8f9f7	2722	* @brief Return the ADC error code.
<>	144:ef7eb2e8f9f7	2723	* @param hadc: ADC handle
AnnaBridge	167:e84263d55307	2724	* @retval ADC error code (bitfield on 32 bits)
<>	144:ef7eb2e8f9f7	2725	*/
<>	144:ef7eb2e8f9f7	2726	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
<>	144:ef7eb2e8f9f7	2727	{
<>	144:ef7eb2e8f9f7	2728	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2729	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	2730
<>	144:ef7eb2e8f9f7	2731	return hadc->ErrorCode;
<>	144:ef7eb2e8f9f7	2732	}
<>	144:ef7eb2e8f9f7	2733
<>	144:ef7eb2e8f9f7	2734	/**
<>	144:ef7eb2e8f9f7	2735	* @}
<>	144:ef7eb2e8f9f7	2736	*/
<>	144:ef7eb2e8f9f7	2737
<>	144:ef7eb2e8f9f7	2738	/**
<>	144:ef7eb2e8f9f7	2739	* @}
<>	144:ef7eb2e8f9f7	2740	*/
<>	144:ef7eb2e8f9f7	2741
<>	144:ef7eb2e8f9f7	2742	/** @defgroup ADC_Private_Functions ADC Private Functions
<>	144:ef7eb2e8f9f7	2743	* @{
<>	144:ef7eb2e8f9f7	2744	*/
<>	144:ef7eb2e8f9f7	2745
<>	144:ef7eb2e8f9f7	2746	/**
<>	144:ef7eb2e8f9f7	2747	* @brief Stop ADC conversion.
<>	144:ef7eb2e8f9f7	2748	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2749	* @param ConversionGroup: ADC group regular and/or injected.
<>	144:ef7eb2e8f9f7	2750	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2751	* @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
<>	144:ef7eb2e8f9f7	2752	* @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
<>	144:ef7eb2e8f9f7	2753	* @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
<>	144:ef7eb2e8f9f7	2754	* @retval HAL status.
<>	144:ef7eb2e8f9f7	2755	*/
<>	144:ef7eb2e8f9f7	2756	HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
<>	144:ef7eb2e8f9f7	2757	{
<>	144:ef7eb2e8f9f7	2758	uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
<>	144:ef7eb2e8f9f7	2759	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	2760	uint32_t Conversion_Timeout_CPU_cycles = 0;
<>	144:ef7eb2e8f9f7	2761
<>	144:ef7eb2e8f9f7	2762	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2763	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	2764	assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
<>	144:ef7eb2e8f9f7	2765
<>	144:ef7eb2e8f9f7	2766	/* Verification if ADC is not already stopped (on regular and injected */
<>	144:ef7eb2e8f9f7	2767	/* groups) to bypass this function if not needed. */
<>	144:ef7eb2e8f9f7	2768	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
<>	144:ef7eb2e8f9f7	2769	{
<>	144:ef7eb2e8f9f7	2770	/* Particular case of continuous auto-injection mode combined with */
<>	144:ef7eb2e8f9f7	2771	/* auto-delay mode. */
<>	144:ef7eb2e8f9f7	2772	/* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
<>	144:ef7eb2e8f9f7	2773	/* injected group stop ADC_CR_JADSTP). */
<>	144:ef7eb2e8f9f7	2774	/* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
<>	144:ef7eb2e8f9f7	2775	/* (see reference manual). */
<>	144:ef7eb2e8f9f7	2776	if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
<>	144:ef7eb2e8f9f7	2777	&& (hadc->Init.ContinuousConvMode==ENABLE)
<>	144:ef7eb2e8f9f7	2778	&& (hadc->Init.LowPowerAutoWait==ENABLE))
<>	144:ef7eb2e8f9f7	2779	{
<>	144:ef7eb2e8f9f7	2780	/* Use stop of regular group */
<>	144:ef7eb2e8f9f7	2781	ConversionGroup = ADC_REGULAR_GROUP;
<>	144:ef7eb2e8f9f7	2782
<>	144:ef7eb2e8f9f7	2783	/* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
<>	144:ef7eb2e8f9f7	2784	while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
<>	144:ef7eb2e8f9f7	2785	{
<>	144:ef7eb2e8f9f7	2786	if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
<>	144:ef7eb2e8f9f7	2787	{
<>	144:ef7eb2e8f9f7	2788	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2789	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2790
<>	144:ef7eb2e8f9f7	2791	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2792	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2793
<>	144:ef7eb2e8f9f7	2794	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2795	}
<>	144:ef7eb2e8f9f7	2796	Conversion_Timeout_CPU_cycles ++;
<>	144:ef7eb2e8f9f7	2797	}
AnnaBridge	167:e84263d55307	2798
<>	144:ef7eb2e8f9f7	2799	/* Clear JEOS */
<>	144:ef7eb2e8f9f7	2800	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
<>	144:ef7eb2e8f9f7	2801	}
<>	144:ef7eb2e8f9f7	2802
<>	144:ef7eb2e8f9f7	2803	/* Stop potential conversion on going on regular group */
<>	144:ef7eb2e8f9f7	2804	if (ConversionGroup != ADC_INJECTED_GROUP)
<>	144:ef7eb2e8f9f7	2805	{
<>	144:ef7eb2e8f9f7	2806	/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
<>	144:ef7eb2e8f9f7	2807	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
<>	144:ef7eb2e8f9f7	2808	HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
<>	144:ef7eb2e8f9f7	2809	{
<>	144:ef7eb2e8f9f7	2810	/* Stop conversions on regular group */
<>	144:ef7eb2e8f9f7	2811	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTP);
<>	144:ef7eb2e8f9f7	2812	}
<>	144:ef7eb2e8f9f7	2813	}
AnnaBridge	167:e84263d55307	2814
<>	144:ef7eb2e8f9f7	2815	/* Stop potential conversion on going on injected group */
<>	144:ef7eb2e8f9f7	2816	if (ConversionGroup != ADC_REGULAR_GROUP)
<>	144:ef7eb2e8f9f7	2817	{
<>	144:ef7eb2e8f9f7	2818	/* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
<>	144:ef7eb2e8f9f7	2819	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
<>	144:ef7eb2e8f9f7	2820	HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
<>	144:ef7eb2e8f9f7	2821	{
<>	144:ef7eb2e8f9f7	2822	/* Stop conversions on injected group */
<>	144:ef7eb2e8f9f7	2823	SET_BIT(hadc->Instance->CR, ADC_CR_JADSTP);
<>	144:ef7eb2e8f9f7	2824	}
<>	144:ef7eb2e8f9f7	2825	}
AnnaBridge	167:e84263d55307	2826
<>	144:ef7eb2e8f9f7	2827	/* Selection of start and stop bits with respect to the regular or injected group */
<>	144:ef7eb2e8f9f7	2828	switch(ConversionGroup)
<>	144:ef7eb2e8f9f7	2829	{
<>	144:ef7eb2e8f9f7	2830	case ADC_REGULAR_INJECTED_GROUP:
<>	144:ef7eb2e8f9f7	2831	tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART \| ADC_CR_JADSTART);
<>	144:ef7eb2e8f9f7	2832	break;
<>	144:ef7eb2e8f9f7	2833	case ADC_INJECTED_GROUP:
<>	144:ef7eb2e8f9f7	2834	tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
<>	144:ef7eb2e8f9f7	2835	break;
<>	144:ef7eb2e8f9f7	2836	/* Case ADC_REGULAR_GROUP only*/
<>	144:ef7eb2e8f9f7	2837	default:
<>	144:ef7eb2e8f9f7	2838	tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
<>	144:ef7eb2e8f9f7	2839	break;
<>	144:ef7eb2e8f9f7	2840	}
<>	144:ef7eb2e8f9f7	2841
<>	144:ef7eb2e8f9f7	2842	/* Wait for conversion effectively stopped */
AnnaBridge	167:e84263d55307	2843
<>	144:ef7eb2e8f9f7	2844
<>	144:ef7eb2e8f9f7	2845	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2846
<>	144:ef7eb2e8f9f7	2847	while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
<>	144:ef7eb2e8f9f7	2848	{
<>	144:ef7eb2e8f9f7	2849	if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
<>	144:ef7eb2e8f9f7	2850	{
<>	144:ef7eb2e8f9f7	2851	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2852	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2853
<>	144:ef7eb2e8f9f7	2854	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2855	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2856
<>	144:ef7eb2e8f9f7	2857	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2858	}
<>	144:ef7eb2e8f9f7	2859	}
<>	144:ef7eb2e8f9f7	2860
<>	144:ef7eb2e8f9f7	2861	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) */
AnnaBridge	167:e84263d55307	2862
<>	144:ef7eb2e8f9f7	2863	/* Return HAL status */
<>	144:ef7eb2e8f9f7	2864	return HAL_OK;
<>	144:ef7eb2e8f9f7	2865	}
<>	144:ef7eb2e8f9f7	2866
<>	144:ef7eb2e8f9f7	2867
<>	144:ef7eb2e8f9f7	2868
<>	144:ef7eb2e8f9f7	2869	/**
<>	144:ef7eb2e8f9f7	2870	* @brief Enable the selected ADC.
<>	144:ef7eb2e8f9f7	2871	* @note Prerequisite condition to use this function: ADC must be disabled
<>	144:ef7eb2e8f9f7	2872	* and voltage regulator must be enabled (done into HAL_ADC_Init()).
<>	144:ef7eb2e8f9f7	2873	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2874	* @retval HAL status.
<>	144:ef7eb2e8f9f7	2875	*/
<>	144:ef7eb2e8f9f7	2876	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	2877	{
<>	144:ef7eb2e8f9f7	2878	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	2879
<>	144:ef7eb2e8f9f7	2880	/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
AnnaBridge	167:e84263d55307	2881	/* enabling phase not yet completed: flag ADC ready not yet set). */
AnnaBridge	167:e84263d55307	2882	/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
<>	144:ef7eb2e8f9f7	2883	/* causes: ADC clock not running, ...). */
<>	144:ef7eb2e8f9f7	2884	if (ADC_IS_ENABLE(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2885	{
<>	144:ef7eb2e8f9f7	2886	/* Check if conditions to enable the ADC are fulfilled */
<>	144:ef7eb2e8f9f7	2887	if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2888	{
<>	144:ef7eb2e8f9f7	2889	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2890	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2891
<>	144:ef7eb2e8f9f7	2892	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2893	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2894
<>	144:ef7eb2e8f9f7	2895	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2896	}
<>	144:ef7eb2e8f9f7	2897
<>	144:ef7eb2e8f9f7	2898	/* Enable the ADC peripheral */
<>	144:ef7eb2e8f9f7	2899	ADC_ENABLE(hadc);
<>	144:ef7eb2e8f9f7	2900
<>	144:ef7eb2e8f9f7	2901
<>	144:ef7eb2e8f9f7	2902	/* Wait for ADC effectively enabled */
<>	144:ef7eb2e8f9f7	2903	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2904
<>	144:ef7eb2e8f9f7	2905	while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
<>	144:ef7eb2e8f9f7	2906	{
<>	144:ef7eb2e8f9f7	2907	/* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
<>	144:ef7eb2e8f9f7	2908	has been cleared (after a calibration), ADEN bit is reset by the
<>	144:ef7eb2e8f9f7	2909	calibration logic.
<>	144:ef7eb2e8f9f7	2910	The workaround is to continue setting ADEN until ADRDY is becomes 1.
<>	144:ef7eb2e8f9f7	2911	Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
<>	144:ef7eb2e8f9f7	2912	4 ADC clock cycle duration */
<>	144:ef7eb2e8f9f7	2913	ADC_ENABLE(hadc);
<>	144:ef7eb2e8f9f7	2914
<>	144:ef7eb2e8f9f7	2915	if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
<>	144:ef7eb2e8f9f7	2916	{
<>	144:ef7eb2e8f9f7	2917	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2918	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2919
<>	144:ef7eb2e8f9f7	2920	/* Set ADC error code to ADC IP internal error */
AnnaBridge	167:e84263d55307	2921	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2922
<>	144:ef7eb2e8f9f7	2923	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2924	}
AnnaBridge	167:e84263d55307	2925	}
<>	144:ef7eb2e8f9f7	2926	}
<>	144:ef7eb2e8f9f7	2927
<>	144:ef7eb2e8f9f7	2928	/* Return HAL status */
<>	144:ef7eb2e8f9f7	2929	return HAL_OK;
<>	144:ef7eb2e8f9f7	2930	}
<>	144:ef7eb2e8f9f7	2931
<>	144:ef7eb2e8f9f7	2932	/**
<>	144:ef7eb2e8f9f7	2933	* @brief Disable the selected ADC.
<>	144:ef7eb2e8f9f7	2934	* @note Prerequisite condition to use this function: ADC conversions must be
<>	144:ef7eb2e8f9f7	2935	* stopped.
<>	144:ef7eb2e8f9f7	2936	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2937	* @retval HAL status.
<>	144:ef7eb2e8f9f7	2938	*/
<>	144:ef7eb2e8f9f7	2939	HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	2940	{
<>	144:ef7eb2e8f9f7	2941	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	2942
<>	144:ef7eb2e8f9f7	2943	/* Verification if ADC is not already disabled: */
<>	144:ef7eb2e8f9f7	2944	/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
AnnaBridge	167:e84263d55307	2945	/* disabled. */
AnnaBridge	167:e84263d55307	2946	if (ADC_IS_ENABLE(hadc) != RESET)
<>	144:ef7eb2e8f9f7	2947	{
<>	144:ef7eb2e8f9f7	2948	/* Check if conditions to disable the ADC are fulfilled */
<>	144:ef7eb2e8f9f7	2949	if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
<>	144:ef7eb2e8f9f7	2950	{
<>	144:ef7eb2e8f9f7	2951	/* Disable the ADC peripheral */
<>	144:ef7eb2e8f9f7	2952	ADC_DISABLE(hadc);
<>	144:ef7eb2e8f9f7	2953	}
<>	144:ef7eb2e8f9f7	2954	else
<>	144:ef7eb2e8f9f7	2955	{
<>	144:ef7eb2e8f9f7	2956	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2957	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2958
<>	144:ef7eb2e8f9f7	2959	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2960	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2961
<>	144:ef7eb2e8f9f7	2962	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2963	}
<>	144:ef7eb2e8f9f7	2964
<>	144:ef7eb2e8f9f7	2965	/* Wait for ADC effectively disabled */
AnnaBridge	167:e84263d55307	2966	/* Get tick count */
<>	144:ef7eb2e8f9f7	2967	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2968
<>	144:ef7eb2e8f9f7	2969	while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
<>	144:ef7eb2e8f9f7	2970	{
AnnaBridge	167:e84263d55307	2971	if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
AnnaBridge	167:e84263d55307	2972	{
<>	144:ef7eb2e8f9f7	2973	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2974	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2975
<>	144:ef7eb2e8f9f7	2976	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2977	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2978
<>	144:ef7eb2e8f9f7	2979	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2980	}
<>	144:ef7eb2e8f9f7	2981	}
<>	144:ef7eb2e8f9f7	2982	}
<>	144:ef7eb2e8f9f7	2983
<>	144:ef7eb2e8f9f7	2984	/* Return HAL status */
<>	144:ef7eb2e8f9f7	2985	return HAL_OK;
<>	144:ef7eb2e8f9f7	2986	}
<>	144:ef7eb2e8f9f7	2987
<>	144:ef7eb2e8f9f7	2988	/**
<>	144:ef7eb2e8f9f7	2989	* @brief DMA transfer complete callback.
<>	144:ef7eb2e8f9f7	2990	* @param hdma: pointer to DMA handle.
<>	144:ef7eb2e8f9f7	2991	* @retval None
<>	144:ef7eb2e8f9f7	2992	*/
<>	144:ef7eb2e8f9f7	2993	void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2994	{
<>	144:ef7eb2e8f9f7	2995	/* Retrieve ADC handle corresponding to current DMA handle */
<>	144:ef7eb2e8f9f7	2996	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge	167:e84263d55307	2997
<>	144:ef7eb2e8f9f7	2998	/* Update state machine on conversion status if not in error state */
<>	144:ef7eb2e8f9f7	2999	if (HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL\|HAL_ADC_STATE_ERROR_DMA)))
<>	144:ef7eb2e8f9f7	3000	{
<>	144:ef7eb2e8f9f7	3001	/* Update ADC state machine */
<>	144:ef7eb2e8f9f7	3002	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<>	144:ef7eb2e8f9f7	3003	/* Is it the end of the regular sequence ? */
<>	144:ef7eb2e8f9f7	3004	if (HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS))
<>	144:ef7eb2e8f9f7	3005	{
<>	144:ef7eb2e8f9f7	3006	/* Are conversions software-triggered ? */
<>	144:ef7eb2e8f9f7	3007	if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
<>	144:ef7eb2e8f9f7	3008	{
<>	144:ef7eb2e8f9f7	3009	/* Is CONT bit set ? */
<>	144:ef7eb2e8f9f7	3010	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET)
<>	144:ef7eb2e8f9f7	3011	{
<>	144:ef7eb2e8f9f7	3012	/* CONT bit is not set, no more conversions expected */
<>	144:ef7eb2e8f9f7	3013	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	3014	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	3015	{
<>	144:ef7eb2e8f9f7	3016	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	3017	}
<>	144:ef7eb2e8f9f7	3018	}
<>	144:ef7eb2e8f9f7	3019	}
<>	144:ef7eb2e8f9f7	3020	}
<>	144:ef7eb2e8f9f7	3021	else
<>	144:ef7eb2e8f9f7	3022	{
<>	144:ef7eb2e8f9f7	3023	/* DMA End of Transfer interrupt was triggered but conversions sequence
<>	144:ef7eb2e8f9f7	3024	is not over. If DMACFG is set to 0, conversions are stopped. */
<>	144:ef7eb2e8f9f7	3025	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET)
<>	144:ef7eb2e8f9f7	3026	{
<>	144:ef7eb2e8f9f7	3027	/* DMACFG bit is not set, conversions are stopped. */
<>	144:ef7eb2e8f9f7	3028	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	3029	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	3030	{
<>	144:ef7eb2e8f9f7	3031	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	3032	}
<>	144:ef7eb2e8f9f7	3033	}
<>	144:ef7eb2e8f9f7	3034	}
<>	144:ef7eb2e8f9f7	3035
<>	144:ef7eb2e8f9f7	3036	/* Conversion complete callback */
AnnaBridge	167:e84263d55307	3037	HAL_ADC_ConvCpltCallback(hadc);
<>	144:ef7eb2e8f9f7	3038	}
<>	144:ef7eb2e8f9f7	3039	else /* DMA or internal error occurred (or both) */
<>	144:ef7eb2e8f9f7	3040	{
<>	144:ef7eb2e8f9f7	3041	/* In case of internal error, */
<>	144:ef7eb2e8f9f7	3042	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<>	144:ef7eb2e8f9f7	3043	{
<>	144:ef7eb2e8f9f7	3044	/* call Error Callback function */
<>	144:ef7eb2e8f9f7	3045	HAL_ADC_ErrorCallback(hadc);
<>	144:ef7eb2e8f9f7	3046	}
<>	144:ef7eb2e8f9f7	3047	}
<>	144:ef7eb2e8f9f7	3048	}
<>	144:ef7eb2e8f9f7	3049
<>	144:ef7eb2e8f9f7	3050	/**
<>	144:ef7eb2e8f9f7	3051	* @brief DMA half transfer complete callback.
<>	144:ef7eb2e8f9f7	3052	* @param hdma: pointer to DMA handle.
<>	144:ef7eb2e8f9f7	3053	* @retval None
<>	144:ef7eb2e8f9f7	3054	*/
AnnaBridge	167:e84263d55307	3055	void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	3056	{
<>	144:ef7eb2e8f9f7	3057	/* Retrieve ADC handle corresponding to current DMA handle */
<>	144:ef7eb2e8f9f7	3058	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	3059
<>	144:ef7eb2e8f9f7	3060	/* Half conversion callback */
<>	144:ef7eb2e8f9f7	3061	HAL_ADC_ConvHalfCpltCallback(hadc);
<>	144:ef7eb2e8f9f7	3062	}
<>	144:ef7eb2e8f9f7	3063
<>	144:ef7eb2e8f9f7	3064	/**
<>	144:ef7eb2e8f9f7	3065	* @brief DMA error callback.
<>	144:ef7eb2e8f9f7	3066	* @param hdma: pointer to DMA handle.
<>	144:ef7eb2e8f9f7	3067	* @retval None
<>	144:ef7eb2e8f9f7	3068	*/
AnnaBridge	167:e84263d55307	3069	void ADC_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	3070	{
<>	144:ef7eb2e8f9f7	3071	/* Retrieve ADC handle corresponding to current DMA handle */
<>	144:ef7eb2e8f9f7	3072	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	3073
AnnaBridge	167:e84263d55307	3074	/* Set ADC state */
<>	144:ef7eb2e8f9f7	3075	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<>	144:ef7eb2e8f9f7	3076
<>	144:ef7eb2e8f9f7	3077	/* Set ADC error code to DMA error */
<>	144:ef7eb2e8f9f7	3078	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
<>	144:ef7eb2e8f9f7	3079
<>	144:ef7eb2e8f9f7	3080	/* Error callback */
<>	144:ef7eb2e8f9f7	3081	HAL_ADC_ErrorCallback(hadc);
<>	144:ef7eb2e8f9f7	3082	}
<>	144:ef7eb2e8f9f7	3083
AnnaBridge	167:e84263d55307	3084	/**
AnnaBridge	167:e84263d55307	3085	* @}
AnnaBridge	167:e84263d55307	3086	*/
AnnaBridge	167:e84263d55307	3087
AnnaBridge	167:e84263d55307	3088	#endif /* HAL_ADC_MODULE_ENABLED */
AnnaBridge	167:e84263d55307	3089	/**
AnnaBridge	167:e84263d55307	3090	* @}
AnnaBridge	167:e84263d55307	3091	*/
<>	144:ef7eb2e8f9f7	3092
<>	144:ef7eb2e8f9f7	3093	/**
<>	144:ef7eb2e8f9f7	3094	* @}
<>	144:ef7eb2e8f9f7	3095	*/
<>	144:ef7eb2e8f9f7	3096
<>	144:ef7eb2e8f9f7	3097	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	11 Feb 2018
Imports:	0
Forks:	0
Commits:	182
Dependents:	0
Dependencies:	0
Followers:	1

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c@181:96ed750bd169, 2018-01-17 (annotated)

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