Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c@181:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
181:96ed750bd169
Parent:
149:156823d33999 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "device.h"
<> 144:ef7eb2e8f9f7 35 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 36 #include "ioman_regs.h"
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /*
<> 144:ef7eb2e8f9f7 39 * To select a peripheral function on Maxim microcontrollers, multiple
<> 144:ef7eb2e8f9f7 40 * configurations must be made. The mbed PinMap structure only includes one
<> 144:ef7eb2e8f9f7 41 * data member to hold this information. To extend the configuration storage,
<> 144:ef7eb2e8f9f7 42 * the "function" data member is used as a pointer to a pin_function_t
<> 144:ef7eb2e8f9f7 43 * structure. This structure is defined in objects.h. The definitions below
<> 144:ef7eb2e8f9f7 44 * include the creation of the pin_function_t structures and the assignment of
<> 144:ef7eb2e8f9f7 45 * the pointers to the "function" data members.
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 #ifdef TOOLCHAIN_ARM_STD
<> 144:ef7eb2e8f9f7 49 #pragma diag_suppress 1296
<> 144:ef7eb2e8f9f7 50 #endif
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /************I2C***************/
<> 144:ef7eb2e8f9f7 53 const PinMap PinMap_I2C_SDA[] = {
<> 144:ef7eb2e8f9f7 54 { P2_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 55 { P2_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 56 { P1_6, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 57 { P2_2, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 58 { P7_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 59 { P7_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 60 { P7_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 61 { P7_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 62 { P0_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 63 { P0_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 64 { NC, NC, 0 }
<> 144:ef7eb2e8f9f7 65 };
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 const PinMap PinMap_I2C_SCL[] = {
<> 144:ef7eb2e8f9f7 68 { P2_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 69 { P2_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 70 { P1_7, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 71 { P2_3, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 72 { P7_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 73 { P7_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 74 { P7_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 75 { P7_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 76 { P0_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 77 { P0_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 78 { NC, NC, 0 }
<> 144:ef7eb2e8f9f7 79 };
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /************UART***************/
<> 144:ef7eb2e8f9f7 82 const PinMap PinMap_UART_TX[] = {
<> 144:ef7eb2e8f9f7 83 { P1_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 84 { P1_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 85 { P2_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 86 { P2_5, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 87 { P7_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 88 { P7_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 89 { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 90 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 91 { NC, NC, 0 }
<> 144:ef7eb2e8f9f7 92 };
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 const PinMap PinMap_UART_RX[] = {
<> 144:ef7eb2e8f9f7 95 { P1_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 96 { P1_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 97 { P2_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 98 { P2_4, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 99 { P7_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 100 { P7_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 101 { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 102 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 103 { NC, NC, 0 }
<> 144:ef7eb2e8f9f7 104 };
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 const PinMap PinMap_UART_CTS[] = {
<> 144:ef7eb2e8f9f7 107 { P1_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
<> 144:ef7eb2e8f9f7 108 { P2_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
<> 144:ef7eb2e8f9f7 109 { P1_4, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
<> 144:ef7eb2e8f9f7 110 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
<> 144:ef7eb2e8f9f7 111 { P7_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
<> 144:ef7eb2e8f9f7 112 { P7_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
<> 144:ef7eb2e8f9f7 113 { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
<> 144:ef7eb2e8f9f7 114 { NC, NC, 0 }
<> 144:ef7eb2e8f9f7 115 };
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 const PinMap PinMap_UART_RTS[] = {
<> 144:ef7eb2e8f9f7 118 { P1_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
<> 144:ef7eb2e8f9f7 119 { P2_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
<> 144:ef7eb2e8f9f7 120 { P1_5, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
<> 144:ef7eb2e8f9f7 121 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
<> 144:ef7eb2e8f9f7 122 { P7_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
<> 144:ef7eb2e8f9f7 123 { P7_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
<> 144:ef7eb2e8f9f7 124 { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
<> 144:ef7eb2e8f9f7 125 { NC, NC, 0 }
<> 144:ef7eb2e8f9f7 126 };
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /************SPI***************/
<> 144:ef7eb2e8f9f7 129 const PinMap PinMap_SPI_SCLK[] = {
<> 144:ef7eb2e8f9f7 130 { P0_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 131 { P0_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 132 { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 133 { P1_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 134 { P2_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 135 { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 136 { P6_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 137 { P6_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 138 { NC, NC, 0}
<> 144:ef7eb2e8f9f7 139 };
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 const PinMap PinMap_SPI_MOSI[] = {
<> 144:ef7eb2e8f9f7 142 { P0_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 143 { P0_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 144 { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 145 { P1_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 146 { P2_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 147 { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 148 { P6_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 149 { P6_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 150 { NC, NC, 0}
<> 144:ef7eb2e8f9f7 151 };
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 const PinMap PinMap_SPI_MISO[] = {
<> 144:ef7eb2e8f9f7 154 { P0_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 155 { P0_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 156 { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 157 { P1_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 158 { P2_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 159 { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 160 { P6_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 161 { P6_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 162 { NC, NC, 0}
<> 144:ef7eb2e8f9f7 163 };
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 const PinMap PinMap_SPI_SSEL[] = {
<> 144:ef7eb2e8f9f7 166 #if (defined(EM9301_CSN) && (EM9301_CSN == P0_3))
<> 144:ef7eb2e8f9f7 167 { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) },
<> 144:ef7eb2e8f9f7 168 #else
<> 144:ef7eb2e8f9f7 169 { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
<> 144:ef7eb2e8f9f7 170 #endif
<> 144:ef7eb2e8f9f7 171 { P0_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
<> 144:ef7eb2e8f9f7 172 { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
<> 144:ef7eb2e8f9f7 173 { P1_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
<> 144:ef7eb2e8f9f7 174 { P2_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
<> 144:ef7eb2e8f9f7 175 #if (defined(EM9301_CSN) && (EM9301_CSN == P2_3))
<> 144:ef7eb2e8f9f7 176 { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) },
<> 144:ef7eb2e8f9f7 177 #else
<> 144:ef7eb2e8f9f7 178 { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
<> 144:ef7eb2e8f9f7 179 #endif
<> 144:ef7eb2e8f9f7 180 { P6_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
<> 144:ef7eb2e8f9f7 181 { P6_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
<> 144:ef7eb2e8f9f7 182 { NC, NC, 0}
<> 144:ef7eb2e8f9f7 183 };
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /************PWM***************/
<> 144:ef7eb2e8f9f7 186 const PinMap PinMap_PWM[] = {
<> 144:ef7eb2e8f9f7 187 {P0_0, PWM_0, 1}, {P0_0, PWM_0, 2}, {P0_0, PWM_4, 3},
<> 144:ef7eb2e8f9f7 188 {P0_1, PWM_1, 1}, {P0_1, PWM_4, 2}, {P0_1, PWM_0, 3},
<> 144:ef7eb2e8f9f7 189 {P0_2, PWM_2, 1}, {P0_2, PWM_1, 2}, {P0_2, PWM_5, 3},
<> 144:ef7eb2e8f9f7 190 {P0_3, PWM_3, 1}, {P0_3, PWM_5, 2}, {P0_3, PWM_1, 3},
<> 144:ef7eb2e8f9f7 191 {P0_4, PWM_4, 1}, {P0_4, PWM_2, 2}, {P0_4, PWM_6, 3},
<> 144:ef7eb2e8f9f7 192 {P0_5, PWM_5, 1}, {P0_5, PWM_6, 2}, {P0_5, PWM_2, 3},
<> 144:ef7eb2e8f9f7 193 {P0_6, PWM_6, 1}, {P0_6, PWM_3, 2}, {P0_6, PWM_7, 3},
<> 144:ef7eb2e8f9f7 194 {P0_7, PWM_7, 1}, {P0_7, PWM_7, 2}, {P0_7, PWM_3, 3},
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 {P1_0, PWM_0, 1}, {P1_0, PWM_0, 2}, {P1_0, PWM_4, 3},
<> 144:ef7eb2e8f9f7 197 {P1_1, PWM_1, 1}, {P1_1, PWM_4, 2}, {P1_1, PWM_0, 3},
<> 144:ef7eb2e8f9f7 198 {P1_2, PWM_2, 1}, {P1_2, PWM_1, 2}, {P1_2, PWM_5, 3},
<> 144:ef7eb2e8f9f7 199 {P1_3, PWM_3, 1}, {P1_3, PWM_5, 2}, {P1_3, PWM_1, 3},
<> 144:ef7eb2e8f9f7 200 {P1_4, PWM_4, 1}, {P1_4, PWM_2, 2}, {P1_4, PWM_6, 3},
<> 144:ef7eb2e8f9f7 201 {P1_5, PWM_5, 1}, {P1_5, PWM_6, 2}, {P1_5, PWM_2, 3},
<> 144:ef7eb2e8f9f7 202 {P1_6, PWM_6, 1}, {P1_6, PWM_3, 2}, {P1_6, PWM_7, 3},
<> 144:ef7eb2e8f9f7 203 {P1_7, PWM_7, 1}, {P1_7, PWM_7, 2}, {P1_7, PWM_3, 3},
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 {P2_0, PWM_0, 1}, {P2_0, PWM_0, 2}, {P2_0, PWM_4, 3},
<> 144:ef7eb2e8f9f7 206 {P2_1, PWM_1, 1}, {P2_1, PWM_4, 2}, {P2_1, PWM_0, 3},
<> 144:ef7eb2e8f9f7 207 {P2_2, PWM_2, 1}, {P2_2, PWM_1, 2}, {P2_2, PWM_5, 3},
<> 144:ef7eb2e8f9f7 208 {P2_3, PWM_3, 1}, {P2_3, PWM_5, 2}, {P2_3, PWM_1, 3},
<> 144:ef7eb2e8f9f7 209 {P2_4, PWM_4, 1}, {P2_4, PWM_2, 2}, {P2_4, PWM_6, 3},
<> 144:ef7eb2e8f9f7 210 {P2_5, PWM_5, 1}, {P2_5, PWM_6, 2}, {P2_5, PWM_2, 3},
<> 144:ef7eb2e8f9f7 211 {P2_6, PWM_6, 1}, {P2_6, PWM_3, 2}, {P2_6, PWM_7, 3},
<> 144:ef7eb2e8f9f7 212 {P2_7, PWM_7, 1}, {P2_7, PWM_7, 2}, {P2_7, PWM_3, 3},
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 {P6_0, PWM_0, 1}, {P6_0, PWM_0, 2}, {P6_0, PWM_4, 3},
<> 144:ef7eb2e8f9f7 215 {P6_1, PWM_1, 1}, {P6_1, PWM_4, 2}, {P6_1, PWM_0, 3},
<> 144:ef7eb2e8f9f7 216 {P6_2, PWM_2, 1}, {P6_2, PWM_1, 2}, {P6_2, PWM_5, 3},
<> 144:ef7eb2e8f9f7 217 {P6_3, PWM_3, 1}, {P6_3, PWM_5, 2}, {P6_3, PWM_1, 3},
<> 144:ef7eb2e8f9f7 218 {P6_4, PWM_4, 1}, {P6_4, PWM_2, 2}, {P6_4, PWM_6, 3},
<> 144:ef7eb2e8f9f7 219 {P6_5, PWM_5, 1}, {P6_5, PWM_6, 2}, {P6_5, PWM_2, 3},
<> 144:ef7eb2e8f9f7 220 {P6_6, PWM_6, 1}, {P6_6, PWM_3, 2}, {P6_6, PWM_7, 3},
<> 144:ef7eb2e8f9f7 221 {P6_7, PWM_7, 1}, {P6_7, PWM_7, 2}, {P6_7, PWM_3, 3},
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 {P7_0, PWM_0, 1}, {P7_0, PWM_0, 2}, {P7_0, PWM_4, 3},
<> 144:ef7eb2e8f9f7 224 {P7_1, PWM_1, 1}, {P7_1, PWM_4, 2}, {P7_1, PWM_0, 3},
<> 144:ef7eb2e8f9f7 225 {P7_2, PWM_2, 1}, {P7_2, PWM_1, 2}, {P7_2, PWM_5, 3},
<> 144:ef7eb2e8f9f7 226 {P7_3, PWM_3, 1}, {P7_3, PWM_5, 2}, {P7_3, PWM_1, 3},
<> 144:ef7eb2e8f9f7 227 {P7_4, PWM_4, 1}, {P7_4, PWM_2, 2}, {P7_4, PWM_6, 3},
<> 144:ef7eb2e8f9f7 228 {P7_5, PWM_5, 1}, {P7_5, PWM_6, 2}, {P7_5, PWM_2, 3},
<> 144:ef7eb2e8f9f7 229 {P7_6, PWM_6, 1}, {P7_6, PWM_3, 2}, {P7_6, PWM_7, 3},
<> 144:ef7eb2e8f9f7 230 {P7_7, PWM_7, 1}, {P7_7, PWM_7, 2}, {P7_7, PWM_3, 3},
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 233 };
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /************ADC***************/
<> 144:ef7eb2e8f9f7 236 const PinMap PinMap_ADC[] = {
<> 144:ef7eb2e8f9f7 237 {AIN_0P, ADC, 0},
<> 144:ef7eb2e8f9f7 238 {AIN_1P, ADC, 0},
<> 144:ef7eb2e8f9f7 239 {AIN_2P, ADC, 0},
<> 144:ef7eb2e8f9f7 240 {AIN_3P, ADC, 0},
<> 144:ef7eb2e8f9f7 241 {AIN_4P, ADC, 0},
<> 144:ef7eb2e8f9f7 242 {AIN_5P, ADC, 0},
<> 144:ef7eb2e8f9f7 243 {AIN_6P, ADC, 0},
<> 144:ef7eb2e8f9f7 244 {AIN_7P, ADC, 0},
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 {AIN_0N, ADC, 0},
<> 144:ef7eb2e8f9f7 247 {AIN_1N, ADC, 0},
<> 144:ef7eb2e8f9f7 248 {AIN_2N, ADC, 0},
<> 144:ef7eb2e8f9f7 249 {AIN_3N, ADC, 0},
<> 144:ef7eb2e8f9f7 250 {AIN_4N, ADC, 0},
<> 144:ef7eb2e8f9f7 251 {AIN_5N, ADC, 0},
<> 144:ef7eb2e8f9f7 252 {AIN_6N, ADC, 0},
<> 144:ef7eb2e8f9f7 253 {AIN_7N, ADC, 0},
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 {AIN_0D, ADC, 1},
<> 144:ef7eb2e8f9f7 256 {AIN_1D, ADC, 1},
<> 144:ef7eb2e8f9f7 257 {AIN_2D, ADC, 1},
<> 144:ef7eb2e8f9f7 258 {AIN_3D, ADC, 1},
<> 144:ef7eb2e8f9f7 259 {AIN_4D, ADC, 1},
<> 144:ef7eb2e8f9f7 260 {AIN_5D, ADC, 1},
<> 144:ef7eb2e8f9f7 261 {AIN_6D, ADC, 1},
<> 144:ef7eb2e8f9f7 262 {AIN_7D, ADC, 1},
<> 144:ef7eb2e8f9f7 263 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 264 };
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /************DAC***************/
<> 144:ef7eb2e8f9f7 267 const PinMap PinMap_DAC[] = {
<> 144:ef7eb2e8f9f7 268 {AOUT_AO, DAC0, 0},
<> 144:ef7eb2e8f9f7 269 {AOUT_BO, DAC1, 0},
<> 144:ef7eb2e8f9f7 270 {AOUT_CO, DAC2, 0},
<> 144:ef7eb2e8f9f7 271 {AOUT_DO, DAC3, 0},
<> 144:ef7eb2e8f9f7 272 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 273 };